This commit introduces a new qtest for the Aspeed SGPIO controller The test covers the following: - Setting and clearing SGPIO output pins and verifying the pin state. - Setting and clearing SGPIO input pins and verifying the pin state. - Verifying that level-high interrupts are correctly triggered and cleared.
Signed-off-by: Yubin Zou <[email protected]> --- tests/qtest/ast2700-sgpio-test.c | 152 +++++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 153 insertions(+) diff --git a/tests/qtest/ast2700-sgpio-test.c b/tests/qtest/ast2700-sgpio-test.c new file mode 100644 index 0000000000000000000000000000000000000000..fc52839c4b149a3010c6a035d8b29f9ad295930a --- /dev/null +++ b/tests/qtest/ast2700-sgpio-test.c @@ -0,0 +1,152 @@ +/* + * QTest testcase for the ASPEED AST2700 GPIO Controller. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright (C) 2025 Google LLC. + */ + +#include "qemu/osdep.h" +#include "qobject/qdict.h" +#include "qemu/bitops.h" +#include "qemu/timer.h" +#include "qobject/qdict.h" +#include "libqtest-single.h" +#include "qemu/error-report.h" +#include "hw/registerfields.h" +#include "hw/gpio/aspeed_sgpio.h" + +#define ASPEED_SGPIO_MAX_PIN_PAIR 256 +#define AST2700_SGPIO0_BASE 0x14C0C000 +#define AST2700_SGPIO1_BASE 0x14C0D000 + +static void test_output_pins(const char *machine, const uint32_t base, int idx) +{ + QTestState *s = qtest_init(machine); + char name[16]; + char qom_path[64]; + uint32_t offset = 0; + uint32_t value = 0; + for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { + /* Odd index is output port */ + sprintf(name, "sgpio%d", i * 2 + 1); + sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); + offset = base + (R_SGPIO_0_CONTROL + i) * 4; + /* set serial output */ + qtest_writel(s, offset, 0x00000001); + value = qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_OUT_VAL), ==, 1); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), ==, true); + + /* clear serial output */ + qtest_writel(s, offset, 0x00000000); + value = qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_OUT_VAL), ==, 0); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), ==, false); + } + qtest_quit(s); +} + +static void test_input_pins(const char *machine, const uint32_t base, int idx) +{ + QTestState *s = qtest_init(machine); + char name[16]; + char qom_path[64]; + uint32_t offset = 0; + uint32_t value = 0; + for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { + /* Even index is input port */ + sprintf(name, "sgpio%d", i * 2); + sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); + offset = base + (R_SGPIO_0_CONTROL + i) * 4; + /* set serial input */ + qtest_qom_set_bool(s, qom_path, name, true); + value = qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), ==, 1); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), ==, true); + + /* clear serial input */ + qtest_qom_set_bool(s, qom_path, name, false); + value = qtest_readl(s, offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), ==, 0); + g_assert_cmphex(qtest_qom_get_bool(s, qom_path, name), ==, false); + } + qtest_quit(s); +} + +static void test_irq_level_high(const char *machine, + const uint32_t base, int idx) +{ + QTestState *s = qtest_init(machine); + char name[16]; + char qom_path[64]; + uint32_t ctrl_offset = 0; + uint32_t int_offset = 0; + uint32_t int_reg_idx = 0; + uint32_t int_bit_idx = 0; + uint32_t value = 0; + for (int i = 0; i < ASPEED_SGPIO_MAX_PIN_PAIR; i++) { + /* Even index is input port */ + sprintf(name, "sgpio%d", i * 2); + sprintf(qom_path, "/machine/soc/sgpio[%d]", idx); + int_reg_idx = i / 32; + int_bit_idx = i % 32; + int_offset = base + (R_SGPIO_INT_STATUS_0 + int_reg_idx) * 4; + ctrl_offset = base + (R_SGPIO_0_CONTROL + i) * 4; + + /* Enable the interrupt */ + value = SHARED_FIELD_DP32(value, SGPIO_INT_EN, 1); + qtest_writel(s, ctrl_offset, value); + + /* Set the interrupt type to level-high trigger */ + value = SHARED_FIELD_DP32(qtest_readl(s, ctrl_offset), + SGPIO_INT_TYPE, 3); + qtest_writel(s, ctrl_offset, value); + + /* Set serial input high */ + qtest_qom_set_bool(s, qom_path, name, true); + value = qtest_readl(s, ctrl_offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), ==, 1); + + /* Interrupt status is set */ + value = qtest_readl(s, int_offset); + g_assert_cmphex(extract32(value, int_bit_idx, 1), ==, 1); + + /* Clear Interrupt */ + value = SHARED_FIELD_DP32(qtest_readl(s, ctrl_offset), + SGPIO_INT_STATUS, 1); + qtest_writel(s, ctrl_offset, value); + value = qtest_readl(s, int_offset); + g_assert_cmphex(extract32(value, int_bit_idx, 1), ==, 0); + + /* Clear serial input */ + qtest_qom_set_bool(s, qom_path, name, false); + value = qtest_readl(s, ctrl_offset); + g_assert_cmphex(SHARED_FIELD_EX32(value, SGPIO_SERIAL_IN_VAL), ==, 0); + } + qtest_quit(s); +} + +static void test_2700_input_pins(void) +{ + test_input_pins("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_input_pins("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); + test_output_pins("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_output_pins("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO0_BASE, 0); + test_irq_level_high("-machine ast2700-evb", + AST2700_SGPIO1_BASE, 1); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/ast2700/sgpio/input_pins", test_2700_input_pins); + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 669d07c06bdedc6be0c69acadeba989dc15ddf3f..5c80b2ed6de1f453d2483db482c1b0e7801ba980 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -221,6 +221,7 @@ qtests_aspeed = \ qtests_aspeed64 = \ ['ast2700-gpio-test', 'ast2700-hace-test', + 'ast2700-sgpio-test', 'ast2700-smc-test'] qtests_stm32l4x5 = \ -- 2.52.0.223.gf5cc29aaa4-goog
