diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c
new file mode 100644
index
0000000000000000000000000000000000000000..8676fa7ced134f1f62dc9e30b42c5fe6db3de268
--- /dev/null
+++ b/hw/gpio/aspeed_sgpio.c
@@ -0,0 +1,154 @@
+/*
+ * ASPEED Serial GPIO Controller
+ *
+ * Copyright 2025 Google LLC.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "hw/qdev-properties.h"
+#include "hw/gpio/aspeed_sgpio.h"
+
+static uint64_t aspeed_sgpio_2700_read_int_status_reg(AspeedSGPIOState *s,
+ uint32_t reg)
+{
+ return 0;
+}
+
+static uint64_t aspeed_sgpio_2700_read_control_reg(AspeedSGPIOState *s,
+ uint32_t reg)
+{
+ AspeedSGPIOClass *agc = ASPEED_SGPIO_GET_CLASS(s);
+ uint32_t idx = reg - R_SGPIO_0_CONTROL;
+ if (idx >= agc->nr_sgpio_pin_pairs) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: pin index: %d, out of bounds\n",
+ __func__, idx);
+ return 0;
+ }
+ return s->ctrl_regs[idx];
+}
+
+static void aspeed_sgpio_2700_write_control_reg(AspeedSGPIOState *s,
+ uint32_t reg, uint64_t data)
+{
+ AspeedSGPIOClass *agc = ASPEED_SGPIO_GET_CLASS(s);
+ uint32_t idx = reg - R_SGPIO_0_CONTROL;
+ if (idx >= agc->nr_sgpio_pin_pairs) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: pin index: %d, out of bounds\n",
+ __func__, idx);
+ return;
+ }
+ s->ctrl_regs[idx] = data;
+}
+
+static uint64_t aspeed_sgpio_2700_read(void *opaque, hwaddr offset,
+ uint32_t size)
+{
+ AspeedSGPIOState *s = ASPEED_SGPIO(opaque);
+ uint64_t value = 0;
+ uint64_t reg;
+
+ reg = offset >> 2;
+
+ switch (reg) {
+ case R_SGPIO_INT_STATUS_0 ... R_SGPIO_INT_STATUS_7:
+ aspeed_sgpio_2700_read_int_status_reg(s, reg);
+ break;
+ case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL:
+ value = aspeed_sgpio_2700_read_control_reg(s, reg);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%"
+ PRIx64"\n", __func__, offset);
+ return 0;
+ }
+
+ return value;
+}
+
+static void aspeed_sgpio_2700_write(void *opaque, hwaddr offset, uint64_t data,
+ uint32_t size)
+{
+ AspeedSGPIOState *s = ASPEED_SGPIO(opaque);
+ uint64_t reg;
+
+ reg = offset >> 2;
+
+ switch (reg) {
+ case R_SGPIO_0_CONTROL ... R_SGPIO_255_CONTROL:
+ aspeed_sgpio_2700_write_control_reg(s, reg, data);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%"
+ PRIx64"\n", __func__, offset);
+ return;
+ }
+}
+
+static const MemoryRegionOps aspeed_gpio_2700_ops = {
+ .read = aspeed_sgpio_2700_read,
+ .write = aspeed_sgpio_2700_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+};
+
+static void aspeed_sgpio_realize(DeviceState *dev, Error **errp)
+{
+ AspeedSGPIOState *s = ASPEED_SGPIO(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ AspeedSGPIOClass *agc = ASPEED_SGPIO_GET_CLASS(s);
+
+ /* Interrupt parent line */
+ sysbus_init_irq(sbd, &s->irq);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), agc->reg_ops, s,
+ TYPE_ASPEED_SGPIO, agc->mem_size);
+
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = aspeed_sgpio_realize;
+ dc->desc = "Aspeed SGPIO Controller";
+}
+
+static void aspeed_sgpio_2700_class_init(ObjectClass *klass, const void *data)
+{
+ AspeedSGPIOClass *agc = ASPEED_SGPIO_CLASS(klass);
+ agc->nr_sgpio_pin_pairs = 256;
+ agc->mem_size = 0x1000;
+ agc->reg_ops = &aspeed_gpio_2700_ops;
+}
+
+static const TypeInfo aspeed_sgpio_info = {
+ .name = TYPE_ASPEED_SGPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedSGPIOState),
+ .class_size = sizeof(AspeedSGPIOClass),
+ .class_init = aspeed_sgpio_class_init,
+ .abstract = true,
+};
+
+static const TypeInfo aspeed_sgpio_ast2700_info = {
+ .name = TYPE_ASPEED_SGPIO "-ast2700",
+ .parent = TYPE_ASPEED_SGPIO,
+ .class_init = aspeed_sgpio_2700_class_init,
+};
+
+static void aspeed_sgpio_register_types(void)
+{
+ type_register_static(&aspeed_sgpio_info);
+ type_register_static(&aspeed_sgpio_ast2700_info);
+}
+
+type_init(aspeed_sgpio_register_types);
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
index
74840619c01bf4d9a02c058c434c3ec9d2a55bee..6a67ee958faace69ffd3fe08e8ade31ced0faf7e
100644
--- a/hw/gpio/meson.build
+++ b/hw/gpio/meson.build
@@ -16,5 +16,6 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files(
))
system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true:
files('stm32l4x5_gpio.c'))
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
+system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sgpio.c'))
system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
system_ss.add(when: 'CONFIG_PCF8574', if_true: files('pcf8574.c'))
diff --git a/include/hw/gpio/aspeed_sgpio.h b/include/hw/gpio/aspeed_sgpio.h
new file mode 100644
index
0000000000000000000000000000000000000000..ffdc54a112da8962a7bc5773d524f1d86eb85d39
--- /dev/null
+++ b/include/hw/gpio/aspeed_sgpio.h
@@ -0,0 +1,66 @@
+/*
+ * ASPEED Serial GPIO Controller
+ *
+ * Copyright 2025 Google LLC.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#ifndef ASPEED_SGPIO_H
+#define ASPEED_SGPIO_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+#include "hw/registerfields.h"
+
+#define TYPE_ASPEED_SGPIO "aspeed.sgpio"
+OBJECT_DECLARE_TYPE(AspeedSGPIOState, AspeedSGPIOClass, ASPEED_SGPIO)
+
+#define ASPEED_SGPIO_MAX_PIN_PAIR 256
+#define ASPEED_SGPIO_MAX_INT 8
+
+/* AST2700 SGPIO Register Address Offsets */
+REG32(SGPIO_INT_STATUS_0, 0x40)
+REG32(SGPIO_INT_STATUS_1, 0x44)
+REG32(SGPIO_INT_STATUS_2, 0x48)
+REG32(SGPIO_INT_STATUS_3, 0x4C)
+REG32(SGPIO_INT_STATUS_4, 0x50)
+REG32(SGPIO_INT_STATUS_5, 0x54)
+REG32(SGPIO_INT_STATUS_6, 0x58)
+REG32(SGPIO_INT_STATUS_7, 0x5C)
+/* AST2700 SGPIO_0 - SGPIO_255 Control Register */
+REG32(SGPIO_0_CONTROL, 0x80)
+ SHARED_FIELD(SGPIO_SERIAL_OUT_VAL, 0, 1)
+ SHARED_FIELD(SGPIO_PARALLEL_OUT_VAL, 1, 1)
+ SHARED_FIELD(SGPIO_INT_EN, 2, 1)
+ SHARED_FIELD(SGPIO_INT_TYPE, 3, 3)
+ SHARED_FIELD(SGPIO_RESET_POLARITY, 6, 1)
+ SHARED_FIELD(SGPIO_RESERVED_1, 7, 2)
+ SHARED_FIELD(SGPIO_INPUT_MASK, 9, 1)
+ SHARED_FIELD(SGPIO_PARALLEL_EN, 10, 1)
+ SHARED_FIELD(SGPIO_PARALLEL_IN_MODE, 11, 1)
+ SHARED_FIELD(SGPIO_INT_STATUS, 12, 1)
+ SHARED_FIELD(SGPIO_SERIAL_IN_VAL, 13, 1)
+ SHARED_FIELD(SGPIO_PARALLEL_IN_VAL, 14, 1)
+ SHARED_FIELD(SGPIO_RESERVED_2, 15, 12)
+ SHARED_FIELD(SGPIO_WRITE_PROTECT, 31, 1)
+REG32(SGPIO_255_CONTROL, 0x47C)
+
+struct AspeedSGPIOClass {
+ SysBusDevice parent_obj;
+ uint32_t nr_sgpio_pin_pairs;
+ uint64_t mem_size;
+ const MemoryRegionOps *reg_ops;
+};
