On Fri, Apr 24, 2015 at 01:28:41PM -0700, Peter Crosthwaite wrote:
> Rename some A57 CP register variables in preparation for support for
> Cortex A53. Use "a57_a53" to describe the shareable features. Some of
> the CP15 registers (such as ACTLR) are specific to implementation, but
> we currently just RAZ them so continue with that as the policy for both
> A57 and A53 processors under a shared definition.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
> ---
> changed since v4 (PMM review):
> Use a57_a53 instead of axx
> Drop initfn refactorings
>
> target-arm/cpu64.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index 270bc2f..13e042e 100644
> --- a/target-arm/cpu64.c
> +++ b/target-arm/cpu64.c
> @@ -38,22 +38,22 @@ static inline void unset_feature(CPUARMState *env, int
> feature)
> }
>
> #ifndef CONFIG_USER_ONLY
> -static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> +static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> {
> /* Number of processors is in [25:24]; otherwise we RAZ */
> return (smp_cpus - 1) << 24;
> }
> #endif
>
> -static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
> +static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
> #ifndef CONFIG_USER_ONLY
> { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
> - .access = PL1_RW, .readfn = a57_l2ctlr_read,
> + .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
> .writefn = arm_cp_write_ignore },
> { .name = "L2CTLR",
> .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
> - .access = PL1_RW, .readfn = a57_l2ctlr_read,
> + .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
> .writefn = arm_cp_write_ignore },
> #endif
> { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
> @@ -140,7 +140,7 @@ static void aarch64_a57_initfn(Object *obj)
> cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
> cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
> cpu->dcz_blocksize = 4; /* 64 bytes */
> - define_arm_cp_regs(cpu, cortexa57_cp_reginfo);
> + define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
> }
>
> #ifdef CONFIG_USER_ONLY
> --
> 2.3.6.3.g2cc70ee
>
