On Fri, Apr 24, 2015 at 01:28:41PM -0700, Peter Crosthwaite wrote:
> Add the ARM cortex A53 processor definition. Similar to A57, but with
> different L1 I cache policy, phys addr size and different cache
> geometries. The cache sizes is implementation configurable, but use
> these values (from Xilinx Zynq MPSoC) as a default until cache size
> configurability is added.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
Acked-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
> ---
> Changed since v4:
> Fix a53/a57 typo in commit message (Ozaki)
> Use standalone init fn rather than a57-shared one (PMM).
> Changed since v2:
> Added dtb compatible string
>
> target-arm/cpu64.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index 13e042e..bf7dd68 100644
> --- a/target-arm/cpu64.c
> +++ b/target-arm/cpu64.c
> @@ -143,6 +143,56 @@ static void aarch64_a57_initfn(Object *obj)
> define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
> }
>
> +static void aarch64_a53_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,cortex-a53";
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + set_feature(&cpu->env, ARM_FEATURE_VFP4);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> + set_feature(&cpu->env, ARM_FEATURE_V8_AES);
> + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
> + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
> + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
> + set_feature(&cpu->env, ARM_FEATURE_CRC);
> + cpu->midr = 0x410fd034;
> + cpu->reset_fpsid = 0x41034070;
> + cpu->mvfr0 = 0x10110222;
> + cpu->mvfr1 = 0x12111111;
> + cpu->mvfr2 = 0x00000043;
> + cpu->ctr = 0x84448004; /* L1Ip = VIPT */
> + cpu->reset_sctlr = 0x00c50838;
> + cpu->id_pfr0 = 0x00000131;
> + cpu->id_pfr1 = 0x00011011;
> + cpu->id_dfr0 = 0x03010066;
> + cpu->id_afr0 = 0x00000000;
> + cpu->id_mmfr0 = 0x10101105;
> + cpu->id_mmfr1 = 0x40000000;
> + cpu->id_mmfr2 = 0x01260000;
> + cpu->id_mmfr3 = 0x02102211;
> + cpu->id_isar0 = 0x02101110;
> + cpu->id_isar1 = 0x13112111;
> + cpu->id_isar2 = 0x21232042;
> + cpu->id_isar3 = 0x01112131;
> + cpu->id_isar4 = 0x00011142;
> + cpu->id_isar5 = 0x00011121;
> + cpu->id_aa64pfr0 = 0x00002222;
> + cpu->id_aa64dfr0 = 0x10305106;
> + cpu->id_aa64isar0 = 0x00011120;
> + cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
> + cpu->dbgdidr = 0x3516d000;
> + cpu->clidr = 0x0a200023;
> + cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
> + cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
> + cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
> + cpu->dcz_blocksize = 4; /* 64 bytes */
> + define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
> +}
> +
> #ifdef CONFIG_USER_ONLY
> static void aarch64_any_initfn(Object *obj)
> {
> @@ -170,6 +220,7 @@ typedef struct ARMCPUInfo {
>
> static const ARMCPUInfo aarch64_cpus[] = {
> { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
> + { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
> #ifdef CONFIG_USER_ONLY
> { .name = "any", .initfn = aarch64_any_initfn },
> #endif
> --
> 2.3.6.3.g2cc70ee
>
