On 01/16/2017 07:58 PM, mar.krzeminski wrote: > > > W dniu 16.01.2017 o 09:18, Cédric Le Goater pisze: >>> I did not notice that this function is also called in writes, isn't it? >>> If yes, dummy cycles are used only during reads so probably CTRL_FREADMODE >>> needs to be tested. >> yes. I can take care of that in a follow up patchset for >> dummy support. >> Dummies in user mode is a bit painful to implement, as I had >> to snoop into the command flow to catch the fast read op. >> Not sure this is the right approach so I kept it for later. > Definitelly wrong, controller should not be aware of tha, fix is still on me > :(
ok. np. I will send the support for command mode though, as this is a must have for booting. >> >> >> Did you have time to take look at the other patches adding >> Command mode and extending the tests ? I should have addressed >> your comments there. > Yes, there is one more thing that could be important. It popped out in > Sabrelite > SPI model. The question is does SCM support different CS active (so device > is active at CS high). Your code assume that SMC will always use CS LOW to > activate > device. If this is not true you might be interested in update this too. Aspeed SoC does not let you configure the chip select polarity (nor the clock phase ) So it is active low only. Thanks, C.
