On 06/26/2018 06:38 AM, Peter Maydell wrote:
> On 21 June 2018 at 02:53, Richard Henderson
> <richard.hender...@linaro.org> wrote:
>> The original commit failed to pass, or use, the index.
>>
>> Fixes: d17b7cdcf4ea
>> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
>> ---
>> target/arm/translate-a64.c | 21 ++++++++++++---------
>> target/arm/vec_helper.c | 10 ++++++----
>> 2 files changed, 18 insertions(+), 13 deletions(-)
>>
>> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
>> index 8d8a4cecb0..038e48278f 100644
>> --- a/target/arm/translate-a64.c
>> +++ b/target/arm/translate-a64.c
>> @@ -12669,15 +12669,18 @@ static void disas_simd_indexed(DisasContext *s,
>> uint32_t insn)
>> case 0x13: /* FCMLA #90 */
>> case 0x15: /* FCMLA #180 */
>> case 0x17: /* FCMLA #270 */
>> - tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
>> - vec_full_reg_offset(s, rn),
>> - vec_reg_offset(s, rm, index, size), fpst,
>> - is_q ? 16 : 8, vec_full_reg_size(s),
>> - extract32(insn, 13, 2), /* rot */
>> - size == MO_64
>> - ? gen_helper_gvec_fcmlas_idx
>> - : gen_helper_gvec_fcmlah_idx);
>> - tcg_temp_free_ptr(fpst);
>> + {
>> + int rot = extract32(insn, 13, 2);
>> + int data = index * 4 + rot;
>
> Using arithmetic to do bit operations again.
>
>> + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
>> + vec_full_reg_offset(s, rn),
>> + vec_reg_offset(s, rm, index, size), fpst,
>> + is_q ? 16 : 8, vec_full_reg_size(s), data,
>> + size == MO_64
>> + ? gen_helper_gvec_fcmlas_idx
>> + : gen_helper_gvec_fcmlah_idx);
>
> We're already using vec_reg_offset() to pass the helper the address
> of the index'th element in Vm -- why do we need to also add
> 2*index when we use that pointer as an array base in the helper?
Ah, bug. Because of SVE, we must pass index (since it applies per 128-bit
segment), and we should pass the full_reg as the pointer.
r~
