On Thu, 11 Jul 2019 at 13:43, Richard Henderson <richard.hender...@linaro.org> wrote: > > On 7/11/19 2:12 PM, Peter Maydell wrote: > > @@ -1713,6 +1719,12 @@ static void arm1026_initfn(Object *obj) > > }; > > define_one_arm_cp_reg(cpu, &ifar); > > } > > + /* > > + * Similarly, we need to set MVFR0 fields to enable double precision > > + * and short vector support even though ARMv5 doesn't have this > > register. > > + */ > > + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); > > + cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); > > } > > I would have placed this immediately after the Jazelle isar setup, so that the > "Similarly" comment had the proper referent. But, no biggie.
Yes, I'll move it. I'd misread the chunk of code that sets the custom IFAR as "ISAR" and assumed it was all of a piece with the Jazelle ISAR setup. thanks -- PMM