On Thu, 11 Jul 2019 at 14:01, Alex Bennée <alex.ben...@linaro.org> wrote: > > > Peter Maydell <peter.mayd...@linaro.org> writes: > > > The ARMv5 architecture didn't specify detailed per-feature ID > > registers. Now that we're using the MVFR0 register fields to > > gate the existence of VFP instructions, we need to set up > > the correct values in the cpu->isar structure so that we still > > provide an FPU to the guest. > > > > This fixes a regression in the arm926 and arm1026 CPUs, which > > are the only ones that both have VFP and are ARMv5 or earlier. > > This regression was introduced by the VFP refactoring, and more > > specifically by commits 1120827fa182f0e76 and 266bd25c485597c, > > which accidentally disabled VFP short-vector support and > > double-precision support on these CPUs. > > > > Reported-by: Christophe Lyon <christophe.l...@linaro.org> > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > > Fixes: 1120827fa182f0e > > Fixes: 266bd25c485597c > > Fixes: https://bugs.launchpad.net/qemu/+bug/1836192 > > --- > > I've followed the existing approach we used for ISAR1 here > > of just filling in the fields we care about, rather than trying > > to set the entire register value. > > Reviewed-by: Alex Bennée <alex.ben...@linaro.org> > > Do you think we have caught them all now? If we end up removing the > other ARM_FEATURE_foo flags in favour of isar tests we shall have to be > careful not to re-introduce these sort of bugs.
I checked that these were the only two extra ID-reg checks we added as part of the VFP conversion, at any rate (ignoring the checks for features the ARMv5 cores don't have). thanks -- PMM