On Mon, Feb 01, 2021 at 05:33:53PM +0100, Florian Weimer wrote: > * Daniel P. Berrangé: > > > and supported by GCC, CLang, GLibC and more. > > Clang and glibc are the official spellings, I think.
Ok. > > diff --git a/docs/system/cpu-models-x86-abi.csv > > b/docs/system/cpu-models-x86-abi.csv > > new file mode 100644 > > index 0000000000..4565e6a535 > > --- /dev/null > > +++ b/docs/system/cpu-models-x86-abi.csv > > > +Icelake-Client,✅,✅,✅, > > +Icelake-Client-noTSX,✅,✅,✅, > > +Icelake-Client-v1,✅,✅,✅, > > +Icelake-Client-v2,✅,✅,✅, > > Icelake Client supports x86-64-v4 according to Intel ARK and a quick > test on a reference system. Have you defined it differently in QEMU? QEMU's Icelake-Client CPU models appear to be missing most of the AVX-512 CPUIDs bits: https://gitlab.com/qemu-project/qemu/-/blob/master/target/i386/cpu.c#L3291 Compared to Icelake-Server which does have them: https://gitlab.com/qemu-project/qemu/-/blob/master/target/i386/cpu.c#L3409 I don't know why it is specified this way in QEMU. It could easily be a bug in QEMU's definitions. Alternatively there might be a subset of Icelake-Client SKUs which genuinely do lack these features, and this influenced the decision to omit them from QEMU models. > > +KnightsMill,✅,✅,✅, > > +KnightsMill-v1,✅,✅,✅, > > This one is correct. Even though Knights Mill supports AVX-512, it does > not cover the variants that are considered definitive for x86-64-v4. > > > +Skylake-Server,✅,✅,✅,✅ > > +Skylake-Server-IBRS,✅,✅,✅,✅ > > +Skylake-Server-noTSX-IBRS,✅,✅,✅,✅ > > +Skylake-Server-v1,✅,✅,✅,✅ > > +Skylake-Server-v2,✅,✅,✅,✅ > > +Skylake-Server-v3,✅,✅,✅,✅ > > +Skylake-Server-v4,✅,✅,✅,✅ > > This one is a little bit odd. Skylake Xeons which are not Xeon Scalable > Processors exist, and they do not support x86-64-v4. Is this again a > matter of different naming in QEMU? Most likely this is just a case of the QEMU Skylake-Server model being written in terms of the most common SKUs, and ignoring the inconvenience of certain SKUs lacking the features. In general there are waaaay too many different variants of Intel CPUs for QEMU to provide a named model to cope with every scenario. So the QEMU models are always an approximation of what exists in the silicon. If there are places where we've made bad mistake, we do now have the ability to do CPU versioning. So in theory we could introduce a new Skylake-Server-v5 which removes the AVX512 stuff if there's a genuine problem with some variants of silicon not supporting it. Alternatively people with such hosts can just use an older named model like Skylake-Client. Regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
