On Sat, Nov 13, 2021 at 1:19 AM Frédéric Pétrot
<frederic.pet...@univ-grenoble-alpes.fr> wrote:
>
> Adding the high part of a very minimal set of csr.
>
> Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.por...@grenoble-inp.org>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 4 ++++
> target/riscv/machine.c | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index ae1f9cb876..15609a5533 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -195,6 +195,10 @@ struct CPURISCVState {
> target_ulong hgatp;
> uint64_t htimedelta;
>
> + /* Upper 64-bits of 128-bit CSRs */
> + uint64_t mscratchh;
> + uint64_t sscratchh;
> +
> /* Virtual CSRs */
> /*
> * For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 7e2d02457e..6f0eabf66a 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -179,6 +179,8 @@ static const VMStateDescription vmstate_rv128 = {
> .needed = rv128_needed,
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
> + VMSTATE_UINT64(env.mscratchh, RISCVCPU),
> + VMSTATE_UINT64(env.sscratchh, RISCVCPU),
> VMSTATE_END_OF_LIST()
> }
> };
> --
> 2.33.1
>
>
