On 4 January 2012 16:53, Mark Langsdorf <mark.langsd...@calxeda.com> wrote:
> + if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
> + switch (crm) {
> + case 0:
> + if ((op1 == 4) && (op2 == 0)) {
> + /* The config_base_address should hold the value of
> + * the peripheral base. ARM should get this from a CPU
> + * object property, but that support isn't available in
> + * December 2011. Default to 0 for now and board models
> + * that care can set it by a private hook */
> + return env->cp15.c15_config_base_address;
> + } else if ((op1 == 0) && (op2 == 0)) {
> + /* power_control should be set to maximum latency. Again,
> + default to 0 and set by private hook */
> + return env->cp15.c15_power_control;
> + }
This one's read-write, which means it needs (a) support in set_cp15
(b) save/load
support.
> + break;
> + case 1: /* NEON Busy */
> + return 0;
> + case 5: /* tlb lockdown */
> + case 6:
> + case 7:
> + if ((op1 == 5) && (op2 == 2)) {
> + return 0;
> + }
> + break;
> + default:
> + break;
> + }
> + goto bad_reg;
> + }
You also need to implement the diagnostic register c15,c0,0,1
otherwise Linux won't boot when it tries to run this code:
http://lxr.linux.no/#linux+v3.1.7/arch/arm/mm/proc-v7.S#L345
I suggest that should be implemented as reads-as-written. (Again, will
need save/load
support.) Ditto for the power diagnostic control register c15,c0,0,2, as used in
this patch: http://www.spinics.net/lists/arm-kernel/msg115817.html
-- PMM
