On Wed, 15 Sep 2010 19:18:33 +0200, Peter Graf wrote: > Thierry wrote: > > > A phase locked loop with a programmable counter would do... > > That won't work well. The only signals permanently available for PLL input > are the QL sync signals and they are not stable enough to generate a > decent pixel clock to feed TFT monitors. > I'd use a separate time base for output, and decouple input and output > via screen RAM.
I was speaking about the pixel sampling rate, for the input. Converters using the same clock as for the output pixel clock fail to sample the QL video signal, since there is no integer divisor common with 512 and 640 (or 800), and even with a 1024 pixels/line clock rate, the blanking times are not the same (meaning the apparent 2 divisor is in fact not the right one). Of course, to generate the (S)VGA signal, you'd need a perfectly stable and independent clock. A dual port RAM would probably be needed as well. For the QL, since there are only 8 colours, no A/D neither D/A are needed (but they would be needed of the Q40/Q60). > > It could for example also be used (with different parameters) to > > adapt a Q40/Q60 videao signal > > Not the same hardware then. It would require faster RAM, more RAM, > much better A/D and D/A conversion, and a more complex logic. Yes, but if the hardware can do the Q40, it can do the QL, as long as the parameters required to rebuild the pixel clock can be adjusted (thus why a microcontroler would be a good idea). > > to standard SVGA (I still could not find a modern LCD monitor that > could properly display the 1024x512 screen of a Q60... > > I think you can give up that search :-( > It only works with a modified video chip, and that only for a minority > of monitors. If you know any such monitor, please let us know. Thierry. _______________________________________________ QL-Users Mailing List http://www.q-v-d.demon.co.uk/smsqe.htm
