On Wed, Feb 16, 2011 at 6:30 AM, David Tubbs <davet...@tiscali.co.uk> wrote:
> If it is present, > Modified eprom board, just as easyly hold two full ROM & TK2 versions, > Mainboard ROMs removed of course. > Unfortunately, the lines aren't brought through to the ROM port to select chips outside of the 48-64K memory block, so OS chips can't be read through the port. (strictly speaking, the $8000 upper ROM could be placed in the ROM port and be readable, but that wouldn't be very useful. All that can be done with the ROM port is individual 16K ROM images can be placed there. There could be a choice of images switched in and out, but that's about it. They limited the internal $8000 ROM slot the same way - it only gets a CS signal for that 16K block, so you can't address a full 32k EPROM unless you attach the CS line from the ROM port to the upper ROM slot CS line. For those to whom this is Greek: CS means Chip Select. Take memory for example: there are 8 identical RAM chips, and each has access to the same address line (which tell the chip what address you're looking for) and data lines (where it puts the data for the address you asserted on the data lines.) As every chip is connected to the same address and data bus, you need a way to tell the chips "I'm talking to you" and so CHIP SELECT was born. So with 8 imaginary chips, and 128K of RAM, each chip stores 16k. You need an "address decoder" which takes the relevent lines of the address bus and creates an output to each chip as required. If the address bus on this imaginary computer is 16 bits wide (A0 to A15) and this 128K sits at a block from 0-128K (for example) then: A0 to A7 get passed to each chip. A8 thru A10 get passed to an address decoder A11 thru A15 get passed to a chip which makes sure they're all 0. IF they are all zero, and the address isn't over 128K, that chip tells the address decoder "this is for you." The address decoder now knows that 1. "This address is for you" and two, it has three pins which it can now pas through a 3 to 8 line decoder: input output on 8 pins 000 = 00000001 001 = 00000010 010 = 00000100 011 = 00001000 100 = 00010000 101 = 00100000 110 = 01000000 111 = 10000000 So now the lines A8 through A10 work through the address decoder, permitted by the logic from A11+, to select which memory chip is being addressed. Obviously, this is a gross simplification of memory addressing, and the QL does it in two banks, and uses 4-bit chips so 2 chips need selecting to make the 8 bit wide data bus... But in principle, this is how it works, and this decision tree happens for every single memory access. Fun, huh? :) Dave _______________________________________________ QL-Users Mailing List http://www.q-v-d.demon.co.uk/smsqe.htm
