Marcel, do you know if any free VHDL simulation/analysis tools exist that may be close to a code debugger (breakpoints etc., if that makes sense)?
I wouldn't mind giving the occasional look and fix some instructions, but only if there is an efficient way of doing it. Going through countless iterations of experiments and/or needing the hardware would exceed my available time. Thanks, Daniele > Date: Sat, 22 Mar 2014 01:35:26 +0100 > From: [email protected] > To: [email protected] > Subject: Re: [Ql-Users] New QL > > [email protected] wrote: > > In case you are thinking about hiring someone to design a better > > CPU, I'm not sure if software developers are the ones to ask. This > > is not software, it's hardware design. I'm sure folks like Daniele, > > Richard and Marcel know a lot about 68K instructions, but it seems > > unlikely one of them would also like to learn chip design. > > Actually I have dabbled with VHDL in University and would love to do > more with FPGAs, but no, I have enough pet projects going as it is. > Perhaps in another life ;-) > > Without even having seen the code I guess the remaining bugs are in > the processor flag handling. If you don't get them exactly right > everything kind of works, but then after a few million flawless > instructions some tiny thing breaks and things go down from there. I > remember tracing thousands of lines side by side with a real QL to > catch the remaining differences. But it did pay off, in the 18 years > since the first release only a handful bugs have been found in the > emulation core, most by George Gwilt. You should send him a board ;-) > > Cheers, Marcel > > _______________________________________________ > QL-Users Mailing List > http://www.q-v-d.demon.co.uk/smsqe.htm _______________________________________________ QL-Users Mailing List http://www.q-v-d.demon.co.uk/smsqe.htm
