Hal Murray wrote:
In article <[email protected]>,
Brian Inglis <[email protected]> writes:
Something like a Thunderbolt GPSDO feeding data, PPS, and 10MHz clock to a
chip executing instructions at some clock multiple and handling interrupts
in a deterministic time to feed the PTP GM?
Why use interrupts? Suppose you put a clock and ethernet in a FPGA.
How much extra logic does it take to process NTP packets? Everything
but the simple case gets punted off to a real CPU.
Having PTP hw support in the network card would seem to be sufficient:
Incoming packets are timestamped by the network card, so when the host
OS retrieves them, both the packet timestamp and the current PTP time
can be queried, giving an exact offset from the current OS time.
I.e. this gives you sub-us OS-level timestamping of incoming packets.
If you then also have the capability to query the network card/os queues
and only pass off outgoing packets when the transmit buffer is empty,
you should be able to calculate and enter into the response packet an
outgoing timestamp which is very accurate.
If you want even better performance you'll have to move to full PTP,
including hw support in all intermediate switches/routers.
Terje
--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"
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