On Thu, Oct 31, 2013 at 10:24 AM, Sebastian Huber <sebastian.hu...@embedded-brains.de> wrote: > On 2013-10-31 15:18, Daniel Hellstrom wrote: >> >> Bool is char, a 4 CPU 8-bit variable array will crate a race, where CPU1 >> might >> over write CPU2 and CPU3 task execution status. There is no atomic locking >> of >> the TaskRan array. > > > In case they write to different memory locations, there is no data race > under the C11 memory model. > Yes this is what I thought too. I assume the LEON uses an 8-bit store (stb) for the variables. Maybe the problem comes from the cache? If the cache line size is 32 bits then conflicting 8-bit stores to the same cache line could cause a problem.
> > -- > Sebastian Huber, embedded brains GmbH > > Address : Dornierstr. 4, D-82178 Puchheim, Germany > Phone : +49 89 189 47 41-16 > Fax : +49 89 189 47 41-09 > E-Mail : sebastian.hu...@embedded-brains.de > PGP : Public key available on request. > > Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. > _______________________________________________ > rtems-devel mailing list > rtems-devel@rtems.org > http://www.rtems.org/mailman/listinfo/rtems-devel _______________________________________________ rtems-devel mailing list rtems-devel@rtems.org http://www.rtems.org/mailman/listinfo/rtems-devel
