On 2013-10-31 15:37, Gedare Bloom wrote:
On Thu, Oct 31, 2013 at 10:24 AM, Sebastian Huber
<sebastian.hu...@embedded-brains.de> wrote:
>On 2013-10-31 15:18, Daniel Hellstrom wrote:
>>
>>Bool is char, a 4 CPU 8-bit variable array will crate a race, where CPU1
>>might
>>over write CPU2 and CPU3 task execution status. There is no atomic locking
>>of
>>the TaskRan array.
>
>
>In case they write to different memory locations, there is no data race
>under the C11 memory model.
For reference "5.1.2.4 Multi-threaded executions and data races" paragraph 2.
>
Yes this is what I thought too. I assume the LEON uses an 8-bit store
(stb) for the variables. Maybe the problem comes from the cache? If
the cache line size is 32 bits then conflicting 8-bit stores to the
same cache line could cause a problem.
In this case the cache coherency protocol is broken.
--
Sebastian Huber, embedded brains GmbH
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