Hello, Is this needed for CPU0 also? Otherwise I think it would be enough to invalidate the caches when the other cache parameters to save one instruction, they are modified in leon3_secondary_cpu_initialize():
- sparc_leon3_set_cctrl( 0x80000F ); + sparc_leon3_set_cctrl( 0xE0000F ); Regards, Daniel On 02/18/2014 12:53 PM, Sebastian Huber wrote:
--- c/src/lib/libbsp/sparc/shared/start/start.S | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/sparc/shared/start/start.S b/c/src/lib/libbsp/sparc/shared/start/start.S index df17a9b..d0eb512 100644 --- a/c/src/lib/libbsp/sparc/shared/start/start.S +++ b/c/src/lib/libbsp/sparc/shared/start/start.S @@ -223,6 +223,8 @@ SYM(hard_reset): nop#if defined(START_LEON3_ENABLE_SMP)+ flush ! invalidate L1 caches of this CPU + rd %asr17, %o0 ! get CPU identifier srl %o0, LEON3_ASR17_PROCESSOR_INDEX_SHIFT, %o0
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