On 2014-02-18 15:10, Daniel Hellstrom wrote:
On 02/18/2014 02:58 PM, Sebastian Huber wrote:
On 2014-02-18 14:49, Daniel Hellstrom wrote:
Is this needed for CPU0 also?
I don't know. In which state are the caches after a power-on-reset?
It is the boot loaders job to initialize hardware and to load RTEMS into RAM
before jumping into it. Since single-core version seems to be working as it is
I see no reason why the behaviour have changed with SMP. The bootloader
initializes also the secondary CPUs and RTEMS is waiting in a loop for the
secondary CPU (not modifying anything) to wake up, so I guess it shouldn't be
needed there either.
If I understand this correctly, then the bootloader will place the secondary
processors into the halt state and
uint32_t _CPU_SMP_Initialize( uint32_t configured_cpu_count )
{
[...]
for ( cpu = 1 ; cpu < used_cpu_count ; ++cpu ) {
#if defined(RTEMS_DEBUG)
printk( "Waking CPU %d\n", cpu );
#endif
LEON3_IrqCtrl_Regs->mpstat = 1 << cpu;
}
[...]
}
will request them to resume execution at the reset vector?
Is it guaranteed that in the L1 caches of such a secondary processor all valid
cache lines (if they exist) reflect the state observable by the main processor?
In other words, is it guaranteed that a secondary processor will read the
value last written by other processors?
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
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