That may depend on the hardware and PCI bridge configuration,
but from experience with our ISA CAN boards I would expect the
time to be in the range of 1-3us. We achieve complete cycles
with synchronisation to the processor on the board and more
than one ISA access in about 20us.
Best regards,
Thomas Wuensche
Victor Yodaiken wrote:
>
> On Wed, Jul 07, 1999 at 04:16:44PM +0000, Paolo Mantegazza wrote:
> > Victor Yodaiken wrote:
> >
> > > the disadvantage of one-shot on uniprocessor x86 machines is that
> > > reprogramming the clock takes 10 microseconds or so.
> >
> > That is not true, provided you do not want to use 486s, but is due to
> > the type of implementation of the concept adopted in RTL. In fact I can
> > prove that with a different implementation, e.g our older variant for
> > RTL based on 2.0.xx and RTAI for 2.2.xx, it can go down to 2-3 us on ony
> > PENTIUM and compatible. In that case you can use the CPU clock and have
> > just to do two "outb-s" to reprogram the 8254 timer chip counter for the
>
> You can prove whatever you want, but I have timed a single outb to the isa
> interface at 12microseconds on a PII LX chipset.
>
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