On Fri, Jul 09, 1999 at 07:23:01PM +0000, Paolo Mantegazza wrote:
> What I want to say and prove is that if you:
>
> just set the 8254 in oneshot mode once for all,
>
> use the tsc clock to do all the timing, instead of reading timer2 of the
> 8254 twice for scheduling, which is 6 in-outb operations,
>
> do just two outb to program the next shot;
>
> you gain 6 slow in out operations on the ISA bus, and a lot of
> performances.
OK. That's what is done in the V2 code anyways -- see rtl_time.c -- two outbs.
The problem, though, is typical ISA writes are on the order of a microsecond, but
there are atypical long operations, caused by ISA bus contention, I believe.
For example, if you put any IO device on the ISA bus, you get immediate problems
with dma operations locking the ISA bus for significant times. If you see a serious
time difference with V2 RTL, then something else is going on. I think that your
measurement, however, is not catching worst case times. If you run the test codes
in the new examples/regression directory, you may see some interesting results.
I'd be interested in hearing about any timings you might find.
Victor Yodaiken
USA.
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