On (05 Dec 94) [EMAIL PROTECTED] wrote... > QAA04381 for sam-users-outgoing; Mon, 5 Dec 1994 16:20:53 +0100 > by sabre-wulf.nvg.unit.no (8.6.9/8.6.9) with SMTP id QAA04375 for > <[email protected]>; Mon, 5 Dec 1994 16:20:46 +0100 > Date: Mon, 5 Dec 1994 16:20:06 +0100 > From: [EMAIL PROTECTED]
> Apologies for a rather technical message... > On Fri, 2 Dec 94 16:38:39 CET, Arne Di Russo said: > -----, + - ANALOG OUT > | 15k ,---------------------+-||-----, ,-------> > 9 |--#####--+--#####-,7.5k | 5.0F | | > | 15k ,--------' | ###<-' > 8 |--#####--+--#####-,7.5k === ### > | 15k ,--------' | 4700pF | 100K > 7 |--#####--+--#####-,7.5k | | > | 15k ,--------' _|_ _|_ > 6 |--#####--+--#####-,7.5k > | 15k ,--------' > 5 |--#####--+--#####-,7.5k > | 15k ,--------' > 4 |--#####--+--#####-,7.5k > | 15k ,--------' > 3 |--#####--+--#####-,7.5k > | 15k | > 2 |--#####---+-------' > | ### > | ###15k > 18 |----------|--------------------------------------> GND > -----' _|_ > This looked so strange that I had to try it out (mathematically, not > physically). We can rewrite the left-hand part of this diagram as > follows: > R1 R1 R1 R3 > out <---+--###--+--###--+--###--+--###--<-- GND > | | | | > # # # # > #R2 #R2 #R2 #R2 > | | | | > ^ ^ ^ ^ > bit 3 bit 2 bit 1 bit 0 > (I've only used 4 bits to make things slightly easier). In the diagram > above, we have R3=R2=15K and R1=7.5K. > In an extremely simplistic view of things that assumes no current flows and > takes this as a sequence of potential dividers, all the resistors have to > be equal in order for the output to be correct. > In order for the diagram to look more symmetric, R3 should equal R1 and > not R2. > Despite the above facts, the circuit does work. What I would like to know > is how. It seems to be magic. I think you may not be taking into acount that when a bit is NOT high it is LOW and therefore the resistor connected to it is effectivly connected to ground and acts as a potential divider to any lesser significant bits voltage derrived from it's portion of the divider chain. Because the biggest action of this circuit is as a compound potential divider ie it's the logic zero's in a higher significant position that make the lsb's so low. R3 is equal to an absolutely least-significant-bit set perminantly to zero so MUST be equal to 2R to be part of the R2R equation. I've not bothered to attempt to prove or disprove the logic of it as it works well enough to accept it, uptil now anyway;-) > According to Maple, the answer fills an 80x40 window twice. > The output voltage is equal to -R3*i[5]-R1*(i[6]+i[7]+i[8]). According to > Maple, the answer for that fills my 80x40 window. > And yet, if we put R1=1, R2=2 and R3=2, the output voltage turns out to > equal > 1/16 bit0 + 1/8 bit1 + 1/4 bit2 + 1/2 bit3 > which is the correct answer. But the value of I still looks completely > random. Can anyone give a rational explanation of why the figures just > happen to combine to give the right answer? Rationality! that's asking a bit much;-) Examining with just the lsb at 1 and the remaining 3 more significant bits set to 0... going from lsb to msb nodes the attenuation to 4dp is:- bit0 0.3354 bit1 0.5098 bit2 0.5455 bit3 0.6666 which in all is 0.06212 or 1/16.09 or probably exactly 1/16 if infinite presision maths is used. Obviously theres a lot more to it especially when multiple bits are 1's but I think it's better to look at those 1's as switching resistors out of the parallel resistors in the compond resistance in the lower section of the more significant potential divider and thus increasing the output potential dependant on how much they effect the value of that compound resistance. No way can I be bothered to model that particular idea with pen and paper! This is the sort of thing that human intelect can deduce to work from a couple of itterative tests but computers have to perform every possible logical configuration before it can be sure it'll work at all times;-) I think it's just an applied exception to murphies law<grin> I'm not 100% certain that the unloaded output voltages accuratly represent the binary value but they are a close enough approximation to get away with it:-) The R2R ladder is used in proper DAC chips so it must be quite accurate! None of my calculations of combined resistance took into account the voltage drop of the logic 0 output and assumed it to be an *ideal* logic output. ie. in a real R2R ladder the lowest voltage that can be represented would be at least 0.6V with all bits set to 0 due to the ttl output stage used as voltage source. Johnathan. ... DATA COMPRESSION..What You Get When You Squish An Android -- |Fidonet: Johnathan Taylor 2:2501/307.9 |Internet: [EMAIL PROTECTED] | | Standard disclaimer: The views of this user are strictly his own.
