> On (13 Feb 95) [EMAIL PROTECTED] wrote... > > eh, what's all that stuff for? /RAS remaines active during subsiquent /CAS > so a pair of inverters cascaded will provide more than enough delay. > Check out the Zx Spectrum's RAS&CAS handling although the schematic uses C63 & > C64 to produce a delay in /CAS signal ALL Zx iss 2&3 pcb's I've had NEVER had > them even fitted at all and relied solely on the OR gate used propogation > delay!
*grins* Okay... I'll look at it in more detail.. > s> Ah, but the /RFSH line is the problem -- it doesn't appear to refresh > s> often enough... > > get your calculator out, an active /RFSH pulse occours once during each > instruction-decode phase... all DRAMS I've seen allow a standard refreshing > cycle length so when twice as many addresses need to be refreshed they usually > allow twice as long.. > > a 256K x N DRAM may require 512 refresh address cycles within 8mS which is > easily done on any z80! 512 instructions in 8mS is only 64000 instructions > a second even with the ASIC slowing things as much as it can that speed should > be achievable with ease. The problem that I was thinking of is the frequency of WAIT states buggering it up -- and what if an external device uses BUSREQ too? > > s> On another note -- remember the paging "bug" you were talking about? It > s> may be something to do with the fact that the ASIC only samples IORQ for > s> its logic -- not M1 as well, so as Prodos uses IM2, the RETI sequence may > s> trigger spurious I/O (as when you do a RETI, IORQ and M1 both drop low). > > RETI differs from RET only by OP-code and duration for the benifit of true > Zilog peripheral chips interupt priorities. > /IORQ & M1 ocour during any maskable interupt acknowledge to request the > interupting device to place an IM2 vector or IM0 instruction onto the z80 > data-bus, looong before the end of service routine where the RETI may be > placed, nice try tho;) Yeah, but could it be the IORQ & M1 both going low at the start of the interrupt that causes the problems? Could the ASIC be receiving spurious IO read/writes? Simon
