> WRONG! Something else is wrong here.
> > On a sensible machine, a JP instruction does this. > > fetch+decode 4 cycles > fetch 3 cycles > fetch 3 cycles > --------- > 10 cycles With rounding this adds up to 12. Correct. > > The jump takes no time since (if the condition is true) the bytes are > loaded straight into the PC. > > A JR does this. > > fetch+decode 4 cycles > fetch 3 cycles > if true then jump 5 cycles > --------- > 12 cycles With rouding this adds up to 13. Or will the 3+5 be 'evened out' as it adds up to 8? > > The jump takes 5 cycles because the CPU has to add a signed 7-bit number to > an unsigned 16-bit number using an 8-bit ALU. These 5 cycles are not used > if the condition turns out to be false (aside: guess why LDIR takes 5 more > cycles when BC>0 than it does when BC=0...). > > Hence, on a sensible machine, JP is faster even though it takes one more > machine cycle. > > On a Sam, both instructions take 12 because each fetch is restricted by the > ASIC to take place at a multiple of 4 clock cycles. > > imc > -Frode -- Frode Tenneboe, ECP/PT, CERN, CH-1211 Geneva 23, Switzerland [EMAIL PROTECTED] http://www.himolde.no/~frodet
