Having checked, the full complement of z80 lines are on the expansion connector so it wouldn't be a problem to figure out when the z80 is accessing memory. That being said, if the ULA fetches aren't there then there would appear to be a problem.
Maybe a smarter plan would be something that plugs into the memory expansion port at the bottom? It's obviously completely feasible from a hardware point of view that you could fit a modified 256 kb expansion with some memory-mapped registers (as I can't find a pinout for that so I'm not sure if IOREQ is down there) so that, if enabled by pushing a suitably arcane initiation sequence (as per the precedent of the CPC+), you can subsequently specify a 16 or 18 bit memory offset that's added to the incoming address (overflow being lost if you go 16 bit, I guess) before that section of RAM is accessed. So you'd need to keep your program code in the internal 256 kb, and then you'd be able to use the other 256 kb for hardware scrollable screens. On 2 February 2012 12:47, Thomas Harte <[email protected]> wrote: >>> a) tell the difference between a normal address request and an ASIC request > > Is the z80's MREQ line available to peripherals? I forget whether > that's active during refresh cycles but it would probably give the > game away. Alternatively, the WAIT line probably gives something of > the game away.
