[PATCH] D48044: [Power9] Update fp128 as a valid homogenous aggregate base type

lei created this revision. lei added reviewers: hfinkel, kbarton, nemanjai, power-llvm-team. Update clang to treat fp128 as a valid base type for homogeneous aggregate passing and returning. https://reviews.llvm.org/D48044 Files: include/clang/AST/Type.h lib/CodeGen/TargetInfo.cpp test/C

[PATCH] D48044: [Power9] Update fp128 as a valid homogenous aggregate base type

lei updated this revision to Diff 150821. https://reviews.llvm.org/D48044 Files: include/clang/AST/Type.h lib/CodeGen/TargetInfo.cpp test/CodeGen/ppc64le-f128Aggregates.c Index: test/CodeGen/ppc64le-f128Aggregates.c === --- /d

[PATCH] D48044: [Power9] Update fp128 as a valid homogenous aggregate base type

This revision was automatically updated to reflect the committed changes. Closed by commit rL336308: [Power9] Update fp128 as a valid homogenous aggregate base type (authored by lei, committed by ). Herald added a subscriber: llvm-commits. Changed prior to commit: https://reviews.llvm.org/D4804

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

lei added inline comments. Comment at: clang/lib/Basic/Targets/PPC.cpp:339 if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) && llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) { NeHuang wrote: > I think we also need to check

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

lei updated this revision to Diff 266073. lei marked 7 inline comments as done. lei added a comment. address review comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80020/new/ https://reviews.llvm.org/D80020 Files: clang/lib/Basic/Targets/

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

lei updated this revision to Diff 266283. lei added a comment. update as per reviewers comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80020/new/ https://reviews.llvm.org/D80020 Files: clang/lib/Basic/Targets/PPC.cpp clang/lib/Basic/Tar

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

This revision was automatically updated to reflect the committed changes. Closed by commit rG7eb666b1556b: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm (authored by lei). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80020/new/ https

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

lei updated this revision to Diff 266321. lei added a comment. change how we generate p10 feature list. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80020/new/ https://reviews.llvm.org/D80020 Files: clang/lib/Basic/Targets/PPC.cpp clang/lib/B

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

lei updated this revision to Diff 266533. lei added a comment. rebased Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80020/new/ https://reviews.llvm.org/D80020 Files: clang/lib/Basic/Targets/PPC.cpp clang/lib/Basic/Targets/PPC.h Index: clang

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

lei updated this revision to Diff 266548. lei added a comment. fix up rebase issue after revert Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80020/new/ https://reviews.llvm.org/D80020 Files: clang/lib/Basic/Targets/PPC.cpp clang/lib/Basic/Tar

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

This revision was automatically updated to reflect the committed changes. Closed by commit rG2368bf52cd77: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm (authored by lei). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80020/new/ https

[PATCH] D80757: [PowerPC] Add clang option -m[no-]pcrel

lei created this revision. lei added reviewers: stefanp, nemanjai, hfinkel, power-llvm-team. Herald added subscribers: shchenz, wuzish. Herald added a project: clang. Add user-facing front end option to turn off pc-relative memops. This will be compatible with gcc. Repository: rG LLVM Github M

[PATCH] D80757: [PowerPC] Add clang option -m[no-]pcrel

lei marked an inline comment as done. lei added inline comments. Comment at: clang/test/Driver/ppc-pcrel.cpp:1 +// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mpcrel -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PCREL %s +// RUN: %clang -target powerpc64-

[PATCH] D80758: [PowerPC] Add -m[no-]power10-vector clang and llvm option

lei added inline comments. Comment at: clang/lib/Basic/Targets/PPC.cpp:414 +if (Name == "power9-vector") + Features["power10-vector"] = false; Features[Name] = false; I think it would be good to change this into a switch-stmt as there are enough co

[PATCH] D80757: [PowerPC] Add clang option -m[no-]pcrel

This revision was automatically updated to reflect the committed changes. Closed by commit rG7cfded350a7e: [PowerPC] Add clang option -m[no-]pcrel (authored by lei). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80757/new/ https://reviews.llvm.org/D

[PATCH] D80758: [PowerPC] Add -m[no-]power10-vector clang and llvm option

lei accepted this revision. lei added a comment. LGTM. Minor nit can be addressed during commit. Comment at: clang/lib/Basic/Targets/PPC.cpp:413 + Features["power9-vector"] = Features["power10-vector"] = false; +if (Name == "power9-vector") + Features["power10-ve

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

lei accepted this revision. lei added a comment. This revision is now accepted and ready to land. LGTM, Please add tests for BE in llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll prior to committing. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll:2 +; NOTE: Asse

[PATCH] D84197: [PowerPC][Power10] 128-bit Vector String Isolate instruction definitions and MC Tests

lei added a comment. Why are you removing MC tests for here? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84197/new/ https://reviews.llvm.org/D84197 ___ cfe-commits mailing list cfe-commits@lists.llv

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14166 + + SDValue LoadOps[] = {LD->getChain(), LD->getBasePtr(), DAG.getIntPtrConstant(MemoryType.getScalarSizeInBits(), dl)}; + nit: indentation. Comment at:

[PATCH] D84382: [PowerPC][Power10] Cleanup p10vector clang test

lei accepted this revision. lei added a comment. This revision is now accepted and ready to land. LGTM thx! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84382/new/ https://reviews.llvm.org/D84382 ___

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14156 + + // This transformation is only valid if the we are loading either a byte, + // halfword, word, or doubleword. Conanap wrote: > NeHuang wrote: > > nit: if we are loading

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

lei added a comment. Please address the auto generated clang-format issues for the added code in this patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83338/new/ https://reviews.llvm.org/D83338 __

[PATCH] D83722: [PowerPC] Add options to control paired vector memops support

This revision was automatically updated to reflect the committed changes. Closed by commit rG7aaa85627b59: [PowerPC] Add options to control paired vector memops support (authored by bsaleil, committed by lei). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm

[PATCH] D80970: [PowerPC][Power10] Implement centrifuge, vector gather every nth bit, vector evaluate Builtins in LLVM/Clang

lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80970/new/ https://reviews.llvm.org/D80970 _

[PATCH] D81774: [PowerPC][Power10] Implement VSX PCV Generate Operations in LLVM/Clang

lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81774/new/ https://reviews.llvm.org/D81774 _

[PATCH] D80935: [PowerPC][Power10] Implement Parallel Bits Deposit/Extract Builtins in LLVM/Clang

lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM, just 1 minor comment/question. Comment at: llvm/lib/Target/PowerPC/PPCScheduleP9.td:47 + let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PCRelativeMemops, +

[PATCH] D81707: [PowerPC][Power10] Implement Vector Clear Left/Rightmost Bytes Builtins in LLVM/Clang

lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM Minor nit to be addressed during commit. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:522 + [(set v16i8:$vD, +

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

lei requested changes to this revision. lei added inline comments. This revision now requires changes to proceed. Comment at: clang/lib/Sema/DeclSpec.cpp:1155 + // TODO: Update comment with correct Programming Interface Manual + // version once it is available. __int128

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

lei added inline comments. Comment at: clang/test/Parser/altivec-bool-128.c:2 +// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-feature +altivec -fsyntax-on

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

lei added inline comments. Comment at: clang/lib/Sema/DeclSpec.cpp:1155 + // TODO: Update comment with correct Programming Interface Manual + // version once it is available. __int128 has also been added + // to vector bool for Power10. saghir wrot

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

lei added inline comments. Comment at: clang/lib/Sema/DeclSpec.cpp:1170 // Only 'short' and 'long long' are valid with vector bool. (PIM 2.1) if ((TypeSpecWidth != TSW_unspecified) && (TypeSpecWidth != TSW_short) && Do we not need to add a check f

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

lei added inline comments. Comment at: clang/test/Parser/p10-vector-bool-128.c:2 +// RUN: %clang_cc1 -triple=powerpc64-unknown-linux-gnu -target-feature +altivec -target-feature +vsx -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-featu

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

lei added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:108 + signed char *__c) { + // CHECK-BE: store i8 %{{.+}}, i8* %{{.+}}, align 1 + // CHECK-LE: store i8 %{{.+}}, i8* %{{.+}}, align 1 amyk wrote: > lei

[PATCH] D82440: [Power10] Implement Vector Shift Double Bit Immediate Builtins in LLVM/Clang

This revision was automatically updated to reflect the committed changes. Closed by commit rG88874f074644: [PowerPC]Implement Vector Shift Double Bit Immediate Builtins (authored by biplmish, committed by lei). Herald added a project: clang. Herald added a subscriber: cfe-commits. Repository: r

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:487 +/// Allows utilization of the Load VSX Vector Rightmost Instructions. +LXVRZX + missing `,`? Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:220

[PATCH] D82869: [Power10] Implement Vector Permute Extended Builtins in LLVM/Clang

This revision was automatically updated to reflect the committed changes. Closed by commit rG286073484f7d: [PowerPC]Implement Vector Permute Extended Builtin (authored by biplmish, committed by lei). Herald added a project: clang. Herald added a subscriber: cfe-commits. Changed prior to commit:

[PATCH] D82774: [Power10] Implement Vector Blend Builtins in LLVM/Clang

This revision was automatically updated to reflect the committed changes. Closed by commit rGca464639a1c9: [PowerPC] Implement Vector Blend Builtins in LLVM/Clang (authored by biplmish, committed by lei). Herald added a project: clang. Herald added a subscriber: cfe-commits. Changed prior to comm

[PATCH] D82365: [Power10] Implement Vector Insert Builtins in LLVM/Clang

This revision was automatically updated to reflect the committed changes. Closed by commit rG0939e04e4176: [PowerPC] Implement Vector Insert Builtins in LLVM/Clang (authored by biplmish, committed by lei). Herald added a project: clang. Herald added a subscriber: cfe-commits. Repository: rG LLV

[PATCH] D82365: [Power10] Implement Vector Insert Builtins in LLVM/Clang

lei added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:12 +// RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \ +// RUN: -o - | FileCheck %s -check-prefix=CHECK-LE + I just noticed this. There is no need t

[PATCH] D82365: [Power10] Implement Vector Insert Builtins in LLVM/Clang

lei added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:12 +// RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \ +// RUN: -o - | FileCheck %s -check-prefix=CHECK-LE + biplmish wrote: > lei wrote: > > I just

[PATCH] D82520: [Power10] Implement Vector Splat Immediate Builtins in LLVM/Clang

This revision was automatically updated to reflect the committed changes. Closed by commit rG0c6b6e28e70c: [PowerPC] Implement Vector Splat Immediate Builtins in Clang (authored by biplmish, committed by lei). Herald added a project: clang. Herald added a subscriber: cfe-commits. Changed prior to

[PATCH] D82520: [Power10] Implement Vector Splat Immediate Builtins in LLVM/Clang

This revision was not accepted when it landed; it landed in state "Needs Revision". This revision was automatically updated to reflect the committed changes. Closed by commit rG0c6b6e28e70c: [PowerPC] Implement Vector Splat Immediate Builtins in Clang (authored by biplmish, committed by lei). Her

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13791 + // Ensure that the load from the narrow width is being zero extended to i128. + if ((!ValidLDType) || (LD->getValueType(0) != MVT::i128) || + (LD->getExtensionType() != ISD::ZEXTLOAD

[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:431 +let mayLoad = 1, mayStore = 0, Predicates = [IsISA3_1] in { + // The XFormMemOp flag is set on the instruction format. Instead of creating a new section like this, why not ad

[PATCH] D82609: [PowerPC][Power10] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

lei added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:79 +vector signed int test_vec_dive_si(void) { + // CHECK: @llvm.ppc.altivec.vdivesw(<4 x i32> + // CHECK-NEXT: ret <4 x i32> why does the ck stops matching at the first param?

[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

lei accepted this revision. lei added a comment. LGTM thx. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83364/new/ https://reviews.llvm.org/D83364 ___ cfe-commits mailing list cfe-commits@lists.llvm.o

[PATCH] D83500: [PowerPC][Power10] Implement custom codegen for the vec_replace_elt and vec_replace_unaligned builtins.

lei added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:14273 +// The third argument to vec_replace_elt will be emitted to either +// the vinsw or vinsd instruction. It must be a compile time constant. +ConstantInt *ArgCI = dyn_cast(Ops[2]); ---

[PATCH] D83516: [PowerPC][Power10] 128-bit Binary Integer Operation instruction definitions and MC Tests

lei accepted this revision. lei added a comment. This revision is now accepted and ready to land. LGTM Please address the nits on commit. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:1022 + def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>; + def XSCVSQQP: X_V

[PATCH] D81816: [PowerPC] Add support for vector bool __int128 for Power10

lei accepted this revision as: lei. lei added a comment. LGTM, please address the 1 comment I have on commit. Comment at: clang/test/Parser/altivec-bool-128.c:6 +// RUN: %clang_cc1 -triple=powerpc64le-unknown-linux-gnu -target-cpu pwr10 \ +// RUN:-target-feature +al

[PATCH] D81836: [PowerPC][Power10] Implement Vector Permute Builtins in LLVM/Clang

lei added a comment. This is PR still valid? I see dup def in https://reviews.llvm.org/D82365. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81836/new/ https://reviews.llvm.org/D81836 ___ cfe-commits

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82431/new/ https://reviews.llvm.org/D82431 ___ cfe-commits mailing list cfe-commits

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

lei added a comment. encoding tests need to be placed in corresponding `ppc64-encoding-ISA31*` files Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82431/new/ https://reviews.llvm.org/D82431 ___ cfe-com

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

lei added a comment. Please move encoding tests to `ppc64-encoding-ISA31.[txt|s]`. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13792 + if ((LD->getValueType(0) != MVT::i128) || + (LD->getExtensionType() != ISD::ZEXTLOAD) || (!ValidLDType)) +return SDValue(

[PATCH] D82467: [PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

lei requested changes to this revision. lei added a comment. This revision now requires changes to proceed. Please move encoding tests to ppc64-encoding-ISA31.[txt|s]. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:108 + signed char *__c) { +

[PATCH] D82431: [PowerPC][Power10] Implement Test LSB by Byte Builtins in LLVM/Clang

lei accepted this revision. lei added a comment. LGTM thx! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82431/new/ https://reviews.llvm.org/D82431 ___ cfe-commits mailing list cfe-commits@lists.llvm.o

[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()

lei created this revision. lei added reviewers: nemanjai, stefanp. Herald added subscribers: shchenz, kbarton. Herald added a project: clang. This function keeps growing, refactor to use lambda. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D78308 Files: clang/lib/Basic/Targ

[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()

lei updated this revision to Diff 258119. lei added a comment. Fix mistake in code Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78308/new/ https://reviews.llvm.org/D78308 Files: clang/lib/Basic/Targets/PPC.cpp Index: clang/lib/Basic/Targets/P

[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()

lei updated this revision to Diff 258121. lei added a comment. update Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78308/new/ https://reviews.llvm.org/D78308 Files: clang/lib/Basic/Targets/PPC.cpp Index: clang/lib/Basic/Targets/PPC.cpp ==

[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()

lei updated this revision to Diff 258175. lei added a comment. updated. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78308/new/ https://reviews.llvm.org/D78308 Files: clang/lib/Basic/Targets/PPC.cpp Index: clang/lib/Basic/Targets/PPC.cpp

[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()

lei marked an inline comment as done. lei added inline comments. Comment at: clang/lib/Basic/Targets/PPC.cpp:243 + bool Passed = CheckVSXSubfeature("+power8-vector", "-mpower8-vector"); + Passed |= CheckVSXSubfeature("+direct-move", "-mdirect-move"); + Passed |= CheckVSXSubfea

[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()

lei updated this revision to Diff 258375. lei added a comment. Address review comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78308/new/ https://reviews.llvm.org/D78308 Files: clang/lib/Basic/Targets/PPC.cpp clang/test/Driver/ppc-depend

[PATCH] D78308: [NFC][PowerPC] Refactor ppcUserFeaturesCheck()

This revision was automatically updated to reflect the committed changes. lei marked an inline comment as done. Closed by commit rG10b60dde7670: [PowerPC] Refactor ppcUserFeaturesCheck() (authored by lei). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org

[PATCH] D77542: [PowerPC] Treat 'Z' inline asm constraint as a true memory constraint

lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77542/new/ https://reviews.llvm.org/D77542 _

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in the front end

lei created this revision. lei added reviewers: stefanp, nemanjai, amyk, hfinkel, power-llvm-team. Herald added subscribers: shchenz, wuzish. Herald added a project: clang. jsji added a reviewer: PowerPC. jsji added a project: PowerPC. This patch simply adds support for the new CPU in anticipation

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

lei updated this revision to Diff 264301. lei added a comment. Herald added subscribers: llvm-commits, hiraditya. Herald added a project: LLVM. Add support in llvm. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80020/new/ https://reviews.llvm.org/D

[PATCH] D80020: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

lei updated this revision to Diff 264303. lei retitled this revision from " [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm" to "[PowerPC] Add support for -mcpu=pwr10 in both clang and llvm". lei added a comment. missed a file Repository: rG LLVM Github Monorepo CHANGES SINCE L

[PATCH] D128288: [PowerPC] Fix signatures for vec_replace_unaligned builtin

This revision was automatically updated to reflect the committed changes. Closed by commit rGcaf7243a6b53: [PowerPC] Fix signatures for vec_replace_unaligned builtin (authored by lei). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D128288/new/ https:

[PATCH] D129016: [PowerPC] implemented @llvm.ppc.kill.canary to corrupt stack guard

lei added inline comments. Comment at: llvm/test/CodeGen/PowerPC/kill-canary-intrinsic.ll:4 +; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=AIX +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux \ +; RUN: --ppc-asm-full-reg-names < %s | File

[PATCH] D131622: [NFC][PowerPC] Add missing NOCOMPAT checks for builtins-ppc-xlcompat.c

lei created this revision. lei added reviewers: nemanjai, amyk, power-llvm-team. Herald added a subscriber: shchenz. Herald added a project: All. lei requested review of this revision. Herald added a project: clang. Followup patch to address request from https://reviews.llvm.org/D124093 Reposito

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

lei added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1569 + def int_ppc_sthcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrWriteMem]>; + def int_ppc_lharx : GCCBuiltin<"__builtin_ppc_lharx">, + Intrinsic<[llvm_i32

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

lei added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3371 +return SemaFeatureCheck(*this, TheCall, "extdiv", +diag::err_ppc_builtin_only_on_arch, "8"); #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \ need tests

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

lei updated this revision to Diff 359050. lei marked 3 inline comments as done. lei added a comment. Address review comments to add/upate: - builtin encoding for params that need to be folded into constant expr - llvm intrinsic property for immediates - test line for `-mattr=-vsx` Repository:

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:3650 +// XL Compat intrinsics. +def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>; +def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>; nemanja

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

lei updated this revision to Diff 359070. lei added a comment. rebase to ToT Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105930/new/ https://reviews.llvm.org/D105930 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Basic/Targets/PP

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

lei added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1569 } - nit: un-related line deletion Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:5449 + def : Pat<(int_ppc_sthcx xoaddr:$dst, gprc:$A), + (STH

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:3087 // RM should be set. +let hasSideEffects = 1 in { def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), nemanjai wrote: > nemanjai wrote: > > I think we should conservatively s

[PATCH] D105930: [PowerPC] Implement XL compact math builtins

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc8937b6cb975: [PowerPC] Implement XL compact math builtins (authored by lei). Changed prior to commit: https://reviews.llvm.org/D105930?vs=359070&

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

lei added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:15 + // CHECK-LABEL: @test_lwarx // CHECK: %0 = tail call i32 asm sideeffect "lwarx $0, ${1:y}", "=r,*Z,~{memory}"(i32* %a) return __lwarx(a); where is

[PATCH] D105957: [PowerPC] Implement intrinsics for mtfsf[i]

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG35a18a981f6b: [PowerPC] Implement intrinsics for mtfsf[i] (authored by nemanjai, committed by lei). Changed prior to commit: https://reviews.llvm.

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

lei added inline comments. Comment at: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll:3 +; NOTE: Had to manually modify the last test case (mtmsr) to allow the +; NOTE: common check of mtmsr instead of 4 different check prefixes ; RUN: llc -verify-machineinstrs -mtr

[PATCH] D103986: [PowerPC] Floating Point Builtins for XL Compat.

lei added a comment. please rebase to ToT Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103986/new/ https://reviews.llvm.org/D103986 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.

[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

lei added inline comments. Comment at: clang/include/clang/Basic/BuiltinsPPC.def:116 BUILTIN(__builtin_ppc_fres, "ff", "") +BUILTIN(__builtin_ppc_stbcx, "icD*i", "") maybe move this up to where `__builtin_ppc_stdcx` is defined. To match what you did in `PPC.

[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

lei added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15133 +bool IsLE = getTarget().isLittleEndian(); +auto StoreSubVec = [&](unsigned Width, unsigned Offset, unsigned EltNo) { + switch (Width) { I find the nested switch to be a bit

[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

lei accepted this revision. lei added a comment. thx for the update! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106757/new/ https://reviews.llvm.org/D106757 ___ cfe-commits mailing list cfe-commits@li

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

lei created this revision. lei added reviewers: stefanp, nemanjai, NeHuang, power-llvm-team. Herald added subscribers: shchenz, hiraditya. lei requested review of this revision. Herald added projects: clang, LLVM. Add builtin and intrinsic for `__addex`. This patch is part of a series of patches

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

lei updated this revision to Diff 362535. lei added a comment. fix minor wording and spelling mistakes. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107002/new/ https://reviews.llvm.org/D107002 Files: clang/include/clang/Basic/BuiltinsPPC.def

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

lei updated this revision to Diff 362536. lei added a comment. remove extra space Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107002/new/ https://reviews.llvm.org/D107002 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/include/clang/B

[PATCH] D107002: [PowerPC] Implement XL compatibility builtin __addex

lei updated this revision to Diff 362734. lei added a comment. put back unintentional space change Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107002/new/ https://reviews.llvm.org/D107002 Files: clang/include/clang/Basic/BuiltinsPPC.def clan

[PATCH] D125506: [PowerPC] Implement XL compat __fnabs and __fnabss builtins.

lei accepted this revision. lei added a comment. This revision is now accepted and ready to land. LGTM with minor updates before commit. Comment at: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.c:25 +// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix \

[PATCH] D125506: [PowerPC] Implement XL compat __fnabs and __fnabss builtins.

lei added inline comments. Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fnabs.ll:46 +; RUN: -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX + +declare double @llvm.ppc.fnabs(double) nit: same as before no need to test all combination f

[PATCH] D84968: [PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types

lei accepted this revision. lei added a comment. This revision is now accepted and ready to land. Just some minor comments. Please address them prior to commit. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:10519 + // 2 or 4 vsx registers. + if (VT == MVT::v256i1 ||

[PATCH] D87804: [PowerPC][Power10] Implement Vector signed/unsigned __int128 overloads for the comparison builtins

lei added a comment. please fix the clang format issues. Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:365 + def int_ppc_altivec_vcmpequq : GCCBuiltin<"__builtin_altivec_vcmpequq">, + Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty, llvm_v1i128_ty], +

[PATCH] D82609: [PowerPC] Implement Vector Multiply High/Divide Extended Builtins in LLVM/Clang

lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM Thx! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82609/new/ https://reviews.llvm.org/D82609 __

[PATCH] D90799: [PowerPC] Add paired vector load and store builtins and intrinsics

lei added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:2658 + return false; +} + There's alot of nested `if`s, would it be possible to refactor to have some early exits instead? Comment at: llvm/test/CodeGen/Power

[PATCH] D102191: [PowerPC] Add clang option -m[no-]prefixed

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG9469ff15b779: [PowerPC] Add clang option -m[no-]prefixed (authored by lei). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https

[PATCH] D95634: [PowerPC][Power10] Fix XXSPLI32DX not correctly exploiting specific cases

lei accepted this revision. lei added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95634/new/ https://reviews.llvm.org/D95634 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http

[PATCH] D109652: [PowerPC] Restrict various P10 options to P10 only.

lei added inline comments. Comment at: clang/lib/Basic/Targets/PPC.cpp:566-569 + if (llvm::find(FeaturesVec, "+pcrel") != FeaturesVec.end()) { +Diags.Report(diag::err_opt_not_valid_without_opt) << "-mpcrel" + <

[PATCH] D109996: [PowerPC] Fix signature of lxvp and stxvp builtins

lei accepted this revision as: lei. lei added a comment. LTGM Thx! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109996/new/ https://reviews.llvm.org/D109996 ___ cfe-commits mailing list cfe-commits@list

[PATCH] D109780: [PowerPC] Add range check for vec_genpcvm builtins

lei accepted this revision. lei added a comment. LGTM. Thx! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D109780/new/ https://reviews.llvm.org/D109780 ___ cfe-commits mailing list cfe-commits@lists.llvm.

[PATCH] D108823: [PowerPC] Mark splat immediate instructions as rematerializable

lei accepted this revision as: lei. lei added a comment. This revision is now accepted and ready to land. LGTM Thx. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D108823/new/ https://reviews.llvm.org/D108823

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