Please ignore the typo in my previous email and use this tag instead.
Acked-by: Rajneesh Bhardwaj
On Wed, Apr 7, 2021 at 11:48 AM Rajneesh Bhardwaj
wrote:
>
> Acked-by: Rajneesh Bhardwaj
>
> On Wed, Mar 31, 2021 at 11:06 PM David E. Box
> wrote:
> >
> > From: Ga
Acked-by: Rajenesh Bhardwaj
On Wed, Mar 31, 2021 at 11:06 PM David E. Box
wrote:
>
> Alder PCH-P is based on Tiger Lake PCH.
>
> Signed-off-by: David E. Box
> ---
> drivers/platform/x86/intel_pmc_core.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/platform/x86/intel_pmc_cor
Acked-by: Rajneesh Bhardwaj
On Wed, Mar 31, 2021 at 11:06 PM David E. Box
wrote:
>
> From: Gayatri Kammela
>
> Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information
> and supports a few additional registers. Hence add the LTR registers
> specif
On Wed, Mar 31, 2021 at 11:06 PM David E. Box
wrote:
>
> From: Gayatri Kammela
>
> Add the debugfs file, substate_requirements, to view the low power mode
> (LPM) requirements for each enabled mode alongside the last latched status
> of the condition.
>
> After this patch, the new file will look
On Wed, Mar 31, 2021 at 11:06 PM David E. Box
wrote:
>
> From: Gayatri Kammela
>
> Platforms that support low power modes (LPM) such as Tiger Lake maintain
> requirements for each sub-state that a readable in the PMC. However, unlike
> LPM status registers, requirement registers are not memory ma
Reviewed-by: Rajneesh Bhardwaj
On Wed, Mar 31, 2021 at 11:06 PM David E. Box
wrote:
>
> From: Gayatri Kammela
>
> Modify the low power mode (LPM or sub-state) residency counters to display
> in microseconds just like the slp_s0_residency counter. The granularity of
&
A minor suggestion, num_modes should be called num_lpm_modes since
it's a pmcdev's property.
Acked-by: Rajneesh Bhardwaj
On Wed, Mar 31, 2021 at 11:06 PM David E. Box
wrote:
>
> From: Gayatri Kammela
>
> The current implementation of pmc_core_substate_res_show() is writ
Reviewed-by: Rajneesh Bhardwaj
On Wed, Mar 31, 2021 at 11:06 PM David E. Box
wrote:
>
> The intel_pmc_core driver did not always bind to a device which meant it
> lacked a struct device that could be used to maintain driver data. So a
> global instance of struct pmc_dev was u
Reviewed-by: Rajneesh Bhardwaj
On Wed, Mar 31, 2021 at 11:06 PM David E. Box
wrote:
>
> The DMI callbacks, used for quirks, currently access the PMC by getting
> the address a global pmc_dev struct. Instead, have the callbacks set a
> global quirk specific variable. In probe, a
On Mon, Mar 8, 2021 at 12:20 PM Limonciello, Mario
wrote:
>
> >
> > [EXTERNAL EMAIL]
> >
> > Due to a HW limitation, the Latency Tolerance Reporting (LTR) value
> > programmed in the Tiger Lake GBE controller is not large enough to allow
> > the platform to enter Package C10, which in turn prevent
On Mon, Mar 8, 2021 at 9:04 AM Rajneesh Bhardwaj
wrote:
>
> Hi David
>
> Overall, it looks like the right thing to do but i have a few
> comments. See below.
>
> On Fri, Mar 5, 2021 at 2:07 PM David E. Box
> wrote:
> >
> > Due to a HW limitation, the Lat
Hi David
Overall, it looks like the right thing to do but i have a few
comments. See below.
On Fri, Mar 5, 2021 at 2:07 PM David E. Box wrote:
>
> Due to a HW limitation, the Latency Tolerance Reporting (LTR) value
> programmed in the Tiger Lake GBE controller is not large enough to allow
> the
eave a space in IP
names such as "Tiger Lake", "Rocket Lake" like it's done in previous
patches too. I am not sure whether it's a new convention but it's good
to be consistent throughout the series.
Other than that, the series is:
Reviewed-by: Rajneesh Bh
Commit-ID: 5f4318c1b1d23a9290e4def78ee76017c288bf60
Gitweb: https://git.kernel.org/tip/5f4318c1b1d23a9290e4def78ee76017c288bf60
Author: Rajneesh Bhardwaj
AuthorDate: Fri, 14 Jun 2019 13:47:01 +0530
Committer: Thomas Gleixner
CommitDate: Fri, 14 Jun 2019 11:30:47 +0200
perf/x86: Add
Commit-ID: e32d045cd4ba06b59878323e434bad010e78e658
Gitweb: https://git.kernel.org/tip/e32d045cd4ba06b59878323e434bad010e78e658
Author: Rajneesh Bhardwaj
AuthorDate: Thu, 6 Jun 2019 06:54:19 +0530
Committer: Thomas Gleixner
CommitDate: Thu, 13 Jun 2019 19:37:42 +0200
x86/cpu: Add Ice
a
Cc: Len Brown
Cc: Thomas Gleixner
Cc: x86-ml
Cc: Linux PM
Fixes: e39875d15ad6 ("perf/x86: add Intel Icelake uncore support")
Link: https://lkml.org/lkml/2019/6/5/1034
Signed-off-by: Rajneesh Bhardwaj
---
arch/x86/events/intel/uncore.c | 1 +
1 file changed, 1 insertion(+)
diff --g
Ice Lake Neural Network Processor for deep learning inference a.k.a.
ICL-NNPI can re-use Ice Lake Mobile regmap to enable Intel PMC Core
driver on it.
Cc: Darren Hart
Cc: Andy Shevchenko
Cc: platform-driver-...@vger.kernel.org
Link: https://lkml.org/lkml/2019/6/5/1034
Signed-off-by: Rajneesh
Enables support for ICL-NNPI, which is a neural network processor for deep
learning inference. From RAPL point of view it is same as Ice Lake Mobile
processor.
Cc: "Rafael J. Wysocki"
Cc: linux...@vger.kernel.org
Link: https://lkml.org/lkml/2019/6/5/1034
Signed-off-by: Rajnees
Enables support for ICL-NNPI, neural network processor for deep learning
inference. From RAPL point of view it is same as Ice Lake Mobile
processor.
Cc: "Rafael J. Wysocki"
Cc: linux...@vger.kernel.org
Link: https://lkml.org/lkml/2019/6/5/1034
Signed-off-by: Rajneesh Bhardwaj
--
This enables turbostat utility on Ice Lake NNPI SoC.
Cc: Len Brown
Cc: Linux PM
Link: https://lkml.org/lkml/2019/6/5/1034
Signed-off-by: Rajneesh Bhardwaj
---
tools/power/x86/turbostat/turbostat.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/power/x86/turbostat/turbostat.c
b
Commit-ID: 61caa8621b9979a78b04e353ab2ee44a47ef7a62
Gitweb: https://git.kernel.org/tip/61caa8621b9979a78b04e353ab2ee44a47ef7a62
Author: Rajneesh Bhardwaj
AuthorDate: Thu, 6 Jun 2019 06:54:19 +0530
Committer: Thomas Gleixner
CommitDate: Wed, 12 Jun 2019 11:43:42 +0200
x86/cpu: Add Ice
: Andy Shevchenko
Cc: "H. Peter Anvin"
Cc: Ingo Molnar
Cc: Kan Liang
Cc: Peter Zijlstra
Cc: platform-driver-...@vger.kernel.org
Cc: Qiuxu Zhuo
Cc: Srinivas Pandruvada
Cc: Len Brown
Cc: Thomas Gleixner
Cc: x86-ml
Cc: Linux PM
Signed-off-by: Rajneesh Bhardwaj
---
Changes in v2:
Shevchenko
Cc: "H. Peter Anvin"
Cc: Ingo Molnar
Cc: Kan Liang
Cc: Peter Zijlstra
Cc: platform-driver-...@vger.kernel.org
Cc: Qiuxu Zhuo
Cc: Srinivas Pandruvada
Cc: Len Brown
Cc: Thomas Gleixner
Cc: x86-ml
Cc: Linux PM
Signed-off-by: Rajneesh Bhardwaj
---
arch/x86/include
On Fri, Apr 05, 2019 at 01:35:58PM -0700, Rajat Jain wrote:
> Add code to instantiate the pmc_core platform device and thus attach to
> the driver, if the ACPI device for the same ("INT33A1") is not present
> in a system where it should be. This was discussed here:
> https://www.mail-archive.com/li
On Mon, Apr 01, 2019 at 11:05:04AM -0700, Evan Green wrote:
> The PMC driver performs a 32-bit read on the sleep s0 residency counter,
> followed by a hard-coded multiplication to convert into microseconds.
> The maximum value this counter could have would be 0x*0x64
> microseconds, which b
On Mon, Mar 18, 2019 at 08:18:56AM -0700, Rajat Jain wrote:
> On Mon, Mar 18, 2019 at 2:31 AM Somayaji, Vishwanath
> wrote:
> >
> >
> >
> > >-Original Message-
> > >From: Rajat Jain
> > >Sent: Thursday, March 14, 2019 3:51 AM
> > >To: Bhardwaj, Rajneesh ; Somayaji, Vishwanath
> > >; Darre
On Wed, Mar 13, 2019 at 03:21:24PM -0700, Rajat Jain wrote:
> Add a module parameter which when enabled, will check on resume, if the
> last S0ix attempt was successful. If not, the driver would provide
> helpful debug information (which gets latched during the failed suspend
> attempt) to debug th
On Wed, Mar 13, 2019 at 03:21:23PM -0700, Rajat Jain wrote:
> Convert the intel_pmc_core driver to a platform driver. There is no
> functional change. Some code that tries to determine what kind of
> CPU this is, has been moved code is moved from pmc_core_probe() to
Possible typo here.
> pmc_core
Commit-ID: 8cd8f0ce0d6aafe661cb3d6781c8b82bc696c04d
Gitweb: https://git.kernel.org/tip/8cd8f0ce0d6aafe661cb3d6781c8b82bc696c04d
Author: Rajneesh Bhardwaj
AuthorDate: Thu, 14 Feb 2019 17:27:08 +0530
Committer: Borislav Petkov
CommitDate: Thu, 14 Feb 2019 13:18:30 +0100
x86/CPU: Add
: Anshuman Gupta
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 59 +--
drivers/platform/x86/intel_pmc_core.h | 4 ++
2 files changed, 50 insertions(+), 13 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers/pl
/show_bug.cgi?id=201579
Tested-by: "David E. Box"
Reported-and-tested-by: russianneuromancer
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 34 +++
drivers/platform/x86/intel_pmc_core.h | 5
2 files changed, 39 insertions(+)
di
INTEL_CPU_FAM6() macro provides better abstraction and reduces code size
so use it instead of custom grown ICPU().
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/platform/x86
Gleixner
Cc: Dave Hansen
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Signed-off-by: Rajneesh Bhardwaj
---
arch/x86/include/asm/intel-family.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h
b/arch/x86/include/asm/intel-family.h
index 0d
x9ef4be15c5
Package C7 : 0x1e011904
Package C8 : 0x3c5653cfe5a
Package C9 : 0x0
Package C10 : 0x16fff4289
Cc: Arjan van de Ven
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Cc: Anshuman Gupta
Cc: Len Brown
Cc: Rafael J. Wysocki
Acked-and-tested-by: Anshuman Gu
D to intel-family.h
- Enables PMC driver for ICL
- Introduces a new "package cstate show" feature
- Fixes a customer issue related to S0ix on latest HP laptops
- Fixes some minor bugs
Rajneesh Bhardwaj (5):
x86/cpu: Add Icelake to Intel family
platform/x86: intel_pmc_core: Conve
: Anshuman Gupta
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 59 +--
drivers/platform/x86/intel_pmc_core.h | 4 ++
2 files changed, 50 insertions(+), 13 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers/pl
/show_bug.cgi?id=201579
Tested-by: "David E. Box"
Reported-and-tested-by: russianneuromancer
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 34 +++
drivers/platform/x86/intel_pmc_core.h | 5
2 files changed, 39 insertions(+)
di
INTEL_CPU_FAM6() macro provides better abstraction and reduces code size so use
it instead of custom grown ICPU().
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/platform/x86
SHA1 as reported by Stephen Rothwell]
Fixes: 2eb150558bb7 ("platform/x86: intel_pmc_core: Show Latency Tolerance
info")
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/platform/x
dex printing
for "ltr_show" is missing. For example, w/o this change, a user that wants
to ignore LTR from ME would do something like
echo 5 > ltr_ignore
but the index for ME is 6. Printing a reserved IP helps to properly
calculate LTR ignore offsets.
Cc: "David E. Box"
x9ef4be15c5
Package C7 : 0x1e011904
Package C8 : 0x3c5653cfe5a
Package C9 : 0x0
Package C10 : 0x16fff4289
Cc: Arjan van de Ven
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Cc: Anshuman Gupta
Cc: Len Brown
Cc: Rafael J. Wysocki
Acked-and-tested-by: Anshuman Gu
: x...@kernel.org
Cc: Peter Zijlstra
Cc: Thomas Gleixner
Cc: Dave Hansen
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Signed-off-by: Rajneesh Bhardwaj
---
arch/x86/include/asm/intel-family.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h
ectly read PCH IP power
gating status for Cannonlake and beyond.
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Fixes: c977b98bbef5 ("platform/x86: intel_pmc_core: Make the driver PCH family
agnostic")
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c
.
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Fixes: 661405bd817b ("platform/x86: intel_pmc_core: Special case for
Coffeelake")
Acked-by: "David E. Box"
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 2 +-
1 file changed, 1 insertion(+
upport")
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers/platform/x86/intel_pmc_core.c
index 9f143cdbea05..80936e6bdc61 100644
--- a/drivers/platform/
This series:
- Adds ICL U/Y CPUID to intel-family.h
- Enables PMC driver for ICL
- Introduces a new "package cstate show" feature
- Fixes a customer issue related to S0ix on latest HP laptops
- Fixes some minor bugs
Rajneesh Bhardwaj (10):
platform/x86: intel_pmc_core: Handle
.
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Fixes: 661405bd817b ("platform/x86: intel_pmc_core: Special case for
Coffeelake")
Acked-by: "David E. Box"
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 2 +-
1 file changed, 1 insertion(+
/show_bug.cgi?id=201579
Tested-by: "David E. Box"
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 34 +++
drivers/platform/x86/intel_pmc_core.h | 5
2 files changed, 39 insertions(+)
diff --git a/drivers/platform/x86/intel_pmc_core.c
tform/x86: intel_pmc_core: Show Latency Tolerance
info")
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers/platform/x86/intel_pmc_core.c
index 809
minor bugs
Rajneesh Bhardwaj (10):
platform/x86: intel_pmc_core: Handle CFL regmap properly
platform/x86: intel_pmc_core: Fix PCH IP sts reading
platform/x86: intel_pmc_core: Fix PCH IP name
platform/x86: intel_pmc_core: Fix file permissions for ltr_show
platform/x86: intel_pmc_core: Include R
x9ef4be15c5
Package C7 : 0x1e011904
Package C8 : 0x3c5653cfe5a
Package C9 : 0x0
Package C10 : 0x16fff4289
Cc: Arjan van de Ven
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Cc: Anshuman Gupta
Cc: Len Brown
Cc: Rafael J. Wysocki
Signed-off-by: Rajneesh Bhardw
Icelake can resue most of the CNL PCH IPs as they are mostly similar.
This patch enables the PMC Core driver for ICL family.
It also addresses few other minor issues like upper case conversions and
some tab alignments.
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Signed-off-by: Rajnees
: x...@kernel.org
Cc: Peter Zijlstra
Cc: Thomas Gleixner
Cc: Dave Hansen
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Signed-off-by: Rajneesh Bhardwaj
---
arch/x86/include/asm/intel-family.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h
upport")
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers/platform/x86/intel_pmc_core.c
index 9f143cdbea05..80936e6bdc61 100644
--- a/drivers/platform/
INTEL_CPU_FAM6() macro provides better abstraction and reduces code size so use
it instead of custom grown ICPU().
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/platform/x86
dex printing
for "ltr_show" is missing. For example, w/o this change, a user that wants
to ignore LTR from ME would do something like
echo 5 > ltr_ignore
but the index for ME is 6. Printing a reserved IP helps to properly
calculate LTR ignore offsets.
Cc: "David E. Box"
ectly read PCH IP power
gating status for Cannonlake and beyond.
Cc: "David E. Box"
Cc: Srinivas Pandruvada
Fixes: c977b98bbef5 ("platform/x86: intel_pmc_core: Make the driver PCH family
agnostic")
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c
On Wed, Dec 05, 2018 at 10:42:21AM +0200, Andy Shevchenko wrote:
> On Wed, Dec 5, 2018 at 3:47 AM Frank Lee wrote:
> > On Wed, Dec 5, 2018 at 1:39 AM Andy Shevchenko
> > wrote:
> > > On Tue, Dec 4, 2018 at 6:58 PM Frank Lee wrote:
>
> > > > $ git remote set-branches --add origin for-next
> > >
.
Signed-off-by: Rajneesh Bhardwaj
---
Changes in v4:
* Moved bits.h include to intel_pmc_core.h
* Reordered LTR related #defines in increasing manner.
drivers/platform/x86/intel_pmc_core.c | 62 ++-
drivers/platform/x86/intel_pmc_core.h | 7 +++
2 files changed, 67
converting to tabs at some places.
Signed-off-by: Rajneesh Bhardwaj
---
Changes in v4:
* Removed unnecessary comments related to reserved IPs
* Reordered #defines in the header in chronological order
* Worked on patch taken from review-andy branch that removed LTR
duplication strings and other
Cannonlake PCH allows us to ignore LTR from more IPs than Sunrisepoint
PCH so make the LTR ignore platform specific.
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 4 +++-
drivers/platform/x86/intel_pmc_core.h | 4 +++-
2 files changed, 6 insertions(+), 2 deletions
.
Signed-off-by: Rajneesh Bhardwaj
---
Changes in v3:
* No more IP printing
* Addressed convert_ltr_scale suggestions
* Added bits.h
* Reworked seq_printf for ltr decode but didnt use 0x%016x since
leading zeroes made output look odd.
drivers/platform/x86/intel_pmc_core.c | 63
Cannonlake PCH allows us to ignore LTR from more IPs than Sunrisepoint
PCH so make the LTR ignore platform specific.
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 4 +++-
drivers/platform/x86/intel_pmc_core.h | 4 +++-
2 files changed, 6 insertions(+), 2 deletions
converting to tabs at some places.
Signed-off-by: Rajneesh Bhardwaj
[andy: fixed output to avoid LTR duplication and put space after colon]
Signed-off-by: Andy Shevchenko
---
Changes in v3:
* Removed IP index printing.
drivers/platform/x86/intel_pmc_core.c | 72
Signed-off-by: Rajneesh Bhardwaj
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 22065048d89d..f33ebd1b8034 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7530,7 +7530,8 @@ F:arch/x86/crypto/sha*-mb/
F: crypto
Add myself and David as the new maintainers for Intel Telemetry driver.
Signed-off-by: Box, David E
Signed-off-by: Rajneesh Bhardwaj
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 22065048d89d..f33ebd1b8034 100644
--- a
converting to tabs at some places.
Signed-off-by: Rajneesh Bhardwaj
---
Changes in v2:
* Removed IP # from map and displaying IP # while printing.
* Other style fixes as per Andy's suggestion.
drivers/platform/x86/intel_pmc_core.c | 73 +++
drivers/platfor
entries under
/sys/kernel/debug/telemetry/* when there is no apparent failure at boot.
Cc: Matt Turner
Cc: Len Brown
Cc: Souvik Kumar Chakravarty
Cc: Kuppuswamy Sathyanarayanan
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=198779
Acked-by: Matt Turner
Signed-off-by: Rajneesh Bhardwaj
.
Signed-off-by: Rajneesh Bhardwaj
---
Changes in v2:
* Get rid of union and bitfields to decode LTR and use FIELD_GET macro
* Change get_ltr_scale to convert_ltr_scale.
* Other style fixes and misc. improvements suggested by Andy for v1.
drivers/platform/x86/intel_pmc_core.c | 64
Cannonlake PCH allows us to ignore LTR from more IPs than Sunrisepoint
PCH so make the LTR ignore platform specific.
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 4 +++-
drivers/platform/x86/intel_pmc_core.h | 4 +++-
2 files changed, 6 insertions(+), 2 deletions
S section:
> > >
> > > 7441 INTEL PMC CORE DRIVER
> > > 7442M: Rajneesh Bhardwaj
> > > 7443M: Vishwanath Somayaji
> > >
> > > 7444L: platform-driver-...@vger.kernel.org
> > &g
This removes the entry for pmc_core.h file in the MAINTAINERS as the
file is already removed by a previous commit.
"platform/x86: intel_pmc_core: Remove unused header file"
Reported-by: Joe Perches
Signed-off-by: Rajneesh Bhardwaj
---
MAINTAINERS | 1 -
1 file changed, 1 deletio
ote:
> >>On 26-Sep-18 7:26 PM, Andy Shevchenko wrote:
> >>>On Mon, Sep 3, 2018 at 9:05 PM Rajneesh Bhardwaj
> >>> wrote:
> >>>>not be obtained and result in a invalid telemetry_plt_config.
> >>>What is telemetry_plt_config?
> >>In
change allows to create the above cpuidle attributes only if
FADT table supports Low Power S0 Idle.
Cc: Rafael J . Wysocki
Cc: Srinivas Pandruvada
Signed-off-by: Rajneesh Bhardwaj
---
drivers/acpi/acpi_lpit.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/acpi/acpi_lpit.c b
.
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 62 ++-
drivers/platform/x86/intel_pmc_core.h | 14 ++
2 files changed, 74 insertions(+), 2 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers/platform/x86
Cc: Souvik Kumar Chakravarty
Cc: Kuppuswamy Sathyanarayanan
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=198779
Acked-by: Matt Turner
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_telemetry_debugfs.c | 14 ++
1 file changed, 10 insertions(+), 4
converting to tabs at some places.
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 75 +++
drivers/platform/x86/intel_pmc_core.h | 55 +---
2 files changed, 123 insertions(+), 7 deletions(-)
diff --git a/drivers/platform/x86
Cannonlake PCH allows us to ignore LTR from more IPs than Sunrisepoint
PCH so make the LTR ignore platform specific.
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 4 +++-
drivers/platform/x86/intel_pmc_core.h | 4 +++-
2 files changed, 6 insertions(+), 2 deletions
On Mon, Jul 02, 2018 at 03:19:22PM +0300, Andy Shevchenko wrote:
> On Fri, Jun 15, 2018 at 2:27 PM, Rajneesh Bhardwaj
> wrote:
> > On Thu, Jun 14, 2018 at 03:13:02PM -0700, David E. Box wrote:
> >> From:
> >>
> >> Adds debugfs access to registers in the
> whenever the package enters C10 and can be read from slp_s0_debug_status.
> The pm states may also be latched by writing 1 to slp_s0_debug_latch
> which will immediately capture the current state on the next read of
> slp_s0_debug_status.
Reviewed-and-tested-by: Rajneesh Bhardwaj
>
On Fri, Jun 08, 2018 at 05:02:37PM -0700, Box, David E wrote:
I am ok with the design and approach and also verified it on a Cannonlake
system. I wont insist for a V4 unless Andy feels a need for respin but there
are minor things that were missed.
> Adds debugfs access to registers in the Cannon
On Wed, May 30, 2018 at 03:53:12AM -0700, David E. Box wrote:
Hi Dave,
> Hi Rajneesh,
>
> On Mon, 2018-05-28 at 12:30 +0530, Rajneesh Bhardwaj wrote:
> > On Thu, May 24, 2018 at 06:10:56PM -0700, David E. Box wrote:
> >
> > Thanks for sending this, Dave. Few comm
On Thu, May 24, 2018 at 06:10:56PM -0700, David E. Box wrote:
Thanks for sending this, Dave. Few comments below.
> Adds debugfs access to registers in the Cannon Point PCH PMC that are
Please use Cannonlake PCH.
> useful for debugging #SLP_S0 signal assertion and other low power related
assert
Commit-ID: f79b1c573cb4dc551919f81ed5797419f6fc1f3a
Gitweb: https://git.kernel.org/tip/f79b1c573cb4dc551919f81ed5797419f6fc1f3a
Author: Rajneesh Bhardwaj
AuthorDate: Thu, 29 Mar 2018 20:36:55 +0530
Committer: Thomas Gleixner
CommitDate: Fri, 27 Apr 2018 16:44:29 +0200
x86/i8237
On Mon, Mar 26, 2018 at 03:34:44AM -0700, h...@zytor.com wrote:
> On March 26, 2018 2:11:51 AM PDT, Thomas Gleixner wrote:
> >On Mon, 26 Mar 2018, Rajneesh Bhardwaj wrote:
> >
> >> On Sun, Mar 25, 2018 at 01:50:40PM +0200, Thomas Gleixner wrote:
> >> > On Th
On Sun, Mar 25, 2018 at 01:50:40PM +0200, Thomas Gleixner wrote:
> On Thu, 22 Mar 2018, Anshuman Gupta wrote:
>
> > From: Rajneesh Bhardwaj
> >
> > >From Skylake onwards, the platform controller hub (Sunrisepoint PCH) does
> > not support legacy DMA operations
On Thu, Mar 22, 2018 at 03:51:58PM +0530, Anshuman Gupta wrote:
Adding Thomas.
> From: Rajneesh Bhardwaj
>
> From Skylake onwards, the platform controller hub (Sunrisepoint PCH) does
> not support legacy DMA operations to IO ports 81h-83h, 87h, 89h-8Bh, 8Fh.
> Currently this d
On Fri, Mar 16, 2018 at 01:51:01PM +0100, Rafael J. Wysocki wrote:
> From: Rafael J. Wysocki
>
> Introduce a driver for the ACPI Time and Alarm Device (TAD) based on
> Section 9.18 of ACPI 6.2.
Does UEFI bios for CNL support it already? Perhaps we can try this out and
share some feedback. Some m
orm Controller Hub Family: BIOS Specification.
https://www.intel.in/content/www/in/en/embedded/products/skylake/u-mobile/software-and-drivers.html
Cc: Alan Cox
Reviewed-by: Andy Shevchenko
Signed-off-by: Anshuman Gupta
Signed-off-by: Rajneesh Bhardwaj
---
Changes in v2:
* changed to dma_inb()
T
orm Controller Hub Family: BIOS Specification.
https://www.intel.in/content/www/in/en/embedded/products/skylake/u-mobile/software-and-drivers.html
Cc: Alan Cox
Cc: Andy Shevchenko
Signed-off-by: Anshuman Gupta
Signed-off-by: Rajneesh Bhardwaj
---
This depends on recently introduced dmi_get_bios_y
calculate the PMC base
address.
Cc: Rafael J. Wysocki
Cc: Len Brown
Cc: linux-a...@vger.kernel.org
Acked-by: Rafael J. Wysocki
Tested-by: Rajneesh Bhardwaj
Signed-off-by: Srinivas Pandruvada
---
drivers/acpi/acpi_lpit.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/acpi/acpi_lpit.c b
-
KBL | Y | Y |
-
CFL | Y | N |
-
Signed-off-by: Srinivas Pandruvada
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c
This adds support for Cannonlake PCH which is used by Cannonlake and
Coffeelake SoCs.
Signed-off-by: Srinivas Pandruvada
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 85 +++
drivers/platform/x86/intel_pmc_core.h | 11 +
2
From: Srinivas Pandruvada
Read SLP_S0 address from ACPI LPIT table when present and use PMC
specific SLP_S0 offset to get the base address of PMC MMIO.
Signed-off-by: Rajneesh Bhardwaj
Signed-off-by: Srinivas Pandruvada
---
drivers/platform/x86/intel_pmc_core.c | 9 -
1 file changed
Add CPUID of Cannonlake (CNL) processors to Intel family list.
Cc: Dave Hansen
Cc: Thomas Gleixner
cc: Ingo Molnar
Cc: "H. Peter Anvin"
Cc: x...@kernel.org
Reviewed-by: Thomas Gleixner
Suggested-by: Tony Luck
Signed-off-by: Megha Dey
Signed-off-by: Rajneesh Bhardwaj
---
arch/x
. Wysocki
Cc: Len Brown
Cc: Thomas Gleixner
Cc: linux-a...@vger.kernel.org
Cc: x...@kernel.org
Rajneesh Bhardwaj (3):
x86/cpu: Add Cannonlake to Intel family
platform/x86: intel_pmc_core: Add CannonLake PCH support
platform/x86: intel_pmc_core: Special case for Coffeelake
Srinivas
On Fri, Jan 26, 2018 at 02:39:47PM +0200, Andy Shevchenko wrote:
> On Fri, Jan 19, 2018 at 10:58 AM, Rajneesh Bhardwaj
> wrote:
> > Add CPUID of Cannonlake (CNL) processors to Intel family list.
> >
> > Cc: Dave Hansen
> > Cc: Thomas Gleixner
> > cc:
x for the
same.
Signed-off-by: Rajneesh Bhardwaj
---
arch/x86/include/asm/pmc_core.h | 27 ---
drivers/platform/x86/intel_pmc_core.c | 1 -
2 files changed, 28 deletions(-)
delete mode 100644 arch/x86/include/asm/pmc_core.h
diff --git a/arch/x86/include/asm/pmc
This adds support for Cannonlake PCH which is used by Cannonlake and
Coffeelake SoCs.
Signed-off-by: Srinivas Pandruvada
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 85 +++
drivers/platform/x86/intel_pmc_core.h | 11 +
2
-
KBL | Y | Y |
-
CFL | Y | N |
-
Signed-off-by: Srinivas Pandruvada
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c
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