On Jum, 2017-05-05 at 13:11 +0200, Marek Vasut wrote:
> On 05/05/2017 12:26 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Convert Macro #define configuration to Kconfig method. All FPGA
> > devices
> > enable configuration based on
On Rab, 2017-03-29 at 11:28 +0800, tien.fong.c...@intel.com wrote:
> From: "Chee, Tien Fong" <tien.fong.c...@intel.com>
>
> Commit ce62e57fc571 ("ARM: boot0 hook: remove macro, include whole
> header file") miss out cleaning macro in this header file
On Sel, 2017-03-28 at 11:38 +0200, Marek Vasut wrote:
> On 03/28/2017 11:25 AM, tien.fong.c...@intel.com wrote:
> >
> > From: "Chee, Tien Fong" <tien.fong.c...@intel.com>
> >
> > Fixing the broken implementation caused by the patch
> > commit:ce6
On Sel, 2017-03-07 at 04:45 +0100, Marek Vasut wrote:
> On 03/06/2017 05:45 AM, Chee, Tien Fong wrote:
> >
> > On Ahd, 2017-03-05 at 01:57 +0100, Marek Vasut wrote:
> > >
> > > On 03/03/2017 01:50 PM, Chee Tien Fong wrote:
> > > >
> > > >
On Ahd, 2017-03-05 at 01:57 +0100, Marek Vasut wrote:
> On 03/03/2017 01:50 PM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> >
> > This patch removes the unused passing parameter of
> > socfpga_bridges_reset
> > func
On Jum, 2017-03-03 at 20:50 +0800, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.c...@intel.com>
>
> This patchset adds FPGA driver to Intel Arria 10 SoC.
>
> This series is working on top of [1] initial patchset which enables
> the basic
> support for
From: Tien Fong Chee
Add FPGA driver support for Arria 10.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ching Liang See
Cc: Ley Foon
From: Tien Fong Chee
This patch adding the Arria10 FPGA manager program assembly driver
which can be used for feeding bitstream to configure FPGA.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
Move the Gen5 specific code to gen5 files. No functional change.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ching Liang See
Cc: Ley
From: Tien Fong Chee
This patch removes the unused passing parameter of socfpga_bridges_reset
function in Arria10.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ching Liang See
From: Tien Fong Chee
This patchset adds FPGA driver to Intel Arria 10 SoC.
This series is working on top of [1] initial patchset which enables the basic
support for Arria 10 and other features.
[1]: https://www.mail-archive.com/u-boot@lists.denx.de/msg240053.html
On Sab, 2017-02-25 at 22:43 +0100, Marek Vasut wrote:
> On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> >
> > Add SPL support for Arria 10.
> >
> > Signed-off-by: Tien Fong Chee
> > Signed-off-by: Ley Foon Tan
> > ---
> >
On Sel, 2017-01-10 at 23:06 +0100, Marek Vasut wrote:
> On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> >
> > *** BLURB HERE ***
> Please at least fill the blanks next time ... :)
>
By the way,
On Sel, 2017-01-10 at 23:06 +0100, Marek Vasut wrote:
> On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> >
> > *** BLURB HERE ***
> Please at least fill the blanks next time ... :)
>
Oppss
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek
From: Tien Fong Chee
This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
drivers/Makefile | 2 +-
1 file
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions. and
arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh
From: Tien Fong Chee
Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.
Signed-off-by: Tien Fong Chee
From: Tien Fong Chee
This patch enables SPL build and implementation for Arria 10.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
From: Tien Fong Chee
This is initial version of device tree for the Intel socfpga arria10
development kit with sdmmc.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
From: Tien Fong Chee
These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.
Update the dwmac_deassert_reset
From: Tien Fong Chee
Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong
From: Tien Fong Chee
These functions are already in arch/arm/mach-socfpga/board.c
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
From: Tien Fong Chee
On the Arria10 device, the bridges are not mapped through the interconnect.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.
Signed-off-by: Dinh Nguyen
From: Tien Fong Chee
On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.
Suggested-by: Marek Vasut
Signed-off-by: Dinh
From: Tien Fong Chee
The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
From: Tien Fong Chee
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
From: Tien Fong Chee
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
Add config for the Arria10 SoC Development Kit.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Acked-by: Marek Vasut
Cc: Marek Vasut
Cc: Dinh
From: Tien Fong Chee
Add a defconfig file for Arria10, which does not include enabling SPL.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Acked-by: Marek Vasut
Cc: Marek Vasut
From: Tien Fong Chee
Add system manager defines for Arria10.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
From: Tien Fong Chee
Add minimal support for the Arria10 SoCDK.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
From: Tien Fong Chee
Add the structures for the SDRAM controller on Arria10.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc:
From: Tien Fong Chee
Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien
From: Tien Fong Chee
Add remaining 3 I2C base addresses for the Arria10.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Reviewed-by: Stefan Roese
Cc: Marek Vasut
Cc:
From: Tien Fong Chee
*** BLURB HERE ***
Tien Fong Chee (28):
arm: socfpga: arria10: add additional i2c nodes for Arria10
arm: socfpga: arria10: add sdram defines for Arria10
arm: socfpga: arria10: add board files for the Arria10 SoCDK
arm: socfpga: arria10: add
On Isn, 2017-01-09 at 08:47 -0600, Dinh Nguyen wrote:
>
> On 01/09/2017 05:31 AM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> >
> > Add base address header file for Stratix10 SoC
> >
> > Signed-off-by:
On Isn, 2017-01-09 at 13:43 +0100, Marek Vasut wrote:
> On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> >
> > Add remaining 3 I2C base addresses for the Arria10.
> >
> > Signed-off-by
On Isn, 2017-01-09 at 10:54 -0600, Dinh Nguyen wrote:
> On Mon, Jan 9, 2017 at 6:43 AM, Marek Vasut <ma...@denx.de> wrote:
> >
> > On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> > >
> > > From: Tien Fong Chee <tien.fong.c...@intel.com>
&g
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
drivers/Makefile |2 +-
1
From: Tien Fong Chee
This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions. and
arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh
From: Tien Fong Chee
Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.
Signed-off-by: Tien Fong Chee
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
From: Tien Fong Chee
This patch enables SPL build and implementation for Arria 10.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
From: Tien Fong Chee
These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
This is initial version of device tree for the Intel socfpga arria10
development kit with sdmmc.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
From: Tien Fong Chee
Add base address header file for Stratix10 SoC
Signed-off-by: Chin Liang See
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon
From: Tien Fong Chee
On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.
Update the dwmac_deassert_reset
From: Tien Fong Chee
On the Arria10 device, the bridges are not mapped through the interconnect.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong
From: Tien Fong Chee
These functions are already in arch/arm/mach-socfpga/board.c
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.
Signed-off-by: Dinh Nguyen
From: Tien Fong Chee
There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
From: Tien Fong Chee
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
From: Tien Fong Chee
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
From: Tien Fong Chee
On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.
Suggested-by: Marek Vasut
Signed-off-by: Dinh
From: Tien Fong Chee
Add a defconfig file for Arria10, which does not include enabling SPL.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Acked-by: Marek Vasut
Cc: Marek Vasut
From: Tien Fong Chee
Add config for the Arria10 SoC Development Kit.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Acked-by: Marek Vasut
Cc: Marek Vasut
Cc: Dinh
From: Tien Fong Chee
Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien
From: Tien Fong Chee
Add minimal support for the Arria10 SoCDK.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
From: Tien Fong Chee
Add system manager defines for Arria10.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
From: Tien Fong Chee
Add the structures for the SDRAM controller on Arria10.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc:
From: Tien Fong Chee
Add remaining 3 I2C base addresses for the Arria10.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Reviewed-by: Stefan Roese
Cc: Marek Vasut
Cc:
On Jum, 2017-01-06 at 17:03 -0600, Dinh Nguyen wrote:
>
> On 01/06/2017 05:19 AM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> >
> > Drivers for reset manager is restructured such that common
> > functions,
>
On Jum, 2017-01-06 at 12:12 -0600, Dinh Nguyen wrote:
>
> On 01/06/2017 05:19 AM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee <tien.fong.c...@intel.com>
> >
> > Enhanced defconfig file for Arria10 to enable SPL build and
> > supporting
> >
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
Changes for V3
- no changes
Changes
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek
From: Tien Fong Chee
This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
Changes for V3
- no changes
Changes
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
Changes for V3
- no changes
Changes
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions. and
arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
Changes for v3
- no changes
changes
From: Tien Fong Chee
Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.
Signed-off-by: Tien Fong Chee
From: Tien Fong Chee
Enhanced defconfig file for Arria10 to enable SPL build and supporting
device tree build for SDMMC.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
From: Tien Fong Chee
This patch enables SPL build and implementation for Arria 10.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
From: Tien Fong Chee
This is initial version of device tree for the Intel socfpga arria10
development kit with sdmmc.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
From: Tien Fong Chee
These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
Add base address header file for Stratix10 SoC
Signed-off-by: Chin Liang See
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ley Foon
From: Tien Fong Chee
On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.
Update the dwmac_deassert_reset
From: Tien Fong Chee
Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong
From: Tien Fong Chee
There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
From: Tien Fong Chee
These functions are already in arch/arm/mach-socfpga/board.c
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
On the Arria10 device, the bridges are not mapped through the interconnect.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
From: Tien Fong Chee
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
From: Tien Fong Chee
The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.
Signed-off-by: Dinh Nguyen
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