Hi Ben,
I saw you have phy lib in your branch. What is the current state?
Are there any problems? When do you want to add to mainline?
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Mi
On Tuesday 25 August 2009 01:45:57 benix samuel wrote:
> I am a newbie, would like to tailor U-Boot specific to my board. Where to
> start?
you didnt describe your hardware at all. are you using a Blackfin part like
your truncated subject indicates ?
-mike
signature.asc
Description: This is a
Hi Michal,
On Tuesday 25 August 2009 09:02:14 Michal Simek wrote:
> I saw you have phy lib in your branch. What is the current state?
> Are there any problems? When do you want to add to mainline?
IIRC, Jean-Christophe is also working on a PHY lib implementation (port from
the Linux version).
J
On Mon, 24 Aug 2009 12:01:54 +0200
Wolfgang Denk wrote:
> Dear Simon Kagstrom,
>
> In message <20090824105935.038bd...@marrow.netinsight.se> you wrote:
> >
> > I updated my git tree today and got this patch (among other things). It
> > does not work very well for me, unfortunately. I've tried t
Hi Stefan,
Stefan Roese wrote:
> Hi Michal,
>
> On Tuesday 25 August 2009 09:02:14 Michal Simek wrote:
>> I saw you have phy lib in your branch. What is the current state?
>> Are there any problems? When do you want to add to mainline?
>
> IIRC, Jean-Christophe is also working on a PHY lib imple
Hi again!
I just wanted to check if there has been any progress on the issue
below (4-bit ECC support to read for the kernel / U-boot) during the
summer.
On Wed, 8 Jul 2009 15:59:27 +0200
Simon Kagstrom wrote:
> Hi Prafulla (and the list)!
>
> I'm wondering a bit how Sheevaplug handles the U-b
Hi Stephen,
On Mon, Aug 24, 2009 at 10:01:16PM -0400, Stephen Caudle wrote :
> I tried using your patches for the TNY-A9G20 on my QIL-A9G20 board from
> Calao.
I guess you mean SBC35-A9G20?
> Everything seems to work properly except the RTC. They use the same M41T94
> part and the CS is the s
I am using Blackfin BF531 ( a customized board). when I browsed the u-boot
code it has chunks of folder for different platforms. Can you provide me the
source code for this particulare platform alone?
Thanks,
Benix.
On Tue, Aug 25, 2009 at 12:33 PM, Mike Frysinger wrote:
> On Tuesday 25 August
Commit 16fc32f introduced an error in include/environment.h, which makes u-boot
fail to compile due to a missing #endif.
This also fixes a merge conflict remaining in include/configs/EB+MCF-EV123.h
which was caused by the same commit
Signed-off-by: Albin Tonnerre
---
include/configs/EB+MCF-EV123
MPC8379E RM says (10-34):
Once LCRR[CLKDIV] is written, the register should be read, and then
an isync should be executed.
So update this in code.
Also define a LCRR mask for processors, which uses not all bits
in the LCRR register (as for example mpc832x did).
Signed-off-by: Heiko Schocher
---
> MPC8379E RM says (10-34):
> Once LCRR[CLKDIV] is written, the register should be read, and then
> an isync should be executed.
> So update this in code.
> Also define a LCRR mask for processors, which uses not all bits
> in the LCRR register (as for example mpc832x did).
>
> Signed-off-by: Heiko
On Tuesday 25 August 2009 04:45:14 benix samuel wrote:
please do not top post
> I am using Blackfin BF531 ( a customized board). when I browsed the u-boot
> code it has chunks of folder for different platforms. Can you provide me
> the source code for this particulare platform alone?
please read
On 09:08 Tue 25 Aug , Stefan Roese wrote:
> Hi Michal,
>
> On Tuesday 25 August 2009 09:02:14 Michal Simek wrote:
> > I saw you have phy lib in your branch. What is the current state?
> > Are there any problems? When do you want to add to mainline?
>
> IIRC, Jean-Christophe is also working on
Hi,
Albin Tonnerre a écrit :
> Currently, I don't really have any idea. Besides, it's going to be hard for me
> to debug this, as I don't have an oscilloscope at hand. Would you please try
> to
> run u-boot within a debugger to see where exactly the CS line is driven low?
isn't the RTC connected
> -Original Message-
> From: Simon Kagstrom [mailto:simon.kagst...@netinsight.net]
> Sent: Tuesday, August 25, 2009 1:00 PM
> To: U-Boot ML
> Cc: Prafulla Wadaskar; Nicolas Pitre
> Subject: Re: [U-Boot] U-boot environment on Sheevaplug
>
> Hi again!
>
> I just wanted to check if there
On Tuesday 25 August 2009 04:46:07 Albin Tonnerre wrote:
> Commit 16fc32f introduced an error in include/environment.h, which makes
> u-boot fail to compile due to a missing #endif.
> This also fixes a merge conflict remaining in
> include/configs/EB+MCF-EV123.h which was caused by the same commit
This patch has been abandoned - It's place in the patch series has been kept
so as not to disrupt the versioning of later patches
Signed-off-by: Graeme Russ
---
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
This patch is in readiness for moving all u-boot code + data from Flash to
RAM. Low level init code is not needed after bootstrap and therefore does
not need to be copied. Moving this code into dedicated sections makes it
easier
Signed-off-by: Graeme Russ
---
Version 2
- Modified slightly to acc
On Tue, Aug 25, 2009 at 06:16:24AM -0400, Mike Frysinger wrote :
> On Tuesday 25 August 2009 04:46:07 Albin Tonnerre wrote:
> > Commit 16fc32f introduced an error in include/environment.h, which makes
> > u-boot fail to compile due to a missing #endif.
> > This also fixes a merge conflict remaining
The SPI controller on the S3C24X0 has 8 bit registers, not 32 bit.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Wolfgang Denk
---
include/s3c24x0.h | 22 ++
1 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/include/s3c24x0.h b/include/s3c24x
Dear Graeme Russ,
In message <1251195588-7799-1-git-send-email-graeme.r...@gmail.com> you wrote:
> This patch is in readiness for moving all u-boot code + data from Flash to
> RAM. Low level init code is not needed after bootstrap and therefore does
> not need to be copied. Moving this code into d
Dear Albin Tonnerre,
In message <20090825102110.ge10...@pc-ras4041.res.insa> you wrote:
>
> > guess this needs to get squashed into the relevant change rather than added
> > as
> > a new commit. thanks for the update.
>
> How exactly would you do that? The commit actually got pushed, and AFAIK
Dear Ben Warren,
In message <4a9069e9.2030...@gmail.com> you wrote:
>
> > Tested on mx31ads: works like a charm.
> >
> Great news! Thanks!
> > Will try to debug the trab issues later tonight (if I manage to find a
> > matching JTAG connector for this board ).
OK, tested on trab (= SMDK2400),
Wolfgang Denk wrote:
> Dear Graeme Russ,
>
> In message <1251195588-7799-1-git-send-email-graeme.r...@gmail.com> you wrote:
>> This patch is in readiness for moving all u-boot code + data from Flash to
>> RAM. Low level init code is not needed after bootstrap and therefore does
>> not need to be c
Dear Albin Tonnerre,
In message
<1251189967-11702-1-git-send-email-albin.tonne...@free-electrons.com> you wrote:
> Commit 16fc32f introduced an error in include/environment.h, which makes
> u-boot
> fail to compile due to a missing #endif.
> This also fixes a merge conflict remaining in include/
Hi all,
unfortunately some merge conflicts have creeped in undetected into
the next branch. To fix the mess I had to rebase the "next" branch.
Sorry if this is causing inconveniences.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 1652
MPC8379E RM says (10-34):
Once LCRR[CLKDIV] is written, the register should be read, and then
an isync should be executed.
So update this in code.
Also define a LCRR mask for processors, which uses not all bits
in the LCRR register (as for example mpc832x did).
Signed-off-by: Heiko Schocher
---
Wolfgang,
is there any chance this patch can be applied before the merge window
closes ?
Is there anything you want me to do or change, i.e. have I missed
something ?
Surely I don't want to bother you - just asking.
Regards,
Andre
On Wed, 2009-08-19 at 13:41 +0200, André Schwarz wrote:
> clea
> -Original Message-
> From: Heiko Schocher [mailto:h...@denx.de]
> Sent: Tuesday, August 25, 2009 7:32 PM
> To: Liu Dave-R63238
> Cc: Phillips Kim-R1AAHA; U-Boot user list
> Subject: [PATCH v2] mpc83xx: update LCRR register handling
>
> MPC8379E RM says (10-34):
> Once LCRR[CLKDIV] is wr
Hi Albin,
On Tue, Aug 25, 2009 at 4:37 AM, Albin Tonnerre
wrote:
> I guess you mean SBC35-A9G20?
I actually tried it with the patches for both boards (TNY & SBC35) and
saw the same result.
> > Everything seems to work properly except the RTC. They use the same M41T94
> > part and the CS is the
Hello Eric,
On Tue, Aug 25, 2009 at 5:38 AM, Eric Bénard wrote:
> isn't the RTC connected to the SPI chip select that the internal firmware
> toggle on boot to probe for a SPI Flash ?
That is certainly possible. This problem went away for me when I upgraded to
the "next" branch. Could the SPI d
Renato Andreola wrote:
> From 21d84ab72266f118794233176bd356d8b1cfdf35 Mon Sep 17 00:00:00 2001
> From: Renato Andreola
> Date: Fri, 21 Aug 2009 18:05:51 +0200
> Subject: [PATCH] drivers/mtd/cfi_flash: precision and underflow problem in
> tout calculation
>
> With old configuration it could hap
Reset any i2c devices that may have been interrupted by a system reset.
Normally this would be accomplished by clocking the line until SCL and SDA
are released and then sending a start condtiion (From an Atmel datasheet).
But since there is only write access to these lines on the MPC5200 we can
onl
Add chip select region for an Epson S1D15313.
Signed-off-by: Eric Millbrandt
---
include/configs/galaxy5200.h |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h
index eb2cae6..54c6b80 100644
--- a/include/confi
Modify mpc5xxx_gpio structure to include the i2c output-only enable
and data value out registers.
Signed-off-by: Eric Millbrandt
---
A quick string search shows that no in-tree code is currently using any of
the modified fields and the structure size does not change.
include/mpc5xxx.h |
Hi,
I'm having a big problem with my board reset that it's very similar to
MPC8548CDS. I've been using for a long time a reset just in MPC8548 core,
using DBCR0 register. But after many resets, my u-boot crash when try to
relocate code to ram, and I can't debug it with BDI.
I saw the MPC8548 erra
The time that the sequencer power source stays the HRESET down is
configurable, as the time waiting to rise up.
On Tue, Aug 25, 2009 at 11:14 AM, Werner Nedel wrote:
> Hi,
>
> I'm having a big problem with my board reset that it's very similar to
> MPC8548CDS. I've been using for a long time a r
Hi Eric,
On Tue, 2009-08-25 at 08:57 -0500, Eric Millbrandt wrote:
> Reset any i2c devices that may have been interrupted by a system reset.
> Normally this would be accomplished by clocking the line until SCL and SDA
> are released and then sending a start condtiion (From an Atmel datasheet).
> B
This patch is necessary to fix the common case in which CONFIG_SYS_HZ is
just below 1000 (e.g. 999 that results from an integer division between
a system clock frequency like 8333Hz and a divisor like 83334).
In that case the CONFIG_SYS_HZ/1000 expression returns 0 and the tout *=
CONFIG_SYS
Reset any i2c devices that may have been interrupted by a system reset.
Normally this would be accomplished by clocking the line until SCL and SDA
are released and then sending a start condtiion (From an Atmel datasheet).
But since there is only write access to these lines on the MPC5200 we can
onl
Cleanup typo and trailing whitespace from galaxy5200.h
Signed-off-by: Eric Millbrandt
---
include/configs/galaxy5200.h |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h
index e9a4569..8d530d8 100644
--- a/i
Hello,
I am working with a mpc8260ads(actually QUICC 8248 processor) based board.
There are two hardware rs-232 ports available.
I can switch the console between the two by switching the CONFIG_CONS_INDEX
configuration variable between 1 and 4.
I would like to have both ports in service, when
On Tue, 25 Aug 2009 13:31:34 +0200
Heiko Schocher wrote:
> MPC8379E RM says (10-34):
> Once LCRR[CLKDIV] is written, the register should be read, and then
> an isync should be executed.
> So update this in code.
> Also define a LCRR mask for processors, which uses not all bits
> in the LCRR regis
On Monday 24 August 2009 10:32:17 Renato Andreola wrote:
> From 21d84ab72266f118794233176bd356d8b1cfdf35 Mon Sep 17 00:00:00 2001
> From: Renato Andreola
> Date: Fri, 21 Aug 2009 18:05:51 +0200
> Subject: [PATCH] drivers/mtd/cfi_flash: precision and underflow problem in
> tout calculation
>
> Wit
On Tuesday 25 August 2009 17:39:56 Stefan Roese wrote:
> > + if ((ulong)CONFIG_SYS_HZ > 10)
> > + tout *= (ulong)CONFIG_SYS_HZ/1000; /* for a big HZ, avoid
>
> overflow */
>
> Please insert spaces before and after the "/" above.
>
> > + else
> > + tout = DIV_ROUND_UP(to
On Friday 21 August 2009 19:59:42 Feng Kan wrote:
> Fix ECC Correction bug where the byte offset location were double
> flipped causing correction routine to toggle the wrong byte location
> in the ECC segment. The ndfc_calculate_ecc routine change the order
> of getting the ECC code.
> /*
Hi Wolfgang,
please pull this fix into master. Thanks.
The following changes since commit a794f59a75bf9fd4a44f1ad2349cae903c42b89c:
Jean-Christophe PLAGNIOL-VILLARD (1):
sh/rsk7203: add missing include net.h
are available in the git repository at:
git://www.denx.de/git/u-boot-ppc4x
Hi Detlev-
I just wanted to let you know that I got Netconsole to work on my board.
It turned out that the NetLoop routine was halting and initialing the
TSEC driver over and over as part of the packet reception process. This
was causing the interface to go up and down over and over and the
packe
Wolfgang,
Wolfgang Denk wrote:
> Dear Ben Warren,
>
> In message <4a9069e9.2030...@gmail.com> you wrote:
>
>>> Tested on mx31ads: works like a charm.
>>>
>>>
>> Great news! Thanks!
>>
>>> Will try to debug the trab issues later tonight (if I manage to find a
>>> matching JTAG co
Hi Michal,
Michal Simek wrote:
> Hi Stefan,
>
> Stefan Roese wrote:
>
>> Hi Michal,
>>
>> On Tuesday 25 August 2009 09:02:14 Michal Simek wrote:
>>
>>> I saw you have phy lib in your branch. What is the current state?
>>> Are there any problems? When do you want to add to mainline?
>>>
On Tue, Aug 25, 2009 at 08:51:56AM -0400, Stephen Caudle wrote :
> Hello Eric,
>
> On Tue, Aug 25, 2009 at 5:38 AM, Eric Bénard wrote:
> > isn't the RTC connected to the SPI chip select that the internal firmware
> > toggle on boot to probe for a SPI Flash ?
>
> That is certainly possible. This
On Tue, Aug 25, 2009 at 08:37:11AM -0700, AGKohler wrote:
>
> Hello,
>
> I am working with a mpc8260ads(actually QUICC 8248 processor) based board.
> There are two hardware rs-232 ports available.
> I can switch the console between the two by switching the CONFIG_CONS_INDEX
> configuration var
Dear E Robertson,
In message <200908251403.20809.e.robertson@gmail.com> you wrote:
>
> I am using the at91sam9263 device from which the bootstrap code load u-boot
> to
> the desired ram address. However, I would like to re-relocate this at the
> different address based on memory availabilit
On Tuesday 25 August 2009 02:11:36 pm Wolfgang Denk wrote:
> Dear E Robertson,
>
> In message <200908251403.20809.e.robertson@gmail.com> you wrote:
> > I am using the at91sam9263 device from which the bootstrap code load
> > u-boot to the desired ram address. However, I would like to re-relocat
Hi All,
I am using the at91sam9263 device from which the bootstrap code load u-boot to
the desired ram address. However, I would like to re-relocate this at the
different address based on memory availability. Can / or should this be done?
___
U-Boot ma
On Tuesday 25 August 2009 02:11:36 pm Wolfgang Denk wrote:
> Dear E Robertson,
>
> In message <200908251403.20809.e.robertson@gmail.com> you wrote:
> > I am using the at91sam9263 device from which the bootstrap code load
> > u-boot to the desired ram address. However, I would like to re-relocat
All in-tree boards that use this controller have CONFIG_NET_MULTI added
Also:
- changed CONFIG_DRIVER_CS8900 to CONFIG_CS8900
- changed CS8900_BASE to CONFIG_CS8900_BASE
- changed CS8900_BUS?? to CONFIG_CS8900_BUS??
- cleaned up line lengths
- modified VCMA9 command function that accesses
Ben Warren wrote:
> All in-tree boards that use this controller have CONFIG_NET_MULTI added
> Also:
> - changed CONFIG_DRIVER_CS8900 to CONFIG_CS8900
> - changed CS8900_BASE to CONFIG_CS8900_BASE
> - changed CS8900_BUS?? to CONFIG_CS8900_BUS??
> - cleaned up line lengths
> - modified VCMA
Wolfgang,
The following changes since commit 307ecb6db04eebdc06b8c87d48bf48d3cbd5e9d7:
Eric Millbrandt (1):
Add support for USB on PSC3 for the mpc5200
are available in the git repository at:
git://git.denx.de/u-boot-net.git next
Alessandro Rubini (4):
net: defragment IP packe
Dear E Robertson,
In message <200908251428.55255.e.robertson@gmail.com> you wrote:
>
> > In message <200908251403.20809.e.robertson@gmail.com> you wrote:
> > > I am using the at91sam9263 device from which the bootstrap code load
> > > u-boot to the desired ram address. However, I would lik
Robin Getz wrote:
> Add a simple print for the Blackfin's Ethernet Rx function,
> so we can debug incomming Ethernet functions easier.
>
> Signed-off-by: Robin Getz
> ---
> drivers/net/bfin_mac.c |3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/bfin_mac.
Dear Mikhail Zaturenskiy,
In message <97dd5fd20908251235ic0e64eela7c75fb138143...@mail.gmail.com> you
wrote:
>
> static uint sdram_table[] = { /* Single read (offset 0x00 in UPM RAM) */
> 0x0F03C004, 0x0FFFC004, 0x00FCC004, 0x0FFFC000, 0x0FF30004, 0x0FFFC004,
> 0xC005, 0xC005, /* Burst re
Dear E Robertson,
In message <200908251442.53461.e.robertson@gmail.com> you wrote:
>
> By the way, my reason for doing this is that i want to maintain a
> proportional
> memory space available so if I increase the ram size I would like to relocate
> the boot loader without doing a separate
In message <1251197076-20081-1-git-send-email...@denx.de> I wrote:
> The SPI controller on the S3C24X0 has 8 bit registers, not 32 bit.
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
> Signed-off-by: Wolfgang Denk
> ---
> include/s3c24x0.h | 22 ++
> 1 files changed,
Dear Mike Frysinger,
In message <1251149433-30297-1-git-send-email-vap...@gentoo.org> you wrote:
> The following changes since commit a794f59a75bf9fd4a44f1ad2349cae903c42b89c:
> Jean-Christophe PLAGNIOL-VILLARD (1):
> sh/rsk7203: add missing include net.h
>
> are available in the git re
Dear Stefan Roese,
In message <200908251747.23905...@denx.de> you wrote:
> Hi Wolfgang,
>
> please pull this fix into master. Thanks.
>
>
> The following changes since commit a794f59a75bf9fd4a44f1ad2349cae903c42b89c:
> Jean-Christophe PLAGNIOL-VILLARD (1):
> sh/rsk7203: add missing in
Hi Robin,
Robin Getz wrote:
> On Mon 27 Jul 2009 17:47, Ben Warren pondered:
>
>> Ben Warren wrote:
>>
>>> All in-tree boards that use this controller have CONFIG_NET_MULTI
>>> added
>>> Also:
>>> - changed CONFIG_DRIVER_SMC9 to CONFIG_SMC9
>>> - cleaned up line lengths
>>> -
Dears,
I am using u-boot 1.2.0 for mpc8315e processor with BDI2000 debugger in
a new design based on MPC8315ERDB. Our board has a different DDR2 and
Flash memory. The flash memory works fine. The problem could be DDR2.
We are using Samsung K4T1G164QE DDR2 Memory. I can read/write DDR2
memory
Robin Getz wrote:
> Optionally add RFC 2349 "Transfer Size Option", so we can minimize the
> time spent sending data over the UART (now print a single line during a
> tftp transfer).
>
> - If turned on (CONFIG_TFTP_TSIZE), U-Boot asks for the size of the file.
> - if receives the file size, a sin
Kim Phillips wrote:
> if you don't have firmware installed for the PHY to come to life, this
> wait can be painful - let's give the option to avoid it if we want.
>
> Signed-off-by: Kim Phillips
> ---
> drivers/net/tsec.c |7 +++
> 1 files changed, 7 insertions(+), 0 deletions(-)
>
> diff
Dear Ben Warren,
In message <4a944bb0.9010...@gmail.com> you wrote:
> Wolfgang,
>
> The following changes since commit 307ecb6db04eebdc06b8c87d48bf48d3cbd5e9d7:
> Eric Millbrandt (1):
> Add support for USB on PSC3 for the mpc5200
>
> are available in the git repository at:
>
> git:/
Hi Michal,
mon...@monstr.eu wrote:
> Hi Ben,
>
> I updated LL-temac driver - all fixes are there.
> Ad to your point Microblaze uses only one ethernet core. It is possible
> to use a lot of IPs but I don't have board like this to test it that's
> why I don't want change it.
>
>
If it's possibl
Dear Marcos Cunha,
In message <4a944ee0.1000...@atlantico.com.br> you wrote:
>
> I am using u-boot 1.2.0 for mpc8315e processor with BDI2000 debugger in
> a new design based on MPC8315ERDB. Our board has a different DDR2 and
> Flash memory. The flash memory works fine. The problem could be DDR2.
On Aug 15, 2009, at 9:24 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:45 Fri 14 Aug , Kumar Gala wrote:
>>
>> On Aug 14, 2009, at 3:13 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
>>
>>> On 14:00 Fri 14 Aug , Kumar Gala wrote:
Added a arch_preboot() function that cpu specific c
On Aug 14, 2009, at 2:00 PM, Kumar Gala wrote:
> Added a arch_preboot() function that cpu specific code can implement
> to
> allow for various modifications to the state of the machine right
> before
> we boot. This can be useful to setup register state to a specific
> configuration.
>
> Sig
Hi Wolfgang,
On Tuesday 25 August 2009 22:53:54 Wolfgang Denk wrote:
> > Feng Kan (1):
> > ppc4xx: Fix ECC Correction bug with SMC ordering for NDFC driver
> >
> > drivers/mtd/nand/ndfc.c |4 ++--
> > 1 files changed, 2 insertions(+), 2 deletions(-)
>
> Applied, thanks.
Thanks.
> What
Hello Kim,
Kim Phillips wrote:
> On Tue, 25 Aug 2009 13:31:34 +0200
> Heiko Schocher wrote:
>
>> MPC8379E RM says (10-34):
>> Once LCRR[CLKDIV] is written, the register should be read, and then
>> an isync should be executed.
>> So update this in code.
>> Also define a LCRR mask for processors,
Hello Eric,
Eric Millbrandt wrote:
> Reset any i2c devices that may have been interrupted by a system reset.
> Normally this would be accomplished by clocking the line until SCL and SDA
> are released and then sending a start condtiion (From an Atmel datasheet).
> But since there is only write acc
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