Re: [PATCH v2 0/8] HMM profiler interface

[Deucher, Alexander]

[Public]

Please provide a link to the proposed userspace branch that makes use of this.

Alex

From: amd-gfx  on behalf of Philip Yang 

Sent: Thursday, January 20, 2022 6:13 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Yang, Philip ; Kuehling, Felix 
Subject: [PATCH v2 0/8] HMM profiler interface

The ROCm profiler would expose the data from KFD profiling APIs to
application developers to tune the applications based on how the address
range attributes affect the behavior and performance.

Per process event log use the existing SMI (system management interface)
event API. Each event log is one line of text with the event specific
information.

v2:
 * Keep existing events behaviour
 * Use ktime_get_boottime_ns() as timestamp to correlate with other APIs
 * Use compact message layout, stick with existing message convention
 * Add unmap from GPU event

Philip Yang (8):
  drm/amdkfd: Correct SMI event read size
  drm/amdkfd: Add KFD SMI event IDs and triggers
  drm/amdkfd: Enable per process SMI event
  drm/amdkfd: Add GPU recoverable fault SMI event
  drm/amdkfd: add migration SMI event
  drm/amdkfd: Add user queue eviction restore SMI event
  drm/amdkfd: Add unmap from GPU SMI event
  drm/amdkfd: Bump KFD API version for SMI profiling event

 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|   7 +-
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  11 +-
 drivers/gpu/drm/amd/amdkfd/kfd_device.c   |   4 +-
 drivers/gpu/drm/amd/amdkfd/kfd_migrate.c  |  67 ---
 drivers/gpu/drm/amd/amdkfd/kfd_migrate.h  |   5 +-
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h |   2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_process.c  |  37 +++-
 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c   | 163 +-
 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h   |  19 +-
 drivers/gpu/drm/amd/amdkfd/kfd_svm.c  |  63 +--
 include/uapi/linux/kfd_ioctl.h|  30 +++-
 11 files changed, 343 insertions(+), 65 deletions(-)

--
2.17.1

Re: [PATCH 1/2] drm/amdgpu/display: adjust msleep limit in dp_wait_for_training_aux_rd_interval

[Deucher, Alexander]

[Public]

It just changes the limit for when we use msleep vs udelay, not the units.

Alex

From: Chen, Guchun 
Sent: Thursday, January 20, 2022 8:49 PM
To: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander 
Subject: RE: [PATCH 1/2] drm/amdgpu/display: adjust msleep limit in 
dp_wait_for_training_aux_rd_interval

[Public]

If we change if condition, how about the division by "wait_in_micro_secs/1000", 
as the sleep time is less now. Shall we adjust it as well?

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Friday, January 21, 2022 2:04 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH 1/2] drm/amdgpu/display: adjust msleep limit in 
dp_wait_for_training_aux_rd_interval

Some architectures (e.g., ARM) have relatively low udelay limits.
On most architectures, anything longer than 2000us is not recommended.
Change the check to align with other similar checks in DC.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 1f8831156bc4..aa1c67c3c386 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -202,7 +202,7 @@ void dp_wait_for_training_aux_rd_interval(
 uint32_t wait_in_micro_secs)
 {
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-   if (wait_in_micro_secs > 16000)
+   if (wait_in_micro_secs > 1000)
 msleep(wait_in_micro_secs/1000);
 else
 udelay(wait_in_micro_secs);
--
2.34.1

Re: [PATCH Review 1/1] drm/amdgpu: remove unused variable warning

[Deucher, Alexander]

[AMD Official Use Only]

Please include a patch description even if it's similar to the subject.

Alex


From: amd-gfx  on behalf of Stanley.Yang 

Sent: Wednesday, January 19, 2022 6:30 AM
To: amd-gfx@lists.freedesktop.org ; Zhang, 
Hawking ; Ziya, Mohammad zafar 
; Clements, John ; Zhou1, 
Tao 
Cc: Yang, Stanley 
Subject: [PATCH Review 1/1] drm/amdgpu: remove unused variable warning

Change-Id: Ic2a488ee253a913d806bd33ee9c90e31a71af320
Signed-off-by: Stanley.Yang 
---
 drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 23 ---
 drivers/gpu/drm/amd/amdgpu/umc_v8_7.c |  6 --
 2 files changed, 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
index 6953426f0bed..526de1ca9b8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
@@ -61,22 +61,9 @@ static void 
umc_v6_7_ecc_info_query_correctable_error_count(struct amdgpu_device
uint32_t channel_index,
unsigned long *error_count)
 {
-   uint32_t ecc_err_cnt;
 uint64_t mc_umc_status;
 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);

-   /*
-* select the lower chip and check the error count
-* skip add error count, calc error counter only from mca_umc_status
-*/
-   ecc_err_cnt = ras->umc_ecc.ecc[channel_index].ce_count_lo_chip;
-
-   /*
-* select the higher chip and check the err counter
-* skip add error count, calc error counter only from mca_umc_status
-*/
-   ecc_err_cnt = ras->umc_ecc.ecc[channel_index].ce_count_hi_chip;
-
 /* check for SRAM correctable error
   MCUMC_STATUS is a 64 bit register */
 mc_umc_status = ras->umc_ecc.ecc[channel_index].mca_umc_status;
@@ -110,15 +97,11 @@ static void umc_v6_7_ecc_info_query_ras_error_count(struct 
amdgpu_device *adev,

 uint32_t umc_inst= 0;
 uint32_t ch_inst = 0;
-   uint32_t umc_reg_offset  = 0;
 uint32_t channel_index   = 0;

 /*TODO: driver needs to toggle DF Cstate to ensure
  * safe access of UMC registers. Will add the protection */
 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
-   umc_reg_offset = get_umc_v6_7_reg_offset(adev,
-umc_inst,
-ch_inst);
 channel_index = get_umc_v6_7_channel_index(adev,
  umc_inst,
  ch_inst);
@@ -133,7 +116,6 @@ static void umc_v6_7_ecc_info_query_ras_error_count(struct 
amdgpu_device *adev,

 static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,
  struct ras_err_data *err_data,
-uint32_t umc_reg_offset,
  uint32_t ch_inst,
  uint32_t umc_inst)
 {
@@ -192,18 +174,13 @@ static void 
umc_v6_7_ecc_info_query_ras_error_address(struct amdgpu_device *adev

 uint32_t umc_inst= 0;
 uint32_t ch_inst = 0;
-   uint32_t umc_reg_offset  = 0;

 /*TODO: driver needs to toggle DF Cstate to ensure
  * safe access of UMC resgisters. Will add the protection
  * when firmware interface is ready */
 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
-   umc_reg_offset = get_umc_v6_7_reg_offset(adev,
-umc_inst,
-ch_inst);
 umc_v6_7_ecc_info_query_error_address(adev,
  err_data,
-umc_reg_offset,
  ch_inst,
  umc_inst);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c 
b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
index 05f79eea307c..cd57f39df7d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_7.c
@@ -114,7 +114,6 @@ static void umc_v8_7_ecc_info_query_ras_error_count(struct 
amdgpu_device *adev,

 static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev,
 struct ras_err_data *err_data,
-   uint32_t umc_reg_offset,
 uint32_t ch_inst,
 uint32_t umc_inst)
 {
@@ -173,19 +172,14 @@ static void 
umc_v8_7_ecc_info_query_ras_error_address(struct amdgpu_device *adev

 uint32_t umc_inst= 0;
 uint32_t ch_inst = 0;
-   uint32_t 

Re: [PATCH] amd/amdkfd:Fix the return value in kfd_process_queue_manager

[Deucher, Alexander]

[AMD Official Use Only]

You can just drop the whole line.

Alex


From: amd-gfx  on behalf of majun 

Sent: Wednesday, January 19, 2022 7:57 AM
To: amd-gfx@lists.freedesktop.org 
Subject: [PATCH] amd/amdkfd:Fix the return value in kfd_process_queue_manager

Change the return value of set_queue_properties_from_criu()

Signed-off-by: majun 
Change-Id: I11362eb76eee84e64c5207c24a2b78141f62e63a
---
 drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index ec62897914da..f70e972d1d33 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -826,7 +826,7 @@ static void set_queue_properties_from_criu(struct 
queue_properties *qp,
 qp->type = q_data->type;
 qp->format = q_data->format;

-   return 0;
+   return;
 }


--
2.25.1

Re: [PATCH 1/2] drm/amdgpu: drop redundant check of ip discovery_bin

[Deucher, Alexander]

[Public]

Series is:
Reviewed-by: Alex Deucher 

From: Chen, Guchun 
Sent: Friday, January 14, 2022 12:58 AM
To: amd-gfx@lists.freedesktop.org ; Deucher, 
Alexander ; Koenig, Christian 
; Pan, Xinhui ; Zhang, Hawking 
; Zhou, Peng Ju 
Cc: Chen, Guchun 
Subject: [PATCH 1/2] drm/amdgpu: drop redundant check of ip discovery_bin

Early check in amdgpu_discovery_reg_base_init promises this.

Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 57e001d73ec9..2f891ae90bad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1194,11 +1194,6 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device 
*adev)
 return -EINVAL;

 amdgpu_discovery_harvest_ip(adev);
-
-   if (!adev->mman.discovery_bin) {
-   DRM_ERROR("ip discovery uninitialized\n");
-   return -EINVAL;
-   }
 break;
 }

--
2.17.1

Re: [PATCH] drm/amdkfd: Fix indentation on switch statement

[Deucher, Alexander]

[AMD Official Use Only]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Graham Sider 

Sent: Tuesday, January 11, 2022 3:19 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Sider, Graham 
Subject: [PATCH] drm/amdkfd: Fix indentation on switch statement

Cases should be same indentation as switch. Also fix string spanning
across multiple lines.

Signed-off-by: Graham Sider 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 55 -
 1 file changed, 27 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 2b65d0acae2c..5a47f437b455 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -64,34 +64,33 @@ static void kfd_device_info_set_sdma_queue_num(struct 
kfd_dev *kfd)
 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0];

 switch (sdma_version) {
-   case IP_VERSION(4, 0, 0):/* VEGA10 */
-   case IP_VERSION(4, 0, 1):/* VEGA12 */
-   case IP_VERSION(4, 1, 0):/* RAVEN */
-   case IP_VERSION(4, 1, 1):/* RAVEN */
-   case IP_VERSION(4, 1, 2):/* RENOIR */
-   case IP_VERSION(5, 2, 1):/* VANGOGH */
-   case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
-   kfd->device_info.num_sdma_queues_per_engine = 2;
-   break;
-   case IP_VERSION(4, 2, 0):/* VEGA20 */
-   case IP_VERSION(4, 2, 2):/* ARCTURUS */
-   case IP_VERSION(4, 4, 0):/* ALDEBARAN */
-   case IP_VERSION(5, 0, 0):/* NAVI10 */
-   case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
-   case IP_VERSION(5, 0, 2):/* NAVI14 */
-   case IP_VERSION(5, 0, 5):/* NAVI12 */
-   case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
-   case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
-   case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
-   case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
-   kfd->device_info.num_sdma_queues_per_engine = 8;
-   break;
-   default:
-   dev_warn(kfd_device,
-   "Default sdma queue per engine(8) is set due to 
"
-   "mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
-sdma_version);
-   kfd->device_info.num_sdma_queues_per_engine = 8;
+   case IP_VERSION(4, 0, 0):/* VEGA10 */
+   case IP_VERSION(4, 0, 1):/* VEGA12 */
+   case IP_VERSION(4, 1, 0):/* RAVEN */
+   case IP_VERSION(4, 1, 1):/* RAVEN */
+   case IP_VERSION(4, 1, 2):/* RENOIR */
+   case IP_VERSION(5, 2, 1):/* VANGOGH */
+   case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
+   kfd->device_info.num_sdma_queues_per_engine = 2;
+   break;
+   case IP_VERSION(4, 2, 0):/* VEGA20 */
+   case IP_VERSION(4, 2, 2):/* ARCTURUS */
+   case IP_VERSION(4, 4, 0):/* ALDEBARAN */
+   case IP_VERSION(5, 0, 0):/* NAVI10 */
+   case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
+   case IP_VERSION(5, 0, 2):/* NAVI14 */
+   case IP_VERSION(5, 0, 5):/* NAVI12 */
+   case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
+   case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
+   case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
+   case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
+   kfd->device_info.num_sdma_queues_per_engine = 8;
+   break;
+   default:
+   dev_warn(kfd_device,
+   "Default sdma queue per engine(8) is set due to 
mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
+   sdma_version);
+   kfd->device_info.num_sdma_queues_per_engine = 8;
 }
 }

--
2.25.1

Re: [PATCH] drm/amdgpu: Enable recovery on yellow carp

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: VURDIGERENATARAJ, CHANDAN 
Sent: Tuesday, January 11, 2022 10:25 AM
To: Deucher, Alexander 
Cc: amd-gfx@lists.freedesktop.org ; 
VURDIGERENATARAJ, CHANDAN 
Subject: [PATCH] drm/amdgpu: Enable recovery on yellow carp

Add yellow carp to devices which support recovery

Signed-off-by: CHANDAN VURDIGERE NATARAJ 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f0fc015bd11e..2f519cbe7af9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -4473,6 +4473,7 @@ bool amdgpu_device_should_recover_gpu(struct 
amdgpu_device *adev)
 case CHIP_BEIGE_GOBY:
 case CHIP_VANGOGH:
 case CHIP_ALDEBARAN:
+   case CHIP_YELLOW_CARP:
 break;
 default:
 goto disabled;
--
2.25.1

Re: [PATCH 1/1] Add available memory ioctl for libhsakmt

[Deucher, Alexander]

[Public]

This is missing your signed-off-by.  Additionally, for UAPI changes, we need a 
link the patches for the userspace component that will make use of it.

Alex


From: amd-gfx  on behalf of Daniel 
Phillips 
Sent: Monday, January 10, 2022 3:54 PM
To: amd-gfx@lists.freedesktop.org ; 
dri-de...@lists.freedesktop.org 
Cc: Phillips, Daniel 
Subject: [PATCH 1/1] Add available memory ioctl for libhsakmt

From: Daniel Phillips 

Add an ioctl to inquire memory available for allocation by libhsakmt
per node, allowing for space consumed by page translation tables.
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h  |  1 +
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c| 14 ++
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c| 17 +
 include/uapi/linux/kfd_ioctl.h  | 14 --
 4 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index fcbc8a9c9e06..64c6c36685d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -266,6 +266,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct 
amdgpu_device *adev,
 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
 void *drm_priv);
 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
+size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev);
 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 struct amdgpu_device *adev, uint64_t va, uint64_t size,
 void *drm_priv, struct kgd_mem **mem,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 86a1a6c109d9..b7490a659173 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -190,6 +190,20 @@ static int amdgpu_amdkfd_reserve_mem_limit(struct 
amdgpu_device *adev,
 return ret;
 }

+size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev)
+{
+   uint64_t reserved_for_pt =
+   ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
+   size_t available_memory;
+
+   spin_lock(_mem_limit.mem_limit_lock);
+   available_memory =
+   adev->gmc.real_vram_size -
+   adev->kfd.vram_used - reserved_for_pt;
+   spin_unlock(_mem_limit.mem_limit_lock);
+   return available_memory;
+}
+
 static void unreserve_mem_limit(struct amdgpu_device *adev,
 uint64_t size, u32 alloc_flag)
 {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 4bfc0c8ab764..5c2f6d97ff1c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -486,6 +486,20 @@ static int kfd_ioctl_get_queue_wave_state(struct file 
*filep,
 return r;
 }

+static int kfd_ioctl_get_available_memory(struct file *filep,
+struct kfd_process *p, void *data)
+{
+   struct kfd_ioctl_get_available_memory_args *args = data;
+   struct kfd_dev *dev;
+
+   dev = kfd_device_by_id(args->gpu_id);
+   if (!dev)
+   return -EINVAL;
+
+   args->available = amdgpu_amdkfd_get_available_memory(dev->adev);
+   return 0;
+}
+
 static int kfd_ioctl_set_memory_policy(struct file *filep,
 struct kfd_process *p, void *data)
 {
@@ -1959,6 +1973,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {

 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE,
 kfd_ioctl_set_xnack_mode, 0),
+
+   AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY,
+   kfd_ioctl_get_available_memory, 0),
 };

 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h
index af96af174dc4..94a99add2432 100644
--- a/include/uapi/linux/kfd_ioctl.h
+++ b/include/uapi/linux/kfd_ioctl.h
@@ -32,9 +32,10 @@
  * - 1.4 - Indicate new SRAM EDC bit in device properties
  * - 1.5 - Add SVM API
  * - 1.6 - Query clear flags in SVM get_attr API
+ * - 1.7 - Add available_memory ioctl
  */
 #define KFD_IOCTL_MAJOR_VERSION 1
-#define KFD_IOCTL_MINOR_VERSION 6
+#define KFD_IOCTL_MINOR_VERSION 7

 struct kfd_ioctl_get_version_args {
 __u32 major_version;/* from KFD */
@@ -98,6 +99,12 @@ struct kfd_ioctl_get_queue_wave_state_args {
 __u32 pad;
 };

+struct kfd_ioctl_get_available_memory_args {
+   __u64 available;/* from KFD */
+   __u32 gpu_id;   /* to KFD */
+   __u32 pad;
+};
+
 /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
 #define KFD_IOC_CACHE_POLICY_COHERENT 0
 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
@@ -742,7 +749,10 @@ struct kfd_ioctl_set_xnack_mode_args {
 #define 

Re: [PATCH] drm/amdgpu: Fix unused variable warning

[Deucher, Alexander]

[Public]

Please add:
Fixes: 36324c09d848 ("drm/amdgpu: Modify sdma block to fit for the unified ras 
block data and ops")

With that,
Reviewed-by: Alex Deucher 

From: Tuikov, Luben 
Sent: Monday, January 10, 2022 3:32 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Tuikov, Luben ; Deucher, Alexander 

Subject: [PATCH] drm/amdgpu: Fix unused variable warning

Fix this:

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c: In function 
‘amdgpu_ras_query_error_status’:
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:945:6: warning: unused variable ‘i’ 
[-Wunused-variable]
  945 |  int i;

Cc: Alex Deucher 
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Luben Tuikov 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index b1bedfd4febc4b..517650d286a722 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -942,7 +942,6 @@ int amdgpu_ras_query_error_status(struct amdgpu_device 
*adev,
 struct amdgpu_ras_block_object* block_obj = NULL;
 struct ras_manager *obj = amdgpu_ras_find_obj(adev, >head);
 struct ras_err_data err_data = {0, 0, 0, NULL};
-   int i;

 if (!obj)
 return -EINVAL;

base-commit: 9b7d59707fe1ff51cdfa0a048629446ff3945bfd
--
2.34.0

Re: [PATCH] drm/amd/display: Not to call dpcd_set_source_specific_data during resume.

[Deucher, Alexander]

[Public]

Seems reasonable.

Acked-by: Alex Deucher 

From: Mahapatra, Rajib 
Sent: Monday, January 10, 2022 4:06 AM
To: Wu, Hersen ; Wentland, Harry ; 
Deucher, Alexander 
Cc: amd-gfx@lists.freedesktop.org ; S, Shirish 
; Mahapatra, Rajib 
Subject: [PATCH] drm/amd/display: Not to call dpcd_set_source_specific_data 
during resume.

[Why]
During resume path, dpcd_set_source_specific_data is taking
extra time when core_link_write_dpcd fails on DP_SOURCE_OUI+0x03
and DP_SOURCE_MINIMUM_HBLANK_SUPPORTED. Here,aux->transfer fails
with multiple retries and consume sigficantamount time during
S0i3 resume.

[How]
Not to call dpcd_set_source_specific_data during resume path
when there is no oled panel connected and achieve faster resume
during S0i3.

Signed-off-by: Rajib Mahapatra 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c0bdc23702c8..04086c199dbb 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -892,7 +892,8 @@ static bool dc_link_detect_helper(struct dc_link *link,
 (!link->dc->config.allow_edp_hotplug_detection)) &&
 link->local_sink) {
 // need to re-write OUI and brightness in resume case
-   if (link->connector_signal == SIGNAL_TYPE_EDP) {
+   if (link->connector_signal == SIGNAL_TYPE_EDP &&
+   (link->dpcd_sink_ext_caps.bits.oled == 1)) {
 dpcd_set_source_specific_data(link);
 msleep(post_oui_delay);
 dc_link_set_default_brightness_aux(link);
--
2.25.1

Re: [PATCH] drm/amdgpu: use spin_lock_irqsave to avoid deadlock by local interrupt

[Deucher, Alexander]

[AMD Official Use Only]

Acked-by: Alex Deucher 

From: Chen, Guchun 
Sent: Monday, January 10, 2022 12:13 AM
To: amd-gfx@lists.freedesktop.org ; Deucher, 
Alexander ; Koenig, Christian 
; Pan, Xinhui ; Zytaruk, Kelly 
; Huang, Qiliang (Warden) ; 
Zhang, Bokun 
Cc: Chen, Guchun 
Subject: [PATCH] drm/amdgpu: use spin_lock_irqsave to avoid deadlock by local 
interrupt

This is observed in SRIOV case with virtual KMS as display.

_raw_spin_lock_irqsave+0x37/0x40
drm_handle_vblank+0x69/0x350 [drm]
? try_to_wake_up+0x432/0x5c0
? amdgpu_vkms_prepare_fb+0x1c0/0x1c0 [amdgpu]
drm_crtc_handle_vblank+0x17/0x20 [drm]
amdgpu_vkms_vblank_simulate+0x4d/0x80 [amdgpu]
__hrtimer_run_queues+0xfb/0x230
hrtimer_interrupt+0x109/0x220
__sysvec_apic_timer_interrupt+0x64/0xe0
asm_call_irq_on_stack+0x12/0x20

Fixes: ba5317109d0c("drm/amdgpu: create amdgpu_vkms (v4)")
Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index 2dcc68e04e84..d99c8779b51e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -144,15 +144,16 @@ static void amdgpu_vkms_crtc_atomic_disable(struct 
drm_crtc *crtc,
 static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc,
   struct drm_atomic_state *state)
 {
+   unsigned long flags;
 if (crtc->state->event) {
-   spin_lock(>dev->event_lock);
+   spin_lock_irqsave(>dev->event_lock, flags);

 if (drm_crtc_vblank_get(crtc) != 0)
 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 else
 drm_crtc_arm_vblank_event(crtc, crtc->state->event);

-   spin_unlock(>dev->event_lock);
+   spin_unlock_irqrestore(>dev->event_lock, flags);

 crtc->state->event = NULL;
 }
--
2.17.1

Re: [PATCH] drm/amd/amdgpu: Add pcie indirect support to amdgpu_mm_wreg_mmio_rlc()

[Deucher, Alexander]

[AMD Official Use Only]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Tom St Denis 

Sent: Friday, January 7, 2022 7:07 AM
To: amd-gfx@lists.freedesktop.org 
Cc: StDenis, Tom 
Subject: [PATCH] drm/amd/amdgpu: Add pcie indirect support to 
amdgpu_mm_wreg_mmio_rlc()

The function amdgpu_mm_wreg_mmio_rlc() is used by debugfs to write to
MMIO registers.  It didn't support registers beyond the BAR mapped MMIO
space.  This adds pcie indirect write support.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c38e0e87090b..53a04095a6db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -552,7 +552,7 @@ void amdgpu_device_wreg(struct amdgpu_device *adev,
 }

 /**
- * amdgpu_mm_wreg_mmio_rlc -  write register either with mmio or with RLC path 
if in range
+ * amdgpu_mm_wreg_mmio_rlc -  write register either with direct/indirect mmio 
or with RLC path if in range
  *
  * this function is invoked only the debugfs register access
  */
@@ -567,6 +567,8 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
 adev->gfx.rlc.funcs->is_rlcg_access_range) {
 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
 return adev->gfx.rlc.funcs->sriov_wreg(adev, reg, v, 
0, 0);
+   } else if ((reg * 4) >= adev->rmmio_size) {
+   adev->pcie_wreg(adev, reg * 4, v);
 } else {
 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 }
--
2.32.0

RE: [PATCH v2] drm/amdgpu: Enable second VCN for certain Navy Flounder.

[Deucher, Alexander]

[Public]

> -Original Message-
> From: amd-gfx  On Behalf Of
> Peng Ju Zhou
> Sent: Thursday, January 6, 2022 2:30 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: [PATCH v2] drm/amdgpu: Enable second VCN for certain Navy
> Flounder.
> 
> Certain Navy Flounder cards have 2 VCNs, enable it.
> 
> Signed-off-by: Peng Ju Zhou 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 580a5b387122..57e001d73ec9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -550,7 +550,8 @@ void amdgpu_discovery_harvest_ip(struct
> amdgpu_device *adev)
>   }
>   /* some IP discovery tables on Navy Flounder don't have this set
> correctly */
>   if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
> - (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2)))
> + (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2)) &&
> + (adev->pdev->revision != 0xFF))

We added this check because some navy flounder boards did not correctly set the 
harvesting in the IP discovery table.  It would be nice to sort that out so we 
only enable this workaround on the boards with the bad harvest table.  I 
suppose that would probably come down to the PCI revision anyway, so this is 
probably fine.

Acked-by: Alex Deucher 


>   adev->vcn.harvest_config |=
> AMDGPU_VCN_HARVEST_VCN1;
>   if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
>   adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
> --
> 2.33.1

RE: [PATCH] drm/amdgpu: Use correct VIEWPORT_DIMENSION for DCN2

[Deucher, Alexander]

[Public]

> -Original Message-
> From: amd-gfx  On Behalf Of
> Harry Wentland
> Sent: Wednesday, January 5, 2022 3:39 PM
> To: amd-gfx@lists.freedesktop.org; Koenig, Christian
> ; Lee, Becle ; Huang,
> Rex ; Huang, Ray 
> Cc: Wentland, Harry 
> Subject: [PATCH] drm/amdgpu: Use correct VIEWPORT_DIMENSION for
> DCN2
> 
> For some reason this file isn't using the appropriate register headers for DCN
> headers, which means that on DCN2 we're getting the
> VIEWPORT_DIMENSION offset wrong.
> 
> This means that we're not correctly carving out the framebuffer memory
> correctly for a framebuffer allocated by EFI and therefore see corruption
> when loading amdgpu before the display driver takes over control of the
> framebuffer scanout.
> 
> Fix this by checking the DCE_HWIP and picking the correct offset accordingly.
> 
> Long-term we should expose this info from DC as GMC shouldn't need to
> know about DCN registers.
> 
> Signed-off-by: Harry Wentland 
> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 57f2729a7bd0..8367ecf61af1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -72,6 +72,9 @@
>  #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0
> 0x049d
>  #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX
> 2
> 
> +#define DCN2_mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
> 0x05ea
> +#define
> DCN2_mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX
> 2
> +

We normally append the _DCN2 to the end in these cases of the macro.  With that 
fixed,
Reviewed-by: Alex Deucher 

> 
>  static const char *gfxhub_client_ids[] = {
>   "CB",
> @@ -1142,7 +1145,6 @@ static unsigned
> gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
>   switch (adev->ip_versions[DCE_HWIP][0]) {
>   case IP_VERSION(1, 0, 0):
>   case IP_VERSION(1, 0, 1):
> - case IP_VERSION(2, 1, 0):
>   viewport = RREG32_SOC15(DCE, 0,
> mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
>   size = (REG_GET_FIELD(viewport,
> 
> HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
> @@ -1150,6 +1152,14 @@ static unsigned
> gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
> 
> HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
>   4);
>   break;
> + case IP_VERSION(2, 1, 0):
> + viewport = RREG32_SOC15(DCE, 0,
> DCN2_mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
> + size = (REG_GET_FIELD(viewport,
> +
> HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
> + REG_GET_FIELD(viewport,
> +
> HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
> + 4);
> + break;
>   default:
>   viewport = RREG32_SOC15(DCE, 0,
> mmSCL0_VIEWPORT_SIZE);
>   size = (REG_GET_FIELD(viewport,
> SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
> --
> 2.34.1

Re: [PATCH 2/2] drm/amdgpu: don't set s3 and s0ix at the same time

[Deucher, Alexander]

[AMD Official Use Only]

I don't think this will work properly.  The in_s3 flag was mainly for runtime 
pm vs system suspend.  I'm not sure if in_s0ix is properly handled everywhere 
we check in_s3.

Alex


From: amd-gfx  on behalf of Mario 
Limonciello 
Sent: Monday, January 3, 2022 10:23 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Limonciello, Mario 
Subject: [PATCH 2/2] drm/amdgpu: don't set s3 and s0ix at the same time

This makes it clearer which codepaths are in use specifically in
one state or the other.

Signed-off-by: Mario Limonciello 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index db2a9dfd5918..413fecc89e6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -2165,9 +2165,9 @@ static int amdgpu_pmops_suspend(struct device *dev)

 if (amdgpu_acpi_is_s0ix_active(adev))
 adev->in_s0ix = true;
-   adev->in_s3 = true;
+   else
+   adev->in_s3 = true;
 r = amdgpu_device_suspend(drm_dev, true);
-   adev->in_s3 = false;
 if (r)
 return r;
 if (!adev->in_s0ix)
@@ -2188,6 +2188,8 @@ static int amdgpu_pmops_resume(struct device *dev)
 r = amdgpu_device_resume(drm_dev, true);
 if (amdgpu_acpi_is_s0ix_active(adev))
 adev->in_s0ix = false;
+   else
+   adev->in_s3 = false;
 return r;
 }

--
2.25.1

Re: [PATCH 1/2] drm/amdgpu: explicitly check for s0ix when evicting resources

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Mario 
Limonciello 
Sent: Monday, January 3, 2022 10:23 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Limonciello, Mario 
Subject: [PATCH 1/2] drm/amdgpu: explicitly check for s0ix when evicting 
resources

This codepath should be running in both s0ix and s3, but only does
currently because s3 and s0ix are both set in the s0ix case.

Signed-off-by: Mario Limonciello 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ce93a304292c..412f377f80b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3956,8 +3956,8 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)
  */
 static void amdgpu_device_evict_resources(struct amdgpu_device *adev)
 {
-   /* No need to evict vram on APUs for suspend to ram */
-   if (adev->in_s3 && (adev->flags & AMD_IS_APU))
+   /* No need to evict vram on APUs for suspend to ram or s2idle */
+   if ((adev->in_s3 || adev->in_s0ix) && (adev->flags & AMD_IS_APU))
 return;

 if (amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM))
--
2.25.1

RE: Expecting to revert commit 55285e21f045 "fbdev/efifb: Release PCI device ..."

[Deucher, Alexander]

[Public]

> -Original Message-
> From: Deucher, Alexander
> Sent: Tuesday, December 21, 2021 12:01 PM
> To: Linus Torvalds ; Imre Deak
> ; amd-gfx@lists.freedesktop.org
> Cc: Daniel Vetter ; Kai-Heng Feng
> 
> Subject: RE: Expecting to revert commit 55285e21f045 "fbdev/efifb: Release
> PCI device ..."
> 
> [Public]
> 
> > -Original Message-
> > From: Linus Torvalds 
> > Sent: Monday, December 20, 2021 5:05 PM
> > To: Imre Deak 
> > Cc: Daniel Vetter ; Deucher, Alexander
> > ; Kai-Heng Feng
> > 
> > Subject: Re: Expecting to revert commit 55285e21f045 "fbdev/efifb:
> > Release PCI device ..."
> >
> > On Mon, Dec 20, 2021 at 1:33 PM Imre Deak 
> wrote:
> > >
> > > amdgpu.runpm=0
> >
> > Hmmm.
> >
> > This does seem to "work", but not very well.
> >
> > With this, what seems to happen is odd: I lock the screen, wait, it
> > goes "No signal, shutting down", but then doesn't actually shut down
> > but stays black (with the backlight on). After _another_ five seconds
> > or so, the monitor goes "No signal, shutting down" _again_, and at that
> point it actually does it.
> >
> > So it solves my immediate problem - in that yes, the backlight finally
> > does turn off in the end - but it does seem to be still broken.
> >
> > I'm very surprised if no AMD drm developers can see this exact same thing.
> > This is a very simple setup. The only possibly slightly less common
> > thing is that I have two monitors, but while that is not necessarily
> > the _most_ common setup in an absolute sense, I'd expect it to be very
> > common among DRM developers..
> >
> > I guess I can just change the revert to just a
> >
> > -int amdgpu_runtime_pm = -1;
> > +int amdgpu_runtime_pm = 0;
> >
> > instead. The auto-detect is apparently broken. Maybe it should only
> > kick in for LVDS screens on actual laptops?
> >
> > Note: on my machine, I get that
> >
> >amdgpu :49:00.0: amdgpu: Using BACO for runtime pm
> >
> > so maybe the other possible runtime pm models (ARPX and BOCO) are ok,
> > and it's only that BACO case that is broken.
> >
> > I have no idea what any of those three things are - I'm just looking
> > at the uses of that amdgpu_runtime_pm variable.
> >
> > amdgpu people: if you don't want that amdgpu_runtime_pm turned off by
> > default, tell me something else to try.
> 
> For a little background, runtime PM support was added about 10 year ago
> originally to support laptops with multiple GPUs (integrated and discrete).
> It's not specific to the display hardware.  When the GPU is idle, it can be
> powered down completely.  In the case of these laptops, it's D3 cold
> (managed by ACPI, we call this BOCO in AMD parlance - Bus Off, Chip Off)
> which powers off the dGPU completely (i.e., it disappears from the bus).  A
> few years ago we extended this to support desktop dGPUs as well which
> support their own version of runtime D3 (called BACO in AMD parlance - Bus
> Active, Chip Off).  The driver can put the chip into a low power state where
> everything except the bus interface is powered down (to avoid the device
> disappearing from the bus).  So this has worked for almost 2 years now on
> BACO capable parts and for a decade or more on BOCO systems.
> Unfortunately, changing the default runpm parameter setting would cause a
> flood of bug reports about runtime power management breaking and
> suddenly systems are using more power.
> 
> Imre's commit (55285e21f045) fixes another commit (a6c0fd3d5a8b).
> Runtime pm was working on amdgpu prior to that commit.  Is it possible
> there is still some race between when amdgpu takes over from efifb?  Does
> it work properly when all pm_runtime calls in efifb are removed or if efifb is
> not enabled?  Runtime pm for Polaris boards has been enabled by default
> since 4fdda2e66de0b which predates both of those patches.

Thinking about this more, I wonder if there was some change in some userspace 
component which was hidden by the changes in 55285e21f045 and a6c0fd3d5a8b.  
E.g., some desktop component started polling for display changes or GPU 
temperature or something like that and when a6c0fd3d5a8b was in place the GPU 
never entered runtime suspend.  Then when 55285e21f045 was applied, it unmasked 
the new behavior in the userpace component.

What should happen is that when all of the displays blank, assuming the GPU is 
otherwise idle, the GPU will runtime suspend after  seconds.  When you move the 
mouse or hit the keyboard, that should trigger the GPU should runtime resume 
an

RE: Expecting to revert commit 55285e21f045 "fbdev/efifb: Release PCI device ..."

[Deucher, Alexander]

[Public]

> -Original Message-
> From: Linus Torvalds 
> Sent: Monday, December 20, 2021 5:21 PM
> To: Imre Deak ; Koenig, Christian
> ; Pan, Xinhui ;
> Wentland, Harry 
> Cc: Daniel Vetter ; Deucher, Alexander
> ; Kai-Heng Feng
> ; amd-gfx list  g...@lists.freedesktop.org>
> Subject: Re: Expecting to revert commit 55285e21f045 "fbdev/efifb: Release
> PCI device ..."
> 
> [ Adding back in more amd people and the amd list, the people Daniel added
> seem to have gotten lost again, but I think people at least saw my original
> report thanks to Daniel ]
> 
> With "amdgpu.runpm=0", things are better, but not perfect. With that I can
> lock the screen, and it has to go through *two* cycles of "No signal, turning
> off", but on the second cycle it does finally work.
> 
> This was exposed by commit 55285e21f045 ("fbdev/efifb: Release PCI
> device's runtime PM ref during FB destroy"), probably because that made
> runtime PM actually potentially work, but it is then broken on amdgpu.
> 
> Absolutely nothing odd in my setup. Two monitors, one GPU. PCI ID
> 1002:67df rev e7, subsystem ID 1da2:e353.
> 
> I'd expect pretty much any amdgpu person to see this.
> 
> On Mon, Dec 20, 2021 at 2:04 PM Linus Torvalds  foundation.org> wrote:
> >
> > Note: on my machine, I get that
> >
> >amdgpu :49:00.0: amdgpu: Using BACO for runtime pm
> >
> > so maybe the other possible runtime pm models (ARPX and BOCO) are ok,
> > and it's only that BACO case that is broken.
> 
> Hmm. The *documentation* says:
> 
> PX runtime pm
> 2 = force enable with BAMACO,
> 1 = force enable with BACO,
> 0 = disable,
> -1 = PX only default
> 
> but the code actually makes anything != 0 enable it, except on VEGA20 and
> ARCTURUS, where it needs to be positive.
> 
> My card is apparently "POLARIS10", whatever that means, which means that
> any non-zero value of amdgpu_runtime_pm will enable runtime PM as long
> as "amdgpu_device_supports_baco()" is true. Which it is.
> 
> Whatever. Now I'm just kwetching about the documentation not matching
> what I see the code doing, which is never a great sign when things don't
> work.

Apologies on the documentation.  -1 is the default and is enabled for all dGPUs 
which support runtime D3.  It was never fixed up when we extended support for 
runtime pm beyond PX/HG laptops.  Fixed up the documentation here:
https://patchwork.freedesktop.org/patch/467681/

Alex

RE: Expecting to revert commit 55285e21f045 "fbdev/efifb: Release PCI device ..."

[Deucher, Alexander]

[Public]

> -Original Message-
> From: Linus Torvalds 
> Sent: Monday, December 20, 2021 5:05 PM
> To: Imre Deak 
> Cc: Daniel Vetter ; Deucher, Alexander
> ; Kai-Heng Feng
> 
> Subject: Re: Expecting to revert commit 55285e21f045 "fbdev/efifb: Release
> PCI device ..."
> 
> On Mon, Dec 20, 2021 at 1:33 PM Imre Deak  wrote:
> >
> > amdgpu.runpm=0
> 
> Hmmm.
> 
> This does seem to "work", but not very well.
> 
> With this, what seems to happen is odd: I lock the screen, wait, it goes "No
> signal, shutting down", but then doesn't actually shut down but stays black
> (with the backlight on). After _another_ five seconds or so, the monitor goes
> "No signal, shutting down" _again_, and at that point it actually does it.
> 
> So it solves my immediate problem - in that yes, the backlight finally does
> turn off in the end - but it does seem to be still broken.
> 
> I'm very surprised if no AMD drm developers can see this exact same thing.
> This is a very simple setup. The only possibly slightly less common thing is 
> that
> I have two monitors, but while that is not necessarily the _most_ common
> setup in an absolute sense, I'd expect it to be very common among DRM
> developers..
> 
> I guess I can just change the revert to just a
> 
> -int amdgpu_runtime_pm = -1;
> +int amdgpu_runtime_pm = 0;
> 
> instead. The auto-detect is apparently broken. Maybe it should only kick in
> for LVDS screens on actual laptops?
> 
> Note: on my machine, I get that
> 
>amdgpu :49:00.0: amdgpu: Using BACO for runtime pm
> 
> so maybe the other possible runtime pm models (ARPX and BOCO) are ok,
> and it's only that BACO case that is broken.
> 
> I have no idea what any of those three things are - I'm just looking at the
> uses of that amdgpu_runtime_pm variable.
> 
> amdgpu people: if you don't want that amdgpu_runtime_pm turned off by
> default, tell me something else to try.

For a little background, runtime PM support was added about 10 year ago 
originally to support laptops with multiple GPUs (integrated and discrete).  
It's not specific to the display hardware.  When the GPU is idle, it can be 
powered down completely.  In the case of these laptops, it's D3 cold (managed 
by ACPI, we call this BOCO in AMD parlance - Bus Off, Chip Off) which powers 
off the dGPU completely (i.e., it disappears from the bus).  A few years ago we 
extended this to support desktop dGPUs as well which support their own version 
of runtime D3 (called BACO in AMD parlance - Bus Active, Chip Off).  The driver 
can put the chip into a low power state where everything except the bus 
interface is powered down (to avoid the device disappearing from the bus).  So 
this has worked for almost 2 years now on BACO capable parts and for a decade 
or more on BOCO systems.  Unfortunately, changing the default runpm parameter 
setting would cause a flood of bug reports about runtime power management 
breaking and suddenly systems are using more power.

Imre's commit (55285e21f045) fixes another commit (a6c0fd3d5a8b).  Runtime pm 
was working on amdgpu prior to that commit.  Is it possible there is still some 
race between when amdgpu takes over from efifb?  Does it work properly when all 
pm_runtime calls in efifb are removed or if efifb is not enabled?  Runtime pm 
for Polaris boards has been enabled by default since 4fdda2e66de0b which 
predates both of those patches.

Alex

Re: [PATCH 10/19] drm/amd/display: Changed pipe split policy to allow for multi-display pipe split

[Deucher, Alexander]

[AMD Official Use Only]

Maybe add Bug links for:
https://gitlab.freedesktop.org/drm/amd/-/issues/1522
https://gitlab.freedesktop.org/drm/amd/-/issues/1709
https://gitlab.freedesktop.org/drm/amd/-/issues/1655
https://gitlab.freedesktop.org/drm/amd/-/issues/1403





From: amd-gfx  on behalf of Rodrigo 
Siqueira 
Sent: Friday, December 17, 2021 4:23 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Wang, Chao-kai (Stylon) ; Cyr, Aric 
; Li, Sun peng (Leo) ; Wentland, Harry 
; Zhuo, Qingqing (Lillian) ; 
Siqueira, Rodrigo ; Li, Roman ; 
Chiu, Solomon ; Pillai, Aurabindo 
; Wang, Angus ; Lin, Wayne 
; Lipski, Mikita ; Lakha, Bhawanpreet 
; Gutierrez, Agustin ; 
Kotarac, Pavle 
Subject: [PATCH 10/19] drm/amd/display: Changed pipe split policy to allow for 
multi-display pipe split

From: Angus Wang 

[WHY]
Current implementation of pipe split policy prevents pipe split with
multiple displays connected, which caused the MCLK speed to be stuck at
max

[HOW]
Changed the pipe split policies so that pipe split is allowed for
multi-display configurations

Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
Signed-off-by: Angus Wang 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c   | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2a72517e2b28..2bc93df023ad 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1069,7 +1069,7 @@ static const struct dc_debug_options debug_defaults_drv = 
{
 .timing_trace = false,
 .clock_trace = true,
 .disable_pplib_clock_request = true,
-   .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+   .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 .force_single_disp_pipe_split = false,
 .disable_dcc = DCC_ENABLE,
 .vsr_support = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
index d6acf9a8590a..0bb7d3dd53fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c
@@ -603,7 +603,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 .timing_trace = false,
 .clock_trace = true,
 .disable_pplib_clock_request = true,
-   .pipe_split_policy = MPC_SPLIT_AVOID,
+   .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 .force_single_disp_pipe_split = false,
 .disable_dcc = DCC_ENABLE,
 .vsr_support = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index ca1bbc942fd4..e5cc6bf45743 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -873,7 +873,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 .clock_trace = true,
 .disable_pplib_clock_request = true,
 .min_disp_clk_khz = 10,
-   .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+   .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 .force_single_disp_pipe_split = false,
 .disable_dcc = DCC_ENABLE,
 .vsr_support = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 369ceeeddc7e..e12660c609ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -840,7 +840,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 .timing_trace = false,
 .clock_trace = true,
 .disable_pplib_clock_request = true,
-   .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
+   .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 .force_single_disp_pipe_split = false,
 .disable_dcc = DCC_ENABLE,
 .vsr_support = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index b4001233867c..c1c6e602b06c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -686,7 +686,7 

Re: [PATCH 4/4] drm/amdgpu: Access the FRU on Aldebaran

[Deucher, Alexander]

[AMD Official Use Only]

Series is:
Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Kent Russell 

Sent: Friday, December 17, 2021 10:31 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Russell, Kent 
Subject: [PATCH 4/4] drm/amdgpu: Access the FRU on Aldebaran

This is supported, although the offset is different from VG20, so fix
that with a variable and enable getting the product name and serial
number from the FRU. Do this for all SKUs since all SKUs have the FRU

Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index 5ed24701f9cf..80f43e69e659 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -56,6 +56,9 @@ static bool is_fru_eeprom_supported(struct amdgpu_device 
*adev)
 return true;
 else
 return false;
+   case CHIP_ALDEBARAN:
+   /* All Aldebaran SKUs have the FRU */
+   return true;
 default:
 return false;
 }
@@ -91,6 +94,10 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
 unsigned char buff[PRODUCT_NAME_LEN+2];
 u32 addrptr;
 int size, len;
+   int offset = 2;
+
+   if (adev->asic_type == CHIP_ALDEBARAN)
+   offset = 0;

 if (!is_fru_eeprom_supported(adev))
 return 0;
@@ -137,7 +144,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
 len = PRODUCT_NAME_LEN - 1;
 }
 /* Start at 2 due to buff using fields 0 and 1 for the address */
-   memcpy(adev->product_name, [2], len);
+   memcpy(adev->product_name, [offset], len);
 adev->product_name[len] = '\0';

 addrptr += size + 1;
@@ -155,7 +162,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
 DRM_WARN("FRU Product Number is larger than 16 characters. 
This is likely a mistake");
 len = sizeof(adev->product_number) - 1;
 }
-   memcpy(adev->product_number, [2], len);
+   memcpy(adev->product_number, [offset], len);
 adev->product_number[len] = '\0';

 addrptr += size + 1;
@@ -182,7 +189,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
 DRM_WARN("FRU Serial Number is larger than 16 characters. This 
is likely a mistake");
 len = sizeof(adev->serial) - 1;
 }
-   memcpy(adev->serial, [2], len);
+   memcpy(adev->serial, [offset], len);
 adev->serial[len] = '\0';

 return 0;
--
2.25.1

Re: [PATCH] drm/amdgpu: Try To using WARN() instead BUG() avoid kernel panic

[Deucher, Alexander]

[Public]

I think these are pretty fundamental errors.  You should never hit them in 
practice and if you do, I think a BUG is fine.

Alex


From: ZhiJie.Zhang 
Sent: Thursday, December 16, 2021 9:38 PM
To: Koenig, Christian ; Deucher, Alexander 
; amd-gfx@lists.freedesktop.org 

Cc: zhangzhi...@loongson.cn ; botton_zh...@163.com 
; airl...@linux.ie ; dan...@ffwll.ch 
; jack.zha...@amd.com 
Subject: [PATCH] drm/amdgpu: Try To using WARN() instead BUG() avoid kernel 
panic

Signed-off-by: ZhiJie.Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c|  4 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 +++---
 drivers/gpu/drm/amd/amdgpu/cik_sdma.c  |  5 +++-
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c  | 18 +
 4 files changed, 41 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index f1a050379190..edf2de4cec8c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -76,7 +76,7 @@ static uint32_t amdgpu_cgs_read_ind_register(struct 
cgs_device *cgs_device,
 DRM_ERROR("audio endpt register access not implemented.\n");
 return 0;
 default:
-   BUG();
+   adev->accel_working = false;
 }
 WARN(1, "Invalid indirect register space");
 return 0;
@@ -104,9 +104,9 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device 
*cgs_device,
 DRM_ERROR("audio endpt register access not implemented.\n");
 return;
 default:
-   BUG();
 }
 WARN(1, "Invalid indirect register space");
+   adev->accel_working = false;
 }

 static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t 
fw_type)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 188accb71249..b9ecf7f70409 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -488,7 +488,11 @@ uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, 
uint32_t offset)

 if (offset < adev->rmmio_size)
 return (readb(adev->rmmio + offset));
-   BUG();
+
+   WARN(1, "Invalid indirect register space");
+   adev->accel_working = false;
+
+   return 0;
 }

 /*
@@ -513,8 +517,10 @@ void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t 
offset, uint8_t value)

 if (offset < adev->rmmio_size)
 writeb(value, adev->rmmio + offset);
-   else
-   BUG();
+   else {
+   WARN(1, "Invalid indirect register space");
+   adev->accel_working = false;
+   }
 }

 /**
@@ -803,7 +809,8 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device 
*adev,
 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 {
 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
-   BUG();
+
+   adev->accel_working = false;
 return 0;
 }

@@ -821,7 +828,8 @@ static void amdgpu_invalid_wreg(struct amdgpu_device *adev, 
uint32_t reg, uint32
 {
 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
   reg, v);
-   BUG();
+
+   adev->accel_working = false;
 }

 /**
@@ -837,7 +845,8 @@ static void amdgpu_invalid_wreg(struct amdgpu_device *adev, 
uint32_t reg, uint32
 static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg)
 {
 DRM_ERROR("Invalid callback to read 64 bit register 0x%04X\n", reg);
-   BUG();
+
+   adev->accel_working = false;
 return 0;
 }

@@ -855,7 +864,8 @@ static void amdgpu_invalid_wreg64(struct amdgpu_device 
*adev, uint32_t reg, uint
 {
 DRM_ERROR("Invalid callback to write 64 bit register 0x%04X with 
0x%08llX\n",
   reg, v);
-   BUG();
+
+   adev->accel_working = false;
 }

 /**
@@ -874,7 +884,9 @@ static uint32_t amdgpu_block_invalid_rreg(struct 
amdgpu_device *adev,
 {
 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
   reg, block);
-   BUG();
+
+   adev->accel_working = false;
+
 return 0;
 }

@@ -895,7 +907,8 @@ static void amdgpu_block_invalid_wreg(struct amdgpu_device 
*adev,
 {
 DRM_ERROR("Invalid block callback to write register 0x%04X in block 
0x%04X with 0x%08X\n",
   reg, block, v);
-   BUG();
+
+   adev->accel_working = false;
 }

 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c 
b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index c8ebd108548d..957169142e57 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -129,7 +129,10 @@ sta

Re: [PATCH 4/5] drm/amdgpu: Initialize Aldebaran RLC function pointers

[Deucher, Alexander]

[Public]

If it needs to be in drm-next, please make sure it lands there.

Alex


From: amd-gfx  on behalf of Liu, Shaoyun 

Sent: Thursday, December 16, 2021 12:51 PM
To: Skvortsov, Victor ; Alex Deucher 

Cc: Ming, Davis ; Chen, JingWen ; 
amd-gfx list ; Deng, Emily ; 
Chen, Horace ; Liu, Monk ; Nieto, David 
M 
Subject: RE: [PATCH 4/5] drm/amdgpu: Initialize Aldebaran RLC function pointers

[AMD Official Use Only]

Actually I don't know why  the change " a35f147621bc drm/amdgpu: get xgmi info 
at eary_init " not in drm-next , instead it’s in amd-mainline-dkms-5.13.
That change is necessary for passthrough XGMI hive  to a VM and rely on our 
driver to do the reset on whole hive  when driver is loaded .

I checked the code again,  it seems we should be ok as long as we get xgmi info 
at eary_init.  So since gfx_v9_0_set_rlc_funcs() already gets called in 
gfx_v9_0_early_init(), we can  move get xgmi info out of gmc_early_init and 
call  it at the last step  early_init .

Regards
Shaoyun.liu

-Original Message-
From: Skvortsov, Victor 
Sent: Thursday, December 16, 2021 9:28 AM
To: Alex Deucher 
Cc: amd-gfx list ; Deng, Emily 
; Liu, Monk ; Ming, Davis 
; Liu, Shaoyun ; Zhou, Peng Ju 
; Chen, JingWen ; Chen, Horace 
; Nieto, David M 
Subject: RE: [PATCH 4/5] drm/amdgpu: Initialize Aldebaran RLC function pointers

[AMD Official Use Only]

Gotcha, I will skip this patch for drm-next

-Original Message-
From: Alex Deucher 
Sent: Thursday, December 16, 2021 8:53 AM
To: Skvortsov, Victor 
Cc: amd-gfx list ; Deng, Emily 
; Liu, Monk ; Ming, Davis 
; Liu, Shaoyun ; Zhou, Peng Ju 
; Chen, JingWen ; Chen, Horace 
; Nieto, David M 
Subject: Re: [PATCH 4/5] drm/amdgpu: Initialize Aldebaran RLC function pointers

[CAUTION: External Email]

On Wed, Dec 15, 2021 at 6:58 PM Skvortsov, Victor  
wrote:
>
> [AMD Official Use Only]
>
> Hey Alex,
>
> This change was based on the fact that amd-mainline-dkms-5.13 calls 
> get_xgmi_info() in gmc_v9_0_early_init(). But I can see that drm-next it's 
> instead called in gmc_v9_0_sw_init(). So, I'm not sure whats the correct 
> behavior. But I do agree that the change is kind of ugly. I don't know where 
> else to put it if we do need to call get_xgmi_info() in early_init.
>

We could skip this patch for drm-next and just apply it to the dkms branch.  
There's already a lot of ugly stuff in there to deal with multiple kernel 
versions.

Alex


> Thanks,
> Victor
>
> -Original Message-
> From: Alex Deucher 
> Sent: Wednesday, December 15, 2021 4:38 PM
> To: Skvortsov, Victor 
> Cc: amd-gfx list ; Deng, Emily
> ; Liu, Monk ; Ming, Davis
> ; Liu, Shaoyun ; Zhou, Peng
> Ju ; Chen, JingWen ; Chen,
> Horace ; Nieto, David M 
> Subject: Re: [PATCH 4/5] drm/amdgpu: Initialize Aldebaran RLC function
> pointers
>
> [CAUTION: External Email]
>
> On Wed, Dec 15, 2021 at 1:56 PM Victor Skvortsov  
> wrote:
> >
> > In SRIOV, RLC function pointers must be initialized early as we rely
> > on the RLCG interface for all GC register access.
> >
> > Signed-off-by: Victor Skvortsov 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 ++
> >  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +--
> >  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 2 ++
> >  3 files changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > index 65e1f6cc59dd..1bc92a38d124 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> > @@ -844,6 +844,8 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct 
> > amdgpu_device *adev)
> > case IP_VERSION(9, 4, 1):
> > case IP_VERSION(9, 4, 2):
> > amdgpu_device_ip_block_add(adev,
> > _v9_0_ip_block);
> > +   if (amdgpu_sriov_vf(adev) && adev->ip_versions[GC_HWIP][0] 
> > == IP_VERSION(9, 4, 2))
> > +   gfx_v9_0_set_rlc_funcs(adev);
>
> amdgpu_discovery.c is IP independent.  I'd rather not add random IP specific 
> function calls.  gfx_v9_0_set_rlc_funcs() already gets called in 
> gfx_v9_0_early_init().  Is that not early enough?  In general we shouldn't be 
> touching the hardware much if at all in early_init.
>
> Alex
>
> > break;
> > case IP_VERSION(10, 1, 10):
> > case IP_VERSION(10, 1, 2):
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index edb3e3b08eed..d252b06efa43 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -816,7 +816,6 @@ static void gfx_v9_0_sriov_wreg(struct
> > amdgpu_device *adev, u32 offset,  static void
> > gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);  static void
> > gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);  static void
> > gfx_v9_0_set_gds_init(struct amdgpu_device *adev); -static void
> > 

Re: [PATCH] drm/amdgpu: Filter security violation registers

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Bokun Zhang 

Sent: Wednesday, December 15, 2021 7:52 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Zhang, Bokun 
Subject: [PATCH] drm/amdgpu: Filter security violation registers

Recently, there is security policy update under SRIOV.
We need to filter the registers that hit the violation
and move the code to the host driver side so that
the guest driver can execute correctly.

Signed-off-by: Bokun Zhang 
Change-Id: Ida893bb17de17a80e865c7662f04c5562f5d2727
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 83 ++
 1 file changed, 46 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 4f546f632223..d3d6d5b045b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -542,9 +542,6 @@ static void sdma_v5_2_ctx_switch_enable(struct 
amdgpu_device *adev, bool enable)
 }

 for (i = 0; i < adev->sdma.num_instances; i++) {
-   f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_CNTL));
-   f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
-   AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 if (enable && amdgpu_sdma_phase_quantum) {
 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_PHASE0_QUANTUM),
phase_quantum);
@@ -553,7 +550,13 @@ static void sdma_v5_2_ctx_switch_enable(struct 
amdgpu_device *adev, bool enable)
 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_PHASE2_QUANTUM),
phase_quantum);
 }
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), 
f32_cntl);
+
+   if (!amdgpu_sriov_vf(adev)) {
+   f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_CNTL));
+   f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
+   AUTO_CTXSW_ENABLE, enable ? 1 : 0);
+   WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), 
f32_cntl);
+   }
 }

 }
@@ -576,10 +579,12 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, 
bool enable)
 sdma_v5_2_rlc_stop(adev);
 }

-   for (i = 0; i < adev->sdma.num_instances; i++) {
-   f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_F32_CNTL));
-   f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable 
? 0 : 1);
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), 
f32_cntl);
+   if (!amdgpu_sriov_vf(adev)) {
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_F32_CNTL));
+   f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, 
HALT, enable ? 0 : 1);
+   WREG32(sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_F32_CNTL), f32_cntl);
+   }
 }
 }

@@ -608,7 +613,8 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 ring = >sdma.instance[i].ring;
 wb_offset = (ring->rptr_offs * 4);

-   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
+   if (!amdgpu_sriov_vf(adev))
+   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

 /* Set ring buffer size in dwords */
 rb_bufsz = order_base_2(ring->ring_size / 4);
@@ -683,32 +689,34 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device 
*adev)
 sdma_v5_2_ring_set_wptr(ring);

 /* set minor_ptr_update to 0 after wptr programed */
-   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);

-   /* set utc l1 enable flag always to 1 */
-   temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
-   temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
-
-   /* enable MCBP */
-   temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 
1);
-   WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
-
-   /* Set up RESP_MODE to non-copy addresses */
-   temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_UTCL1_CNTL));
-   temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
-   temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
-   WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 
mmSDMA0_UTCL1_CNTL), temp);
-
-   /* program default cache read and write policy */
-   temp = 

Re: [PATCH v2 1/2] drm/amd/pm: fix reading SMU FW version from amdgpu_firmware_info on YC

[Deucher, Alexander]

[Public]

Series is:
Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Mario 
Limonciello 
Sent: Monday, December 13, 2021 10:08 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Limonciello, Mario 
Subject: [PATCH v2 1/2] drm/amd/pm: fix reading SMU FW version from 
amdgpu_firmware_info on YC

This value does not get cached into adev->pm.fw_version during
startup for smu13 like it does for other SMU like smu12.

Signed-off-by: Mario Limonciello 
---
v1->v2:
* Run on all v13 APU to match v12 behavior
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 55421ea622fb..7fdb63da1316 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -196,6 +196,7 @@ int smu_v13_0_check_fw_status(struct smu_context *smu)

 int smu_v13_0_check_fw_version(struct smu_context *smu)
 {
+   struct amdgpu_device *adev = smu->adev;
 uint32_t if_version = 0xff, smu_version = 0xff;
 uint16_t smu_major;
 uint8_t smu_minor, smu_debug;
@@ -208,6 +209,8 @@ int smu_v13_0_check_fw_version(struct smu_context *smu)
 smu_major = (smu_version >> 16) & 0x;
 smu_minor = (smu_version >> 8) & 0xff;
 smu_debug = (smu_version >> 0) & 0xff;
+   if (smu->is_apu)
+   adev->pm.fw_version = smu_version;

 switch (smu->adev->ip_versions[MP1_HWIP][0]) {
 case IP_VERSION(13, 0, 2):
--
2.25.1

Re: [PATCH] drm/amdgpu: use adev_to_drm to get drm_device pointer

[Deucher, Alexander]

[AMD Official Use Only]

Reviewed-by: Alex Deucher 

From: Chen, Guchun 
Sent: Sunday, December 12, 2021 11:08 PM
To: amd-gfx@lists.freedesktop.org ; Deucher, 
Alexander ; Koenig, Christian 
; Pan, Xinhui ; Yu, Lang 

Cc: Chen, Guchun 
Subject: [PATCH] drm/amdgpu: use adev_to_drm to get drm_device pointer

Updated for consistency when accessing drm_device from amdgpu driver.

Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 48aeca3b8f16..b2c3892e8e7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -5705,7 +5705,7 @@ void amdgpu_device_invalidate_hdp(struct amdgpu_device 
*adev,
 void amdgpu_device_halt(struct amdgpu_device *adev)
 {
 struct pci_dev *pdev = adev->pdev;
-   struct drm_device *ddev = >ddev;
+   struct drm_device *ddev = adev_to_drm(adev);

 drm_dev_unplug(ddev);

--
2.17.1

Re: [PATCH] drm/amdgpu: fix dropped backing store handling in amdgpu_dma_buf_move_notify

[Deucher, Alexander]

[Public]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Christian 
König 
Sent: Friday, December 10, 2021 3:39 AM
To: amd-gfx@lists.freedesktop.org ; 
alexdeuc...@gmail.com 
Subject: [PATCH] drm/amdgpu: fix dropped backing store handling in 
amdgpu_dma_buf_move_notify

bo->tbo.resource can now be NULL.

Signed-off-by: Christian König 
Bug: 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1811data=04%7C01%7Calexander.deucher%40amd.com%7C8ece16670f1b44091a4308d9bbb897e5%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637747223768954678%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000sdata=N4gltO0T3wozmHbROWRr3RiWFWXNu522ghTewe8T3bA%3Dreserved=0
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index ae6ab93c868b..784a12bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -384,7 +384,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment 
*attach)
 struct amdgpu_vm_bo_base *bo_base;
 int r;

-   if (bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
+   if (!bo->tbo.resource || bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
 return;

 r = ttm_bo_validate(>tbo, , );
--
2.25.1

Re: [PATCH] drm/amdgpu: don't skip runtime pm get on A+A config

[Deucher, Alexander]

[Public]

No objections from me.
Acked-by: Alex Deucher 

From: Christian König 
Sent: Thursday, December 9, 2021 10:34 AM
To: Quan, Evan ; Deucher, Alexander 

Cc: amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH] drm/amdgpu: don't skip runtime pm get on A+A config

Am 07.12.21 um 08:40 schrieb Quan, Evan:
> [AMD Official Use Only]
>> -Original Message-
>> From: Christian König 
>> Sent: Tuesday, December 7, 2021 3:03 PM
>> To: Quan, Evan ; Deucher, Alexander
>> 
>> Cc: amd-gfx@lists.freedesktop.org
>> Subject: Re: [PATCH] drm/amdgpu: don't skip runtime pm get on A+A config
>>
>> You are looking at outdated code, that stuff is gone by now.
>> amd-staging-drm-next probably needs a rebase.
> Yep, I can see it in the vanilla kernel.
> The patch is acked-by: Evan Quan 

Thanks.

Alex any objections that I push this to drm-misc-next? It was found
while working on changes already upstream in that function and would
conflict if we push it through amd-staging-drm-next.

Regards,
Christian.

>
> BR
> Evan
>> And this code was what the check was initially good for. Just skipping the PM
>> stuff as well on A+A was unintentionally.
>>
>> Regards,
>> Christian.
>>
>> Am 07.12.21 um 02:58 schrieb Quan, Evan:
>>> [AMD Official Use Only]
>>>
>>> It seems more jobs(below) other than bumping the runpm counter are
>> performed.
>>> Are they desired also?
>>>
>>>  r = __dma_resv_make_exclusive(bo->tbo.base.resv);
>>>  if (r)
>>>  goto out;
>>>
>>>  bo->prime_shared_count++;
>>>
>>> BR
>>> Evan
>>>> -Original Message-
>>>> From: amd-gfx  On Behalf Of
>>>> Christian König
>>>> Sent: Monday, December 6, 2021 4:46 PM
>>>> To: Deucher, Alexander 
>>>> Cc: amd-gfx@lists.freedesktop.org
>>>> Subject: [PATCH] drm/amdgpu: don't skip runtime pm get on A+A config
>>>>
>>>> The runtime PM get was incorrectly added after the check.
>>>>
>>>> Signed-off-by: Christian König 
>>>> ---
>>>>drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 3 ---
>>>>1 file changed, 3 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
>>>> index ae6ab93c868b..4896c876ffec 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
>>>> @@ -61,9 +61,6 @@ static int amdgpu_dma_buf_attach(struct dma_buf
>>>> *dmabuf,
>>>> if (pci_p2pdma_distance_many(adev->pdev, >dev, 1, true)
>> <
>>>> 0)
>>>> attach->peer2peer = false;
>>>>
>>>> -  if (attach->dev->driver == adev->dev->driver)
>>>> -  return 0;
>>>> -
>>>> r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
>>>> if (r < 0)
>>>> goto out;
>>>> --
>>>> 2.25.1

Re: [PATCH] drm/amd/pm: skip gfx cgpg in the s0ix suspend-resume

[Deucher, Alexander]

[Public]

Acked-by: Alex Deucher 

From: Liang, Prike 
Sent: Wednesday, December 8, 2021 8:51 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Huang, Ray 
; Limonciello, Mario ; Liang, 
Prike 
Subject: [PATCH] drm/amd/pm: skip gfx cgpg in the s0ix suspend-resume

In the s0ix entry need retain gfx in the gfxoff state,we don't
disable gfx cgpg in the suspend so there is also needn't enable
gfx cgpg in the s0ix resume.

Signed-off-by: Prike Liang 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 5839918..185269f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1607,7 +1607,8 @@ static int smu_resume(void *handle)
 return ret;
 }

-   if (smu->is_apu)
+   /* skip gfx cgpg in the s0ix suspend-resume case*/
+   if (smu->is_apu && !adev->in_s0ix)
 smu_set_gfx_cgpg(>smu, true);

 smu->disable_uclk_switch = 0;
--
2.7.4

Re: [PATCH 2/2] drm/amdgpu: free vkms_output after use

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Flora Cui 

Sent: Monday, December 6, 2021 1:34 AM
To: =guchun.c...@amd.com <=guchun.c...@amd.com>; Yuan, Perry 
; Shi, Leslie ; 
amd-gfx@lists.freedesktop.org 
Cc: Shi, Leslie ; Cui, Flora 
Subject: [PATCH 2/2] drm/amdgpu: free vkms_output after use

Signed-off-by: Flora Cui 
Reviewed-by: Leslie Shi 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index acc2d31ea93f..af3a2f8c12b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -480,6 +480,11 @@ static int amdgpu_vkms_sw_init(void *handle)
 int r, i;
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;

+   adev->amdgpu_vkms_output = kcalloc(adev->mode_info.num_crtc,
+   sizeof(struct amdgpu_vkms_output), GFP_KERNEL);
+   if (!adev->amdgpu_vkms_output)
+   return -ENOMEM;
+
 adev_to_drm(adev)->max_vblank_count = 0;

 adev_to_drm(adev)->mode_config.funcs = _vkms_mode_funcs;
@@ -496,10 +501,6 @@ static int amdgpu_vkms_sw_init(void *handle)
 if (r)
 return r;

-   adev->amdgpu_vkms_output = kcalloc(adev->mode_info.num_crtc, 
sizeof(struct amdgpu_vkms_output), GFP_KERNEL);
-   if (!adev->amdgpu_vkms_output)
-   return -ENOMEM;
-
 /* allocate crtcs, encoders, connectors */
 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 r = amdgpu_vkms_output_init(adev_to_drm(adev), 
>amdgpu_vkms_output[i], i);
@@ -522,12 +523,13 @@ static int amdgpu_vkms_sw_fini(void *handle)
 if (adev->mode_info.crtcs[i])
 
hrtimer_cancel(>mode_info.crtcs[i]->vblank_timer);

-   kfree(adev->mode_info.bios_hardcoded_edid);
-   kfree(adev->amdgpu_vkms_output);
-
 drm_kms_helper_poll_fini(adev_to_drm(adev));
+   drm_mode_config_cleanup(adev_to_drm(adev));

 adev->mode_info.mode_config_initialized = false;
+
+   kfree(adev->mode_info.bios_hardcoded_edid);
+   kfree(adev->amdgpu_vkms_output);
 return 0;
 }

--
2.25.1

Re: [PATCH] drm/amdgpu: don't override default ECO_BITs setting

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Hawking 
Zhang 
Sent: Saturday, December 4, 2021 6:24 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: don't override default ECO_BITs setting

Leave this bit as hardware default setting

Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 1 -
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 1 -
 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 1 -
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 1 -
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c  | 1 -
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c  | 1 -
 drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c  | 1 -
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c  | 2 --
 8 files changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 480e41847d7c..ec4d5e15b766 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -162,7 +162,6 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device 
*adev)
 ENABLE_ADVANCED_DRIVER_MODEL, 1);
 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
-   tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 MTYPE, MTYPE_UC);/* XXX for emulation. */
 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
index 14c1c1a297dd..6e0ace2fbfab 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
@@ -196,7 +196,6 @@ static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device 
*adev)
 ENABLE_ADVANCED_DRIVER_MODEL, 1);
 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
-   tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 MTYPE, MTYPE_UC); /* UC, uncached */

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c 
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index e80d1dc43079..b4eddf6e98a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -197,7 +197,6 @@ static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device 
*adev)
 ENABLE_ADVANCED_DRIVER_MODEL, 1);
 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
-   tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
 MTYPE, MTYPE_UC); /* UC, uncached */

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index a99953833820..b3bede1dc41d 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -145,7 +145,6 @@ static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device 
*adev)
 ENABLE_ADVANCED_DRIVER_MODEL, 1);
 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
-   tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 MTYPE, MTYPE_UC);/* XXX for emulation. */
 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
index f80a14a1b82d..f5f7181f9af5 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
@@ -165,7 +165,6 @@ static void mmhub_v1_7_init_tlb_regs(struct amdgpu_device 
*adev)
 ENABLE_ADVANCED_DRIVER_MODEL, 1);
 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
-   tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 MTYPE, MTYPE_UC);/* XXX for emulation. */
 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 25f8e93e5ec3..3718ff610ab2 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -267,7 +267,6 @@ static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device 
*adev)
 ENABLE_ADVANCED_DRIVER_MODEL, 1);
 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
-   tmp = 

Re: [PATCH] drm/amdkfd: Correct the value of the no_atomic_fw_version variable

[Deucher, Alexander]

[Public]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of chen gong 

Sent: Thursday, December 2, 2021 3:56 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Sider, Graham ; Gong, Curry 
Subject: [PATCH] drm/amdkfd: Correct the value of the no_atomic_fw_version 
variable

145:
navi10IP_VERSION(10, 1, 10)
navi12IP_VERSION(10, 1, 2)
navi14IP_VERSION(10, 1, 1)

92:
sienna_cichlidIP_VERSION(10, 3, 0)
navy_flounder IP_VERSION(10, 3, 2)
vangogh   IP_VERSION(10, 3, 1)
dimgrey_cavefish  IP_VERSION(10, 3, 4)
beige_gobyIP_VERSION(10, 3, 5)
yellow_carp   IP_VERSION(10, 3, 3)

Signed-off-by: chen gong 
---
 drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index e6fded7..267668b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -94,9 +94,9 @@ static void kfd_device_info_init(struct kfd_dev *kfd,
 if (gc_version < IP_VERSION(11, 0, 0)) {
 /* Navi2x+, Navi1x+ */
 if (gc_version >= IP_VERSION(10, 3, 0))
-   kfd->device_info.no_atomic_fw_version = 145;
-   else if (gc_version >= IP_VERSION(10, 1, 1))
 kfd->device_info.no_atomic_fw_version = 92;
+   else if (gc_version >= IP_VERSION(10, 1, 1))
+   kfd->device_info.no_atomic_fw_version = 145;

 /* Navi1x+ */
 if (gc_version >= IP_VERSION(10, 1, 1))
--
2.7.4

Re: [PATCH] drm/amdgpu/display: Only set vblank_disable_immediate when PSR is not enabled

[Deucher, Alexander]

[Public]

Acked-by: Alex Deucher 

From: Nicholas Kazlauskas 
Sent: Tuesday, November 30, 2021 9:53 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Kazlauskas, Nicholas ; Wentland, Harry 
; Deucher, Alexander 
Subject: [PATCH] drm/amdgpu/display: Only set vblank_disable_immediate when PSR 
is not enabled

[Why]
PSR currently relies on the kernel's delayed vblank on/off mechanism
as an implicit bufferring mechanism to prevent excessive entry/exit.

Without this delay the user experience is impacted since it can take
a few frames to enter/exit.

[How]
Only allow vblank disable immediate for DC when psr is not supported.

Leave a TODO indicating that this support should be extended in the
future to delay independent of the vblank interrupt.

Fixes: 3d1508b73ff1 ("drm/amdgpu/display: set vblank_disable_immediate for DC")

Cc: Harry Wentland 
Cc: Alex Deucher 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0747dc7922c2..d582d44c02ad 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1599,9 +1599,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 adev_to_drm(adev)->mode_config.cursor_width = 
adev->dm.dc->caps.max_cursor_size;
 adev_to_drm(adev)->mode_config.cursor_height = 
adev->dm.dc->caps.max_cursor_size;

-   /* Disable vblank IRQs aggressively for power-saving */
-   adev_to_drm(adev)->vblank_disable_immediate = true;
-
 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
 DRM_ERROR(
 "amdgpu: failed to initialize sw for display support.\n");
@@ -4264,6 +4261,14 @@ static int amdgpu_dm_initialize_drm_device(struct 
amdgpu_device *adev)

 }

+   /*
+* Disable vblank IRQs aggressively for power-saving.
+*
+* TODO: Fix vblank control helpers to delay PSR entry to allow this 
when PSR
+* is also supported.
+*/
+   adev_to_drm(adev)->vblank_disable_immediate = !psr_feature_enabled;
+
 /* Software is initialized. Now we can register interrupt handlers. */
 switch (adev->asic_type) {
 #if defined(CONFIG_DRM_AMD_DC_SI)
--
2.25.1

Re: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID

[Deucher, Alexander]

[Public]

Yes, that makes more sense.

Alex


From: Chen, Guchun 
Sent: Wednesday, November 24, 2021 9:21 PM
To: Chen, Guchun ; Alex Deucher ; 
Jian, Jane 
Cc: Deucher, Alexander ; Chen, JingWen 
; amd-gfx list 
Subject: RE: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip 
init for SIENNA_CICHLID

[Public]

A typo.

It's better to move 'case IP_VERSION(3, 0, 192)' after IP_VERSION(3, 0, 2)?

case IP_VERSION(3, 1, 1):
case IP_VERSION(3, 0, 2):
+ case IP_VERSION(3, 0, 192):
amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
if (!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
break;

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Chen, Guchun
Sent: Thursday, November 25, 2021 10:19 AM
To: Alex Deucher ; Jian, Jane 
Cc: Deucher, Alexander ; Chen, JingWen 
; amd-gfx list 
Subject: RE: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip 
init for SIENNA_CICHLID

[Public]

It's better to move 'case IP_VERSION(3, 0, 192)' after IP_VERSION(3, 0, 192)?

case IP_VERSION(3, 1, 1):
case IP_VERSION(3, 0, 2):
+ case IP_VERSION(3, 0, 192):
amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
if (!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
break;

Regards,
Guchun

-Original Message-
From: Alex Deucher 
Sent: Wednesday, November 24, 2021 10:23 PM
To: Jian, Jane 
Cc: Deucher, Alexander ; Chen, Guchun 
; Chen, JingWen ; amd-gfx list 

Subject: Re: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip 
init for SIENNA_CICHLID

On Wed, Nov 24, 2021 at 9:20 AM Jane Jian  wrote:
>
> [WHY]
> for sriov odd# vf will modify vcn0 engine ip revision(due to
> multimedia bandwidth feature), which will be mismatched with original
> vcn0 revision
>
> [HOW]
> add new version check for vcn0 disabled revision(3, 0, 192), typically
> modified under sriov mode
>
> Signed-off-by: Jane Jian 

Reviewed-by: Alex Deucher 

> Change-Id: I1ace32acbf3a13c0baac958508da1324ec387a58
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c   | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 503995c7ff6c..3f9b7b0bab3c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -923,6 +923,7 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct 
> amdgpu_device *adev)
> amdgpu_device_ip_block_add(adev, 
> _v3_0_ip_block);
> break;
> case IP_VERSION(3, 0, 33):
> +   case IP_VERSION(3, 0, 192):
> amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
> break;
> default:
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 4f7c70845785..585961c2f5f2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -135,6 +135,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
> break;
> case IP_VERSION(3, 0, 0):
> case IP_VERSION(3, 0, 64):
> +   case IP_VERSION(3, 0, 192):
> if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
> fw_name = FIRMWARE_SIENNA_CICHLID;
> else
> --
> 2.17.1
>

Re: [PATCH 3/3] drm/amdgpu: check atomic flag to differeniate with legacy path

[Deucher, Alexander]

[AMD Official Use Only]

Series is:
Reviewed-by: Alex Deucher 

From: Cui, Flora 
Sent: Tuesday, November 23, 2021 9:43 PM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org 
; Deucher, Alexander 
Cc: Cui, Flora ; Alex Deucher 
Subject: [PATCH 3/3] drm/amdgpu: check atomic flag to differeniate with legacy 
path

since vkms support atomic KMS interface

Signed-off-by: Flora Cui 
Reviewed-by: Guchun Chen 
Acked-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7d4115d52523..8e9e50aa4a95 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3830,7 +3830,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
 /* disable all interrupts */
 amdgpu_irq_disable_all(adev);
 if (adev->mode_info.mode_config_initialized){
-   if (!amdgpu_device_has_dc_support(adev))
+   if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
 drm_helper_force_disable_all(adev_to_drm(adev));
 else
 drm_atomic_helper_shutdown(adev_to_drm(adev));
@@ -5124,7 +5124,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 drm_sched_start(>sched, 
!tmp_adev->asic_reset_res);
 }

-   if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
+   if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && 
!job_signaled) {
 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
 }

--
2.25.1

Re: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init for SIENNA_CICHLID

[Deucher, Alexander]

[Public]

Can we just add a check for the new IP version in that case?  This looks really 
hacky.

Alex


From: Jane Jian 
Sent: Tuesday, November 23, 2021 6:34 AM
To: amd-gfx@lists.freedesktop.org ; Deucher, 
Alexander ; Chen, Guchun ; 
Chen, JingWen 
Cc: Jian, Jane 
Subject: [PATCH] drm/amdgpu/sriov/vcn: skip ip revision check case to ip init 
for SIENNA_CICHLID

[WHY]
for sriov odd# vf will modify vcn0 engine ip revision(due to multimedia 
bandwidth feature),
which will be mismatched with original vcn0 revision

[HOW]
skip ip revision match case and continue use asic type to check

Signed-off-by: Jane Jian 
Change-Id: I1ace32acbf3a13c0baac958508da1324ec387a58
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 5 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c   | 6 ++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 4e3669407518..0a91e53f520c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1334,7 +1334,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device 
*adev)
 return r;
 }

-   r = amdgpu_discovery_set_mm_ip_blocks(adev);
+   if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_sriov_vf(adev))
+   r = amdgpu_device_ip_block_add(adev, _v3_0_ip_block);
+   else
+   r = amdgpu_discovery_set_mm_ip_blocks(adev);
 if (r)
 return r;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 4f7c70845785..87f56b61be53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -86,6 +86,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
 atomic_set(>vcn.inst[i].dpg_enc_submission_cnt, 0);

+   if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_sriov_vf(adev)) {
+   fw_name = FIRMWARE_SIENNA_CICHLID;
+   goto next;
+   }
 switch (adev->ip_versions[UVD_HWIP][0]) {
 case IP_VERSION(1, 0, 0):
 case IP_VERSION(1, 0, 1):
@@ -168,6 +172,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 return -EINVAL;
 }

+next:
+
 r = request_firmware(>vcn.fw, fw_name, adev->dev);
 if (r) {
 dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n",
--
2.17.1

Re: [PATCH 3/3] drm/amd/pm: Print the error on command submission

[Deucher, Alexander]

[AMD Official Use Only]

Series is:
Reviewed-by: Alex Deucher 

From: Tuikov, Luben 
Sent: Monday, November 22, 2021 5:25 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Tuikov, Luben ; Deucher, Alexander 

Subject: [PATCH 3/3] drm/amd/pm: Print the error on command submission

Print the error on command submission immediately after submitting to
the SMU. This is rate-limited. It helps to immediately know there was an
error on command submission, rather than leave it up to clients to report
the error, as sometimes they do not.

Cc: Alex Deucher 
Signed-off-by: Luben Tuikov 
Acked-by: Alex Deucher 
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index f9a42a07eeaebf..048ca16738638f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -352,7 +352,7 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
 __smu_cmn_send_msg(smu, (uint16_t) index, param);
 reg = __smu_cmn_poll_stat(smu);
 res = __smu_cmn_reg2errno(smu, reg);
-   if (res == -EREMOTEIO)
+   if (res != 0)
 __smu_cmn_reg_print_error(smu, reg, index, param, msg);
 if (read_arg)
 smu_cmn_read_arg(smu, read_arg);
--
2.34.0

Re: [PATCH 2/2] drm/amdgpu: check atomic flag to differeniate with legacy path

[Deucher, Alexander]

[Public]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Flora Cui 

Sent: Monday, November 22, 2021 4:03 AM
To: amd-gfx@lists.freedesktop.org ; Chen, Guchun 

Cc: Cui, Flora 
Subject: [PATCH 2/2] drm/amdgpu: check atomic flag to differeniate with legacy 
path

since vkms support atomic KMS interface

Signed-off-by: Flora Cui 
Reviewed-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ec42a6fd88de..87801f2e50f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3830,7 +3830,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
 /* disable all interrupts */
 amdgpu_irq_disable_all(adev);
 if (adev->mode_info.mode_config_initialized){
-   if (!amdgpu_device_has_dc_support(adev))
+   if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
 drm_helper_force_disable_all(adev_to_drm(adev));
 else
 drm_atomic_helper_shutdown(adev_to_drm(adev));
@@ -5125,7 +5125,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 drm_sched_start(>sched, 
!tmp_adev->asic_reset_res);
 }

-   if (!amdgpu_device_has_dc_support(tmp_adev) && !job_signaled) {
+   if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && 
!job_signaled) {
 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
 }

--
2.25.1

Re: [PATCH 1/2] drm/amdgpu: fix vkms hrtimer settings

[Deucher, Alexander]

[Public]

Can you explain how the current code is failing?  It's not immediately obvious 
to me.  I'm not opposed to this change, it's just not clear to me where the 
current code fails.

Alex


From: Chen, Guchun 
Sent: Monday, November 22, 2021 8:49 AM
To: Cui, Flora ; amd-gfx@lists.freedesktop.org 
; Deucher, Alexander 
Subject: RE: [PATCH 1/2] drm/amdgpu: fix vkms hrtimer settings

[Public]

Series is:
Reviewed-by: Guchun Chen 

+Alex to comment this series as well.

Regards,
Guchun

-Original Message-
From: Cui, Flora 
Sent: Monday, November 22, 2021 5:04 PM
To: amd-gfx@lists.freedesktop.org; Chen, Guchun 
Cc: Cui, Flora 
Subject: [PATCH 1/2] drm/amdgpu: fix vkms hrtimer settings

otherwise adev->mode_info.crtcs[] is NULL

Signed-off-by: Flora Cui 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 38   
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.h |  5 ++--
 2 files changed, 28 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index ce982afeff91..6c62c45e3e3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -16,6 +16,8 @@
 #include "ivsrcid/ivsrcid_vislands30.h"
 #include "amdgpu_vkms.h"
 #include "amdgpu_display.h"
+#include "atom.h"
+#include "amdgpu_irq.h"

 /**
  * DOC: amdgpu_vkms
@@ -41,14 +43,13 @@ static const u32 amdgpu_vkms_formats[] = {

 static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) 
 {
-   struct amdgpu_vkms_output *output = container_of(timer,
-struct 
amdgpu_vkms_output,
-vblank_hrtimer);
-   struct drm_crtc *crtc = >crtc;
+   struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct 
amdgpu_crtc, vblank_timer);
+   struct drm_crtc *crtc = _crtc->base;
+   struct amdgpu_vkms_output *output =
+drm_crtc_to_amdgpu_vkms_output(crtc);
 u64 ret_overrun;
 bool ret;

-   ret_overrun = hrtimer_forward_now(>vblank_hrtimer,
+   ret_overrun = hrtimer_forward_now(_crtc->vblank_timer,
   output->period_ns);
 WARN_ON(ret_overrun != 1);

@@ -65,22 +66,21 @@ static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc)
 unsigned int pipe = drm_crtc_index(crtc);
 struct drm_vblank_crtc *vblank = >vblank[pipe];
 struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc);
+   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

 drm_calc_timestamping_constants(crtc, >mode);

-   hrtimer_init(>vblank_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
-   out->vblank_hrtimer.function = _vkms_vblank_simulate;
 out->period_ns = ktime_set(0, vblank->framedur_ns);
-   hrtimer_start(>vblank_hrtimer, out->period_ns, HRTIMER_MODE_REL);
+   hrtimer_start(_crtc->vblank_timer, out->period_ns,
+HRTIMER_MODE_REL);

 return 0;
 }

 static void amdgpu_vkms_disable_vblank(struct drm_crtc *crtc)  {
-   struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc);
+   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

-   hrtimer_cancel(>vblank_hrtimer);
+   hrtimer_cancel(_crtc->vblank_timer);
 }

 static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, @@ -92,13 
+92,14 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc,
 unsigned int pipe = crtc->index;
 struct amdgpu_vkms_output *output = 
drm_crtc_to_amdgpu_vkms_output(crtc);
 struct drm_vblank_crtc *vblank = >vblank[pipe];
+   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

 if (!READ_ONCE(vblank->enabled)) {
 *vblank_time = ktime_get();
 return true;
 }

-   *vblank_time = READ_ONCE(output->vblank_hrtimer.node.expires);
+   *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires);

 if (WARN_ON(*vblank_time == vblank->time))
 return true;
@@ -165,6 +166,8 @@ static const struct drm_crtc_helper_funcs 
amdgpu_vkms_crtc_helper_funcs = {  static int amdgpu_vkms_crtc_init(struct 
drm_device *dev, struct drm_crtc *crtc,
   struct drm_plane *primary, struct drm_plane *cursor) 
 {
+   struct amdgpu_device *adev = drm_to_adev(dev);
+   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 int ret;

 ret = drm_crtc_init_with_planes(dev, crtc, primary, cursor, @@ -176,6 
+179,17 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct 
drm_crtc *crtc,

 drm_crtc_helper_add(crtc, _vkms_crtc_helper_funcs);

+   amdgpu_crtc->crtc_id = drm_crtc_index(crtc);
+   adev->mode_info.crtcs[drm_crtc_index(c

Re: [PATCH 14/16] drm/amd/display: add else to avoid double destroy clk_mgr

[Deucher, Alexander]

[Public]

Do you want to change the ASICREV_IS_BEIGE_GOBY_P() check to else if as well?  
maybe something like:

if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev) ||
ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev) ||
 ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))
 dcn3_clk_mgr_destroy(clk_mgr);

Alex

From: amd-gfx  on behalf of Qingqing 
Zhuo 
Sent: Friday, November 19, 2021 2:43 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Wang, Chao-kai (Stylon) ; Cyr, Aric 
; Chiu, Solomon ; Li, Sun peng (Leo) 
; Wentland, Harry ; Zhuo, Qingqing 
(Lillian) ; Leung, Martin ; 
Siqueira, Rodrigo ; Li, Roman ; 
Jacob, Anson ; Pillai, Aurabindo 
; Lin, Wayne ; Lipski, Mikita 
; Lakha, Bhawanpreet ; 
Gutierrez, Agustin ; Kotarac, Pavle 

Subject: [PATCH 14/16] drm/amd/display: add else to avoid double destroy clk_mgr

From: Martin Leung 

[Why & How]
when changing some code we accidentally
changed else if-> if. reverting that.

Reviewed-by: Aric Cyr 
Acked-by: Qingqing Zhuo 
Signed-off-by: Martin Leung 
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 26f96ee32472..9200c8ce02ba 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -308,8 +308,7 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
 case FAMILY_NV:
 if 
(ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
 dcn3_clk_mgr_destroy(clk_mgr);
-   }
-   if 
(ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
+   } else if 
(ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
 dcn3_clk_mgr_destroy(clk_mgr);
 }
 if 
(ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
--
2.25.1

Re: [PATCH] drm/amdgpu: Declare Unpin BO api as static

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Ramesh 
Errabolu 
Sent: Thursday, November 18, 2021 5:11 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Errabolu, Ramesh ; kernel test robot 

Subject: [PATCH] drm/amdgpu: Declare Unpin BO api as static

Fixes warning report from kernel test robot

Reported-by: kernel test robot 
Signed-off-by: Ramesh Errabolu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 90b985436878..3463e0d4e5ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1332,7 +1332,7 @@ static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo 
*bo, u32 domain)
  *   - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
  * PIN count decremented. Calls to UNPIN must balance calls to PIN
  */
-void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
+static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
 {
 int ret = 0;

--
2.31.1

Re: [PATCH 2/6] drm/amdgpu: stop getting excl fence separately

[Deucher, Alexander]

[AMD Official Use Only]

Acked-by: Alex Deucher 

From: Christian König 
Sent: Tuesday, November 16, 2021 5:43 AM
To: amd-gfx@lists.freedesktop.org ; Deucher, 
Alexander 
Subject: Re: [PATCH 2/6] drm/amdgpu: stop getting excl fence separately

Adding Alex.

Once more a ping to the mailing list.

Thanks,
Christian.

Am 11.11.21 um 09:58 schrieb Christian König:
> Just a ping to the amd-gfx list.
>
> Trivial cleanup, can anybody give me an rb for that?
>
> Thanks,
> Christian.
>
> Am 28.10.21 um 15:26 schrieb Christian König:
>> Just grab all fences for the display flip in one go.
>>
>> Signed-off-by: Christian König 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 -
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 +-
>>   2 files changed, 1 insertion(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index d58e37fd01f4..4da7eb65e744 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -457,7 +457,6 @@ struct amdgpu_flip_work {
>>   uint64_tbase;
>>   struct drm_pending_vblank_event *event;
>>   struct amdgpu_bo*old_abo;
>> -struct dma_fence*excl;
>>   unsignedshared_count;
>>   struct dma_fence**shared;
>>   struct dma_fence_cbcb;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> index dc50c05f23fc..68108f151dad 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> @@ -83,9 +83,6 @@ static void amdgpu_display_flip_work_func(struct
>> work_struct *__work)
>>   unsigned i;
>>   int vpos, hpos;
>>   -if (amdgpu_display_flip_handle_fence(work, >excl))
>> -return;
>> -
>>   for (i = 0; i < work->shared_count; ++i)
>>   if (amdgpu_display_flip_handle_fence(work, >shared[i]))
>>   return;
>> @@ -203,7 +200,7 @@ int amdgpu_display_crtc_page_flip_target(struct
>> drm_crtc *crtc,
>>   goto unpin;
>>   }
>>   -r = dma_resv_get_fences(new_abo->tbo.base.resv, >excl,
>> +r = dma_resv_get_fences(new_abo->tbo.base.resv, NULL,
>>   >shared_count, >shared);
>>   if (unlikely(r != 0)) {
>>   DRM_ERROR("failed to get fences for buffer\n");
>> @@ -253,7 +250,6 @@ int amdgpu_display_crtc_page_flip_target(struct
>> drm_crtc *crtc,
>> cleanup:
>>   amdgpu_bo_unref(>old_abo);
>> -dma_fence_put(work->excl);
>>   for (i = 0; i < work->shared_count; ++i)
>>   dma_fence_put(work->shared[i]);
>>   kfree(work->shared);
>

Re: [PATCH] drm/amdgpu: always reset the asic in suspend

[Deucher, Alexander]

[AMD Official Use Only]

Well, that handles the case of the GPU needing to be reset on driver (e.g., 
virtualization), but doesn't handle the interrupted suspend case (e.g., when 
suspend is unwound before the power rail was turned off).  We already so 
something similar for hibernate to deal with the multiple freeze and thaw 
cycles.

Alex


From: Christian König 
Sent: Monday, November 15, 2021 8:41 AM
To: Alex Deucher ; Deucher, Alexander 

Cc: amd-gfx list 
Subject: Re: [PATCH] drm/amdgpu: always reset the asic in suspend

I was just about to write up my concern as well.

IIRC we used to have that and it didn't really worked that well and we
switched to resetting the GPU on driver load instead if initializing it
doesn't work of hand.

Christian.

Am 12.11.21 um 17:19 schrieb Alex Deucher:
> Actually, ignore this for now.  This will likely cause problems with S0ix.
>
> Alex
>
> On Fri, Nov 12, 2021 at 11:18 AM Alex Deucher  
> wrote:
>> If the platform suspend happens to fail and the power rail
>> is not turned off, the GPU will be in an unknown state on
>> resume, so reset the asic so that it will be in a known
>> good state on resume even if the platform suspend failed.
>>
>> Signed-off-by: Alex Deucher 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++--
>>   1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index 1db76429a673..42af3d88e0ba 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -2165,8 +2165,9 @@ static int amdgpu_pmops_suspend(struct device *dev)
>>  adev->in_s3 = true;
>>  r = amdgpu_device_suspend(drm_dev, true);
>>  adev->in_s3 = false;
>> -
>> -   return r;
>> +   if (r)
>> +   return r;
>> +   return amdgpu_asic_reset(adev);
>>   }
>>
>>   static int amdgpu_pmops_resume(struct device *dev)
>> --
>> 2.31.1
>>

Re: [PATCH] drm/amd/pm: Remove artificial freq level on Navi1x

[Deucher, Alexander]

[AMD Official Use Only]

Acked-by: Alex Deucher 

From: Lazar, Lijo 
Sent: Monday, November 15, 2021 2:42 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Zhang, Hawking 
; Wang, Yang(Kevin) ; Quan, Evan 

Subject: [PATCH] drm/amd/pm: Remove artificial freq level on Navi1x

Print Navi1x fine grained clocks in a consistent manner with other SOCs.
Don't show aritificial DPM level when the current clock equals min or max.

Signed-off-by: Lijo Lazar 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 71161f6b78fe..60a557068ea4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1265,7 +1265,7 @@ static int navi10_print_clk_levels(struct smu_context 
*smu,
 enum smu_clk_type clk_type, char *buf)
 {
 uint16_t *curve_settings;
-   int i, size = 0, ret = 0;
+   int i, levels, size = 0, ret = 0;
 uint32_t cur_value = 0, value = 0, count = 0;
 uint32_t freq_values[3] = {0};
 uint32_t mark_index = 0;
@@ -1319,14 +1319,17 @@ static int navi10_print_clk_levels(struct smu_context 
*smu,
 freq_values[1] = cur_value;
 mark_index = cur_value == freq_values[0] ? 0 :
  cur_value == freq_values[2] ? 2 : 1;
-   if (mark_index != 1)
-   freq_values[1] = (freq_values[0] + 
freq_values[2]) / 2;

-   for (i = 0; i < 3; i++) {
+   levels = 3;
+   if (mark_index != 1) {
+   levels = 2;
+   freq_values[1] = freq_values[2];
+   }
+
+   for (i = 0; i < levels; i++) {
 size += sysfs_emit_at(buf, size, "%d: %uMhz 
%s\n", i, freq_values[i],
 i == mark_index ? "*" : "");
 }
-
 }
 break;
 case SMU_PCIE:
--
2.17.1

Re: [PATCH v2 3/3] drm/amdkfd: convert misc checks to IP version checking

[Deucher, Alexander]

[AMD Official Use Only]

Series is:
Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Graham Sider 

Sent: Tuesday, November 9, 2021 5:42 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Kuehling, Felix ; Kasiviswanathan, Harish 
; Sider, Graham 
Subject: [PATCH v2 3/3] drm/amdkfd: convert misc checks to IP version checking

Switch to IP version checking instead of asic_type on various KFD
version checks.

Signed-off-by: Graham Sider 
---
 drivers/gpu/drm/amd/amdkfd/kfd_chardev.c  |  2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_crat.c |  2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_device.c   | 27 ++-
 .../drm/amd/amdkfd/kfd_device_queue_manager.c |  3 +--
 .../amd/amdkfd/kfd_device_queue_manager_v9.c  |  2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_events.c   |  6 +++--
 drivers/gpu/drm/amd/amdkfd/kfd_migrate.c  |  2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_process.c  |  7 +++--
 drivers/gpu/drm/amd/amdkfd/kfd_svm.c  |  6 ++---
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c |  4 +--
 10 files changed, 31 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 2466a73b8c7d..f70117b00b14 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1603,7 +1603,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file 
*filep,
 }
 mutex_unlock(>mutex);

-   if (dev->device_info->asic_family == CHIP_ALDEBARAN) {
+   if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) {
 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev,
 (struct kgd_mem *) mem, true);
 if (err) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 19dd472e9b06..b6d887edac85 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1992,7 +1992,7 @@ static int kfd_fill_gpu_direct_io_link_to_cpu(int 
*avail_size,
 sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
 sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI;
 sub_type_hdr->num_hops_xgmi = 1;
-   if (kdev->adev->asic_type == CHIP_ALDEBARAN) {
+   if (KFD_GC_VERSION(kdev) == IP_VERSION(9, 4, 2)) {
 sub_type_hdr->minimum_bandwidth_mbs =
 
amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(
 kdev->adev, NULL, 
true);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index ee813bd57c92..594dd28a391f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -848,23 +848,23 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, 
bool vf)
 static void kfd_cwsr_init(struct kfd_dev *kfd)
 {
 if (cwsr_enable && kfd->device_info->supports_cwsr) {
-   if (kfd->device_info->asic_family < CHIP_VEGA10) {
+   if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) {
 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
 kfd->cwsr_isa = cwsr_trap_gfx8_hex;
 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
-   } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) {
+   } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) {
 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > 
PAGE_SIZE);
 kfd->cwsr_isa = cwsr_trap_arcturus_hex;
 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
-   } else if (kfd->device_info->asic_family == CHIP_ALDEBARAN) {
+   } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) {
 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > 
PAGE_SIZE);
 kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
-   } else if (kfd->device_info->asic_family < CHIP_NAVI10) {
+   } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) {
 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
 kfd->cwsr_isa = cwsr_trap_gfx9_hex;
 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
-   } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) 
{
+   } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) {
 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
 kfd->cwsr_isa = cwsr_trap_nv1x_hex;
 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
@@ -886,14 +886,16 @@ static int kfd_gws_init(struct kfd_dev *kfd)
 return 0;

 if 

Re: [PATCH 0/5] 0 MHz is not a valid current frequency

[Deucher, Alexander]

[Public]

We the current behavior (0 for clock) already crashes the tool, so I don't 
think we can really make things worse.

Alex


From: Quan, Evan 
Sent: Thursday, October 14, 2021 10:25 PM
To: Lazar, Lijo ; Tuikov, Luben ; 
amd-gfx@lists.freedesktop.org ; Russell, Kent 

Cc: Deucher, Alexander 
Subject: RE: [PATCH 0/5] 0 MHz is not a valid current frequency


[AMD Official Use Only]



+Kent who maintains the Rocm tool



From: amd-gfx  On Behalf Of Lazar, Lijo
Sent: Thursday, October 14, 2021 1:07 AM
To: Tuikov, Luben ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: Re: [PATCH 0/5] 0 MHz is not a valid current frequency



[AMD Official Use Only]



[AMD Official Use Only]



>Or maybe just a list without default hint, i.e. no asterisk?



I think this is also fine meaning we are having trouble in determining the 
current frequency or DPM level. Evan/Alex? Don't know if this will crash the 
tools.



Thanks,
Lijo



From: Tuikov, Luben mailto:luben.tui...@amd.com>>
Sent: Wednesday, October 13, 2021 9:52:09 PM
To: Lazar, Lijo mailto:lijo.la...@amd.com>>; 
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Subject: Re: [PATCH 0/5] 0 MHz is not a valid current frequency



On 2021-10-13 00:14, Lazar, Lijo wrote:
>
> On 10/13/2021 8:40 AM, Luben Tuikov wrote:
>> Some ASIC support low-power functionality for the whole ASIC or just
>> an IP block. When in such low-power mode, some sysfs interfaces would
>> report a frequency of 0, e.g.,
>>
>> $cat /sys/class/drm/card0/device/pp_dpm_sclk
>> 0: 500Mhz
>> 1: 0Mhz *
>> 2: 2200Mhz
>> $_
>>
>> An operating frequency of 0 MHz doesn't make sense, and this interface
>> is designed to report only operating clock frequencies, i.e. non-zero,
>> and possibly the current one.
>>
>> When in this low-power state, round to the smallest
>> operating frequency, for this interface, as follows,
>>
> Would rather avoid this -
>
> 1) It is manipulating FW reported value. If at all there is an uncaught
> issue in FW reporting of frequency values, that is masked here.
> 2) Otherwise, if 0MHz is described as GFX power gated case, this
> provides a convenient interface to check if GFX is power gated.
>
> If seeing a '0' is not pleasing, consider changing to something like
>"NA" - not available (frequency cannot be fetched at the moment).

There's a ROCm tool which literally asserts if the values are not ordered in 
increasing order. Now since 0 < 550, but 0 is listed as the second entry, the 
tool simply asserts and crashes.

It is not clear what you'd rather see here:

$cat /sys/class/drm/card0/device/pp_dpm_sclk
0: 550Mhz
1: N/A *
2: 2200MHz
$_

Is this what you want to see? (That'll crash other tools which expect %uMhz.)

Or maybe just a list without default hint, i.e. no asterisk?

$cat /sys/class/drm/card0/device/pp_dpm_sclk
0: 550Mhz
1: 2200MHz
$_

What should the output be?

We want to avoid showing 0, but still show numbers.

Regards,
Luben

>
> Thanks,
> Lijo
>
>> $cat /sys/class/drm/card0/device/pp_dpm_sclk
>> 0: 500Mhz *
>> 1: 2200Mhz
>> $_
>>
>> Luben Tuikov (5):
>>drm/amd/pm: Slight function rename
>>drm/amd/pm: Rename cur_value to curr_value
>>drm/amd/pm: Rename freq_values --> freq_value
>>dpm/amd/pm: Sienna: 0 MHz is not a current clock frequency
>>dpm/amd/pm: Navi10: 0 MHz is not a current clock frequency
>>
>>   .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 60 +--
>>   .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 73 ---
>>   2 files changed, 86 insertions(+), 47 deletions(-)
>>

Re: [PATCH] drm/amdgpu: print warning and taint kernel if lockup timeout is disabled

[Deucher, Alexander]

[AMD Official Use Only]

Acked-by: Alex Deucher 

From: Christian König 
Sent: Thursday, September 30, 2021 6:00 AM
To: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org 
Subject: [PATCH] drm/amdgpu: print warning and taint kernel if lockup timeout 
is disabled

Make sure that we notice this in error reports.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4d34b2da8582..8ee5bbc19f62 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3346,6 +3346,8 @@ static int amdgpu_device_get_job_timeout_settings(struct 
amdgpu_device *adev)
 continue;
 } else if (timeout < 0) {
 timeout = MAX_SCHEDULE_TIMEOUT;
+   dev_warn(adev->dev, "lockup timeout disabled");
+   add_taint(TAINT_SOFTLOCKUP, LOCKDEP_STILL_OK);
 } else {
 timeout = msecs_to_jiffies(timeout);
 }
--
2.25.1

Re: [PATCH 04/66] drm/amdgpu: fill in IP versions from IP discovery table

[Deucher, Alexander]

[AMD Official Use Only]

Fixed locally.  Thanks!

Alex


From: Kuehling, Felix 
Sent: Wednesday, September 22, 2021 12:58 PM
To: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH 04/66] drm/amdgpu: fill in IP versions from IP discovery 
table

Am 2021-09-21 um 2:06 p.m. schrieb Alex Deucher:
> Prerequisite for using IP versions in the driver rather
> than asic type.
>
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 67e7a46f5020..ff52fcce1f93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -244,6 +244,11 @@ void amdgpu_discovery_fini(struct amdgpu_device *adev)
>adev->mman.discovery_bin = NULL;
>  }
>
> +static u32 amdgpu_discovery_convert_version(u32 major, u32 minor, u32 
> revision)
> +{
> + return (major << 16) | (minor << 8) | revision;

This does the same as the IP_VERSION macro defined in the previous
patch. Do you need this function at all?

Regards,
  Felix


> +}
> +
>  int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
>  {
>struct binary_header *bhdr;
> @@ -316,8 +321,9 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device 
> *adev)
>
> hw_id_names[le16_to_cpu(ip->hw_id)]);
>
> adev->reg_offset[hw_ip][ip->number_instance] =
>ip->base_address;
> + adev->ip_versions[hw_ip] =
> + 
> amdgpu_discovery_convert_version(ip->major, ip->minor, ip->revision);
>}
> -
>}
>
>ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 
> 1);

RE: [PATCHv2 1/2] x86/MCE/AMD: Export smca_get_bank_type symbol

[Deucher, Alexander]

[Public]

> -Original Message-
> From: amd-gfx  On Behalf Of
> Borislav Petkov
> Sent: Wednesday, September 22, 2021 7:34 AM
> To: Joshi, Mukul ; Alex Deucher
> 
> Cc: linux-e...@vger.kernel.org; x...@kernel.org; linux-
> ker...@vger.kernel.org; mi...@redhat.com; mche...@kernel.org;
> Ghannam, Yazen ; amd-
> g...@lists.freedesktop.org
> Subject: Re: [PATCHv2 1/2] x86/MCE/AMD: Export smca_get_bank_type
> symbol
> 
> On Sun, Sep 12, 2021 at 10:13:10PM -0400, Mukul Joshi wrote:
> > Export smca_get_bank_type for use in the AMD GPU driver to determine
> > MCA bank while handling correctable and uncorrectable errors in GPU
> > UMC.
> >
> > v1->v2:
> > - Drop the function is_smca_umc_v2().
> > - Drop the patch to introduce a new MCE priority (MCE_PRIO_ACEL)
> >   for GPU/accelarator cards.
> 
> Patch changelog information goes...
> 
> >
> > Signed-off-by: Mukul Joshi 
> > ---
> 
> ... under this line so that it gets automatically removed by git when applying
> the patch.
> 
> Alex, how do you wanna handle this?
> 
> Want me to ACK this and you can carry it through your tree along with the
> second patch?

That would be great.  Thanks!

Alex

> 
> --
> Regards/Gruss,
> Boris.
> 
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpeo
> ple.kernel.org%2Ftglx%2Fnotes-about-
> netiquettedata=04%7C01%7Calexander.deucher%40amd.com%7C12b
> cf4eeffad4e2533b508d97dca1cf4%7C3dd8961fe4884e608e11a82d994e183d%
> 7C0%7C0%7C637679129761221057%7CUnknown%7CTWFpbGZsb3d8eyJWIjoi
> MC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C200
> 0sdata=tK9aK%2FHf5RimF%2FenuTGeJSFFmRuk86Q%2BqY9Jt23gKMQ
> %3Dreserved=0

Re: [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more IP version checking

[Deucher, Alexander]

[Public]

Fixed locally.

From: Lazar, Lijo 
Sent: Wednesday, September 22, 2021 4:16 AM
To: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more IP version 
checking



On 9/21/2021 11:37 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> Signed-off-by: Alex Deucher 
> ---
>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 ++-
>   1 file changed, 18 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 5f372d353d9d..150cac4ea75c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -455,8 +455,7 @@ static int smu_get_power_num_states(void *handle,
>
>   bool is_support_sw_smu(struct amdgpu_device *adev)
>   {
> - if ((adev->asic_type >= CHIP_ARCTURUS) ||
> - (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0)))
> + if (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0))
>return true;
>
>return false;
> @@ -600,23 +599,19 @@ static int smu_set_funcs(struct amdgpu_device *adev)
>case IP_VERSION(11, 0, 8):
>cyan_skillfish_set_ppt_funcs(smu);
>break;
> - default:
> - switch (adev->asic_type) {
> - case CHIP_ARCTURUS:
> - adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> - arcturus_set_ppt_funcs(smu);
> - /* OD is not supported on Arcturus */
> - smu->od_enabled =false;
> - break;
> - case CHIP_ALDEBARAN:
> - aldebaran_set_ppt_funcs(smu);
> - /* Enable pp_od_clk_voltage node */
> - smu->od_enabled = true;
> - break;
> - default:
> - return -EINVAL;
> - }
> + case IP_VERSION(11, 0, 2):
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> + arcturus_set_ppt_funcs(smu);
> + /* OD is not supported on Arcturus */
> + smu->od_enabled =false;
> + break;
> + case IP_VERSION(13, 0, 2):
> + aldebaran_set_ppt_funcs(smu);
> + /* Enable pp_od_clk_voltage node */
> + smu->od_enabled = true;
>break;
> + default:
> + return -EINVAL;
>}
>
>return 0;
> @@ -2288,11 +2283,11 @@ int smu_get_power_limit(void *handle,
>} else {
>switch (limit_level) {
>case SMU_PPT_LIMIT_CURRENT:
> - if ((smu->adev->asic_type == CHIP_ALDEBARAN) ||
> -  (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 
> 7)) ||
> -  (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 
> 11)) ||
> -  (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 
> 12)) ||
> -  (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 
> 13)))
> + if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 
> 2)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 
> 7)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 
> 11)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 
> 12)) ||
> + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 
> 13)))

Maybe seen/commented before, anyway switch...case

Thanks,
Lijo

>ret = smu_get_asic_power_limits(smu,
>
> >current_power_limit,
>NULL,
>

Re: [PATCH 29/66] drm/amdgpu/display/dm: convert to IP version checking

[Deucher, Alexander]

[AMD Official Use Only]

Fixed locally.

Alex


From: Lazar, Lijo 
Sent: Wednesday, September 22, 2021 3:37 AM
To: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH 29/66] drm/amdgpu/display/dm: convert to IP version checking



On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> Signed-off-by: Alex Deucher 
> ---
>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 194 ++
>   1 file changed, 109 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 07adac1a8c42..e189d72f08e9 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1342,16 +1342,23 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
>case CHIP_CARRIZO:
>case CHIP_STONEY:
>case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - init_data.flags.gpu_vm_support = true;
> - if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> - init_data.flags.disable_dmcu = true;
> - break;
> - case CHIP_VANGOGH:
> - case CHIP_YELLOW_CARP:
>init_data.flags.gpu_vm_support = true;
>break;
>default:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 1, 0):
> + init_data.flags.gpu_vm_support = true;
> + if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> + init_data.flags.disable_dmcu = true;
> + break;
> + case IP_VERSION(3, 0, 1):
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> + init_data.flags.gpu_vm_support = true;
> + break;
> + default:
> + break;
> + }
>break;
>}
>
> @@ -1442,7 +1449,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
>   #endif
>
>   #ifdef CONFIG_DRM_AMD_DC_HDCP
> - if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
> + if (adev->dm.dc->caps.max_links > 0 && adev->family >= 
> AMDGPU_FAMILY_RV) {
>adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, 
> _params.cp_psp, adev->dm.dc);
>
>if (!adev->dm.hdcp_workqueue)
> @@ -1637,15 +1644,6 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
>case CHIP_VEGA10:
>case CHIP_VEGA12:
>case CHIP_VEGA20:
> - case CHIP_NAVI10:
> - case CHIP_NAVI14:
> - case CHIP_RENOIR:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_VANGOGH:
> - case CHIP_YELLOW_CARP:
>return 0;
>case CHIP_NAVI12:
>fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
> @@ -1659,6 +1657,20 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
>return 0;
>break;
>default:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 0, 2):
> + case IP_VERSION(2, 0, 0):
> + case IP_VERSION(2, 1, 0):
> + case IP_VERSION(3, 0, 0):
> + case IP_VERSION(3, 0, 2):
> + case IP_VERSION(3, 0, 3):
> + case IP_VERSION(3, 0, 1):
> + case IP_VERSION(3, 1, 2):
> + case IP_VERSION(3, 1, 3):
> + return 0;
> + default:
> + break;
> + }
>DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
>return -EINVAL;
>}
> @@ -1737,34 +1749,36 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
>enum dmub_status status;
>int r;
>
> - switch (adev->asic_type) {
> - case CHIP_RENOIR:
> + switch (adev->ip_versions[DCE_HWIP]) {
> + case IP_VERSION(2, 1, 0):
>dmub_asic = DMUB_ASIC_DCN21;
>fw_name_dmub = FIRMWARE_RENOIR_DMUB;
>if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
>fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
>break;
> - case CHIP_SIENNA_CICHLID:
> - dmub_asic = DMUB_ASIC_DCN30;
> - fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;

Re: [PATCH 23/66] drm/amdgpu/amdgpu_smu: convert to IP version checking

[Deucher, Alexander]

[Public]

Fixed locally.  Thanks!

From: Lazar, Lijo 
Sent: Wednesday, September 22, 2021 3:32 AM
To: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH 23/66] drm/amdgpu/amdgpu_smu: convert to IP version checking



On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> v2: rebase
>
> Signed-off-by: Alex Deucher 
> ---
>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 94 +--
>   1 file changed, 55 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 04863a797115..5f372d353d9d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -455,7 +455,8 @@ static int smu_get_power_num_states(void *handle,
>
>   bool is_support_sw_smu(struct amdgpu_device *adev)
>   {
> - if (adev->asic_type >= CHIP_ARCTURUS)
> + if ((adev->asic_type >= CHIP_ARCTURUS) ||
> + (adev->ip_versions[MP1_HWIP] >= IP_VERSION(11, 0, 0)))
>return true;
>
>return false;
> @@ -575,43 +576,47 @@ static int smu_set_funcs(struct amdgpu_device *adev)
>if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
>smu->od_enabled = true;
>
> - switch (adev->asic_type) {
> - case CHIP_NAVI10:
> - case CHIP_NAVI14:
> - case CHIP_NAVI12:
> + switch (adev->ip_versions[MP1_HWIP]) {
> + case IP_VERSION(11, 0, 0):
> + case IP_VERSION(11, 0, 5):
> + case IP_VERSION(11, 0, 9):
>navi10_set_ppt_funcs(smu);
>break;
> - case CHIP_ARCTURUS:
> - adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> - arcturus_set_ppt_funcs(smu);
> - /* OD is not supported on Arcturus */
> - smu->od_enabled =false;
> - break;
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> + case IP_VERSION(11, 0, 7):
> + case IP_VERSION(11, 0, 11):
> + case IP_VERSION(11, 0, 12):
> + case IP_VERSION(11, 0, 13):
>sienna_cichlid_set_ppt_funcs(smu);
>break;
> - case CHIP_ALDEBARAN:
> - aldebaran_set_ppt_funcs(smu);
> - /* Enable pp_od_clk_voltage node */
> - smu->od_enabled = true;
> - break;
> - case CHIP_RENOIR:
> + case IP_VERSION(12, 0, 0):
>renoir_set_ppt_funcs(smu);
>break;
> - case CHIP_VANGOGH:
> + case IP_VERSION(11, 5, 0):
>vangogh_set_ppt_funcs(smu);
>break;
> - case CHIP_YELLOW_CARP:
> + case IP_VERSION(13, 0, 1):
>yellow_carp_set_ppt_funcs(smu);
>break;
> - case CHIP_CYAN_SKILLFISH:
> + case IP_VERSION(11, 0, 8):
>cyan_skillfish_set_ppt_funcs(smu);
>break;
>default:
> - return -EINVAL;
> + switch (adev->asic_type) {
> + case CHIP_ARCTURUS:
> + adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
> + arcturus_set_ppt_funcs(smu);
> + /* OD is not supported on Arcturus */
> + smu->od_enabled =false;
> + break;
> + case CHIP_ALDEBARAN:
> + aldebaran_set_ppt_funcs(smu);
> + /* Enable pp_od_clk_voltage node */
> + smu->od_enabled = true;
> + break;
> + default:
> + return -EINVAL;
> + }
> + break;
>}
>
>return 0;
> @@ -694,7 +699,7 @@ static int smu_late_init(void *handle)
>return ret;
>}
>
> - if (adev->asic_type == CHIP_YELLOW_CARP)
> + if (adev->ip_versions[MP1_HWIP] == IP_VERSION(13, 0, 1))
>return 0;
>
>if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
> @@ -1140,8 +1145,10 @@ static int smu_smc_hw_setup(struct smu_context *smu)
>if (adev->in_suspend && smu_is_dpm_running(smu)) {
>dev_info(adev->dev, "dpm has been enabled\n");
>/* this is needed specifically */
> - if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
> - (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
> + if ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7)) 

Re: [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs

[Deucher, Alexander]

[AMD Official Use Only]

Fixed locally.  Thanks!

From: Lazar, Lijo 
Sent: Wednesday, September 22, 2021 12:41 AM
To: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH 11/66] drm/amdgpu: filter out radeon PCI device IDs



On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Once we claim all 0x1002 PCI display class devices, we will
> need to filter out devices owned by radeon.
>
> Signed-off-by: Alex Deucher 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 561 +++-
>   1 file changed, 560 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index b6ce53fa9b03..3ab7099a1b16 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -891,6 +891,559 @@ MODULE_PARM_DESC(smu_pptable_id,
>"specify pptable id to be used (-1 = auto(default) value, 0 = use 
> pptable from vbios, > 0 = soft pptable id)");
>   module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
>
> +static const u16 radeon_pciidlist[] = {

Instead of associating to only radeon, maybe rename to something more
generic such that all device ids in the list will be skipped.

Thanks,
Lijo

> + 0x3150,
> + 0x3151,
> + 0x3152,
> + 0x3154,
> + 0x3155,
> + 0x3E50,
> + 0x3E54,
> + 0x4136,
> + 0x4137,
> + 0x4144,
> + 0x4145,
> + 0x4146,
> + 0x4147,
> + 0x4148,
> + 0x4149,
> + 0x414A,
> + 0x414B,
> + 0x4150,
> + 0x4151,
> + 0x4152,
> + 0x4153,
> + 0x4154,
> + 0x4155,
> + 0x4156,
> + 0x4237,
> + 0x4242,
> + 0x4336,
> + 0x4337,
> + 0x4437,
> + 0x4966,
> + 0x4967,
> + 0x4A48,
> + 0x4A49,
> + 0x4A4A,
> + 0x4A4B,
> + 0x4A4C,
> + 0x4A4D,
> + 0x4A4E,
> + 0x4A4F,
> + 0x4A50,
> + 0x4A54,
> + 0x4B48,
> + 0x4B49,
> + 0x4B4A,
> + 0x4B4B,
> + 0x4B4C,
> + 0x4C57,
> + 0x4C58,
> + 0x4C59,
> + 0x4C5A,
> + 0x4C64,
> + 0x4C66,
> + 0x4C67,
> + 0x4E44,
> + 0x4E45,
> + 0x4E46,
> + 0x4E47,
> + 0x4E48,
> + 0x4E49,
> + 0x4E4A,
> + 0x4E4B,
> + 0x4E50,
> + 0x4E51,
> + 0x4E52,
> + 0x4E53,
> + 0x4E54,
> + 0x4E56,
> + 0x5144,
> + 0x5145,
> + 0x5146,
> + 0x5147,
> + 0x5148,
> + 0x514C,
> + 0x514D,
> + 0x5157,
> + 0x5158,
> + 0x5159,
> + 0x515A,
> + 0x515E,
> + 0x5460,
> + 0x5462,
> + 0x5464,
> + 0x5548,
> + 0x5549,
> + 0x554A,
> + 0x554B,
> + 0x554C,
> + 0x554D,
> + 0x554E,
> + 0x554F,
> + 0x5550,
> + 0x5551,
> + 0x5552,
> + 0x5554,
> + 0x564A,
> + 0x564B,
> + 0x564F,
> + 0x5652,
> + 0x5653,
> + 0x5657,
> + 0x5834,
> + 0x5835,
> + 0x5954,
> + 0x5955,
> + 0x5974,
> + 0x5975,
> + 0x5960,
> + 0x5961,
> + 0x5962,
> + 0x5964,
> + 0x5965,
> + 0x5969,
> + 0x5a41,
> + 0x5a42,
> + 0x5a61,
> + 0x5a62,
> + 0x5b60,
> + 0x5b62,
> + 0x5b63,
> + 0x5b64,
> + 0x5b65,
> + 0x5c61,
> + 0x5c63,
> + 0x5d48,
> + 0x5d49,
> + 0x5d4a,
> + 0x5d4c,
> + 0x5d4d,
> + 0x5d4e,
> + 0x5d4f,
> + 0x5d50,
> + 0x5d52,
> + 0x5d57,
> + 0x5e48,
> + 0x5e4a,
> + 0x5e4b,
> + 0x5e4c,
> + 0x5e4d,
> + 0x5e4f,
> + 0x6700,
> + 0x6701,
> + 0x6702,
> + 0x6703,
> + 0x6704,
> + 0x6705,
> + 0x6706,
> + 0x6707,
> + 0x6708,
> + 0x6709,
> + 0x6718,
> + 0x6719,
> + 0x671c,
> + 0x671d,
> + 0x671f,
> + 0x6720,
> + 0x6721,
> + 0x6722,
> + 0x6723,
> + 0x6724,
> + 0x6725,
> + 0x6726,
> + 0x6727,
> + 0x6728,
> + 0x6729,
> + 0x6738,
> + 0x6739,
> + 0x673e,
> + 0x6740,
> + 0x6741,
> + 0x6742,
> + 0x6743,
> + 0x6744,
> + 0x6745,
> + 0x6746,
> + 0x6747,
> + 0x6748,
> + 0x6749,
> + 0x674A,
> + 0x6750,
> + 0x6751,
> + 0x6758,
> + 0x6759,
> + 0x675B,
> + 0x675D,
> + 0x675F,
> + 0x6760,
> + 0x6761,
> + 0x6762,
> + 0x6763,
> + 0x6764,
> + 0x6765,
> + 

Re: [PATCH] drm/amd/display: Set the domain as GTT when VRAM size <= 32 MB

[Deucher, Alexander]

[Public]

I think this may have already been fixed with this patch:
https://gitlab.freedesktop.org/agd5f/linux/-/commit/2a7b9a8437130fd328001f4edfac8eec98dfe298

Alex


From: Mahapatra, Rajib 
Sent: Thursday, August 26, 2021 2:07 PM
To: Wentland, Harry ; Kazlauskas, Nicholas 
; Deucher, Alexander ; 
Wu, Hersen 
Cc: amd-gfx@lists.freedesktop.org ; Mahapatra, 
Rajib 
Subject: [PATCH] drm/amd/display: Set the domain as GTT when VRAM size <= 32 MB

[Why]
In lower carve out (<= 32 MB) devices, it was unable to pin framebuffer in
VRAM domain for some BO allocations. The device shows below error logs and
sometimes it reboots too.

amdgpu :02:00.0: amdgpu: d721431c pin failed
[drm:dm_plane_helper_prepare_fb] *ERROR* Failed to pin framebuffer with error 
-12

[How]
Place the domain as GTT when VRAM size <= 32 MB.

Signed-off-by: Rajib Mahapatra 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index dc3c6b3a00e5..d719be448eec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -236,6 +236,7 @@ extern int amdgpu_num_kcq;

 #define AMDGPU_VM_MAX_NUM_CTX   4096
 #define AMDGPU_SG_THRESHOLD (256*1024*1024)
+#define AMDGPU_VRAM_MIN_THRESHOLD  (32*1024*1024)
 #define AMDGPU_DEFAULT_GTT_SIZE_MB  3072ULL /* 3GB by default */
 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS  3000
 #define AMDGPU_MAX_USEC_TIMEOUT 10  /* 100 ms */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e1e57e7465a7..f71391599be1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7106,8 +7106,16 @@ static int dm_plane_helper_prepare_fb(struct drm_plane 
*plane,
 return r;
 }

-   if (plane->type != DRM_PLANE_TYPE_CURSOR)
+   if (plane->type != DRM_PLANE_TYPE_CURSOR) {
 domain = amdgpu_display_supported_domains(adev, rbo->flags);
+   /*
+* Handle devices with lower carve out.
+*/
+   if (adev->gmc.real_vram_size <= AMDGPU_VRAM_MIN_THRESHOLD) {
+   domain |= (domain & AMDGPU_GEM_DOMAIN_GTT) ? domain :
+  AMDGPU_GEM_DOMAIN_GTT;
+   }
+   }
 else
 domain = AMDGPU_GEM_DOMAIN_VRAM;

--
2.25.1

Re: [PATCH] drm/amdgpu: reenable BACO support for 699F:C7 polaris12 SKU

[Deucher, Alexander]

[Public]

Acked-by: Alex Deucher 

From: Quan, Evan 
Sent: Tuesday, August 24, 2021 11:58 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Chen, Guchun 
; Quan, Evan 
Subject: [PATCH] drm/amdgpu: reenable BACO support for 699F:C7 polaris12 SKU

This reverts the commit below:
"drm/amdgpu: disable BACO support for 699F:C7 polaris12 SKU temporarily".
As the S3 hang issue has been fixed by another commit:
"drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend".

Change-Id: I5ea08a75eedd7fe32c7fa0b448f5bae1f390abe6
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/vi.c | 9 +
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 42a35d9520f9..fe9a7cc8d9eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -904,14 +904,7 @@ static bool vi_asic_supports_baco(struct amdgpu_device 
*adev)
 case CHIP_POLARIS11:
 case CHIP_POLARIS12:
 case CHIP_TOPAZ:
-   /* Disable BACO support for the specific polaris12 SKU 
temporarily */
-   if ((adev->pdev->device == 0x699F) &&
-(adev->pdev->revision == 0xC7) &&
-(adev->pdev->subsystem_vendor == 0x1028) &&
-(adev->pdev->subsystem_device == 0x0039))
-   return false;
-   else
-   return amdgpu_dpm_is_baco_supported(adev);
+   return amdgpu_dpm_is_baco_supported(adev);
 default:
 return false;
 }
--
2.29.0

Re: [PATCH] drm/amd/amdgpu: New debugfs interface for MMIO registers (v4)

[Deucher, Alexander]

[AMD Official Use Only]

I think it would be good to put the IOCTL structures in their own header to 
make it easier to share with umr.  No need to put it in uapi area though.  We 
also need a umr branch that utilizes this to upstream the changes.

Alex


From: amd-gfx  on behalf of Tom St Denis 

Sent: Wednesday, August 25, 2021 9:09 AM
To: amd-gfx@lists.freedesktop.org 
Cc: StDenis, Tom 
Subject: [PATCH] drm/amd/amdgpu: New debugfs interface for MMIO registers (v4)

This new debugfs interface uses an IOCTL interface in order to pass
along state information like SRBM and GRBM bank switching.  This
new interface also allows a full 32-bit MMIO address range which
the previous didn't.  With this new design we have room to grow
the flexibility of the file as need be.

(v2): Move read/write to .read/.write, fix style, add comment
  for IOCTL data structure

(v3): C style comments

(v4): use u32 in struct and remove offset variable

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 158 
 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h |  29 
 2 files changed, 187 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 277128846dd1..6450f210f6c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -279,6 +279,152 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, 
const char __user *buf,
 return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, 
size, pos);
 }

+static int amdgpu_debugfs_regs2_open(struct inode *inode, struct file *file)
+{
+   struct amdgpu_debugfs_regs2_data *rd;
+
+   rd = kzalloc(sizeof *rd, GFP_KERNEL);
+   if (!rd)
+   return -ENOMEM;
+   rd->adev = file_inode(file)->i_private;
+   file->private_data = rd;
+
+   return 0;
+}
+
+static int amdgpu_debugfs_regs2_release(struct inode *inode, struct file *file)
+{
+   kfree(file->private_data);
+   return 0;
+}
+
+static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 
offset, size_t size, int write_en)
+{
+   struct amdgpu_debugfs_regs2_data *rd = f->private_data;
+   struct amdgpu_device *adev = rd->adev;
+   ssize_t result = 0;
+   int r;
+   uint32_t value;
+
+   if (size & 0x3 || offset & 0x3)
+   return -EINVAL;
+
+   if (rd->id.use_grbm) {
+   if (rd->id.grbm.se == 0x3FF)
+   rd->id.grbm.se = 0x;
+   if (rd->id.grbm.sh == 0x3FF)
+   rd->id.grbm.sh = 0x;
+   if (rd->id.grbm.instance == 0x3FF)
+   rd->id.grbm.instance = 0x;
+   }
+
+   r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
+   if (r < 0) {
+   pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+   return r;
+   }
+
+   r = amdgpu_virt_enable_access_debugfs(adev);
+   if (r < 0) {
+   pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+   return r;
+   }
+
+   if (rd->id.use_grbm) {
+   if ((rd->id.grbm.sh != 0x && rd->id.grbm.sh >= 
adev->gfx.config.max_sh_per_se) ||
+   (rd->id.grbm.se != 0x && rd->id.grbm.se >= 
adev->gfx.config.max_shader_engines)) {
+   pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
+   pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+   amdgpu_virt_disable_access_debugfs(adev);
+   return -EINVAL;
+   }
+   mutex_lock(>grbm_idx_mutex);
+   amdgpu_gfx_select_se_sh(adev, rd->id.grbm.se,
+   rd->id.grbm.sh,
+   
rd->id.grbm.instance);
+   }
+
+   if (rd->id.use_srbm) {
+   mutex_lock(>srbm_mutex);
+   amdgpu_gfx_select_me_pipe_q(adev, rd->id.srbm.me, 
rd->id.srbm.pipe,
+   
rd->id.srbm.queue, rd->id.srbm.vmid);
+   }
+
+   if (rd->id.pg_lock)
+   mutex_lock(>pm.mutex);
+
+   while (size) {
+   if (!write_en) {
+   value = RREG32(offset >> 2);
+   r = put_user(value, (uint32_t *)buf);
+   } else {
+   r = get_user(value, (uint32_t *)buf);
+   if (!r)
+   amdgpu_mm_wreg_mmio_rlc(adev, offset >> 2, 
value);
+   }
+   if (r) {
+   result = r;
+   goto end;
+   }
+   offset += 4;
+   size -= 4;
+   result += 4;
+   buf += 4;
+   }
+end:
+   if (rd->id.use_grbm) {
+ 

RE: [PATCH] drm/amd/pm: And destination bounds checking to struct copy

[Deucher, Alexander]

[Public]

> -Original Message-
> From: Koenig, Christian 
> Sent: Monday, August 23, 2021 3:02 PM
> To: Kees Cook ; Lazar, Lijo
> 
> Cc: Pan, Xinhui ; David Airlie ;
> Daniel Vetter ; Zhang, Hawking
> ; Xu, Feifei ; Gao, Likun
> ; Gu, JiaWei (Will) ; Quan,
> Evan ; amd-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; Deucher, Alexander
> ; Tuikov, Luben
> ; Grodzovsky, Andrey
> ; Li, Dennis ;
> Sundararaju, Sathishkumar ; Kim,
> Jonathan ; Wang, Kevin(Yang)
> ; Nieto, David M ; Feng,
> Kenneth ; Lee Jones ;
> Clements, John ; linux-ker...@vger.kernel.org;
> linux-harden...@vger.kernel.org
> Subject: Re: [PATCH] drm/amd/pm: And destination bounds checking to
> struct copy
> 
> Am 23.08.21 um 16:23 schrieb Kees Cook:
> >
> > On August 22, 2021 11:28:54 PM PDT, "Christian König"
>  wrote:
> >>
> >> Am 19.08.21 um 22:14 schrieb Kees Cook:
> >>> [...]
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> index 96e895d6be35..4605934a4fb7 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >>> @@ -1446,4 +1446,29 @@ static inline int amdgpu_in_reset(struct
> amdgpu_device *adev)
> >>>{
> >>>   return atomic_read(>in_gpu_reset);
> >>>}
> >>> +
> >>> +/**
> >>> + * memcpy_trailing - Copy the end of one structure into the middle
> >>> +of another
> >>> + *
> >>> + * @dst: Pointer to destination struct
> >>> + * @first_dst_member: The member name in @dst where the
> overwrite
> >>> +begins
> >>> + * @last_dst_member: The member name in @dst where the
> overwrite
> >>> +ends after
> >>> + * @src: Pointer to the source struct
> >>> + * @first_src_member: The member name in @src where the copy
> begins
> >>> + *
> >>> + */
> >>> +#define memcpy_trailing(dst, first_dst_member, last_dst_member,
>  \
> >>> + src, first_src_member) \
> >> Please don't add a function like this into amdgpu.h, especially when
> >> it is only used by the SMU code.
> > Sure, I'm happy to move it. It wasn't clear to me which headers were
> considered "immutable". Which header should I put this in?
> 
> I think amdgpu_smuio.h, but I'm not 100% sure. Alex do you have a better
> idea?
> 

No, that's for the SMUIO callbacks for the IP block.  Please use 
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h

Alex

> We don't want to put anything new into amdgpu.h any more since this is
> basically only a legacy leftover.
> 
> Thanks,
> Christian.
> 
> >
> >> And please give it an amdgpu_ prefix so that we are not confusing it
> >> with a core function.
> > Sure, I will include that.
> >
> >> Apart from that looks good to me.
> > Thanks!
> >
> > -Kees

Re: [PATCH] drm/amdgpu: update PSP BL cmd IDs

[Deucher, Alexander]

[Public]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Clements, 
John 
Sent: Tuesday, August 3, 2021 4:20 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: update PSP BL cmd IDs


[AMD Official Use Only]


Submitting patch to resolve issue with incorrect PSP BL cmd IDs

Re: [PATCH] drm/amdgpu/display: fix DMUB firmware version info

[Deucher, Alexander]

[AMD Official Use Only]

Reviewed-by: Alex Deucher 

From: S, Shirish 
Sent: Tuesday, August 3, 2021 4:42 AM
To: Wentland, Harry ; Kazlauskas, Nicholas 
; Deucher, Alexander 
Cc: amd-gfx@lists.freedesktop.org ; S, Shirish 

Subject: [PATCH] drm/amdgpu/display: fix DMUB firmware version info

DMUB firmware info is printed before it gets initialized.
Correct this order to ensure true value is conveyed.

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7e09b6d26a51..396a2dca2fe0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1548,6 +1548,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
 }

 hdr = (const struct dmcub_firmware_header_v1_0 
*)adev->dm.dmub_fw->data;
+   adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);

 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
@@ -1561,7 +1562,6 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
  adev->dm.dmcub_fw_version);
 }

-   adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);

 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
 dmub_srv = adev->dm.dmub_srv;
--
2.17.1

Re: [PATCH] drm/amd/pm: update yellow carp pmfw interface version

[Deucher, Alexander]

[AMD Official Use Only]

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Xiaomeng Hou 

Sent: Thursday, July 29, 2021 10:40 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Hou, Xiaomeng (Matthew) ; Liu, Aaron 

Subject: [PATCH] drm/amd/pm: update yellow carp pmfw interface version

Correct yellow carp driver-PMFW interface version to v4.

Signed-off-by: Xiaomeng Hou 
---
 drivers/gpu/drm/amd/pm/inc/smu_v13_0.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
index 3fea2430dec0..dc91eb608791 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0.h
@@ -26,7 +26,7 @@
 #include "amdgpu_smu.h"

 #define SMU13_DRIVER_IF_VERSION_INV 0x
-#define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x03
+#define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04
 #define SMU13_DRIVER_IF_VERSION_ALDE 0x07

 /* MP Apertures */
--
2.17.1

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Re: [PATCH v4] drm/amdgpu: fix the doorbell missing when in CGPG issue for renoir.

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Yifan Zhang 

Sent: Thursday, July 29, 2021 5:46 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Zhang, Yifan 
Subject: [PATCH v4] drm/amdgpu: fix the doorbell missing when in CGPG issue for 
renoir.

If GC has entered CGPG, ringing doorbell > first page doesn't wakeup GC.
Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround this issue.

Signed-off-by: Yifan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 21 -
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 03acc777adf7..ab79ca770dcd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1295,6 +1295,16 @@ static bool is_raven_kicker(struct amdgpu_device *adev)
 return false;
 }

+static bool check_if_enlarge_doorbell_range(struct amdgpu_device *adev)
+{
+   if ((adev->asic_type == CHIP_RENOIR) &&
+   (adev->gfx.me_fw_version >= 0x00a5) &&
+   (adev->gfx.me_feature_version >= 52))
+   return true;
+   else
+   return false;
+}
+
 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
 {
 if (gfx_v9_0_should_disable_gfxoff(adev->pdev))
@@ -3675,7 +3685,16 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring 
*ring)
 if (ring->use_doorbell) {
 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
 (adev->doorbell_index.kiq * 2) << 2);
-   WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+   /* If GC has entered CGPG, ringing doorbell > first page
+* doesn't wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to
+* workaround this issue. And this change has to align with 
firmware
+* update.
+*/
+   if (check_if_enlarge_doorbell_range(adev))
+   WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
+   (adev->doorbell.size - 4));
+   else
+   WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
 (adev->doorbell_index.userqueue_end * 
2) << 2);
 }

--
2.25.1

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Re: [PATCH] drm/amdgpu: Rename amdgpu_acpi_is_s0ix_supported

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: Vishwakarma, Pratik 
Sent: Monday, July 26, 2021 8:33 AM
To: Deucher, Alexander ; Lazar, Lijo 
; amd-gfx@lists.freedesktop.org 

Cc: Vishwakarma, Pratik 
Subject: [PATCH] drm/amdgpu: Rename amdgpu_acpi_is_s0ix_supported

Rename amdgpu_acpi_is_s0ix_supported to better explain
functionality by renaming to amdgpu_acpi_is_s0ix_active

Signed-off-by: Pratik Vishwakarma 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index dbaa79ddd468..d10baa3338bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1390,12 +1390,12 @@ int amdgpu_acpi_smart_shift_update(struct drm_device 
*dev, enum amdgpu_ss ss_sta
 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);

 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
-bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev);
+bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
 void amdgpu_acpi_detect(void);
 #else
 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
-static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { 
return false; }
+static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { 
return false; }
 static inline void amdgpu_acpi_detect(void) { }
 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return 
false; }
 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index bf59bb263816..0c281c7f5cea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -1031,13 +1031,13 @@ void amdgpu_acpi_detect(void)
 }

 /**
- * amdgpu_acpi_is_s0ix_supported
+ * amdgpu_acpi_is_s0ix_active
  *
  * @adev: amdgpu_device_pointer
  *
  * returns true if supported, false if not.
  */
-bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev)
+bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev)
 {
 #if defined(CONFIG_AMD_PMC) || defined(CONFIG_AMD_PMC_MODULE)
 if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index af1710971ff3..bbc6bfadafd6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1468,7 +1468,7 @@ static int amdgpu_pmops_suspend(struct device *dev)
 struct amdgpu_device *adev = drm_to_adev(drm_dev);
 int r;

-   if (amdgpu_acpi_is_s0ix_supported(adev))
+   if (amdgpu_acpi_is_s0ix_active(adev))
 adev->in_s0ix = true;
 adev->in_s3 = true;
 r = amdgpu_device_suspend(drm_dev, true);
@@ -1484,7 +1484,7 @@ static int amdgpu_pmops_resume(struct device *dev)
 int r;

 r = amdgpu_device_resume(drm_dev, true);
-   if (amdgpu_acpi_is_s0ix_supported(adev))
+   if (amdgpu_acpi_is_s0ix_active(adev))
 adev->in_s0ix = false;
 return r;
 }
--
2.25.1

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Re: [PATCH V2 1/2] drm/amd/pm: restore user customized OD settings properly for NV1x

[Deucher, Alexander]

[AMD Official Use Only]

I haven't had a chance to look at the patches too closely, but if it could be 
done in a generic may, that makes sense to me.  Maybe as a follow up patch?

Alex


From: Lazar, Lijo 
Sent: Friday, July 23, 2021 6:09 AM
To: Quan, Evan ; amd-gfx@lists.freedesktop.org 

Cc: Deucher, Alexander 
Subject: Re: [PATCH V2 1/2] drm/amd/pm: restore user customized OD settings 
properly for NV1x

The series looks good to me, though I prefer to use a common logic to
restore od settings so that smuv12,smuv13 gets the restore feature by
default once they add the user table logic. Don't have strong argument
for it unless Alex, Kenneth or others have some comments.

Anyway, the series is
Reviewed-by: Lijo Lazar 

On 7/23/2021 2:39 PM, Evan Quan wrote:
> The customized OD settings can be divided into two parts: those
> committed ones and non-committed ones.
>- For those changes which had been fed to SMU before S3/S4/Runpm
>  suspend kicked, they are committed changes. They should be properly
>  restored and fed to SMU on S3/S4/Runpm resume.
>- For those non-committed changes, they are restored only without feeding
>  to SMU.
>
> Change-Id: Iea7cf7908dfcd919a4d0205e10bff91b1149a440
> Signed-off-by: Evan Quan 
> --
> v1->v2
>- better naming and logic revised for checking OD setting update(Lijo)
> ---
>   drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h   |  8 +++
>   drivers/gpu/drm/amd/pm/inc/smu_v11_0.h|  2 +
>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c |  9 +++
>   .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 55 +--
>   .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 25 +
>   5 files changed, 82 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h 
> b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index 3e89852e4820..c2c201b8e3cf 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -231,6 +231,7 @@ struct smu_user_dpm_profile {
>uint32_t power_limit;
>uint32_t fan_speed_percent;
>uint32_t flags;
> + uint32_t user_od;
>
>/* user clock state information */
>uint32_t clk_mask[SMU_CLK_COUNT];
> @@ -352,6 +353,7 @@ struct smu_table_context
>
>void*overdrive_table;
>void*boot_overdrive_table;
> + void*user_overdrive_table;
>
>uint32_tgpu_metrics_table_size;
>void*gpu_metrics_table;
> @@ -623,6 +625,12 @@ struct pptable_funcs {
> enum PP_OD_DPM_TABLE_COMMAND type,
> long *input, uint32_t size);
>
> + /**
> +  * @restore_user_od_settings: Restore the user customized
> +  *OD settings on S3/S4/Runpm resume.
> +  */
> + int (*restore_user_od_settings)(struct smu_context *smu);
> +
>/**
> * @get_clock_by_type_with_latency: Get the speed and latency of a 
> clock
> *  domain.
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
> b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> index 385b2ea5379c..1e42aafbb9fd 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
> @@ -302,5 +302,7 @@ void smu_v11_0_interrupt_work(struct smu_context *smu);
>
>   int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable);
>
> +int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
> +
>   #endif
>   #endif
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index ebe672142808..8ca7337ea5fc 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -416,6 +416,15 @@ static void smu_restore_dpm_user_profile(struct 
> smu_context *smu)
>}
>}
>
> + /* Restore user customized OD settings */
> + if (smu->user_dpm_profile.user_od) {
> + if (smu->ppt_funcs->restore_user_od_settings) {
> + ret = smu->ppt_funcs->restore_user_od_settings(smu);
> + if (ret)
> + dev_err(smu->adev->dev, "Failed to upload 
> customized OD settings\n");
> + }
> + }
> +
>/* Disable restore flag */
>smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
>   }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_

Re: [PATCH] drm/amdgpu: Add msix restore for pass-through mode

[Deucher, Alexander]

[Public]

Acked-by: Alex Deucher 

From: Chengzhe Liu 
Sent: Thursday, July 22, 2021 1:49 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Tuikov, Luben ; Koenig, Christian 
; Deucher, Alexander ; 
Xiao, Jack ; Zhang, Hawking ; Xu, 
Feifei ; Wang, Kevin(Yang) ; Liu, Cheng 
Zhe 
Subject: [PATCH] drm/amdgpu: Add msix restore for pass-through mode

In pass-through mode, after mode 1 reset, msix enablement status would
lost and never receives interrupt again. So, we should restore msix
status after mode 1 reset.

Signed-off-by: Chengzhe Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 83af307e97cd..e1aa4a5e6a98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -584,7 +584,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct 
amdgpu_device *adev)
 {
 int i, j, k;

-   if (amdgpu_sriov_vf(adev))
+   if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
 amdgpu_restore_msix(adev);

 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
--
2.25.1

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Re: [PATCH] drm/amdgpu: Check pmops for desired suspend state

[Deucher, Alexander]

[AMD Official Use Only]

I sent a similar patch out a while ago, but never had a chance to follow up on 
it.  The problem is users might change the default.
https://www.spinics.net/lists/amd-gfx/msg60578.html


Alex


From: Vishwakarma, Pratik 
Sent: Thursday, July 22, 2021 1:27 AM
To: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org 
Cc: Vishwakarma, Pratik 
Subject: [PATCH] drm/amdgpu: Check pmops for desired suspend state

[Why]
User might set mem_sleep as deep and it will result
in amdgpu resume errors.

[How]
Check with pm for default suspend state

Signed-off-by: Pratik Vishwakarma 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index af1710971ff3..d92196429741 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1468,7 +1468,8 @@ static int amdgpu_pmops_suspend(struct device *dev)
 struct amdgpu_device *adev = drm_to_adev(drm_dev);
 int r;

-   if (amdgpu_acpi_is_s0ix_supported(adev))
+   if (amdgpu_acpi_is_s0ix_supported(adev)
+   && pm_suspend_default_s2idle())
 adev->in_s0ix = true;
 adev->in_s3 = true;
 r = amdgpu_device_suspend(drm_dev, true);
--
2.25.1

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Re: [PATCH v2 0/2] Fix regression on embedded panels caused by enabling ASSR

[Deucher, Alexander]

[Public]

Series looks good to me. Thanks!

Alex


From: amd-gfx  on behalf of Stylon Wang 

Sent: Wednesday, July 21, 2021 12:25 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Wang, Chao-kai (Stylon) ; Li, Sun peng (Leo) 
; Wentland, Harry ; Zhuo, Qingqing 
; Siqueira, Rodrigo ; Jacob, 
Anson ; Pillai, Aurabindo ; 
Lakha, Bhawanpreet ; R, Bindu 
Subject: [PATCH v2 0/2] Fix regression on embedded panels caused by enabling 
ASSR

Previous ASSR-enabling patches cause blank screen on some embedded
panels. This patch set minimize the changes made to code logic prior to
the ASSR change and also improve on code readability.

Changes from prior rev1 to now:

v2:
 - Update reviewed-by and bug links

Stylon Wang (2):
  drm/amd/display: Revert "Re-enable 'Guard ASSR with internal display
flag'"
  drm/amd/display: Fix ASSR regression on embedded panels

 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 58 +++
 1 file changed, 20 insertions(+), 38 deletions(-)

--
2.32.0

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Re: [PATCH] drm/amdgpu: Fix documentaion for amdgpu_bo_add_to_shadow_list

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Anson Jacob 

Sent: Monday, July 19, 2021 11:19 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Jacob, Anson 
Subject: [PATCH] drm/amdgpu: Fix documentaion for amdgpu_bo_add_to_shadow_list

make htmldocs complaints about parameter for amdgpu_bo_add_to_shadow_list

./drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:739: warning: Excess function 
parameter 'bo' description in 'amdgpu_bo_add_to_shadow_list'
./drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:739: warning: Function parameter 
or member 'vmbo' not described in 'amdgpu_bo_add_to_shadow_list'
./drivers/gpu/drm/amd/amdgpu/amdgpu_object.c:739: warning: Excess function 
parameter 'bo' description in 'amdgpu_bo_add_to_shadow_list'

Signed-off-by: Anson Jacob 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index ea339eaac399..4e2c0270208f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -755,7 +755,7 @@ int amdgpu_bo_validate(struct amdgpu_bo *bo)
 /**
  * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list
  *
- * @bo: BO that will be inserted into the shadow list
+ * @vmbo: BO that will be inserted into the shadow list
  *
  * Insert a BO to the shadow list.
  */
--
2.25.1

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Re: [PATCH 2/5] drm/amdgpu: Change a few function names

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 


From: amd-gfx  on behalf of Oak Zeng 

Sent: Thursday, July 15, 2021 9:25 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Xu, Feifei ; Kuehling, Felix ; 
Liu, Leo ; Zeng, Oak ; Zhang, Hawking 

Subject: [PATCH 2/5] drm/amdgpu: Change a few function names

Function name "psp_np_fw_load" is not proper as people don't
know _np_fw_ means "non psp firmware". Change the function
name to psp_load_non_psp_fw for better understanding. Same
thing for function psp_execute_np_fw_load.

Signed-off-by: Oak Zeng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index d9ddb2c..8d1e2b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2351,7 +2351,7 @@ static int psp_prep_load_ip_fw_cmd_buf(struct 
amdgpu_firmware_info *ucode,
 return ret;
 }

-static int psp_execute_np_fw_load(struct psp_context *psp,
+static int psp_execute_non_psp_fw_load(struct psp_context *psp,
   struct amdgpu_firmware_info *ucode)
 {
 int ret = 0;
@@ -2387,7 +2387,7 @@ static int psp_load_smu_fw(struct psp_context *psp)
 }
 }

-   ret = psp_execute_np_fw_load(psp, ucode);
+   ret = psp_execute_non_psp_fw_load(psp, ucode);

 if (ret)
 DRM_ERROR("PSP load smu failed!\n");
@@ -2442,14 +2442,14 @@ int psp_load_fw_list(struct psp_context *psp,
 for (i = 0; i < ucode_count; ++i) {
 ucode = ucode_list[i];
 psp_print_fw_hdr(psp, ucode);
-   ret = psp_execute_np_fw_load(psp, ucode);
+   ret = psp_execute_non_psp_fw_load(psp, ucode);
 if (ret)
 return ret;
 }
 return ret;
 }

-static int psp_np_fw_load(struct psp_context *psp)
+static int psp_load_non_psp_fw(struct psp_context *psp)
 {
 int i, ret;
 struct amdgpu_firmware_info *ucode;
@@ -2488,7 +2488,7 @@ static int psp_np_fw_load(struct psp_context *psp)

 psp_print_fw_hdr(psp, ucode);

-   ret = psp_execute_np_fw_load(psp, ucode);
+   ret = psp_execute_non_psp_fw_load(psp, ucode);
 if (ret)
 return ret;

@@ -2565,7 +2565,7 @@ static int psp_load_fw(struct amdgpu_device *adev)
 if (ret)
 goto failed;

-   ret = psp_np_fw_load(psp);
+   ret = psp_load_non_psp_fw(psp);
 if (ret)
 goto failed;

@@ -2765,7 +2765,7 @@ static int psp_resume(void *handle)
 if (ret)
 goto failed;

-   ret = psp_np_fw_load(psp);
+   ret = psp_load_non_psp_fw(psp);
 if (ret)
 goto failed;

@@ -2863,7 +2863,7 @@ int psp_update_vcn_sram(struct amdgpu_device *adev, int 
inst_idx,
 ucode.mc_addr = cmd_gpu_addr;
 ucode.ucode_size = cmd_size;

-   return psp_execute_np_fw_load(>psp, );
+   return psp_execute_non_psp_fw_load(>psp, );
 }

 int psp_ring_cmd_submit(struct psp_context *psp,
--
2.7.4

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Re: [PATCH 1/5] drm/amdgpu: Fix a printing message

[Deucher, Alexander]

[Public]

Please use dev_info rather than DRM_INFO.

Alex


From: amd-gfx  on behalf of Oak Zeng 

Sent: Thursday, July 15, 2021 9:25 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Xu, Feifei ; Kuehling, Felix ; 
Liu, Leo ; Zeng, Oak ; Zhang, Hawking 

Subject: [PATCH 1/5] drm/amdgpu: Fix a printing message

The printing message "PSP loading VCN firmware" is mis-leading because
people might think driver is loading VCN firmware. Actually when this
message is printed, driver is just preparing some VCN ucode, not loading
VCN firmware yet. The actual VCN firmware loading will be in the PSP block
hw_init. Fix the printing message

Signed-off-by: Oak Zeng 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 284bb42..1f8e902 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -119,7 +119,7 @@ static int vcn_v1_0_sw_init(void *handle)
 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
 adev->firmware.fw_size +=
 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
-   DRM_INFO("PSP loading VCN firmware\n");
+   DRM_INFO("VCN 1.0: Will use PSP to load VCN firmware\n");
 }

 r = amdgpu_vcn_resume(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 8af567c..ebe4f2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -122,7 +122,7 @@ static int vcn_v2_0_sw_init(void *handle)
 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
 adev->firmware.fw_size +=
 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
-   DRM_INFO("PSP loading VCN firmware\n");
+   DRM_INFO("VCN 2.0: Will use PSP to load VCN firmware\n");
 }

 r = amdgpu_vcn_resume(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 888b17d..5741504 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -152,7 +152,7 @@ static int vcn_v2_5_sw_init(void *handle)
 adev->firmware.fw_size +=
 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), 
PAGE_SIZE);
 }
-   DRM_INFO("PSP loading VCN firmware\n");
+   DRM_INFO("VCN 2.5: Will use PSP to load VCN firmware\n");
 }

 r = amdgpu_vcn_resume(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index c3580de..b81eae3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -158,7 +158,7 @@ static int vcn_v3_0_sw_init(void *handle)
 adev->firmware.fw_size +=
 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), 
PAGE_SIZE);
 }
-   DRM_INFO("PSP loading VCN firmware\n");
+   DRM_INFO("VCN 3.0: Will use PSP to load VCN firmware\n");
 }

 r = amdgpu_vcn_resume(adev);
--
2.7.4

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Re: [PATCH] drm/amdgpu: Put MODE register in wave debug info

[Deucher, Alexander]

[Public]

As far as I know, umr is the only user of this and it shouldn't cause any 
problems there.

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Joseph 
Greathouse 
Sent: Tuesday, June 29, 2021 11:47 PM
To: amd-gfx@lists.freedesktop.org 
Cc: StDenis, Tom ; Greathouse, Joseph 

Subject: [PATCH] drm/amdgpu: Put MODE register in wave debug info

Add the MODE register into the per-wave debug information.
This register holds state such as FP rounding and denorm
modes, which exceptions are enabled, and active clamping
modes.

Signed-off-by: Joseph Greathouse 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 1 +
 5 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ff7e9f49040e..abcd418e51f1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4517,6 +4517,7 @@ static void gfx_v10_0_read_wave_data(struct amdgpu_device 
*adev, uint32_t simd,
 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
+   dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
 }

 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t 
simd,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 3a8d52a54873..6a8dadea40f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3027,6 +3027,7 @@ static void gfx_v6_0_read_wave_data(struct amdgpu_device 
*adev, uint32_t simd, u
 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, 
ixSQ_WAVE_TMA_HI);
 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, 
ixSQ_WAVE_IB_DBG0);
 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
+   dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
 }

 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 685212c3ddae..37b4a3db6360 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4198,6 +4198,7 @@ static void gfx_v7_0_read_wave_data(struct amdgpu_device 
*adev, uint32_t simd, u
 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, 
ixSQ_WAVE_TMA_HI);
 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, 
ixSQ_WAVE_IB_DBG0);
 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
+   dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
 }

 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index c26e06059466..e0302c23e9a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5279,6 +5279,7 @@ static void gfx_v8_0_read_wave_data(struct amdgpu_device 
*adev, uint32_t simd, u
 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, 
ixSQ_WAVE_TMA_HI);
 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, 
ixSQ_WAVE_IB_DBG0);
 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
+   dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
 }

 static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 044076ec1d03..d42363fcf068 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2080,6 +2080,7 @@ static void gfx_v9_0_read_wave_data(struct amdgpu_device 
*adev, uint32_t simd, u
 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, 
ixSQ_WAVE_IB_STS);
 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, 
ixSQ_WAVE_IB_DBG0);
 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
+   dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
 }

 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
--
2.20.1

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Re: [PATCH 2/3] drm/amdgpu: Fix a printing message

[Deucher, Alexander]

[Public]

I think it's more consistent to use dev_info since we already use that pretty 
extensively in the driver.

Alex


From: amd-gfx  on behalf of Chen, 
Jiansong (Simon) 
Sent: Wednesday, July 14, 2021 10:51 PM
To: Alex Deucher ; Zeng, Oak 
Cc: Xu, Feifei ; Kuehling, Felix ; 
Liu, Leo ; amd-gfx list ; 
Zhang, Hawking 
Subject: RE: [PATCH 2/3] drm/amdgpu: Fix a printing message

[Public]

[Public]

Hi Alex,
Is DRM_DEV_INFO more suitable than dev_info as far as DRM subsystem is 
concerned? Thanks!

Regards,
Jiansong
-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Wednesday, July 14, 2021 11:48 PM
To: Zeng, Oak 
Cc: Xu, Feifei ; Kuehling, Felix ; 
Liu, Leo ; amd-gfx list ; 
Zhang, Hawking 
Subject: Re: [PATCH 2/3] drm/amdgpu: Fix a printing message

On Wed, Jul 14, 2021 at 11:25 AM Oak Zeng  wrote:
>
> The printing message "PSP loading VCN firmware" is mis-leading because
> people might think driver is loading VCN firmware. Actually when this
> message is printed, driver is just preparing some VCN ucode, not
> loading VCN firmware yet. The actual VCN firmware loading will be in
> the PSP block hw_init. Fix the printing message
>
> Signed-off-by: Oak Zeng 
> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 284bb42..1f8e902 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -119,7 +119,7 @@ static int vcn_v1_0_sw_init(void *handle)
> adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> -   DRM_INFO("PSP loading VCN firmware\n");
> +   DRM_INFO("VCN 1.0: Will use PSP to load VCN
> + firmware\n");
> }
>
> r = amdgpu_vcn_resume(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 8af567c..ebe4f2b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -122,7 +122,7 @@ static int vcn_v2_0_sw_init(void *handle)
> adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> -   DRM_INFO("PSP loading VCN firmware\n");
> +   DRM_INFO("VCN 2.0: Will use PSP to load VCN
> + firmware\n");

While you are here, switch to dev_info() so we get the device information in 
the output (in case we have multiple GPUs in a system).

Alex

> }
>
> r = amdgpu_vcn_resume(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 888b17d..5741504 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -152,7 +152,7 @@ static int vcn_v2_5_sw_init(void *handle)
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), 
> PAGE_SIZE);
> }
> -   DRM_INFO("PSP loading VCN firmware\n");
> +   DRM_INFO("VCN 2.5: Will use PSP to load VCN
> + firmware\n");
> }
>
> r = amdgpu_vcn_resume(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index c3580de..b81eae3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -158,7 +158,7 @@ static int vcn_v3_0_sw_init(void *handle)
> adev->firmware.fw_size +=
> ALIGN(le32_to_cpu(hdr->ucode_size_bytes), 
> PAGE_SIZE);
> }
> -   DRM_INFO("PSP loading VCN firmware\n");
> +   DRM_INFO("VCN 3.0: Will use PSP to load VCN
> + firmware\n");
> }
>
> r = amdgpu_vcn_resume(adev);
> --
> 2.7.4
>
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Re: [PATCH] drm/amdgpu: update the golden setting for vangogh

[Deucher, Alexander]

[AMD Official Use Only]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Xiaojian Du 

Sent: Wednesday, July 14, 2021 5:32 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Huang, Ray ; Du, Xiaojian 
Subject: [PATCH] drm/amdgpu: update the golden setting for vangogh

This patch is to update the golden setting for vangogh.

Signed-off-by: Xiaojian Du 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 705fa3027199..9144836798c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3383,6 +3383,7 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_3_vangogh[] =
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffbf, 
0x0020),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0x, 
0x00070103),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x17ff, 0x1000),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x0001, 0x00010020),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7, 0x0103),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x0040),
 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x0fff, 
0x00ff),
--
2.17.1

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Re: AMDGPU error: "[drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR* Waiting for fences timed out!"

[Deucher, Alexander]

[Public]

Thanks for narrowing this down.  There is new PCO SDMA firmware available 
(attached).  Can you try it?

Thanks,

Alex

From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Thursday, June 24, 2021 6:51 AM
To: Alex Deucher 
Cc: xgqt ; amd-gfx list 
Subject: Re: AMDGPU error: "[drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR* 
Waiting for fences timed out!"

On 2021-06-04 3:08 p.m., Michel Dänzer wrote:
> On 2021-06-04 2:33 p.m., Alex Deucher wrote:
>> On Fri, Jun 4, 2021 at 3:47 AM Michel Dänzer  wrote:
>>>
>>> On 2021-05-19 3:57 p.m., Alex Deucher wrote:
 On Wed, May 19, 2021 at 4:48 AM Michel Dänzer  wrote:
>
> On 2021-05-19 12:05 a.m., Alex Deucher wrote:
>> On Tue, May 18, 2021 at 10:11 AM Michel Dänzer  
>> wrote:
>>>
>>> On 2021-05-17 11:33 a.m., xgqt wrote:
 Hello!

 I run a AMD laptop "81NC Lenovo IdeaPad S340-15API" - AMD Ryzen 5 
 3500U with Radeon Vega 8 Graphics.
 Recently some breakages started happening for me. In about 1h after 
 boot-up while using a KDE desktop machine GUI would freeze. Sometimes 
 it would be possible to move the mouse but the rest will be frozen. 
 Screen may start blinking or go black.

 I'm not sure if this is my kernel, firmware or the hardware.
 I don't understands dmesg that's why I'm guessing, but I think it is 
 the firmware since this behavior started around 2021-05-15.
 From my Portage logs I see that I updated my firmware on 2021-05-14 at 
 18:16:06.
 So breakages started with my kernel: 5.10.27 and FW: 20210511.
 After breakage I jumped to a older kernel 5.4.97 and compiled 5.12.4. 
 I didn't notice a breakage on 5.4.97 but system ran ~40 minutes.
 So I booted to newly compiled 5.12.4 where I was ~1h and it broke.
 After that I booted to 5.4.97 again and downgraded my FW.
 While I'm writing this I'm booted to kernel: 5.12.4 with FW: 20210315.

 I also described my situation on the Gentoo bugzilla: 
 https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugs.gentoo.org%2F790566data=04%7C01%7Calexander.deucher%40amd.com%7C06c9a5296ad74b0cd02408d936fe00bc%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637601286843342891%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=5HKZUabvEZWI%2BzQUBBPWl3Cpiy7Zjs%2BqaKa4XZyNK1g%3Dreserved=0

 "dmesg.log" attached here is from the time machine run fine (at the 
 moment); "errors_sat_may_15_072825_pm_cest_2021.log" is a dmesg log 
 from the time system broke

 Can I get any help with this? What are the next steps I should take? 
 Any other files I should provide?
>>>
>>> I've hit similar hangs with a Lenovo ThinkPad E595 (Ryzen 7 3700U / 
>>> Picasso / RAVEN 0x1002:0x15D8 0x17AA:0x5124 0xC1). I'm also suspecting 
>>> them to be firware related. The hangs occurred with firmware from the 
>>> AMD 20.50 release. I'm currently running with firmware from the 20.40 
>>> release, no hang in almost 2 weeks (the hangs happened within 1-2 days 
>>> after boot).
>>
>> Can you narrow down which firmware(s) cause the problem?
>
> I'll try, but note I'm not really sure yet my hangs were related to 
> firmware (only). Anyway, I'll try narrowing it down.

 Thanks.  Does this patch help?
 https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.freedesktop.org%2Fpatch%2F433701%2Fdata=04%7C01%7Calexander.deucher%40amd.com%7C06c9a5296ad74b0cd02408d936fe00bc%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637601286843352846%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=1BJky5Nl47A2ytThBe44pAJEHKEARozWTjskAdkK1s8%3Dreserved=0
>>>
>>> Unfortunately not. After no hangs for two weeks with older firmware, I just 
>>> got a hang again within a day with newer firmware and a kernel with this 
>>> fix.
>>>
>>>
>>> I'll try and narrow down which firmware triggers it now. Does Picasso use 
>>> the picasso_*.bin ones only, or others as well?
>>
>> The picasso ones and raven_dmcu.bin.
>
> Thanks. raven_dmcu.bin hasn't changed, so I'm trying to bisect the 8 Picasso 
> ones which have changed:
>
> picasso_asd.bin
> picasso_ce.bin
> picasso_me.bin
> picasso_mec2.bin
> picasso_mec.bin
> picasso_pfp.bin
> picasso_sdma.bin
> picasso_vcn.bin

Things are pointing to picasso_sdma.bin. I'm currently running with only that 
one reverted to linux-firmware 20210315, and haven't got any hangs for a week.

Note that I've previously gone for a week without a hang even with firmware 
which had hung before. So there's still a small chance that I'm just on another 
lucky run.

That said, Pierre-Eric has also homed in on raven_sdma.bin for similar hangs, 
and reverting to older 

Re: [PATCH v3] drm/radeon: Call radeon_suspend_kms() in radeon_pci_shutdown() for Loongson64

[Deucher, Alexander]

[Public]

Applied.  Thanks.  For whatever reason, I never got this patch and couldn't 
find it in patchwork.

Alex


From: Koenig, Christian 
Sent: Wednesday, June 23, 2021 4:25 AM
To: Tiezhu Yang ; Deucher, Alexander 

Cc: airl...@linux.ie ; amd-gfx@lists.freedesktop.org 
; dan...@ffwll.ch ; 
dri-de...@lists.freedesktop.org ; 
linux-ker...@vger.kernel.org ; 
lixuef...@loongson.cn ; lvjian...@loongson.cn 

Subject: Re: [PATCH v3] drm/radeon: Call radeon_suspend_kms() in 
radeon_pci_shutdown() for Loongson64

Looks good to me.

Somebody could try to investigate further why that is necessary on the
platform, but radeon is only in maintenance mode without new feature
developed.

Regards,
Christian.

Am 23.06.21 um 10:14 schrieb Tiezhu Yang:
> Hi Alex and Christian,
>
> Any comments?
> Can this patch be accepted or anything else I need to improve?
>
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fpatchwork%2Fpatch%2F1443649%2Fdata=04%7C01%7Cchristian.koenig%40amd.com%7C2162309822114d2e41b108d9361ef26c%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637600328822651335%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=2uxyAGk6sHO3lqw0FX6HITY%2Fbj%2BzEMfSIcqbzmiguMs%3Dreserved=0
>
>
> Thanks,
> Tiezhu
>

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Re: [PATCH] drm/amdgpu: fix amdgpu_preempt_mgr_new()

[Deucher, Alexander]

[Public]

I've dropped it from my tree in that case.

From: Christian König 
Sent: Monday, June 21, 2021 6:27 AM
To: Alex Deucher ; Kuehling, Felix 

Cc: David Airlie ; Pan, Xinhui ; 
kernel-janit...@vger.kernel.org ; Maling list 
- DRI developers ; amd-gfx list 
; Daniel Vetter ; Deucher, 
Alexander ; Dave Airlie ; 
Koenig, Christian ; Dan Carpenter 

Subject: Re: [PATCH] drm/amdgpu: fix amdgpu_preempt_mgr_new()

Am 18.06.21 um 23:18 schrieb Alex Deucher:
> On Fri, Jun 18, 2021 at 11:40 AM Felix Kuehling  
> wrote:
>> Am 2021-06-18 um 4:39 a.m. schrieb Christian König:
>>> Am 18.06.21 um 10:37 schrieb Dan Carpenter:
>>>> There is a reversed if statement in amdgpu_preempt_mgr_new() so it
>>>> always returns -ENOMEM.
>>>>
>>>> Fixes: 09b020bb05a5 ("Merge tag 'drm-misc-next-2021-06-09' of
>>>> git://anongit.freedesktop.org/drm/drm-misc into drm-next")
>>>> Signed-off-by: Dan Carpenter 
>>> Most be some fallout from merging it with the TTM changes.
>>>
>>> Anyway, patch is Reviewed-by: Christian König 
>> This is obviously not for amd-staging-drm-next. Christian, are you going
>> to apply it to the relevant branches?
> I've applied it to my drm-next branch.

I already pushed it to drm-misc-next last week.

Christian.

>
> Alex
>
>
>> Thanks,
>>Felix
>>
>>
>>> Thanks,
>>> Christian.
>>>
>>>> ---
>>>>drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c | 2 +-
>>>>1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
>>>> index f6aff7ce5160..d02c8637f909 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c
>>>> @@ -71,7 +71,7 @@ static int amdgpu_preempt_mgr_new(struct
>>>> ttm_resource_manager *man,
>>>>struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
>>>>  *res = kzalloc(sizeof(**res), GFP_KERNEL);
>>>> -if (*res)
>>>> +if (!*res)
>>>>return -ENOMEM;
>>>>  ttm_resource_init(tbo, place, *res);
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Re: [PATCH v3] drm/amd/amdgpu: Use IP discovery data to determine VCN enablement instead of MMSCH

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Peng Ju Zhou 

Sent: Thursday, June 17, 2021 3:46 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Zhang, Bokun 
Subject: [PATCH v3] drm/amd/amdgpu: Use IP discovery data to determine VCN 
enablement instead of MMSCH

From: Bokun Zhang 

In the past, we use MMSCH to determine whether a VCN is enabled or not.
This is not reliable since after a FLR, MMSCH may report junk data.

It is better to use IP discovery data.

Signed-off-by: Bokun Zhang 
Signed-off-by: Peng Ju Zhou 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |  8 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h |  3 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c   | 23 
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h   | 13 +
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 53 +--
 5 files changed, 61 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index f949ed8bfd9e..e02405a24fe3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -373,6 +373,14 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device 
*adev, int hw_id, int n
 return -EINVAL;
 }

+
+int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int 
vcn_instance,
+int *major, int *minor, int *revision)
+{
+   return amdgpu_discovery_get_ip_version(adev, VCN_HWID,
+  vcn_instance, major, minor, 
revision);
+}
+
 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
 {
 struct binary_header *bhdr;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
index 02e340cd3a38..48e6b88cfdfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
@@ -32,6 +32,9 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device 
*adev);
 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev);
 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int 
number_instance,
 int *major, int *minor, int *revision);
+
+int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int 
vcn_instance,
+int *major, int *minor, int *revision);
 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);

 #endif /* __AMDGPU_DISCOVERY__ */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 9492b505e69b..84b025405578 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -287,6 +287,29 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 return 0;
 }

+bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type 
type, uint32_t vcn_instance)
+{
+   bool ret = false;
+
+   int major;
+   int minor;
+   int revision;
+
+   /* if cannot find IP data, then this VCN does not exist */
+   if (amdgpu_discovery_get_vcn_version(adev, vcn_instance, , 
, ) != 0)
+   return true;
+
+   if ((type == VCN_ENCODE_RING) && (revision & 
VCN_BLOCK_ENCODE_DISABLE_MASK)) {
+   ret = true;
+   } else if ((type == VCN_DECODE_RING) && (revision & 
VCN_BLOCK_DECODE_DISABLE_MASK)) {
+   ret = true;
+   } else if ((type == VCN_UNIFIED_RING) && (revision & 
VCN_BLOCK_QUEUE_DISABLE_MASK)) {
+   ret = true;
+   }
+
+   return ret;
+}
+
 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
 {
 unsigned size;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index bc76cab67697..d74c62b49795 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -280,6 +280,16 @@ struct amdgpu_vcn_decode_buffer {
 uint32_t pad[30];
 };

+#define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
+#define VCN_BLOCK_DECODE_DISABLE_MASK 0x40
+#define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0
+
+enum vcn_ring_type {
+   VCN_ENCODE_RING,
+   VCN_DECODE_RING,
+   VCN_UNIFIED_RING,
+};
+
 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
 int amdgpu_vcn_suspend(struct amdgpu_device *adev);
@@ -287,6 +297,9 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev);
 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);

+bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev,
+   enum vcn_ring_type type, uint32_t vcn_instance);
+
 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
diff 

Re: [PATCH] drm/amdgpu: use adev_to_drm to get drm_device

[Deucher, Alexander]

[Public]

We already use the macro everywhere else upstream, so this just makes it 
consistent.

Alex


From: amd-gfx  on behalf of Felix 
Kuehling 
Sent: Wednesday, June 9, 2021 11:32 AM
To: Tuikov, Luben ; Chen, Guchun ; 
amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH] drm/amdgpu: use adev_to_drm to get drm_device

Am 2021-06-09 um 11:20 a.m. schrieb Luben Tuikov:
> On 2021-06-09 10:01 a.m., Felix Kuehling wrote:
>> Am 2021-06-09 um 5:23 a.m. schrieb Guchun Chen:
>>> Fixes:
>>> 9faf262c32d3 drm/amdgpu: Add DMA mapping of GTT BOs
>>> 090f3a60d7e8 drm/amdgpu: Use delayed work to collect RAS error counters
>> A Fixes tag implies that something was broken. However, the
>> implementation of adev_to_drm does the exact same thing. I don't see the
>> point of this patch. It doesn't fix any problem, and IMHO doesn't make
>> the code more readable.
> We added this due to some changes in DRM:
>
> 8aba21b75136c3 drm/amdgpu: Embed drm_device into amdgpu_device (v3)
> 4a580877bdcb83 drm/amdgpu: Get DRM dev from adev by inline-f
>
> It's good to use this inline function, to accommodate more flexible DRM.

Thanks for the explanation. I found your changes as well and it makes
sense now, especially for the DKMS branch. Unfortunately that's not a
justification we can use for upstream.

Regards,
  Felix


>
> Regards,
> Luben
>
>> Regards,
>>   Felix
>>
>>
>>> Signed-off-by: Guchun Chen 
>>> ---
>>>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
>>>  drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c  | 2 +-
>>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>>> index 016815b7a773..fb6bcc386de1 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>>> @@ -639,7 +639,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, 
>>> struct kgd_mem *mem,
>>>  }
>>>  }
>>>
>>> -   gobj = amdgpu_gem_prime_import(>ddev, mem->dmabuf);
>>> +   gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
>>>  if (IS_ERR(gobj))
>>>  return PTR_ERR(gobj);
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
>>> index ec936cde2726..bfbcb9ff2453 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
>>> @@ -2122,7 +2122,7 @@ static void amdgpu_ras_counte_dw(struct work_struct 
>>> *work)
>>>  struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
>>>ras_counte_delay_work.work);
>>>  struct amdgpu_device *adev = con->adev;
>>> -   struct drm_device *dev = >ddev;
>>> +   struct drm_device *dev = adev_to_drm(adev->ddev);
>>>  unsigned long ce_count, ue_count;
>>>  int res;
>>>
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Re: [PATCH] drm/amd/display: Fix build break

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Anson Jacob 

Sent: Tuesday, June 8, 2021 11:36 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Brol, Eryk ; Li, Sun peng (Leo) ; 
Wentland, Harry ; Zhuo, Qingqing 
; Siqueira, Rodrigo ; Li, 
Roman ; Jacob, Anson ; Pillai, Aurabindo 
; Lakha, Bhawanpreet ; R, 
Bindu 
Subject: [PATCH] drm/amd/display: Fix build break

1. Remove duplicate OTG_PIXEL_RATE_CNTL from dccg_registers
2. Fixes: 18827ee0cc28 ("drm/amd/display: Refactor visual confirm")

Signed-off-by: Anson Jacob 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 1 -
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 3 +--
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index 6bdab06667c9..62904d7ca100 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -202,7 +202,6 @@ struct dccg_registers {
 #if defined(CONFIG_DRM_AMD_DC_DCN3_1)
 uint32_t PHYDSYMCLK_CLOCK_CNTL;
 uint32_t PHYESYMCLK_CLOCK_CNTL;
-   uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
 uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c 
b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
index 69da1493b277..e3048f8827d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
@@ -100,6 +100,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
 .z10_restore = dcn31_z10_restore,
 .is_abm_supported = dcn31_is_abm_supported,
 .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+   .update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };

 static const struct hwseq_private_funcs dcn31_private_funcs = {
@@ -129,8 +130,6 @@ static const struct hwseq_private_funcs dcn31_private_funcs 
= {
 .program_all_writeback_pipes_in_tree = 
dcn30_program_all_writeback_pipes_in_tree,
 .update_odm = dcn20_update_odm,
 .dsc_pg_control = dcn31_dsc_pg_control,
-   .get_surface_visual_confirm_color = 
dcn10_get_surface_visual_confirm_color,
-   .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 .set_hdr_multiplier = dcn10_set_hdr_multiplier,
 .verify_allow_pstate_change_high = 
dcn10_verify_allow_pstate_change_high,
 .wait_for_blank_complete = dcn20_wait_for_blank_complete,
--
2.25.1

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Re: [PATCH] drm/amd/pm: fix warning reported by kernel test robot

[Deucher, Alexander]

[Public]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Xiaomeng Hou 

Sent: Monday, June 7, 2021 8:45 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Huang, Ray ; Hou, Xiaomeng (Matthew) 
; Wang, Kevin(Yang) 
Subject: [PATCH] drm/amd/pm: fix warning reported by kernel test robot

Kernel test robot throws warning ->

>> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:483:2:
   warning: variable 'member_type' is used uninitialized whenever switch
   default is taken [-Wsometimes-uninitialized]
   default:
   ^~~
   drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:487:47:
   note: uninitialized use occurs here
   return yellow_carp_get_smu_metrics_data(smu, member_type, value);
   ^~~
   drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:465:2:
   note: variable 'member_type' is declared here
   MetricsMember_t member_type;
   ^
   1 warning generated.

Fix this warning by return errno when the clk type is unsupported.

Signed-off-by: Xiaomeng Hou 
Reported-by: kernel test robot 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index 031c49fb4582..0cd7902d5172 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -728,7 +728,7 @@ static int yellow_carp_get_current_clk_freq(struct 
smu_context *smu,
 return smu_cmn_send_smc_msg_with_param(smu,
 SMU_MSG_GetFclkFrequency, 0, value);
 default:
-   break;
+   return -EINVAL;
 }

 return yellow_carp_get_smu_metrics_data(smu, member_type, value);
--
2.17.1

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Re: [PATCH] drm/amdgpu: Modify GC register access to use _SOC15 macros

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: Khaire, Rohit 
Sent: Friday, June 4, 2021 12:38 PM
To: amd-gfx@lists.freedesktop.org ; Deucher, 
Alexander ; Zhang, Hawking ; 
Deng, Emily ; Liu, Monk ; Zhou, Peng Ju 
; Chen, Horace 
Cc: Ming, Davis ; Khaire, Rohit ; 
Koenig, Christian ; Khaire, Rohit 

Subject: [PATCH] drm/amdgpu: Modify GC register access to use _SOC15 macros

In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.

Using _SOC15 read/write macros ensures that they go
through RLC when flag is enabled.

Signed-off-by: Rohit Khaire 
---
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c  | 42 +--
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
index d39cff4a1fe3..1f5620cc3570 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
@@ -95,8 +95,8 @@ static void program_sh_mem_settings_v10_3(struct kgd_dev 
*kgd, uint32_t vmid,

 lock_srbm(kgd, 0, 0, 0, vmid);

-   WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
+   WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
+   WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
 /* APE1 no longer exists on GFX9 */

 unlock_srbm(kgd);
@@ -129,7 +129,7 @@ static int init_interrupts_v10_3(struct kgd_dev *kgd, 
uint32_t pipe_id)

 lock_srbm(kgd, mec, pipe, 0, 0);

-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
+   WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);

@@ -212,10 +212,10 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, 
uint32_t pipe_id,

 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
 mec, pipe, queue_id);
-   value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
+   value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
 ((mec << 5) | (pipe << 3) | queue_id | 0x80));
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);
+   WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value);
 }

 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. 
*/
@@ -224,13 +224,13 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, 
uint32_t pipe_id,

 for (reg = hqd_base;
  reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
-   WREG32(reg, mqd_hqd[reg - hqd_base]);
+   WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);


 /* Activate doorbell logic before triggering WPTR poll. */
 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
  CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
+   WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);

 if (wptr) {
 /* Don't read wptr with get_user because the user
@@ -259,17 +259,17 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, 
uint32_t pipe_id,
 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;

-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+   WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
lower_32_bits(guessed_wptr));
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+   WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
upper_32_bits(guessed_wptr));
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+   WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
lower_32_bits((uint64_t)wptr));
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+   WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
upper_32_bits((uint64_t)wptr));
 pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
  (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
-   WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
+   WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
(uint32_t)get_queue_mask(adev, pipe_id, queue_id));
 }

@@ -279,7 +279,7 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, 
uint32_t pipe_id,
  CP_HQD_EOP_RPTR, INIT_FETCHER, 1));

   

Re: [PATCH] drm/amdgpu: Enable RLCG read/write interface for Sienna Cichlid

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Rohit Khaire 

Sent: Friday, June 4, 2021 11:24 AM
To: amd-gfx@lists.freedesktop.org ; Deucher, 
Alexander ; Zhang, Hawking ; 
Deng, Emily ; Liu, Monk ; Zhou, Peng Ju 
; Chen, Horace 
Cc: Ming, Davis ; Khaire, Rohit ; 
Koenig, Christian 
Subject: [PATCH] drm/amdgpu: Enable RLCG read/write interface for Sienna Cichlid

Enable this only for Sienna Cichild
since only Navi12 and Sienna Cichlid support SRIOV

Signed-off-by: Rohit Khaire 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 4a50c4e9aea0..29017b18470d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9217,7 +9217,6 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device 
*adev)
 switch (adev->asic_type) {
 case CHIP_NAVI10:
 case CHIP_NAVI14:
-   case CHIP_SIENNA_CICHLID:
 case CHIP_NAVY_FLOUNDER:
 case CHIP_VANGOGH:
 case CHIP_DIMGREY_CAVEFISH:
@@ -9225,6 +9224,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device 
*adev)
 adev->gfx.rlc.funcs = _v10_0_rlc_funcs;
 break;
 case CHIP_NAVI12:
+   case CHIP_SIENNA_CICHLID:
 adev->gfx.rlc.funcs = _v10_0_rlc_funcs_sriov;
 break;
 default:
--
2.17.1

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Re: [PATCH] drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid

[Deucher, Alexander]

[AMD Official Use Only]

checks should be adev->asic_type >= CHIP_SIENNA_CICHLID so we cover other 
gfx10.3 asics as well.  With that fixed:
Reviewed-by: Alex Deucher 


From: Khaire, Rohit 
Sent: Friday, June 4, 2021 10:49 AM
To: amd-gfx@lists.freedesktop.org ; Deucher, 
Alexander ; Zhang, Hawking ; 
Deng, Emily ; Liu, Monk ; Zhou, Peng Ju 
; Chen, Horace 
Cc: Ming, Davis ; Khaire, Rohit ; 
Koenig, Christian ; Khaire, Rohit 

Subject: [PATCH] drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid

RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different
offsets for Sienna Cichlid

Signed-off-by: Rohit Khaire 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +-
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 11a64ca8a5ec..1e1ce1e49c70 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -177,6 +177,9 @@
 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid  0x2030
 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0

+#define mmRLC_SPARE_INT_0_Sienna_Cichlid   0x4ca5
+#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX  1
+
 #define GFX_RLCG_GC_WRITE_OLD   (0x8 << 28)
 #define GFX_RLCG_GC_WRITE   (0x0 << 28)
 #define GFX_RLCG_GC_READ(0x1 << 28)
@@ -1489,8 +1492,15 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, 
u32 offset, u32 v, uint32
(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] 
+ mmSCRATCH_REG2) * 4;
 scratch_reg3 = adev->rmmio +
(adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] 
+ mmSCRATCH_REG3) * 4;
-   spare_int = adev->rmmio +
-   (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + 
mmRLC_SPARE_INT) * 4;
+
+   if (adev->asic_type == CHIP_SIENNA_CICHLID) {
+   spare_int = adev->rmmio +
+   
(adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
++ mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
+   } else {
+   spare_int = adev->rmmio +
+   
(adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
+   }

 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + 
mmGRBM_GFX_CNTL;
 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + 
mmGRBM_GFX_INDEX;
@@ -7410,9 +7420,15 @@ static int gfx_v10_0_hw_fini(void *handle)
 if (amdgpu_sriov_vf(adev)) {
 gfx_v10_0_cp_gfx_enable(adev, false);
 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
-   tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
-   tmp &= 0xff00;
-   WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
+   if (adev->asic_type == CHIP_SIENNA_CICHLID) {
+   tmp = RREG32_SOC15(GC, 0, 
mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
+   tmp &= 0xff00;
+   WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, 
tmp);
+   } else {
+   tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
+   tmp &= 0xff00;
+   WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
+   }

 return 0;
 }
--
2.17.1

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Re: [PATCH 1/1] drm/amd/display: WARN_ON cleanups

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: Das, Nirmoy 
Sent: Thursday, May 27, 2021 8:16 AM
To: Wentland, Harry 
Cc: Deucher, Alexander ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org 

Subject: RE: [PATCH 1/1] drm/amd/display: WARN_ON cleanups

[AMD Official Use Only]

s/Uuse/use

-Original Message-
From: Das, Nirmoy 
Sent: Thursday, May 27, 2021 2:15 PM
To: Wentland, Harry 
Cc: Deucher, Alexander ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org; Das, Nirmoy 

Subject: [PATCH 1/1] drm/amd/display: WARN_ON cleanups

Uuse WARN_ON() inside if-condition when possible.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 ---
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f2ed51484980..736eb537a8e4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -315,8 +315,7 @@ get_crtc_by_otg_inst(struct amdgpu_device *adev,
 struct drm_crtc *crtc;
 struct amdgpu_crtc *amdgpu_crtc;

-   if (otg_inst == -1) {
-   WARN_ON(1);
+   if (WARN_ON(otg_inst == -1)) {
 return adev->mode_info.crtcs[0];
 }

@@ -397,8 +396,7 @@ static void dm_pflip_high_irq(void *interrupt_params)
 e = amdgpu_crtc->event;
 amdgpu_crtc->event = NULL;

-   if (!e)
-   WARN_ON(1);
+   WARN_ON(!e);

 vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);

@@ -6698,9 +6696,8 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc 
*crtc,

 dm_update_crtc_active_planes(crtc, crtc_state);

-   if (unlikely(!dm_crtc_state->stream &&
-modeset_required(crtc_state, NULL, 
dm_crtc_state->stream))) {
-   WARN_ON(1);
+   if (WARN_ON(unlikely(!dm_crtc_state->stream &&
+modeset_required(crtc_state, NULL, 
dm_crtc_state->stream {
 return ret;
 }

--
2.31.1
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Re: [PATCH 1/1] drm/amd/display: do not dereference on NULL

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: Das, Nirmoy 
Sent: Thursday, May 27, 2021 8:07 AM
To: Wentland, Harry 
Cc: Deucher, Alexander ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org 
; Das, Nirmoy 
Subject: [PATCH 1/1] drm/amd/display: do not dereference on NULL

WARN_ON() will not kill the process so the second WARN_ON()
will try to dereference NULL pointer.

Signed-off-by: Nirmoy Das 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1134cf6eac82..f2ed51484980 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -9108,7 +9108,10 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
 }

 status = dc_stream_get_status(dm_new_crtc_state->stream);
-   WARN_ON(!status);
+
+   if (WARN_ON(!status))
+   continue;
+
 WARN_ON(!status->plane_count);

 /*
--
2.31.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: Tuikov, Luben 
Sent: Wednesday, May 26, 2021 12:43 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Tuikov, Luben ; Deucher, Alexander 
; Koenig, Christian ; 
Clements, John ; Zhang, Hawking 
Subject: [PATCH 3/3] drm/amdgpu: Use delayed work to collect RAS error counters

On Context Query2 IOCTL return the correctable and
uncorrectable errors in O(1) fashion, from cached
values, and schedule a delayed work function to
calculate and cache them for the next such IOCTL.

v2: Cancel pending delayed work at ras_fini().
v3: Remove conditionals when dealing with delayed
work manipulation as they're inherently racy.

Cc: Alexander Deucher 
Cc: Christian König 
Cc: John Clements 
Cc: Hawking Zhang 
Signed-off-by: Luben Tuikov 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 31 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 40 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h |  5 
 3 files changed, 74 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index bb0cfe871aba..e7a010b7ca1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -331,10 +331,13 @@ static int amdgpu_ctx_query(struct amdgpu_device *adev,
 return 0;
 }

+#define AMDGPU_RAS_COUNTE_DELAY_MS 3000
+
 static int amdgpu_ctx_query2(struct amdgpu_device *adev,
-   struct amdgpu_fpriv *fpriv, uint32_t id,
-   union drm_amdgpu_ctx_out *out)
+struct amdgpu_fpriv *fpriv, uint32_t id,
+union drm_amdgpu_ctx_out *out)
 {
+   struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 struct amdgpu_ctx *ctx;
 struct amdgpu_ctx_mgr *mgr;

@@ -361,6 +364,30 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev,
 if (atomic_read(>guilty))
 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;

+   if (adev->ras_enabled && con) {
+   /* Return the cached values in O(1),
+* and schedule delayed work to cache
+* new vaues.
+*/
+   int ce_count, ue_count;
+
+   ce_count = atomic_read(>ras_ce_count);
+   ue_count = atomic_read(>ras_ue_count);
+
+   if (ce_count != ctx->ras_counter_ce) {
+   ctx->ras_counter_ce = ce_count;
+   out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
+   }
+
+   if (ue_count != ctx->ras_counter_ue) {
+   ctx->ras_counter_ue = ue_count;
+   out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
+   }
+
+   schedule_delayed_work(>ras_counte_delay_work,
+ 
msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS));
+   }
+
 mutex_unlock(>lock);
 return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index ed3c43e8b0b5..ec936cde2726 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 

 #include "amdgpu.h"
 #include "amdgpu_ras.h"
@@ -2116,6 +2117,30 @@ static void amdgpu_ras_check_supported(struct 
amdgpu_device *adev)
 adev->ras_hw_enabled & amdgpu_ras_mask;
 }

+static void amdgpu_ras_counte_dw(struct work_struct *work)
+{
+   struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
+ ras_counte_delay_work.work);
+   struct amdgpu_device *adev = con->adev;
+   struct drm_device *dev = >ddev;
+   unsigned long ce_count, ue_count;
+   int res;
+
+   res = pm_runtime_get_sync(dev->dev);
+   if (res < 0)
+   goto Out;
+
+   /* Cache new values.
+*/
+   amdgpu_ras_query_error_count(adev, _count, _count);
+   atomic_set(>ras_ce_count, ce_count);
+   atomic_set(>ras_ue_count, ue_count);
+
+   pm_runtime_mark_last_busy(dev->dev);
+Out:
+   pm_runtime_put_autosuspend(dev->dev);
+}
+
 int amdgpu_ras_init(struct amdgpu_device *adev)
 {
 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
@@ -2130,6 +2155,11 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
 if (!con)
 return -ENOMEM;

+   con->adev = adev;
+   INIT_DELAYED_WORK(>ras_counte_delay_work, amdgpu_ras_counte_dw);
+   atomic_set(>ras_ce_count, 0);
+   atomic_set(>ras_ue_count, 0);
+
 con->objs = (struct ras_manager *)(con + 1);

 amdgpu_ras_set_context(adev, con);
@@ -2233,6 +2263,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev,
  struct ras_fs_if *fs_info,
   

Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface

[Deucher, Alexander]

[Public]

The structure is not 64 bit aligned.  I think you want something like:

> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u32 pad;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> +};

From: Gu, JiaWei (Will) 
Sent: Tuesday, May 18, 2021 1:58 AM
To: Nieto, David M ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org 
; mar...@gmail.com ; Deucher, 
Alexander 
Cc: Deng, Emily 
Subject: RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface


[Public]


Hi all,



Then the struct looks like:



> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> +};



Sample output:



vbios name : NAVI12 A0 XT D30501 8GB EVAL 1150e/334m HYN/SAM
vbios pn : 113-D3050100-104
vbios version : 285409288
vbios ver_str : 017.003.000.008.016956
vbios date : 2021/05/03 23:32


Please help double confirm that we’re all fine with it and there’s no need to 
add & remove anything.



Best regards,

Jiawei



From: Nieto, David M 
Sent: Tuesday, May 18, 2021 12:40 PM
To: Gu, JiaWei (Will) ; Koenig, Christian 
; amd-gfx@lists.freedesktop.org; mar...@gmail.com; 
Deucher, Alexander 
Cc: Deng, Emily 
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface



[Public]



Yes, let's remove that too,



Thanks,



David



From: Gu, JiaWei (Will) mailto:jiawei...@amd.com>>
Sent: Monday, May 17, 2021 8:07 PM
To: Nieto, David M mailto:david.ni...@amd.com>>; Koenig, 
Christian mailto:christian.koe...@amd.com>>; 
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> 
mailto:amd-gfx@lists.freedesktop.org>>; 
mar...@gmail.com<mailto:mar...@gmail.com> 
mailto:mar...@gmail.com>>; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>
Subject: RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface



[AMD Official Use Only - Internal Distribution Only]



OK let’s remove serial.



dbdf comes from this:

vbios_info.dbdf = PCI_DEVID(adev->pdev->bus->number, adev->pdev->devfn);



I think we can remove dbdf as well.



Best regards,

Jiawei



From: Nieto, David M mailto:david.ni...@amd.com>>
Sent: Tuesday, May 18, 2021 10:45 AM
To: Gu, JiaWei (Will) mailto:jiawei...@amd.com>>; Koenig, 
Christian mailto:christian.koe...@amd.com>>; 
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>; 
mar...@gmail.com<mailto:mar...@gmail.com>; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface



[AMD Official Use Only - Internal Distribution Only]



The serial number is ASIC information, not VBIOS information, and it is still 
available as a sysfs node... I don't think we should put it there.



Not sure what dbdf stands for.



From: Gu, JiaWei (Will) mailto:jiawei...@amd.com>>
Sent: Monday, May 17, 2021 7:11 PM
To: Koenig, Christian 
mailto:christian.koe...@amd.com>>; 
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> 
mailto:amd-gfx@lists.freedesktop.org>>; Nieto, 
David M mailto:david.ni...@amd.com>>; 
mar...@gmail.com<mailto:mar...@gmail.com> 
mailto:mar...@gmail.com>>; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>
Subject: RE: [PATCH] drm/amdgpu: Add vbios info ioctl interface



[AMD Official Use Only - Internal Distribution Only]

So I guess the dbdf is also needed to be removed?
And how about serial?

> +struct drm_amdgpu_info_vbios {
> + __u8 name[64];
> + __u32 dbdf; // do we need this?
> + __u8 vbios_pn[64];
> + __u32 version;
> + __u8 vbios_ver_str[32];
> + __u8 date[32];
> + __u64 serial; // do we need this?
> +};

Best regards,
Jiawei

-Original Message-
From: Koenig, Christian 
mailto:christian.koe...@amd.com>>
Sent: Monday, May 17, 2021 8:26 PM
To: Gu, JiaWei (Will) mailto:jiawei...@amd.com>>; 
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>; Nieto, 
David M mailto:david.ni...@amd.com>>; 
mar...@gmail.com<mailto:mar...@gmail.com>; Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Cc: Deng, Emily mailto:emily.d...@amd.com>>
Subject: Re: [PATCH] drm/amdgpu: Add vbios info ioctl interface

I'm not very familiar with the technical background why we have the fields here 
once more.

But of hand we should at least remove everything which is also available from 
the PCI information.

E.g. dev_id, rev_id, sub_dev_id, sub_ved_id.

Regards,
Christian.

Am 17.05.21 um 1

Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang

[Deucher, Alexander]

[Public]

I thought we had disabled all but one of the compute queues on raven due to 
this issue or at least disabled the schedulers for the additional queues, but 
maybe I'm misremembering.

Alex


From: Chen, Guchun 
Sent: Tuesday, May 18, 2021 11:00 PM
To: Zhu, Changfeng ; Deucher, Alexander 
; Alex Deucher ; Das, Nirmoy 

Cc: Huang, Ray ; amd-gfx list 
Subject: RE: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid 
compute hang


[Public]


Nirmoy’s patch landed already if I understand correctly.



d41a39dda140 drm/scheduler: improve job distribution with multiple queues



Regards,

Guchun



From: amd-gfx  On Behalf Of Zhu, 
Changfeng
Sent: Wednesday, May 19, 2021 10:56 AM
To: Deucher, Alexander ; Alex Deucher 
; Das, Nirmoy 
Cc: Huang, Ray ; amd-gfx list 
Subject: RE: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid 
compute hang



[Public]



[Public]



Hi Alex,



This is the issue exposed by Nirmoy's patch that provided better load balancing 
across queues.



BR,

Changfeng.



From: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Sent: Wednesday, May 19, 2021 10:53 AM
To: Zhu, Changfeng mailto:changfeng@amd.com>>; Alex 
Deucher mailto:alexdeuc...@gmail.com>>; Das, Nirmoy 
mailto:nirmoy@amd.com>>
Cc: Huang, Ray mailto:ray.hu...@amd.com>>; amd-gfx list 
mailto:amd-gfx@lists.freedesktop.org>>
Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid 
compute hang



[Public]



+ Nirmoy



I thought we disabled all but one of the compute queues on raven due to this 
issue.  Maybe that patch never landed?  Wasn't this the same issue that was 
exposed by Nirmoy's patch that provided better load balancing across queues?



Alex





From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Zhu, Changfeng 
mailto:changfeng@amd.com>>
Sent: Tuesday, May 18, 2021 10:28 PM
To: Alex Deucher mailto:alexdeuc...@gmail.com>>
Cc: Huang, Ray mailto:ray.hu...@amd.com>>; amd-gfx list 
mailto:amd-gfx@lists.freedesktop.org>>
Subject: RE: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid 
compute hang



[AMD Official Use Only - Internal Distribution Only]

Hi Alex.

I have submitted the patch: drm/amdgpu: disable 3DCGCG on picasso/raven1 to 
avoid compute hang

Do you mean we have something else to do for re-enabling the extra compute 
queues?

BR,
Changfeng.

-Original Message-
From: Alex Deucher mailto:alexdeuc...@gmail.com>>
Sent: Wednesday, May 19, 2021 10:20 AM
To: Zhu, Changfeng mailto:changfeng@amd.com>>
Cc: Huang, Ray mailto:ray.hu...@amd.com>>; amd-gfx list 
mailto:amd-gfx@lists.freedesktop.org>>
Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid 
compute hang

Care to submit a patch to re-enable the extra compute queues?

Alex

On Mon, May 17, 2021 at 4:09 AM Zhu, Changfeng 
mailto:changfeng@amd.com>> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Ray and Alex,
>
> I have confirmed it can enable the additional compute queues with this patch:
>
> [   41.823013] This is ring mec 1, pipe 0, queue 0, value 1
> [   41.823028] This is ring mec 1, pipe 1, queue 0, value 1
> [   41.823042] This is ring mec 1, pipe 2, queue 0, value 1
> [   41.823057] This is ring mec 1, pipe 3, queue 0, value 1
> [   41.823071] This is ring mec 1, pipe 0, queue 1, value 1
> [   41.823086] This is ring mec 1, pipe 1, queue 1, value 1
> [   41.823101] This is ring mec 1, pipe 2, queue 1, value 1
> [   41.823115] This is ring mec 1, pipe 3, queue 1, value 1
>
> BR,
> Changfeng.
>
>
> -Original Message-
> From: Huang, Ray mailto:ray.hu...@amd.com>>
> Sent: Monday, May 17, 2021 2:27 PM
> To: Alex Deucher mailto:alexdeuc...@gmail.com>>; Zhu, 
> Changfeng
> mailto:changfeng@amd.com>>
> Cc: amd-gfx list 
> mailto:amd-gfx@lists.freedesktop.org>>
> Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to
> avoid compute hang
>
> On Fri, May 14, 2021 at 10:13:55PM +0800, Alex Deucher wrote:
> > On Fri, May 14, 2021 at 4:20 AM 
> > mailto:changfeng@amd.com>> wrote:
> > >
> > > From: changzhu mailto:changfeng@amd.com>>
> > >
> > > From: Changfeng mailto:changfeng@amd.com>>
> > >
> > > There is problem with 3DCGCG firmware and it will cause compute
> > > test hang on picasso/raven1. It needs to disable 3DCGCG in driver
> > > to avoid compute hang.
> > >
> > > Change-Id: Ic7d3c7922b2b32f7ac5193d6a4869cbc5b3baa87
> > > Signed-off-by: Changfeng 
> > > mailto:changfeng@amd.com>>
> >
> > Reviewed-by: Alex Deucher 
> > 

Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang

[Deucher, Alexander]

[Public]

+ Nirmoy

I thought we disabled all but one of the compute queues on raven due to this 
issue.  Maybe that patch never landed?  Wasn't this the same issue that was 
exposed by Nirmoy's patch that provided better load balancing across queues?

Alex


From: amd-gfx  on behalf of Zhu, 
Changfeng 
Sent: Tuesday, May 18, 2021 10:28 PM
To: Alex Deucher 
Cc: Huang, Ray ; amd-gfx list 
Subject: RE: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid 
compute hang

[AMD Official Use Only - Internal Distribution Only]

Hi Alex.

I have submitted the patch: drm/amdgpu: disable 3DCGCG on picasso/raven1 to 
avoid compute hang

Do you mean we have something else to do for re-enabling the extra compute 
queues?

BR,
Changfeng.

-Original Message-
From: Alex Deucher 
Sent: Wednesday, May 19, 2021 10:20 AM
To: Zhu, Changfeng 
Cc: Huang, Ray ; amd-gfx list 
Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid 
compute hang

Care to submit a patch to re-enable the extra compute queues?

Alex

On Mon, May 17, 2021 at 4:09 AM Zhu, Changfeng  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Ray and Alex,
>
> I have confirmed it can enable the additional compute queues with this patch:
>
> [   41.823013] This is ring mec 1, pipe 0, queue 0, value 1
> [   41.823028] This is ring mec 1, pipe 1, queue 0, value 1
> [   41.823042] This is ring mec 1, pipe 2, queue 0, value 1
> [   41.823057] This is ring mec 1, pipe 3, queue 0, value 1
> [   41.823071] This is ring mec 1, pipe 0, queue 1, value 1
> [   41.823086] This is ring mec 1, pipe 1, queue 1, value 1
> [   41.823101] This is ring mec 1, pipe 2, queue 1, value 1
> [   41.823115] This is ring mec 1, pipe 3, queue 1, value 1
>
> BR,
> Changfeng.
>
>
> -Original Message-
> From: Huang, Ray 
> Sent: Monday, May 17, 2021 2:27 PM
> To: Alex Deucher ; Zhu, Changfeng
> 
> Cc: amd-gfx list 
> Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to
> avoid compute hang
>
> On Fri, May 14, 2021 at 10:13:55PM +0800, Alex Deucher wrote:
> > On Fri, May 14, 2021 at 4:20 AM  wrote:
> > >
> > > From: changzhu 
> > >
> > > From: Changfeng 
> > >
> > > There is problem with 3DCGCG firmware and it will cause compute
> > > test hang on picasso/raven1. It needs to disable 3DCGCG in driver
> > > to avoid compute hang.
> > >
> > > Change-Id: Ic7d3c7922b2b32f7ac5193d6a4869cbc5b3baa87
> > > Signed-off-by: Changfeng 
> >
> > Reviewed-by: Alex Deucher 
> >
> > WIth this applied, can we re-enable the additional compute queues?
> >
>
> I think so.
>
> Changfeng, could you please confirm this on all raven series?
>
> Patch is Reviewed-by: Huang Rui 
>
> > Alex
> >
> > > ---
> > >  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++---
> > >  drivers/gpu/drm/amd/amdgpu/soc15.c|  2 --
> > >  2 files changed, 7 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > index 22608c45f07c..feaa5e4a5538 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > @@ -4947,7 +4947,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct 
> > > amdgpu_device *adev,
> > > amdgpu_gfx_rlc_enter_safe_mode(adev);
> > >
> > > /* Enable 3D CGCG/CGLS */
> > > -   if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
> > > +   if (enable) {
> > > /* write cmd to clear cgcg/cgls ov */
> > > def = data = RREG32_SOC15(GC, 0, 
> > > mmRLC_CGTT_MGCG_OVERRIDE);
> > > /* unset CGCG override */ @@ -4959,8 +4959,12 @@
> > > static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
> > > /* enable 3Dcgcg FSM(0x363f) */
> > > def = RREG32_SOC15(GC, 0,
> > > mmRLC_CGCG_CGLS_CTRL_3D);
> > >
> > > -   data = (0x36 << 
> > > RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> > > -   RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
> > > +   if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
> > > +   data = (0x36 << 
> > > RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> > > +   RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
> > > +   else
> > > +   data = 0x0 <<
> > > + RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT;
> > > +
> > > if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
> > > data |= (0x000F << 
> > > RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
> > >
> > > RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > > b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > > index 4b660b2d1c22..080e715799d4 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > > @@ -1393,7 +1393,6 @@ static int 

Re: [PATCH] drm/amdgpu: stop touching sched.ready in the backend

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Christian 
König 
Sent: Tuesday, May 18, 2021 11:50 AM
To: Zhu, James 
Cc: amd-gfx@lists.freedesktop.org 
Subject: [PATCH] drm/amdgpu: stop touching sched.ready in the backend

This unfortunately comes up in regular intervals and breaks
GPU reset for the engine in question.

The sched.ready flag controls if an engine can't get working
during hw_init, but should never be set to false during hw_fini.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 --
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 2 --
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 5 -
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c  | 6 --
 4 files changed, 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c 
b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index 83531997aeba..938ef4ce5b76 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -198,8 +198,6 @@ static int jpeg_v2_5_hw_fini(void *handle)
 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
   RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
 jpeg_v2_5_set_powergating_state(adev, 
AMD_PG_STATE_GATE);
-
-   ring->sched.ready = false;
 }

 return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index de5dfcfb3859..94be35357f7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -166,8 +166,6 @@ static int jpeg_v3_0_hw_fini(void *handle)
   RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
 jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);

-   ring->sched.ready = false;
-
 return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 7c4e0586e26d..2d5d07c80307 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -497,11 +497,6 @@ static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 
0);
 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), 
ib_cntl);
 }
-
-   sdma0->sched.ready = false;
-   sdma1->sched.ready = false;
-   sdma2->sched.ready = false;
-   sdma3->sched.ready = false;
 }

 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index cf165ab5dd26..b512acf0e95f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -388,12 +388,6 @@ static int vcn_v3_0_hw_fini(void *handle)
 vcn_v3_0_set_powergating_state(adev, 
AMD_PG_STATE_GATE);
 }
 }
-   ring->sched.ready = false;
-
-   for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
-   ring = >vcn.inst[i].ring_enc[j];
-   ring->sched.ready = false;
-   }
 }

 return 0;
--
2.25.1

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Re: [PATCH] drm/amdgpu: Unmap all MMIO mappings

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher 

From: Grodzovsky, Andrey 
Sent: Tuesday, May 18, 2021 10:01 AM
To: dri-de...@lists.freedesktop.org ; 
amd-gfx@lists.freedesktop.org ; 
linux-...@vger.kernel.org ; 
ckoenig.leichtzumer...@gmail.com ; 
daniel.vet...@ffwll.ch ; Wentland, Harry 

Cc: ppaala...@gmail.com ; Deucher, Alexander 
; gre...@linuxfoundation.org 
; helg...@kernel.org ; 
Kuehling, Felix 
Subject: Re: [PATCH] drm/amdgpu: Unmap all MMIO mappings

Ping

Andrey

On 2021-05-17 3:31 p.m., Andrey Grodzovsky wrote:
> Access to those must be prevented post pci_remove
>
> v6: Drop BOs list, unampping VRAM BAR is enough.
> v8:
> Add condition of xgmi.connected_to_cpu to MTTR
> handling and remove MTTR handling from the old place.
>
> Signed-off-by: Andrey Grodzovsky 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 26 +++---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  4 
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  4 
>   3 files changed, 23 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index f7cca25c0fa0..8b50315d1fe1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3666,6 +3666,27 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>return r;
>   }
>
> +static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev)
> +{
> + /* Clear all CPU mappings pointing to this device */
> + unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1);
> +
> + /* Unmap all mapped bars - Doorbell, registers and VRAM */
> + amdgpu_device_doorbell_fini(adev);
> +
> + iounmap(adev->rmmio);
> + adev->rmmio = NULL;
> + if (adev->mman.aper_base_kaddr)
> + iounmap(adev->mman.aper_base_kaddr);
> + adev->mman.aper_base_kaddr = NULL;
> +
> + /* Memory manager related */
> + if (!adev->gmc.xgmi.connected_to_cpu) {
> + arch_phys_wc_del(adev->gmc.vram_mtrr);
> + arch_io_free_memtype_wc(adev->gmc.aper_base, 
> adev->gmc.aper_size);
> + }
> +}
> +
>   /**
>* amdgpu_device_fini - tear down the driver
>*
> @@ -3712,6 +3733,8 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
>amdgpu_device_ip_fini_early(adev);
>
>amdgpu_gart_dummy_page_fini(adev);
> +
> + amdgpu_device_unmap_mmio(adev);
>   }
>
>   void amdgpu_device_fini_sw(struct amdgpu_device *adev)
> @@ -3739,9 +3762,6 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)
>}
>if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
>vga_client_register(adev->pdev, NULL, NULL, NULL);
> - iounmap(adev->rmmio);
> - adev->rmmio = NULL;
> - amdgpu_device_doorbell_fini(adev);
>
>if (IS_ENABLED(CONFIG_PERF_EVENTS))
>amdgpu_pmu_fini(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 0adffcace326..8eabe3c9ad17 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -1107,10 +1107,6 @@ int amdgpu_bo_init(struct amdgpu_device *adev)
>   void amdgpu_bo_fini(struct amdgpu_device *adev)
>   {
>amdgpu_ttm_fini(adev);
> - if (!adev->gmc.xgmi.connected_to_cpu) {
> - arch_phys_wc_del(adev->gmc.vram_mtrr);
> - arch_io_free_memtype_wc(adev->gmc.aper_base, 
> adev->gmc.aper_size);
> - }
>   }
>
>   /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 0d54e70278ca..58ad2fecc9e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1841,10 +1841,6 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
>amdgpu_bo_free_kernel(>mman.discovery_memory, NULL, NULL);
>amdgpu_ttm_fw_reserve_vram_fini(adev);
>
> - if (adev->mman.aper_base_kaddr)
> - iounmap(adev->mman.aper_base_kaddr);
> - adev->mman.aper_base_kaddr = NULL;
> -
>amdgpu_vram_mgr_fini(adev);
>amdgpu_gtt_mgr_fini(adev);
>ttm_range_man_fini(>mman.bdev, AMDGPU_PL_GDS);
>
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Re: [PATCH] drm/amdgpu: Complete multimedia bandwidth interface

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Liu, Monk 

Sent: Thursday, May 13, 2021 7:50 AM
To: Zhang, Bokun ; amd-gfx@lists.freedesktop.org 

Cc: Zhang, Bokun 
Subject: RE: [PATCH] drm/amdgpu: Complete multimedia bandwidth interface

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Monk liu 

Better get  open source team's RB as well

Thanks

--
Monk Liu | Cloud-GPU Core team
--

-Original Message-
From: amd-gfx  On Behalf Of Bokun Zhang
Sent: Thursday, May 13, 2021 1:20 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Bokun 
Subject: [PATCH] drm/amdgpu: Complete multimedia bandwidth interface

- Update SRIOV PF2VF header with latest revision

- Extend existing function in amdgpu_virt.c to read MM bandwidth config
  from PF2VF message

- Add SRIOV Sienna Cichlid codec array and update the bandwidth with
  PF2VF message

Change-Id: Id0cfa2e1adb7a097997d53b34d41a6d36a390c00
Signed-off-by: Bokun Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c|  56 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h|  13 +++
 drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h |  54 --
 drivers/gpu/drm/amd/amdgpu/nv.c | 110 +++-
 4 files changed, 226 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index a57842689d42..c64e583347c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -432,6 +432,9 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device 
*adev)
 uint32_t checksum;
 uint32_t checkval;

+   uint32_t i;
+   uint32_t tmp;
+
 if (adev->virt.fw_reserve.p_pf2vf == NULL)
 return -EINVAL;

@@ -472,6 +475,27 @@ static int amdgpu_virt_read_pf2vf_data(struct 
amdgpu_device *adev)
 adev->virt.reg_access =
 ((struct amd_sriov_msg_pf2vf_info 
*)pf2vf_info)->reg_access_flags.all;

+   adev->virt.decode_max_dimension_pixels = 0;
+   adev->virt.decode_max_frame_pixels = 0;
+   adev->virt.encode_max_dimension_pixels = 0;
+   adev->virt.encode_max_frame_pixels = 0;
+   adev->virt.is_mm_bw_enabled = false;
+   for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) {
+   tmp = ((struct amd_sriov_msg_pf2vf_info 
*)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels;
+   adev->virt.decode_max_dimension_pixels = max(tmp,
+adev->virt.decode_max_dimension_pixels);
+
+   tmp = ((struct amd_sriov_msg_pf2vf_info 
*)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels;
+   adev->virt.decode_max_frame_pixels = max(tmp,
+adev->virt.decode_max_frame_pixels);
+
+   tmp = ((struct amd_sriov_msg_pf2vf_info 
*)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels;
+   adev->virt.encode_max_dimension_pixels = max(tmp,
+adev->virt.encode_max_dimension_pixels);
+
+   tmp = ((struct amd_sriov_msg_pf2vf_info 
*)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels;
+   adev->virt.encode_max_frame_pixels = max(tmp, 
adev->virt.encode_max_frame_pixels);
+   }
+   if((adev->virt.decode_max_dimension_pixels > 0) || 
(adev->virt.encode_max_dimension_pixels > 0))
+   adev->virt.is_mm_bw_enabled = true;
+
 break;
 default:
 DRM_ERROR("invalid pf2vf version\n"); @@ -744,3 +768,35 @@ 
enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad

 return mode;
 }
+
+void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
+   struct amdgpu_video_codec_info *encode, uint32_t 
encode_array_size,
+   struct amdgpu_video_codec_info *decode, uint32_t 
decode_array_size)
+{
+   uint32_t i;
+
+   if (!adev->virt.is_mm_bw_enabled)
+   return;
+
+   if (encode) {
+   for (i = 0; i < encode_array_size; i++) {
+   encode[i].max_width = 
adev->virt.encode_max_dimension_pixels;
+   encode[i].max_pixels_per_frame = 
adev->virt.encode_max_frame_pixels;
+   if (encode[i].max_width > 0)
+   encode[i].max_height = 
encode[i].max_pixels_per_frame / encode[i].max_width;
+   else
+   encode[i].max_height = 0;
+   }
+   }
+
+   if (decode) {
+   for (i = 0; i < decode_array_size; i++) {
+   decode[i].max_width = 
adev->virt.decode_max_dimension_pixels;
+   

Re: [PATCH] drm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlid

[Deucher, Alexander]

[AMD Public Use]

Acked-by: Alex Deucher 

From: YuBiao Wang 
Sent: Thursday, May 13, 2021 6:33 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Grodzovsky, Andrey ; Quan, Evan 
; Chen, Horace ; Tuikov, Luben 
; Koenig, Christian ; Deucher, 
Alexander ; Xiao, Jack ; Zhang, 
Hawking ; Liu, Monk ; Xu, Feifei 
; Wang, Kevin(Yang) ; Xiaojie Yuan 
; Wang, YuBiao 
Subject: [PATCH] drm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlid

[Why]
IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it.

[How]
Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov.

Signed-off-by: YuBiao Wang 
---
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 20 ++--
 drivers/gpu/drm/amd/amdgpu/nv.c| 12 +---
 2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c 
b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index f4e4040bbd25..5ee923ccdeb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -151,7 +151,15 @@ static int navi10_ih_toggle_ring_interrupts(struct 
amdgpu_device *adev,
 /* enable_intr field is only valid in ring0 */
 if (ih == >irq.ih)
 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 
: 0));
-   WREG32(ih_regs->ih_rb_cntl, tmp);
+
+   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+   if (psp_reg_program(>psp, ih_regs->psp_reg_id, tmp)) {
+   DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+   return -ETIMEDOUT;
+   }
+   } else {
+   WREG32(ih_regs->ih_rb_cntl, tmp);
+   }

 if (enable) {
 ih->enabled = true;
@@ -261,7 +269,15 @@ static int navi10_ih_enable_ring(struct amdgpu_device 
*adev,
 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
 }
-   WREG32(ih_regs->ih_rb_cntl, tmp);
+
+   if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+   if (psp_reg_program(>psp, ih_regs->psp_reg_id, tmp)) {
+   DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+   return -ETIMEDOUT;
+   }
+   } else {
+   WREG32(ih_regs->ih_rb_cntl, tmp);
+   }

 if (ih == >irq.ih) {
 /* set the ih ring 0 writeback address whether it's enabled or 
not */
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 75d1f9b939b2..2ec5d4e1f363 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -764,9 +764,15 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 case CHIP_SIENNA_CICHLID:
 amdgpu_device_ip_block_add(adev, _common_ip_block);
 amdgpu_device_ip_block_add(adev, _v10_0_ip_block);
-   amdgpu_device_ip_block_add(adev, _ih_ip_block);
-   if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
-   amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
+   if (!amdgpu_sriov_vf(adev)) {
+   amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   if (likely(adev->firmware.load_type == 
AMDGPU_FW_LOAD_PSP))
+   amdgpu_device_ip_block_add(adev, 
_v11_0_ip_block);
+   } else {
+   if (likely(adev->firmware.load_type == 
AMDGPU_FW_LOAD_PSP))
+   amdgpu_device_ip_block_add(adev, 
_v11_0_ip_block);
+   amdgpu_device_ip_block_add(adev, _ih_ip_block);
+   }
 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 is_support_sw_smu(adev))
 amdgpu_device_ip_block_add(adev, _v11_0_ip_block);
--
2.25.1

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RE: [PATCH 1/2] drm/amdgpu: Don't query CE and UE errors

[Deucher, Alexander]

[AMD Public Use]

> -Original Message-
> From: Tuikov, Luben 
> Sent: Wednesday, May 12, 2021 1:03 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Tuikov, Luben ; Deucher, Alexander
> ; sta...@vger.kernel.org
> Subject: [PATCH 1/2] drm/amdgpu: Don't query CE and UE errors
> 
> On QUERY2 IOCTL don't query counts of correctable and uncorrectable
> errors, since when RAS is enabled and supported on Vega20 server boards,
> this takes insurmountably long time, in O(n^3), which slows the system down
> to the point of it being unusable when we have GUI up.
> 
> Fixes: ae363a212b14 ("drm/amdgpu: Add a new flag to
> AMDGPU_CTX_OP_QUERY_STATE2")
> Cc: Alexander Deucher 
> Cc: sta...@vger.kernel.org
> Signed-off-by: Luben Tuikov 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 26 ---
> --
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> index 01fe60fedcbe..d481a33f4eaf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> @@ -363,19 +363,19 @@ static int amdgpu_ctx_query2(struct
> amdgpu_device *adev,
>   out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY;
> 
>   /*query ue count*/
> - ras_counter = amdgpu_ras_query_error_count(adev, false);
> - /*ras counter is monotonic increasing*/
> - if (ras_counter != ctx->ras_counter_ue) {
> - out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
> - ctx->ras_counter_ue = ras_counter;
> - }
> -
> - /*query ce count*/
> - ras_counter = amdgpu_ras_query_error_count(adev, true);
> - if (ras_counter != ctx->ras_counter_ce) {
> - out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
> - ctx->ras_counter_ce = ras_counter;
> - }
> + /* ras_counter = amdgpu_ras_query_error_count(adev, false); */
> + /* /\*ras counter is monotonic increasing*\/ */
> + /* if (ras_counter != ctx->ras_counter_ue) { */
> + /*  out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
> */
> + /*  ctx->ras_counter_ue = ras_counter; */
> + /* } */
> +
> + /* /\*query ce count*\/ */
> + /* ras_counter = amdgpu_ras_query_error_count(adev, true); */
> + /* if (ras_counter != ctx->ras_counter_ce) { */
> + /*  out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
> */
> + /*  ctx->ras_counter_ce = ras_counter; */
> + /* } */
> 

Rather than commenting this out, just drop it in patch 1, and then re-add this 
in patch 2.

Alex

>   mutex_unlock(>lock);
>   return 0;
> --
> 2.31.1.527.g2d677e5b15
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Re: [PATCH] drm/amdgpu: Add compile flag for securedisplay

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

Acked-by: Alex Deucher 

From: amd-gfx  on behalf of Jinzhou Su 

Sent: Tuesday, May 11, 2021 9:51 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Su, Jinzhou (Joe) ; Huang, Ray 
Subject: [PATCH] drm/amdgpu: Add compile flag for securedisplay

Add compile flag CONFIG_DEBUG_FS to clear the warning:
unused variable 'amdgpu_securedisplay_debugfs_ops'

Signed-off-by: Jinzhou Su 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
index 5369c8dd0764..123453999093 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c
@@ -86,6 +86,8 @@ void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, 
struct securedispla
 (*cmd)->cmd_id = command_id;
 }

+#if defined(CONFIG_DEBUG_FS)
+
 static ssize_t amdgpu_securedisplay_debugfs_write(struct file *f, const char 
__user *buf,
 size_t size, loff_t *pos)
 {
@@ -162,6 +164,8 @@ static const struct file_operations 
amdgpu_securedisplay_debugfs_ops = {
 .llseek = default_llseek
 };

+#endif
+
 void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev)
 {
 #if defined(CONFIG_DEBUG_FS)
--
2.27.0

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Re: [PATCH] drm/amdgpu: Align serial size in drm_amdgpu_info_vbios

[Deucher, Alexander]

[AMD Public Use]

It's being used by umr and some other smi tools to provide vbios information 
for debugging.

Alex


From: amd-gfx  on behalf of Marek Olšák 

Sent: Tuesday, May 11, 2021 4:18 AM
To: Christian König 
Cc: Kees Cook ; Gu, JiaWei (Will) ; 
amd-gfx list ; Deng, Emily ; 
Alex Deucher ; Nieto, David M 
Subject: Re: [PATCH] drm/amdgpu: Align serial size in drm_amdgpu_info_vbios

Mesa doesn't use sysfs.

Note that this is a uapi, meaning that once it's in the kernel, it can't be 
changed like that.

What's the use case for this new interface? Isn't it partially redundant with 
the current device info structure, which seems to have the equivalent of dev_id 
and rev_id?

Marek

On Tue, May 11, 2021 at 3:51 AM Christian König 
mailto:ckoenig.leichtzumer...@gmail.com>> 
wrote:
Marek and other userspace folks need to decide that.

Basic question here is if Mesa is already accessing sysfs nodes for OpenGL or 
RADV. If that is the case then we should probably expose the information there 
as well.

If that isn't the case (which I think it is) then we should implement it as 
IOCTL.

Regards,
Christian.

Am 10.05.21 um 22:19 schrieb Nieto, David M:

One of the primary usecases is to add this information to the renderer string, 
I am not sure if there are other cases of UMD drivers accessing sysfs nodes, 
but I think if we think permissions, if a client is authenticated and opens the 
render device then it can use the IOCTL, it is unclear to me we can make a such 
an assumption for sysfs nodes…



I think there is value in having both tbh.



Regards,

David



From: Christian König 

Date: Monday, May 10, 2021 at 6:48 AM
To: "Nieto, David M" , "Gu, 
JiaWei (Will)" 
Cc: Alex Deucher , "Deng, 
Emily" , Kees Cook 
, amd-gfx list 

Subject: Re: [PATCH] drm/amdgpu: Align serial size in drm_amdgpu_info_vbios



Well we could add both as sysfs file(s).

Question here is rather what is the primary use case of this and if the 
application has the necessary access permissions to the sysfs files?

Regards,
Christian.

Am 10.05.21 um 15:42 schrieb Nieto, David M:

Then the application would need to issue the ioctl and then open a sysfs file 
to get all the information it needs. It makes little sense from a programming 
perspective to add an incomplete interface in my opinion





From: Gu, JiaWei (Will) 
Sent: Monday, May 10, 2021 12:13:07 AM
To: Nieto, David M 
Cc: Alex Deucher ; amd-gfx 
list ; 
Kees Cook ; Deng, Emily 

Subject: RE: [PATCH] drm/amdgpu: Align serial size in drm_amdgpu_info_vbios



[AMD Official Use Only - Internal Distribution Only]

Hi David,

What I meant is to ONLY delete the serial[16] from drm_amdgpu_info_vbios, not 
the whole struct.

struct drm_amdgpu_info_vbios {
__u8 name[64];
__u32 dbdf;
__u8 vbios_pn[64];
__u32 version;
__u8 date[32];
__u8 serial[16]; // jiawei: shall we delete this
__u32 dev_id;
__u32 rev_id;
__u32 sub_dev_id;
__u32 sub_ved_id;
};

serial[16] in drm_amdgpu_info_vbios  copied from adev->serial, but there's 
already a sysfs named serial_number, which exposes it already.

static ssize_t amdgpu_device_get_serial_number(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;

return snprintf(buf, PAGE_SIZE, "%s\n", adev->serial);
}

Thanks,
Jiawei


-Original Message-
From: Nieto, David M 
Sent: Monday, May 10, 2021 2:53 PM
To: Gu, JiaWei (Will) 
Cc: Alex Deucher ; amd-gfx 
list ; 
Kees Cook ; Deng, Emily 

Subject: Re: [PATCH] drm/amdgpu: Align serial size in drm_amdgpu_info_vbios

No, this structure contains all the details of the vbios: date, serial number, 
name, etc.

The sysfs node only contains the vbios name string

> On May 9, 2021, at 23:33, Gu, JiaWei (Will) 
>  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> With a second thought,
> __u8 serial[16] in drm_amdgpu_info_vbios is a bit redundant, sysfs 
> serial_number already exposes it.
>
> Is it fine to abandon it from drm_amdgpu_info_vbios struct? @Alex
> Deucher @Nieto, David M
>
> Best regards,
> Jiawei
>
> -Original Message-
> From: Alex Deucher 
> Sent: Sunday, May 9, 

Re: [PATCH v6 04/16] drm/amdkfd: Split kfd suspend from devie exit

[Deucher, Alexander]

[AMD Public Use]

Typo in the subject: devie > device

Alex

From: Grodzovsky, Andrey 
Sent: Monday, May 10, 2021 12:36 PM
To: dri-de...@lists.freedesktop.org ; 
amd-gfx@lists.freedesktop.org ; 
linux-...@vger.kernel.org ; 
ckoenig.leichtzumer...@gmail.com ; 
daniel.vet...@ffwll.ch ; Wentland, Harry 

Cc: ppaala...@gmail.com ; Deucher, Alexander 
; gre...@linuxfoundation.org 
; helg...@kernel.org ; 
Kuehling, Felix ; Grodzovsky, Andrey 

Subject: [PATCH v6 04/16] drm/amdkfd: Split kfd suspend from devie exit

Helps to expdite HW related stuff to amdgpu_pci_remove

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_device.c| 3 ++-
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 5f6696a3c778..2b06dee9a0ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -170,7 +170,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 }
 }

-void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
+void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev)
 {
 if (adev->kfd.dev) {
 kgd2kfd_device_exit(adev->kfd.dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 14f68c028126..f8e10af99c28 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -127,7 +127,7 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
 const void *ih_ring_entry);
 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
-void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev);
+void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
 uint32_t vmid, uint64_t gpu_addr,
 uint32_t *ib_cmd, uint32_t ib_len);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index 357b9bf62a1c..ab6d2a43c9a3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -858,10 +858,11 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
 return kfd->init_complete;
 }

+
+
 void kgd2kfd_device_exit(struct kfd_dev *kfd)
 {
 if (kfd->init_complete) {
-   kgd2kfd_suspend(kfd, false);
 device_queue_manager_uninit(kfd->dqm);
 kfd_interrupt_exit(kfd);
 kfd_topology_remove_device(kfd);
--
2.25.1

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Re: [PATCH] drm/amdgpu: Field type update in drm_amdgpu_info_vbios

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

Please update the umr patch as well.

Acked-by: Alex Deucher 


From: amd-gfx  on behalf of Jiawei Gu 

Sent: Tuesday, May 11, 2021 1:31 AM
To: amd-gfx@lists.freedesktop.org 
Cc: StDenis, Tom ; Gu, JiaWei (Will) ; 
keesc...@chromium.org ; Nieto, David M 

Subject: [PATCH] drm/amdgpu: Field type update in drm_amdgpu_info_vbios

Use numeric type serial in drm_amdgpu_info_vbios instead.

Signed-off-by: Jiawei Gu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
 include/uapi/drm/amdgpu_drm.h   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 75f34a9008e7..e1008a79b441 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -871,7 +871,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, 
sizeof(atom_context->vbios_pn));
 vbios_info.version = atom_context->version;
 memcpy(vbios_info.date, atom_context->date, 
sizeof(atom_context->date));
-   memcpy(vbios_info.serial, adev->serial, 
sizeof(adev->serial));
+   vbios_info.serial = adev->unique_id;
 vbios_info.dev_id = adev->pdev->device;
 vbios_info.rev_id = adev->pdev->revision;
 vbios_info.sub_dev_id = atom_context->sub_dev_id;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 2b487a8d2727..2d9e84658bbc 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -957,7 +957,7 @@ struct drm_amdgpu_info_vbios {
 __u8 vbios_pn[64];
 __u32 version;
 __u8 date[32];
-   __u8 serial[16];
+   __u64 serial;
 __u32 dev_id;
 __u32 rev_id;
 __u32 sub_dev_id;
--
2.17.1

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Re: [PATCH libdrm] Revert "tests/amdgpu: fix bo eviction test issue"

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

For libdrm tests, please open a gitlab merge request:
https://gitlab.freedesktop.org/mesa/drm/-/merge_requests

Alex


From: amd-gfx  on behalf of Yu, Lang 

Sent: Friday, May 7, 2021 3:10 AM
To: Chen, Guchun ; amd-gfx@lists.freedesktop.org 
; Huang, Ray ; Song, Asher 

Subject: RE: [PATCH libdrm] Revert "tests/amdgpu: fix bo eviction test issue"

[AMD Official Use Only - Internal Distribution Only]


Reviewed-by:  Lang Yu 

Regards，
Lang

-Original Message-
From: Chen, Guchun 
Sent: Thursday, May 6, 2021 5:55 PM
To: amd-gfx@lists.freedesktop.org; Yu, Lang ; Huang, Ray 
; Song, Asher 
Cc: Chen, Guchun 
Subject: [PATCH libdrm] Revert "tests/amdgpu: fix bo eviction test issue"

This reverts commit a5a400c9581c3b91598623603067556b18084c5d.

bo evict test was disabled by default per below commit. So still keep it as 
disabled.

1f6a85cc test/amdgpu: disable bo eviction test by default

Signed-off-by: Guchun Chen 
---
 tests/amdgpu/amdgpu_test.c |  3 +++
 tests/amdgpu/basic_tests.c | 13 -
 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 
60f3a508..77bbfbcc 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -496,6 +496,9 @@ static void amdgpu_disable_suites()
 "gfx ring slow bad draw test (set 
amdgpu.lockup_timeout=50)", CU_FALSE))
 fprintf(stderr, "test deactivation failed - %s\n", 
CU_get_error_msg());

+   if (amdgpu_set_test_active(BASIC_TESTS_STR, "bo eviction Test", 
CU_FALSE))
+   fprintf(stderr, "test deactivation failed - %s\n",
+CU_get_error_msg());
+
 /* This test was ran on GFX8 and GFX9 only */
 if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV)
 if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency 
Test", CU_FALSE)) diff --git a/tests/amdgpu/basic_tests.c 
b/tests/amdgpu/basic_tests.c index 8e7c4916..3a4214f5 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -928,15 +928,6 @@ static void amdgpu_bo_eviction_test(void)
0, _info);
 CU_ASSERT_EQUAL(r, 0);

-   r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT,
-  0, _info);
-   CU_ASSERT_EQUAL(r, 0);
-
-   if (vram_info.max_allocation > gtt_info.heap_size/3) {
-   vram_info.max_allocation = gtt_info.heap_size/3;
-   gtt_info.max_allocation = vram_info.max_allocation;
-   }
-
 r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096,
  AMDGPU_GEM_DOMAIN_VRAM, 0, _max[0]);
 CU_ASSERT_EQUAL(r, 0);
@@ -944,6 +935,10 @@ static void amdgpu_bo_eviction_test(void)
  AMDGPU_GEM_DOMAIN_VRAM, 0, _max[1]);
 CU_ASSERT_EQUAL(r, 0);

+   r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT,
+  0, _info);
+   CU_ASSERT_EQUAL(r, 0);
+
 r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096,
  AMDGPU_GEM_DOMAIN_GTT, 0, _max[0]);
 CU_ASSERT_EQUAL(r, 0);
--
2.17.1
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Re: [PATCH] drm/amdgpu: set vcn mgcg flag for picasso

[Deucher, Alexander]

[AMD Public Use]

Acked-by: Alex Deucher 

From: Sundararaju, Sathishkumar 
Sent: Tuesday, May 4, 2021 5:27 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Liu, Leo ; 
Sundararaju, Sathishkumar 
Subject: [PATCH] drm/amdgpu: set vcn mgcg flag for picasso

From: Sathishkumar S 

enable vcn mgcg flag for picasso.

Signed-off-by: Sathishkumar S 
Reviewed-by: Leo Liu 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 28e9f6b726a6..e3f42ad1e6bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1401,7 +1401,8 @@ static int soc15_common_early_init(void *handle)
 AMD_CG_SUPPORT_MC_MGCG |
 AMD_CG_SUPPORT_MC_LS |
 AMD_CG_SUPPORT_SDMA_MGCG |
-   AMD_CG_SUPPORT_SDMA_LS;
+   AMD_CG_SUPPORT_SDMA_LS |
+   AMD_CG_SUPPORT_VCN_MGCG;

 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
 AMD_PG_SUPPORT_MMHUB |
--
2.17.1

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RE: [PATCH] Revert "drm/radeon/si_dpm: Replace one-element array with flexible-array in struct SISLANDS_SMC_SWSTATE"

[Deucher, Alexander]

[AMD Public Use]

> -Original Message-
> From: Gustavo A. R. Silva 
> Sent: Tuesday, May 4, 2021 6:43 PM
> To: Deucher, Alexander ; amd-
> g...@lists.freedesktop.org
> Cc: Gustavo A . R . Silva 
> Subject: Re: [PATCH] Revert "drm/radeon/si_dpm: Replace one-element
> array with flexible-array in struct SISLANDS_SMC_SWSTATE"
> 
> Hi,
> 
> I thought it was this[1] the one causing problems[2].

They are both causing problems.

Alex

> 
> --
> Gustavo
> 
> [1]
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.k
> ernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Ftorvalds%2Flinux.git%
> 2Fcommit%2F%3Fid%3D434fb1e7444a2efc3a4ebd950c7f771ebfcffa31d
> ata=04%7C01%7Calexander.deucher%40amd.com%7C2e5ec39776404b9f1ad
> a08d90f4def14%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6375
> 57649665013301%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiL
> CJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=ItE
> aD0%2FcD8SZYTdHFEzLqhAkz4u40VJ3b8jXmnKubYc%3Dreserved=0
> [2]
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.
> kernel.org%2Fdri-devel%2F3eedbe78-1fbd-4763-a7f3-
> ac5665e76a4a%40xenosoft.de%2Fdata=04%7C01%7Calexander.deuch
> er%40amd.com%7C2e5ec39776404b9f1ada08d90f4def14%7C3dd8961fe4884
> e608e11a82d994e183d%7C0%7C0%7C637557649665013301%7CUnknown%7C
> TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL
> CJXVCI6Mn0%3D%7C1000sdata=oNDZm9xHuOWbelrUrXYXPoyXLlk2dI
> kRH75O43AFNcI%3Dreserved=0
> 
> On 5/4/21 13:42, Alex Deucher wrote:
> > This reverts commit 96e27e8d919e52f30ea6b717e3cb70faa0b102cd.
> >
> > This causes the SMU to fail to load the power state.
> >
> > Bug:
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitl
> > ab.freedesktop.org%2Fdrm%2Famd%2F-
> %2Fissues%2F1583data=04%7C01%7C
> >
> alexander.deucher%40amd.com%7C2e5ec39776404b9f1ada08d90f4def14%7
> C3dd89
> >
> 61fe4884e608e11a82d994e183d%7C0%7C0%7C637557649665013301%7CUnkn
> own%7CT
> >
> WFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLC
> JXVCI
> >
> 6Mn0%3D%7C1000sdata=zo7mfnO2t%2BtQgPxIquuDYIsROlkqECjdX0r
> JOPyklyc
> > %3Dreserved=0
> > Signed-off-by: Alex Deucher 
> > Cc: Gustavo A. R. Silva 
> > ---
> >  drivers/gpu/drm/radeon/si_dpm.c   |  5 +++--
> >  drivers/gpu/drm/radeon/sislands_smc.h | 10 +-
> >  2 files changed, 8 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/si_dpm.c
> > b/drivers/gpu/drm/radeon/si_dpm.c index 918609551804..91bfc4762767
> > 100644
> > --- a/drivers/gpu/drm/radeon/si_dpm.c
> > +++ b/drivers/gpu/drm/radeon/si_dpm.c
> > @@ -5250,9 +5250,10 @@ static int si_upload_sw_state(struct
> radeon_device *rdev,
> > int ret;
> > u32 address = si_pi->state_table_start +
> > offsetof(SISLANDS_SMC_STATETABLE, driverState);
> > +   u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
> > +   ((new_state->performance_level_count - 1) *
> > +sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
> > SISLANDS_SMC_SWSTATE *smc_state = _pi-
> >smc_statetable.driverState;
> > -   size_t state_size = struct_size(smc_state, levels,
> > -   new_state-
> >performance_level_count);
> >
> > memset(smc_state, 0, state_size);
> >
> > diff --git a/drivers/gpu/drm/radeon/sislands_smc.h
> > b/drivers/gpu/drm/radeon/sislands_smc.h
> > index fbd6589bdab9..966e3a556011 100644
> > --- a/drivers/gpu/drm/radeon/sislands_smc.h
> > +++ b/drivers/gpu/drm/radeon/sislands_smc.h
> > @@ -182,11 +182,11 @@ typedef struct
> SISLANDS_SMC_HW_PERFORMANCE_LEVEL
> > SISLANDS_SMC_HW_PERFORMANCE_LEV
> >
> >  struct SISLANDS_SMC_SWSTATE
> >  {
> > -   uint8_t flags;
> > -   uint8_t levelCount;
> > -   uint8_t padding2;
> > -   uint8_t padding3;
> > -   SISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[];
> > +uint8_t flags;
> > +uint8_t levelCount;
> > +uint8_t padding2;
> > +uint8_t padding3;
> > +SISLANDS_SMC_HW_PERFORMANCE_LEVEL   levels[1];
> >  };
> >
> >  typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE;
> >
___
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