Re: [PATCH] drm/amdgpu: fix spelling mistake: "suuport"-> "support"

[Christian König]

Am 25.07.2017 um 00:45 schrieb Colin King:

From: Colin Ian King 

Trivial fix to spelling mistake in WARN_ONCE message

Signed-off-by: Colin Ian King 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 5795f81369f0..06f11e2a32af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1301,7 +1301,7 @@ static int amdgpu_vm_update_ptes(struct 
amdgpu_pte_update_params *params,
  
  		if (params->shadow) {

if (WARN_ONCE(use_cpu_update,
-   "CPU VM update doesn't suuport shadow pages"))
+   "CPU VM update doesn't support shadow pages"))
return 0;
  
  			if (!pt->shadow)



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[PATCH 8/8] drm/amdgpu/sdma4: Enable sdma poll mem addr on vega10 for SRIOV

[Xiangliang . Yu]

From: Frank Min 

While doing flr on VFs, there is possibility to lost the doorbell
writing for sdma, so enable poll mem for sdma, then sdma fw would
check the pollmem holding wptr.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  3 +++
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 48 --
 2 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d287621..79d46fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1208,6 +1208,9 @@ struct amdgpu_sdma_instance {
 
struct amdgpu_ring  ring;
boolburst_nop;
+   struct amdgpu_bo*poll_mem_bo;
+   uint64_t*poll_mem_cpuaddr;
+   uint64_tpoll_mem_gpuaddr;
 };
 
 struct amdgpu_sdma {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 591f3e7..563be32 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -35,6 +35,7 @@
 #include "vega10/MMHUB/mmhub_1_0_offset.h"
 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
 #include "vega10/HDP/hdp_4_0_offset.h"
+#include "vega10/NBIO/nbio_6_1_offset.h"
 #include "raven1/SDMA0/sdma0_4_1_default.h"
 
 #include "soc15_common.h"
@@ -287,6 +288,7 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring 
*ring)
  */
 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 {
+   int i;
struct amdgpu_device *adev = ring->adev;
 
DRM_DEBUG("Setting write pointer\n");
@@ -303,6 +305,16 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring 
*ring)
adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 
2);
DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
ring->doorbell_index, ring->wptr << 2);
+
+   if (amdgpu_sriov_vf(adev)) {
+   for (i = 0; i < adev->sdma.num_instances; i++) {
+   if (>sdma.instance[i].ring == ring) {
+   
*adev->sdma.instance[i].poll_mem_cpuaddr = ring->wptr << 2;
+   WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
+  
mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+   }
+   }
+   }
WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
} else {
int me = (ring == >adev->sdma.instance[0].ring) ? 0 : 1;
@@ -573,7 +585,7 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev, 
bool enable)
 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 {
struct amdgpu_ring *ring;
-   u32 rb_cntl, ib_cntl;
+   u32 rb_cntl, ib_cntl, wptr_poll_addr_lo, wptr_poll_addr_hi, 
wptr_poll_cntl;
u32 rb_bufsz;
u32 wb_offset;
u32 doorbell;
@@ -687,6 +699,19 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 
if (adev->mman.buffer_funcs_ring == ring)
amdgpu_ttm_set_active_vram_size(adev, 
adev->mc.real_vram_size);
+
+   if (amdgpu_sriov_vf(adev)) {
+   wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
+   wptr_poll_addr_lo = RREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO));
+   wptr_poll_addr_lo = REG_SET_FIELD(wptr_poll_addr_lo, 
SDMA0_GFX_RB_WPTR_POLL_ADDR_LO, ADDR,
+   
lower_32_bits(adev->sdma.instance[i].poll_mem_gpuaddr) >> 2);
+   wptr_poll_addr_hi = 
upper_32_bits(adev->sdma.instance[i].poll_mem_gpuaddr);
+   wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 
SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
+
+   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), wptr_poll_addr_lo);
+   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), wptr_poll_addr_hi);
+   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
+   }
}
 
return 0;
@@ -1247,6 +1272,20 @@ static int sdma_v4_0_sw_init(void *handle)
 (i == 0) ?
 AMDGPU_SDMA_IRQ_TRAP0 :
 AMDGPU_SDMA_IRQ_TRAP1);
+
+   if (amdgpu_sriov_vf(adev)) {
+   r = amdgpu_bo_create_kernel(adev, 8, PAGE_SIZE,
+   AMDGPU_GEM_DOMAIN_VRAM, 
>sdma.instance[i].poll_mem_bo,
+ 

[PATCH 3/8] drm/amdgpu/vce4: Remove vce interrupt enable related code for sriov

[Xiangliang . Yu]

From: Frank Min 

Interrupt enable is contained in vce init table and this register could
not be accessed in secure ASICs, so just remove it.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 28532e3..9e0050d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -992,11 +992,13 @@ static int vce_v4_0_set_interrupt_state(struct 
amdgpu_device *adev,
 {
uint32_t val = 0;
 
-   if (state == AMDGPU_IRQ_STATE_ENABLE)
-   val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
+   if (!amdgpu_sriov_vf(adev)) {
+   if (state == AMDGPU_IRQ_STATE_ENABLE)
+   val |= 
VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
 
-   WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,
-   ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
+   WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val,
+   
~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
+   }
return 0;
 }
 
-- 
2.7.4

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[PATCH] drm/amdgpu/dce_virtual: remove error message for vega10

[Xiangliang . Yu]

Vega10 also support virtual display, remove the error message.

Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 6487e40..5e6d6be 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -501,6 +501,8 @@ static int dce_virtual_hw_init(void *handle)
 #endif
/* no DCE */
break;
+   case CHIP_VEGA10:
+   break;
default:
DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", 
adev->asic_type);
}
-- 
2.7.4

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Re: iMac 10,1 with Ubuntu 16.04: black screen after suspend

[Lukas Wunner]

On Tue, Jul 25, 2017 at 07:14:23AM +0200, Mario Kleiner wrote:
> On 07/24/2017 03:45 PM, Florian Echtler wrote:
> > thanks for the hint. I've applied this patch to the v4.12 tree I'm
> > currently running, and it didn't seem to make any difference (i.e.
> > display stays black after suspend).
> 
> That's the same here with my patch applied. After a suspend -> resume, the
> internal panel stays black, the patch doesn't help for that. Somethig i
> didn't notice btw., apparently i never suspend->resumed it.
[...]
> Lukas idea that some hardware mux gets switched into the wrong position on
> models with TDM sounds pretty appealing to me, but how to test?

If all else fails, with a multimeter / oscilloscope. :-)  The board
schematics are available by googling for the right terms, such as
the drawing number "051-7863" and internal codename "K23".

Of interest is the eDP connector on the mainboard, page 90.  Notice
there are two power rails going into it, 3.3V (pin 31) and 12V (pins
27 - 30).  Florian obtained dmesg output of the machine coming out
of suspend by ssh'ing into it and it showed that the eDP link could
be trained properly upon system resume.  Still the panel stayed black.

My guess is that the panel's DisplayPort transceiver is powered via the
3.3V rail.  This rail is powered permanently when the system is in S0,
it cannot be switched off at runtime.  So, the Radeon card can talk to
the DisplayPort transceiver (which has power) but the 12V rail, which
presumably powers the LED backlight, is off.  You could test this theory
by attaching a multimeter after coming out of suspend:  You should see
a voltage difference of 3.3V between pins 31 and 32 (ground) and 0V
between pins 27 - 30 and 32.

The logic for the 12V rail is somewhat complicated, first there's
pin 21 ("VIDEO_ON"), this seems to come *from* the panel and presumably
signals that the link is trained. This should go high after resume.
If it does not then maybe a write to a custom DPCD register is necessary
to make it go high.  If this pin stays low then the 12V rail is not
powered.

Next there's a 74LVC157A mux (page 95 top-left).  Datasheet:
https://assets.nexperia.com/documents/data-sheet/74LVC157A.pdf
The mux can switch four wires, but Apple only needed three.
I guess all outputs (pins 7, 9, 12) must be high for the backlight
to go on.  The mux is under the control of the SMC and is presumably
switched by issuing appropriate commands to the SMC.  It's unclear
to me if the SMC has switched it to the Radeon or to the TDM source
after resume.

Assuming that the mux is switched to the Radeon card, follow input
pins 5, 10 and 14 (MXM_PNL_BL_PWM, MXM_PNL_BL_EN, MXM_PNL_PWR_EN).
They are coming from a "system management" block on the Radeon card
(pins 25, 27, 23, page 85).  Apparently these are GPIO pins for
OEM use and I guess they can be controlled by writing to the PCI BAR
of the Radeon card, but I've no idea at what address their registers
might be located.  I'll try to look at the macOS Radeon drivers with
a disassembler but this is like looking for a needle in a haystack.


> However this is something i got when connecting the external Displayport
> panel:
> 
> Jul  7 04:16:09 kleinerm-MaxtorLinux kernel: [ 1441.344792]
> [drm:radeon_dp_link_train [radeon]] *ERROR* displayport link status failed
> Jul  7 04:16:09 kleinerm-MaxtorLinux kernel: [ 1441.344819]
> [drm:radeon_dp_link_train [radeon]] *ERROR* clock recovery failed
> Jul  7 04:18:07 kleinerm-MaxtorLinux kernel: [ 1559.770783]
> drm_dp_i2c_do_msg: 20 callbacks suppressed
> Jul  7 04:30:19 kleinerm-MaxtorLinux kernel: [ 2291.143406]
> [drm:radeon_dp_link_train [radeon]] *ERROR* displayport link status failed
> Jul  7 04:30:19 kleinerm-MaxtorLinux kernel: [ 2291.143439]
> [drm:radeon_dp_link_train [radeon]] *ERROR* clock recovery failed
> Jul  7 04:30:19 kleinerm-MaxtorLinux kernel: [ 2291.356173]
> [drm:radeon_dp_link_train [radeon]] *ERROR* displayport link status failed
> Jul  7 04:30:19 kleinerm-MaxtorLinux kernel: [ 2291.356205]
> [drm:radeon_dp_link_train [radeon]] *ERROR* clock recovery failed
> 
> So link training failed, because drm_dp_dpcd_read_link_status() already
> failed to read from the dp aux channel.

The AUX channel can be terminated in either of two modes under the control
of the SMC:  100k source termination or weak sink termination (page 94/95).
Failure to communicate over AUX may be explained by being in the incorrect
mode.

HTH,

Lukas
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Re: [PATCH] drm/amdgpu/dce_virtual: remove error message for vega10

[Christian König]

Am 25.07.2017 um 11:50 schrieb Xiangliang.Yu:

Vega10 also support virtual display, remove the error message.

Signed-off-by: Xiangliang.Yu 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
index 6487e40..5e6d6be 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
@@ -501,6 +501,8 @@ static int dce_virtual_hw_init(void *handle)
  #endif
/* no DCE */
break;
+   case CHIP_VEGA10:
+   break;
default:
DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", 
adev->asic_type);
}



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Re: 答复: [PATCH 1/4] drm/amdgpu/gmc6: disable legacy vga features in gmc init (v2)

[Christian König]

The term "legacy VGA" sounds like the whole render functionality which 
actually isn't part of the GMC AFAIK.


But what Alex primary disables here is the old VGA BAR in the CPU 
address space and that is part of the GMC (or at least related to it).


BTW: Patch are Acked-by: Christian König .

Christian.

Am 25.07.2017 um 11:26 schrieb Qu, Jim:

Hi Christian:

Could you share your minds when you are on second glance?

Thanks
JimQu


发件人: amd-gfx  代表 Christian König 

发送时间: 2017年7月25日 17:17
收件人: Alex Deucher; amd-gfx@lists.freedesktop.org
抄送: Deucher, Alexander
主题: Re: [PATCH 1/4] drm/amdgpu/gmc6: disable legacy vga features in gmc init 
(v2)

Am 25.07.2017 um 05:30 schrieb Alex Deucher:

Needs to be done when the MC is set up.

v2: make consistent with other asics

Signed-off-by: Alex Deucher 

On first glance it kind of looks a bit odd to have that in the GMC code,
but on second glance it actually makes sense.

Christian.


---
   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 14 +-
   1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 117c4835..ab0a104 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -249,7 +249,19 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
   dev_warn(adev->dev, "Wait for MC idle timedout !\n");
   }

- WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
+ if (adev->mode_info.num_crtc) {
+ u32 tmp;
+
+ /* Lockout access through VGA aperture*/
+ tmp = RREG32(mmVGA_HDP_CONTROL);
+ tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
+ WREG32(mmVGA_HDP_CONTROL, tmp);
+
+ /* disable VGA render */
+ tmp = RREG32(mmVGA_RENDER_CONTROL);
+ tmp &= ~VGA_VSTATUS_CNTL;
+ WREG32(mmVGA_RENDER_CONTROL, tmp);
+ }
   /* Update configuration */
   WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
  adev->mc.vram_start >> 12);


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[PATCH 7/8] drm/amdgpu/uvd7: optimize uvd initialization sequence for SRIOV

[Xiangliang . Yu]

From: Frank Min 

1.Since in sriov there is no need of decoding, so skip the related code;
2.Vcpu boot up and umc enable need to take at the end of the init sequence;

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 58 +++
 1 file changed, 11 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 590c3f0..3b64951 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -745,11 +745,9 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
init_table += header->uvd_table_offset;
 
ring = >uvd.ring;
+   ring->wptr = 0;
size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 
-   /* disable clock gating */
-   MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_POWER_STATUS),
-  
~UVD_POWER_STATUS__UVD_PG_MODE_MASK, 0);
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_STATUS),
   0x, 0x0004);
/* mc resume*/
@@ -786,12 +784,6 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_VCPU_CACHE_SIZE2),
AMDGPU_UVD_STACK_SIZE + 
(AMDGPU_UVD_SESSION_SIZE * 40));
 
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_UDEC_ADDR_CONFIG),
-   adev->gfx.config.gb_addr_config);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_UDEC_DB_ADDR_CONFIG),
-   adev->gfx.config.gb_addr_config);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_UDEC_DBW_ADDR_CONFIG),
-   adev->gfx.config.gb_addr_config);
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
/* mc resume end*/
 
@@ -828,17 +820,6 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
   
UVD_LMI_CTRL__REQ_MODE_MASK |
   0x0010L));
 
-   /* disable byte swapping */
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_LMI_SWAP_CNTL), 0);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MP_SWAP_CNTL), 0);
-
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MPC_SET_MUXA0), 0x40c2040);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MPC_SET_MUXA1), 0x0);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MPC_SET_MUXB0), 0x40c2040);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MPC_SET_MUXB1), 0x0);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MPC_SET_ALU), 0);
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MPC_SET_MUX), 0x88);
-
/* take all subblocks out of reset, except VCPU */
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_SOFT_RESET),

UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
@@ -847,15 +828,6 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_VCPU_CNTL),
UVD_VCPU_CNTL__CLK_EN_MASK);
 
-   /* enable UMC */
-   MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_LMI_CTRL2),
-  
~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
-
-   /* boot up the VCPU */
-   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_SOFT_RESET), 0);
-
-   MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_STATUS), 0x02, 0x02);
-
/* enable master interrupt */
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, 
mmUVD_MASTINT_EN),
   
~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
@@ -868,32 +840,24 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device 
*adev)
/* force RBC into idle state */
size = order_base_2(ring->ring_size);
tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
-   tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
-   tmp = 

[PATCH 4/8] drm/amdgpu: Skip uvd and vce ring test for SRIOV

[Xiangliang . Yu]

From: Frank Min 

Since rptr would not be accessed on later secure asics in sriov, remove
the ring test.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c   | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index b692ad4..c855366 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -937,9 +937,9 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
unsigned i;
int r, timeout = adev->usec_timeout;
 
-   /* workaround VCE ring test slow issue for sriov*/
+   /* skip ring test for sriov*/
if (amdgpu_sriov_vf(adev))
-   timeout *= 10;
+   return 0;
 
r = amdgpu_ring_alloc(ring, 16);
if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index fbf7b412..ab447e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -165,6 +165,9 @@ static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring 
*ring)
unsigned i;
int r;
 
+   if (amdgpu_sriov_vf(adev))
+   return 0;
+
r = amdgpu_ring_alloc(ring, 16);
if (r) {
DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
-- 
2.7.4

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[PATCH 5/8] drm/amdgpu: According hardware design revert vce and uvd doorbell assignment

[Xiangliang . Yu]

From: Frank Min 

Now uvd doorbell is from 0xf8-0xfb and vce doorbell is from 0xfc-0xff

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   | 18 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c |  6 --
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c |  6 +++---
 3 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index fe96236..d287621 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -680,15 +680,15 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
/* overlap the doorbell assignment with VCN as they are  mutually 
exclusive
 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
 */
-   AMDGPU_DOORBELL64_RING0_1 = 0xF8,
-   AMDGPU_DOORBELL64_RING2_3 = 0xF9,
-   AMDGPU_DOORBELL64_RING4_5 = 0xFA,
-   AMDGPU_DOORBELL64_RING6_7 = 0xFB,
-
-   AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC,
-   AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD,
-   AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE,
-   AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF,
+   AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
+   AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
+   AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
+   AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
+
+   AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
+   AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
+   AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
+   AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
 
AMDGPU_DOORBELL64_MAX_ASSIGNMENT  = 0xFF,
AMDGPU_DOORBELL64_INVALID = 0x
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index ab447e8..590c3f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -435,13 +435,15 @@ static int uvd_v7_0_sw_init(void *handle)
return r;
}
 
-
for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
ring = >uvd.ring_enc[i];
sprintf(ring->name, "uvd_enc%d", i);
if (amdgpu_sriov_vf(adev)) {
ring->use_doorbell = true;
-   ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 
2;
+   if (i == 0)
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
+   else
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
}
r = amdgpu_ring_init(adev, ring, 512, >uvd.irq, 0);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 9e0050d..34c2281 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -446,11 +446,11 @@ static int vce_v4_0_sw_init(void *handle)
/* DOORBELL only works under SRIOV */
ring->use_doorbell = true;
if (i == 0)
-   ring->doorbell_index = 
AMDGPU_DOORBELL64_RING0_1 * 2;
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_VCE_RING0_1 * 2;
else if (i == 1)
-   ring->doorbell_index = 
AMDGPU_DOORBELL64_RING2_3 * 2;
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_VCE_RING2_3 * 2;
else
-   ring->doorbell_index = 
AMDGPU_DOORBELL64_RING2_3 * 2 + 1;
+   ring->doorbell_index = 
AMDGPU_DOORBELL64_VCE_RING2_3 * 2 + 1;
}
r = amdgpu_ring_init(adev, ring, 512, >vce.irq, 0);
if (r)
-- 
2.7.4

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Re: [PATCH 4/4] drm/amdgpu/gmc9: disable legacy vga features in gmc init

[Huang Rui]

On Tue, Jul 25, 2017 at 01:06:42PM +0800, Huang Rui wrote:
> On Tue, Jul 25, 2017 at 04:06:00AM +, Deucher, Alexander wrote:
> > > -Original Message-
> > > From: Alex Deucher [mailto:alexdeuc...@gmail.com]
> > > Sent: Monday, July 24, 2017 11:31 PM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deucher, Alexander
> > > Subject: [PATCH 4/4] drm/amdgpu/gmc9: disable legacy vga features in gmc
> > > init
> > > 
> > > Needs to be done when the MC is set up.
> > > 
> > > Signed-off-by: Alex Deucher 
> > 
> > Can someone see if this patch fixes the problem with the lower 8 MB of vram 
> > on vega10?  I think this may explain what was messing with vram on resume 
> > that caused us to reserve the first 8 MB of vram.
> > 
> 
> Let me have a try. The start of vram overwrite is probably still caused by
> VGA mode. So, here, you disable it at first.
> 

This patch doesn't fix the start 8 MB of vram corruption.
But I just found the 8M corruption issue only encountered when DC is disabled.

Thanks,
Ray
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Re: [PATCH 1/4] drm/amdgpu/gmc6: disable legacy vga features in gmc init (v2)

[Christian König]

Am 25.07.2017 um 05:30 schrieb Alex Deucher:

Needs to be done when the MC is set up.

v2: make consistent with other asics

Signed-off-by: Alex Deucher 


On first glance it kind of looks a bit odd to have that in the GMC code, 
but on second glance it actually makes sense.


Christian.


---
  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 14 +-
  1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 117c4835..ab0a104 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -249,7 +249,19 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
dev_warn(adev->dev, "Wait for MC idle timedout !\n");
}
  
-	WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);

+   if (adev->mode_info.num_crtc) {
+   u32 tmp;
+
+   /* Lockout access through VGA aperture*/
+   tmp = RREG32(mmVGA_HDP_CONTROL);
+   tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
+   WREG32(mmVGA_HDP_CONTROL, tmp);
+
+   /* disable VGA render */
+   tmp = RREG32(mmVGA_RENDER_CONTROL);
+   tmp &= ~VGA_VSTATUS_CNTL;
+   WREG32(mmVGA_RENDER_CONTROL, tmp);
+   }
/* Update configuration */
WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
   adev->mc.vram_start >> 12);



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[PATCH 2/8] drm/amdgpu: Enable uvd and vce gpu re-init for SRIOV gpu reset

[Xiangliang . Yu]

From: Frank Min 

Add uvd and vce re-init after gpu reset.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  | 3 +--
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c  | 4 +---
 3 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9c0f4cc..fe6783e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1953,7 +1953,8 @@ static int amdgpu_sriov_reinit_late(struct amdgpu_device 
*adev)
AMD_IP_BLOCK_TYPE_DCE,
AMD_IP_BLOCK_TYPE_GFX,
AMD_IP_BLOCK_TYPE_SDMA,
-   AMD_IP_BLOCK_TYPE_VCE,
+   AMD_IP_BLOCK_TYPE_UVD,
+   AMD_IP_BLOCK_TYPE_VCE
};
 
for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index e2b17cb..fbf7b412 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -894,9 +894,8 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
header->uvd_table_size = table_size;
 
-   return uvd_v7_0_mmsch_start(adev, >virt.mm_table);
}
-   return -EINVAL; /* already initializaed ? */
+   return uvd_v7_0_mmsch_start(adev, >virt.mm_table);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 9b1de6b..28532e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -300,11 +300,9 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev)
memcpy((void *)init_table, , sizeof(struct 
mmsch_v1_0_cmd_end));
table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
header->vce_table_size = table_size;
-
-   return vce_v4_0_mmsch_start(adev, >virt.mm_table);
}
 
-   return -EINVAL; /* already initializaed ? */
+   return vce_v4_0_mmsch_start(adev, >virt.mm_table);
 }
 
 /**
-- 
2.7.4

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[PATCH 1/8] drm/amdgpu: Clear vce ring wptr for SRIOV

[Xiangliang . Yu]

From: Frank Min 

MMSCH FW need to get the wptr from 0 after it get the mailbox request
from driver, since every time kick the mailbox, mmsch thinks that it
is the first time engine start to initialize.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +-
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 987b958..e2b17cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -685,6 +685,11 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
/* 4, set resp to zero */
WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 
+   WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
+   adev->wb.wb[adev->uvd.ring_enc[0].wptr_offs] = 0;
+   adev->uvd.ring_enc[0].wptr = 0;
+   adev->uvd.ring_enc[0].wptr_old = 0;
+
/* 5, kick off the initialization and wait until 
VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x1001);
 
@@ -702,7 +707,6 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
dev_err(adev->dev, "failed to init MMSCH, 
mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
return -EBUSY;
}
-   WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 1ecd6bb..9b1de6b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -173,6 +173,11 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev,
/* 4, set resp to zero */
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);
 
+   WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
+   adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0;
+   adev->vce.ring[0].wptr = 0;
+   adev->vce.ring[0].wptr_old = 0;
+
/* 5, kick off the initialization and wait until 
VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 
0x1001);
 
@@ -190,7 +195,6 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device *adev,
dev_err(adev->dev, "failed to init MMSCH, 
mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
return -EBUSY;
}
-   WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
 
return 0;
 }
-- 
2.7.4

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[PATCH 6/8] drm/amdgpu/vce4: optimize vce 4.0 init table sequence for SRIOV

[Xiangliang . Yu]

From: Frank Min 

Optimize init table sequence for sriov.

Signed-off-by: Frank Min 
Signed-off-by: Xiangliang.Yu 
---
 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 34c2281..b2c0d70 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -278,7 +278,8 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev)
 
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_LMI_CTRL2), ~0x100, 0);
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_SYS_INT_EN),
-  0x, 
VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
+  
VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,
+  
VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
 
/* end of MC_RESUME */
MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_STATUS),
-- 
2.7.4

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答复: [PATCH 1/4] drm/amdgpu/gmc6: disable legacy vga features in gmc init (v2)

[Qu, Jim]

Hi Christian:

Could you share your minds when you are on second glance?

Thanks
JimQu


发件人: amd-gfx  代表 Christian König 

发送时间: 2017年7月25日 17:17
收件人: Alex Deucher; amd-gfx@lists.freedesktop.org
抄送: Deucher, Alexander
主题: Re: [PATCH 1/4] drm/amdgpu/gmc6: disable legacy vga features in gmc init 
(v2)

Am 25.07.2017 um 05:30 schrieb Alex Deucher:
> Needs to be done when the MC is set up.
>
> v2: make consistent with other asics
>
> Signed-off-by: Alex Deucher 

On first glance it kind of looks a bit odd to have that in the GMC code,
but on second glance it actually makes sense.

Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 14 +-
>   1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 117c4835..ab0a104 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -249,7 +249,19 @@ static void gmc_v6_0_mc_program(struct amdgpu_device 
> *adev)
>   dev_warn(adev->dev, "Wait for MC idle timedout !\n");
>   }
>
> - WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK);
> + if (adev->mode_info.num_crtc) {
> + u32 tmp;
> +
> + /* Lockout access through VGA aperture*/
> + tmp = RREG32(mmVGA_HDP_CONTROL);
> + tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
> + WREG32(mmVGA_HDP_CONTROL, tmp);
> +
> + /* disable VGA render */
> + tmp = RREG32(mmVGA_RENDER_CONTROL);
> + tmp &= ~VGA_VSTATUS_CNTL;
> + WREG32(mmVGA_RENDER_CONTROL, tmp);
> + }
>   /* Update configuration */
>   WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
>  adev->mc.vram_start >> 12);


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Re: [PATCH 4/4] drm/amdgpu/gmc9: disable legacy vga features in gmc init

[Harry Wentland]

Not an expert on GMC but this seems to be the right place to do this in
the sequence.

For the series:
Acked-by: Harry Wentland 

Harry

On 2017-07-24 11:19 PM, Alex Deucher wrote:
> Needs to be done when the MC is set up.
> 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 16 
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 677181f..c22899a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -29,6 +29,8 @@
>  #include "vega10/HDP/hdp_4_0_offset.h"
>  #include "vega10/HDP/hdp_4_0_sh_mask.h"
>  #include "vega10/GC/gc_9_0_sh_mask.h"
> +#include "vega10/DC/dce_12_0_offset.h"
> +#include "vega10/DC/dce_12_0_sh_mask.h"
>  #include "vega10/vega10_enum.h"
>  
>  #include "soc15_common.h"
> @@ -750,6 +752,20 @@ static int gmc_v9_0_hw_init(void *handle)
>   /* The sequence of these two function calls matters.*/
>   gmc_v9_0_init_golden_registers(adev);
>  
> + if (adev->mode_info.num_crtc) {
> + u32 tmp;
> +
> + /* Lockout access through VGA aperture*/
> + tmp = RREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL);
> + tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 
> 1);
> + WREG32_SOC15(DCE, 0, mmVGA_HDP_CONTROL, tmp);
> +
> + /* disable VGA render */
> + tmp = RREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL);
> + tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 
> 0);
> + WREG32_SOC15(DCE, 0, mmVGA_RENDER_CONTROL, tmp);
> + }
> +
>   r = gmc_v9_0_gart_enable(adev);
>  
>   return r;
> 
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Re: iMac 10,1 with Ubuntu 16.04: black screen after suspend

[Florian Echtler]

On 25.07.2017 07:14, Mario Kleiner wrote:
> On 07/24/2017 03:45 PM, Florian Echtler wrote:
> 
> That's the same here with my patch applied. After a suspend -> resume, the
> internal panel stays black, the patch doesn't help for that. Somethig i didn't
> notice btw., apparently i never suspend->resumed it.

OK - I'm guessing if the panel/connector mess gets properly sorted out in
general, then it will probably also start working after suspend/resume...

> The internal panel always works during boot, until the radeon kms driver loads
> and modesetting gets initialized, then the panel goes dark.

Weirdly enough, this is now the behaviour I'm getting, too, no matter if I use
the patched driver or the original one. So there's definitely some bit of
persistent state somewhere that got flipped during experimentation, probably
inside that stupid SMC.

> Without my patch the internal panel stays dark, but plugging in an external
> hdmi/dvi display gets both internal+external to light up.
> 
> Another way i was able to force the internal panel to stay on without my patch
> and without an external display connected is to use the kernel cmdline option
> "video=DP-1:2560x1440D" to force the external output on, although nothing is
> connected.

None of the video options, either with "DP" or "eDP", made a difference in my
case. The one scenario where I suddenly got the internal panel to turn on was
when I plugged in a DP _source_ (my laptop). Also caused the same DP link train
error messages to appear in dmesg.

> So the same machine model behaves differently with the same patch, and worse 
> in
> your case than without it? Maybe different hardware or firmware?
> 
> Apples website lists two models of late 2009 iMac10,1 and Radeon HD 4670, to
> which the patch should apply. One 21.5 inch model without TDM and a 27 inch
> model with TDM. Mine is the 27 inch one. I assume yours as well due to TDM?
> Attached is the output of dmidecode on mine, not sure what to look for for
> differences?

Yes, also 27 inch. I've compared the dmidecode output, only notable differences
are data from RAM modules, so it's the same machine and same FW versions.

> Also attached a dmesg snippet for comparison wrt. SMBIOS version etc.

Nearly everything identical, except my dmesg doesn't show the following lines:

-[0.00] efi: EFI v1.10 by Apple
-[0.00] efi:  ACPI=0xbfeee000  ACPI 2.0=0xbfeee014  SMBIOS=0xbfec4000

I'm booting Linux via rEFIt, so I would have assumed that it's a "regular" EFI
boot, but apparently not. What's your boot configuration?

> Lukas idea that some hardware mux gets switched into the wrong position on
> models with TDM sounds pretty appealing to me, but how to test?

I'm using TDM regularly; interestingly enough, this works completely reliably,
even if the panel was dark before. My code is at
https://github.com/floe/smc_util if you want to give it a try, but apparently
there's more to it than just the two keys (MVMR/MVHR) which I'm currently using.

Maybe you can run smc_dump_linux.sh on your machine (should be safe, only reads
keys) and see if there's some difference between keys depending on what state
the panel is in?

Best, Florian
-- 
SENT FROM MY DEC VT50 TERMINAL



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[PATCH 23/81] drm/amd/display: Enable ipp compilation

[sunpeng.li]

From: Dmytro Laktyushkin 

Update relevant registers

Change-Id: Ic52d3a87ac72420b9919e0ba81d936e5137a120c
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c   | 19 ++---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h   | 91 +++---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  6 +-
 3 files changed, 54 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
index 1e7a55d..a09226c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
@@ -421,7 +421,10 @@ static void dcn10_ipp_enable_cm_block(
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
 
REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
-   REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
+   if (ippn10->ipp_mask->CM_BYPASS_EN)
+   REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
+   else
+   REG_UPDATE(CM_CONTROL, CM_BYPASS, 0);
 }
 
 
@@ -484,7 +487,7 @@ static bool dcn10_cursor_program_control(
 
REG_UPDATE_2(CURSOR0_CONTROL,
CUR0_MODE, color_format,
-   CUR0_INVERT_MODE, 0);
+   CUR0_EXPANSION_MODE, 0);
 
if (color_format == CURSOR_MODE_MONO) {
/* todo: clarify what to program these to */
@@ -501,18 +504,6 @@ static bool dcn10_cursor_program_control(
ALPHA_EN, 1,
FORMAT_EXPANSION_MODE, 0);
 
-   REG_UPDATE(CURSOR0_CONTROL,
-   CUR0_EXPANSION_MODE, 0);
-
-   if (0 /*attributes->attribute_flags.bits.MIN_MAX_INVERT*/) {
-   REG_UPDATE(CURSOR0_CONTROL,
-   CUR0_MAX,
-   0 /* TODO */);
-   REG_UPDATE(CURSOR0_CONTROL,
-   CUR0_MIN,
-   0 /* TODO */);
-   }
-
return true;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
index 5119935..d608abf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
@@ -31,7 +31,7 @@
 #define TO_DCN10_IPP(ipp)\
container_of(ipp, struct dcn10_ipp, base)
 
-#define IPP_DCN10_REG_LIST(id) \
+#define IPP_REG_LIST_DCN(id) \
SRI(CM_ICSC_CONTROL, CM, id), \
SRI(CM_ICSC_C11_C12, CM, id), \
SRI(CM_ICSC_C13_C14, CM, id), \
@@ -39,12 +39,6 @@
SRI(CM_ICSC_C23_C24, CM, id), \
SRI(CM_ICSC_C31_C32, CM, id), \
SRI(CM_ICSC_C33_C34, CM, id), \
-   SRI(CM_COMA_C11_C12, CM, id), \
-   SRI(CM_COMA_C13_C14, CM, id), \
-   SRI(CM_COMA_C21_C22, CM, id), \
-   SRI(CM_COMA_C23_C24, CM, id), \
-   SRI(CM_COMA_C31_C32, CM, id), \
-   SRI(CM_COMA_C33_C34, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
@@ -86,22 +80,31 @@
SRI(CM_DGAM_RAMA_REGION_12_13, CM, id), \
SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
SRI(CM_MEM_PWR_CTRL, CM, id), \
-   SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
-   SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
-   SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
SRI(CM_DGAM_LUT_INDEX, CM, id), \
SRI(CM_DGAM_LUT_DATA, CM, id), \
SRI(CM_CONTROL, CM, id), \
SRI(CM_DGAM_CONTROL, CM, id), \
-   SRI(CM_IGAM_CONTROL, CM, id), \
+   SRI(FORMAT_CONTROL, CNVC_CFG, id), \
SRI(DPP_CONTROL, DPP_TOP, id), \
SRI(CURSOR_SETTINS, HUBPREQ, id), \
SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
-   SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
-   SRI(FORMAT_CONTROL, CNVC_CFG, id), \
+   SRI(CURSOR0_COLOR1, CNVC_CUR, id)
+
+#define IPP_REG_LIST_DCN10(id) \
+   IPP_REG_LIST_DCN(id), \
+   SRI(CM_IGAM_CONTROL, CM, id), \
+   SRI(CM_COMA_C11_C12, CM, id), \
+   SRI(CM_COMA_C13_C14, CM, id), \
+   SRI(CM_COMA_C21_C22, CM, id), \
+   SRI(CM_COMA_C23_C24, CM, id), \
+   SRI(CM_COMA_C31_C32, CM, id), \
+   SRI(CM_COMA_C33_C34, CM, id), \
+   SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
+   SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
+   SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
SRI(CURSOR_SIZE, CURSOR, id), \
@@ -113,7 +116,7 @@
 #define IPP_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
 

[PATCH 77/81] drm/amd/display: fix aviInfoFrame bar Info and add set_avMute

[sunpeng.li]

From: Charlene Liu 

Change-Id: I8933d7bafe3b3cc18bc5aa41cedd89879d59de5a
Signed-off-by: Charlene Liu 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  | 10 ++
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 37 ++
 .../drm/amd/display/dc/dce/dce_stream_encoder.c| 13 +++-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 13 ++--
 .../amd/display/dc/dce110/dce110_hw_sequencer.h|  1 +
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  3 +-
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|  1 +
 .../gpu/drm/amd/display/dc/inc/hw/stream_encoder.h |  3 ++
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  2 ++
 .../display/dc/virtual/virtual_stream_encoder.c|  4 +++
 10 files changed, 77 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fed38fb..036d22f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1911,3 +1911,13 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
 }
 
+void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
+{
+   struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc);
+
+   if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
+   return;
+
+   core_dc->hwss.set_avmute(pipe_ctx, enable);
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 00fed61..d196d0d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1607,6 +1607,8 @@ static void set_avi_info_frame(
uint8_t *check_sum = NULL;
uint8_t byte_index = 0;
union hdmi_info_packet *hdmi_info = 
_frame.avi_info_packet.info_packet_hdmi;
+   unsigned int vic = pipe_ctx->stream->public.timing.vic;
+   enum dc_timing_3d_format format;
 
color_space = pipe_ctx->stream->public.output_color_space;
if (color_space == COLOR_SPACE_UNKNOWN)
@@ -1661,8 +1663,7 @@ static void set_avi_info_frame(
 
/* C0, C1 : Colorimetry */
if (color_space == COLOR_SPACE_YCBCR709 ||
-   color_space == COLOR_SPACE_YCBCR709_LIMITED ||
-   color_space == COLOR_SPACE_2020_YCBCR)
+   color_space == COLOR_SPACE_YCBCR709_LIMITED)
hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
else if (color_space == COLOR_SPACE_YCBCR601 ||
color_space == COLOR_SPACE_YCBCR601_LIMITED)
@@ -1722,9 +1723,29 @@ static void set_avi_info_frame(
hdmi_info->bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
}
-
-   hdmi_info->bits.VIC0_VIC7 =
-   stream->public.timing.vic;
+   ///VIC
+   format = stream->public.timing.timing_3d_format;
+   /*todo, add 3DStereo support*/
+   if (format != TIMING_3D_FORMAT_NONE) {
+   // Based on HDMI specs hdmi vic needs to be converted to cea 
vic when 3D is enabled
+   switch (pipe_ctx->stream->public.timing.hdmi_vic) {
+   case 1:
+   vic = 95;
+   break;
+   case 2:
+   vic = 94;
+   break;
+   case 3:
+   vic = 93;
+   break;
+   case 4:
+   vic = 98;
+   break;
+   default:
+   break;
+   }
+   }
+   hdmi_info->bits.VIC0_VIC7 = vic;
 
/* pixel repetition
 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
@@ -1737,7 +1758,7 @@ static void set_avi_info_frame(
 * barLeft:   Pixel Number of End of Left Bar.
 * barRight:  Pixel Number of Start of Right Bar. */
hdmi_info->bits.bar_top = stream->public.timing.v_border_top;
-   hdmi_info->bits.bar_bottom = (stream->public.timing.v_border_top
+   hdmi_info->bits.bar_bottom = (stream->public.timing.v_total
- stream->public.timing.v_border_bottom + 1);
hdmi_info->bits.bar_left  = stream->public.timing.h_border_left;
hdmi_info->bits.bar_right = (stream->public.timing.h_total
@@ -1776,6 +1797,10 @@ static void set_vendor_info_packet(
uint8_t checksum = 0;
uint32_t i = 0;
enum dc_timing_3d_format format;
+   // Can be different depending on packet content /*todo*/
+   // unsigned int length = pPathMode->dolbyVision ? 24 : 5;
+
+   

[PATCH 40/81] drm/amd/display: call pplib to update clocks

[sunpeng.li]

From: Eric Yang 

Allow pplib to update fclk and dcfclk for different voltage levels.
PPlib's values for dispclk and phyclk is not correct, so we are not
getting it from them. fclk is currently not used correctly, although
does not effect the actual fclk we request.

Change-Id: I649ae641f5367507f4a626be9a4f6358e08385fe
Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 46 +++-
 1 file changed, 4 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 3118c24..a1eabc4 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1226,28 +1226,13 @@ unsigned int dcn_find_dcfclk_suits_all(
 void dcn_bw_update_from_pplib(struct core_dc *dc)
 {
struct dc_context *ctx = dc->ctx;
-   struct dm_pp_clock_levels_with_latency clks = {0};
-   struct dm_pp_clock_levels_with_voltage clks2 = {0};
+   struct dm_pp_clock_levels_with_voltage clks = {0};
 
kernel_fpu_begin();
 
+   /* TODO: This is not the proper way to obtain 
fabric_and_dram_bandwidth, should be min(fclk, memclk) */
+
if (dm_pp_get_clock_levels_by_type_with_voltage(
-   ctx, DM_PP_CLOCK_TYPE_DISPLAY_CLK, ) &&
-   clks2.num_levels >= 3) {
-   dc->dcn_soc.max_dispclk_vmin0p65 = clks2.data[0].clocks_in_khz 
/ 1000.0;
-   dc->dcn_soc.max_dispclk_vmid0p72 = clks2.data[clks2.num_levels 
- 3].clocks_in_khz / 1000.0;
-   dc->dcn_soc.max_dispclk_vnom0p8 = clks2.data[clks2.num_levels - 
2].clocks_in_khz / 1000.0;
-   dc->dcn_soc.max_dispclk_vmax0p9 = clks2.data[clks2.num_levels - 
1].clocks_in_khz / 1000.0;
-   } else
-   BREAK_TO_DEBUGGER();
-/*
-   if (dm_pp_get_clock_levels_by_type_with_latency(
-   ctx, DM_PP_CLOCK_TYPE_MEMORY_CLK, ) &&
-   clks.num_levels != 0) {
-   //this  is to get DRAM data_rate
-   //FabricAndDRAMBandwidth = min(64*FCLK , Data rate * 
single_Channel_Width * number of channels);
-   }*/
-   if (dm_pp_get_clock_levels_by_type_with_latency(
ctx, DM_PP_CLOCK_TYPE_FCLK, ) &&
clks.num_levels != 0) {
ASSERT(clks.num_levels >= 3);
@@ -1265,7 +1250,7 @@ void dcn_bw_update_from_pplib(struct core_dc *dc)
(clks.data[clks.num_levels - 1].clocks_in_khz / 
1000.0) * ddr4_dram_factor_single_Channel / 1000.0;
} else
BREAK_TO_DEBUGGER();
-   if (dm_pp_get_clock_levels_by_type_with_latency(
+   if (dm_pp_get_clock_levels_by_type_with_voltage(
ctx, DM_PP_CLOCK_TYPE_DCFCLK, ) &&
clks.num_levels >= 3) {
dc->dcn_soc.dcfclkv_min0p65 = clks.data[0].clocks_in_khz / 
1000.0;
@@ -1274,30 +1259,7 @@ void dcn_bw_update_from_pplib(struct core_dc *dc)
dc->dcn_soc.dcfclkv_max0p9 = clks.data[clks.num_levels - 
1].clocks_in_khz / 1000.0;
} else
BREAK_TO_DEBUGGER();
-   if (dm_pp_get_clock_levels_by_type_with_voltage(
-   ctx, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, ) &&
-   clks2.num_levels >= 3) {
-   dc->dcn_soc.phyclkv_min0p65 = clks2.data[0].clocks_in_khz / 
1000.0;
-   dc->dcn_soc.phyclkv_mid0p72 = clks2.data[clks2.num_levels - 
3].clocks_in_khz / 1000.0;
-   dc->dcn_soc.phyclkv_nom0p8 = clks2.data[clks2.num_levels - 
2].clocks_in_khz / 1000.0;
-   dc->dcn_soc.phyclkv_max0p9 = clks2.data[clks2.num_levels - 
1].clocks_in_khz / 1000.0;
-   } else
-   BREAK_TO_DEBUGGER();
-   if (dm_pp_get_clock_levels_by_type_with_latency(
-   ctx, DM_PP_CLOCK_TYPE_DPPCLK, ) &&
-   clks.num_levels >= 3) {
-   dc->dcn_soc.max_dppclk_vmin0p65 = clks.data[0].clocks_in_khz / 
1000.0;
-   dc->dcn_soc.max_dppclk_vmid0p72 = clks.data[clks.num_levels - 
3].clocks_in_khz / 1000.0;
-   dc->dcn_soc.max_dppclk_vnom0p8 = clks.data[clks.num_levels - 
2].clocks_in_khz / 1000.0;
-   dc->dcn_soc.max_dppclk_vmax0p9 = clks.data[clks.num_levels - 
1].clocks_in_khz / 1000.0;
-   }
 
-   if (dm_pp_get_clock_levels_by_type_with_latency(
-   ctx, DM_PP_CLOCK_TYPE_SOCCLK, ) &&
-   clks.num_levels >= 3) {
-   dc->dcn_soc.socclk = clks.data[0].clocks_in_khz / 1000.0;
-   } else
-   BREAK_TO_DEBUGGER();
kernel_fpu_end();
 }
 
-- 
2.7.4

[PATCH 28/81] drm/amd/display: Hook dm private state into atomic_check

[sunpeng.li]

From: Harry Wentland 

Change-Id: Ia39ff138e644e6cbe0acaef755a8c77bb5c5919c
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 64 +++---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h|  5 ++
 2 files changed, 37 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index ed48c5e..52d1922 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3126,15 +3126,14 @@ static int do_aquire_global_lock(
 int amdgpu_dm_atomic_check(struct drm_device *dev,
struct drm_atomic_state *state)
 {
+   struct dm_atomic_state *dm_state;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
struct drm_plane *plane;
struct drm_plane_state *plane_state;
int i, j;
int ret;
-   int set_count;
int new_stream_count;
-   struct dc_validation_set set[MAX_STREAMS] = {{ 0 }};
struct dc_stream *new_streams[MAX_STREAMS] = { 0 };
struct drm_crtc *crtc_set[MAX_STREAMS] = { 0 };
struct amdgpu_device *adev = dev->dev_private;
@@ -3159,17 +3158,19 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
ret = -EINVAL;
 
+   dm_state = to_dm_atomic_state(state);
+
/* copy existing configuration */
new_stream_count = 0;
-   set_count = 0;
+   dm_state->set_count = 0;
list_for_each_entry(crtc, >mode_config.crtc_list, head) {
 
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 
if (acrtc->stream) {
-   set[set_count].stream = acrtc->stream;
-   crtc_set[set_count] = crtc;
-   ++set_count;
+   dm_state->set[dm_state->set_count].stream = 
acrtc->stream;
+   crtc_set[dm_state->set_count] = crtc;
+   ++dm_state->set_count;
}
}
 
@@ -3198,16 +3199,16 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
struct dc_stream *new_stream = NULL;
struct drm_connector_state *conn_state = NULL;
-   struct dm_connector_state *dm_state = NULL;
+   struct dm_connector_state *dm_conn_state = NULL;
 
if (aconnector) {
conn_state = 
drm_atomic_get_connector_state(state, >base);
if (IS_ERR(conn_state))
return ret;
-   dm_state = to_dm_connector_state(conn_state);
+   dm_conn_state = 
to_dm_connector_state(conn_state);
}
 
-   new_stream = create_stream_for_sink(aconnector, 
_state->mode, dm_state);
+   new_stream = create_stream_for_sink(aconnector, 
_state->mode, dm_conn_state);
 
/*
 * we can have no stream on ACTION_SET if a display
@@ -3222,10 +3223,10 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
}
 
new_streams[new_stream_count] = new_stream;
-   set_count = update_in_val_sets_stream(
-   set,
+   dm_state->set_count = update_in_val_sets_stream(
+   dm_state->set,
crtc_set,
-   set_count,
+   dm_state->set_count,
acrtc->stream,
new_stream,
crtc);
@@ -3238,9 +3239,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
/* i.e. reset mode */
if (acrtc->stream) {
-   set_count = remove_from_val_sets(
-   set,
-   set_count,
+   dm_state->set_count = remove_from_val_sets(
+   dm_state->set,
+   dm_state->set_count,
acrtc->stream);
aquire_global_lock = true;
}
@@ -3291,10 +3292,10 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
}
 
new_streams[new_stream_count] = new_stream;
-   set_count = update_in_val_sets_stream(
-   set,

[PATCH 18/81] drm/amd/display: Fix for hdmi frame pack stereo

[sunpeng.li]

From: Vitaly Prosyak 

Change-Id: Ifac9634dfbca459afe63fc1e2396ac060c32f7c4
Signed-off-by: Vitaly Prosyak 
Reviewed-by: Charlene Liu 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |   10 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c   |3 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |2 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |   11 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 1615 +++-
 5 files changed, 574 insertions(+), 1067 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 00961bc..4486121 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -987,7 +987,15 @@ bool dcn_validate_bandwidth(
if (pipe->surface) {
struct pipe_ctx *hsplit_pipe = 
pipe->bottom_pipe;
 
-   if (v->dpp_per_plane[input_idx] == 2) {
+   if (v->dpp_per_plane[input_idx] == 2 ||
+   ((pipe->stream->public.view_format ==
+ VIEW_3D_FORMAT_SIDE_BY_SIDE ||
+ pipe->stream->public.view_format ==
+ VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
+   
(pipe->stream->public.timing.timing_3d_format ==
+TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
+
pipe->stream->public.timing.timing_3d_format ==
+TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
if (hsplit_pipe && hsplit_pipe->surface 
== pipe->surface) {
/* update previously split pipe 
*/

hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx];
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a9ddd07..1d2e421e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -967,7 +967,6 @@ bool dc_commit_streams(

DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
 
core_dc->hwss.apply_ctx_for_surface(core_dc, surface, 
context);
-   dc_enable_stereo(dc, context, streams, stream_count);
}
 
CONN_MSG_MODE(sink->link, "{%ux%u, %ux%u@%u, %ux%u@%uKhz}",
@@ -982,7 +981,7 @@ bool dc_commit_streams(
context->streams[i]->public.timing.v_total,
context->streams[i]->public.timing.pix_clk_khz);
}
-
+   dc_enable_stereo(dc, context, streams, stream_count);
dc_resource_validate_ctx_destruct(core_dc->current_context);
dm_free(core_dc->current_context);
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 04579d0..9202bbe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -626,7 +626,7 @@ static void calculate_scaling_ratios(struct pipe_ctx 
*pipe_ctx)
 
if (stream->public.view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
pipe_ctx->scl_data.ratios.horz.value *= 2;
-   else if (surface->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM)
+   else if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
pipe_ctx->scl_data.ratios.vert.value *= 2;
 
pipe_ctx->scl_data.ratios.vert.value = div64_s64(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index cc67707..d38570e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -891,7 +891,6 @@ static void reset_hw_ctx_wrap(
}
 }
 
-
 static bool patch_address_for_sbs_tb_stereo(
struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
 {
@@ -904,11 +903,17 @@ static bool patch_address_for_sbs_tb_stereo(
 pipe_ctx->stream->public.timing.timing_3d_format ==
 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
*addr = surface->public.address.grph_stereo.left_addr;
-   surface->public.address.grph_stereo.left_addr =\
+   surface->public.address.grph_stereo.left_addr =
surface->public.address.grph_stereo.right_addr;
return true;
+   } else {
+   if (pipe_ctx->stream->public.view_format != VIEW_3D_FORMAT_NONE 
&&

[PATCH 12/81] drm/amd/display: enable diags compilation

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: Iea5cddde246293d3b22b66eb7d3956b167767b3d
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Jordan Lazare 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c|  8 ++---
 drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h| 41 --
 .../drm/amd/display/dc/dce120/dce120_resource.c| 17 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  | 22 +++-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h | 23 ++--
 drivers/gpu/drm/amd/display/dc/inc/resource.h  |  1 +
 6 files changed, 27 insertions(+), 85 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
index 4e3f4e5..f30cd4d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
@@ -781,11 +781,7 @@ struct display_clock *dce112_disp_clk_create(
return _dce->base;
 }
 
-struct display_clock *dce120_disp_clk_create(
-   struct dc_context *ctx,
-   const struct dce_disp_clk_registers *regs,
-   const struct dce_disp_clk_shift *clk_shift,
-   const struct dce_disp_clk_mask *clk_mask)
+struct display_clock *dce120_disp_clk_create(struct dc_context *ctx)
 {
struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce));
struct dm_pp_clock_levels_with_voltage clk_level_info = {0};
@@ -800,7 +796,7 @@ struct display_clock *dce120_disp_clk_create(
sizeof(dce120_max_clks_by_state));
 
dce_disp_clk_construct(
-   clk_dce, ctx, regs, clk_shift, clk_mask);
+   clk_dce, ctx, NULL, NULL, NULL);
 
clk_dce->base.funcs = _funcs;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
index 103e905..0e717e0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h
@@ -31,55 +31,30 @@
 
 #define CLK_COMMON_REG_LIST_DCE_BASE() \
.DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
-   .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL, \
-   .MASTER_COMM_DATA_REG1 = mmMASTER_COMM_DATA_REG1, \
-   .MASTER_COMM_CMD_REG = mmMASTER_COMM_CMD_REG, \
-   .MASTER_COMM_CNTL_REG = mmMASTER_COMM_CNTL_REG
+   .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
 
 #define CLK_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
 
 #define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
-   CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \
-   CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
-   CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
-
-#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
-#define CLK_DCN10_REG_LIST()\
-   SR(DPREFCLK_CNTL), \
-   SR(DENTIST_DISPCLK_CNTL), \
-   SR(MASTER_COMM_DATA_REG1), \
-   SR(MASTER_COMM_CMD_REG), \
-   SR(MASTER_COMM_CNTL_REG)
-#endif
-
-#define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
-   CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
-   CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, 
mask_sh), \
-   CLK_SF(DCCG_DFS_MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, 
mask_sh), \
-   CLK_SF(DCCG_DFS_MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
+   CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
 
 #define CLK_REG_FIELD_LIST(type) \
type DPREFCLK_SRC_SEL; \
-   type DENTIST_DPREFCLK_WDIVIDER; \
-   type MASTER_COMM_CMD_REG_BYTE0; \
-   type MASTER_COMM_INTERRUPT
+   type DENTIST_DPREFCLK_WDIVIDER;
 
 struct dce_disp_clk_shift {
-   CLK_REG_FIELD_LIST(uint8_t);
+   CLK_REG_FIELD_LIST(uint8_t)
 };
 
 struct dce_disp_clk_mask {
-   CLK_REG_FIELD_LIST(uint32_t);
+   CLK_REG_FIELD_LIST(uint32_t)
 };
 
 struct dce_disp_clk_registers {
uint32_t DPREFCLK_CNTL;
uint32_t DENTIST_DISPCLK_CNTL;
-   uint32_t MASTER_COMM_DATA_REG1;
-   uint32_t MASTER_COMM_CMD_REG;
-   uint32_t MASTER_COMM_CNTL_REG;
 };
 
 /* Array identifiers and count for the divider ranges.*/
@@ -155,11 +130,7 @@ struct display_clock *dce112_disp_clk_create(
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask);
 
-struct display_clock *dce120_disp_clk_create(
-   struct dc_context *ctx,
-   const struct dce_disp_clk_registers *regs,
-   const struct dce_disp_clk_shift *clk_shift,
-   const struct dce_disp_clk_mask *clk_mask);
+struct display_clock *dce120_disp_clk_create(struct dc_context *ctx);
 
 void dce_disp_clk_destroy(struct display_clock **disp_clk);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 

[PATCH 06/81] drm/amd/display: remove unneeded FBC hw programming code

[sunpeng.li]

From: Bhawanpreet Lakha 

- Removed uneeded FBC code.
- Initial placeholder for FBC implementation on stoney/carrizo

Change-Id: I425164e76d7be44ab397323eac99fba57d1b3826
Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Roman Li 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dce110/dce110_compressor.c  | 534 -
 .../drm/amd/display/dc/dce110/dce110_compressor.h  |   3 +
 drivers/gpu/drm/amd/display/dc/inc/compressor.h|  46 +-
 3 files changed, 137 insertions(+), 446 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 518150a..5fe8304 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -94,199 +94,8 @@ enum fbc_idle_force {
FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x2000,
 };
 
-static uint32_t lpt_size_alignment(struct dce110_compressor *cp110)
-{
-   /*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */
-   return cp110->base.raw_size * cp110->base.banks_num *
-   cp110->base.dram_channels_num;
-}
-
-static uint32_t lpt_memory_control_config(struct dce110_compressor *cp110,
-   uint32_t lpt_control)
-{
-   /*LPT MC Config */
-   if (cp110->base.options.bits.LPT_MC_CONFIG == 1) {
-   /* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS):
-* 00 - 1 CHANNEL
-* 01 - 2 CHANNELS
-* 02 - 4 OR 6 CHANNELS
-* (Only for discrete GPU, N/A for CZ)
-* 03 - 8 OR 12 CHANNELS
-* (Only for discrete GPU, N/A for CZ) */
-   switch (cp110->base.dram_channels_num) {
-   case 2:
-   set_reg_field_value(
-   lpt_control,
-   1,
-   LOW_POWER_TILING_CONTROL,
-   LOW_POWER_TILING_NUM_PIPES);
-   break;
-   case 1:
-   set_reg_field_value(
-   lpt_control,
-   0,
-   LOW_POWER_TILING_CONTROL,
-   LOW_POWER_TILING_NUM_PIPES);
-   break;
-   default:
-   dm_logger_write(
-   cp110->base.ctx->logger, LOG_WARNING,
-   "%s: Invalid LPT NUM_PIPES!!!",
-   __func__);
-   break;
-   }
-
-   /* The mapping for LPT NUM_BANKS is in
-* GRPH_CONTROL.GRPH_NUM_BANKS register field
-* Specifies the number of memory banks for tiling
-* purposes. Only applies to 2D and 3D tiling modes.
-* POSSIBLE VALUES:
-* 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK
-* 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK
-* 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK
-* 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */
-   switch (cp110->base.banks_num) {
-   case 16:
-   set_reg_field_value(
-   lpt_control,
-   3,
-   LOW_POWER_TILING_CONTROL,
-   LOW_POWER_TILING_NUM_BANKS);
-   break;
-   case 8:
-   set_reg_field_value(
-   lpt_control,
-   2,
-   LOW_POWER_TILING_CONTROL,
-   LOW_POWER_TILING_NUM_BANKS);
-   break;
-   case 4:
-   set_reg_field_value(
-   lpt_control,
-   1,
-   LOW_POWER_TILING_CONTROL,
-   LOW_POWER_TILING_NUM_BANKS);
-   break;
-   case 2:
-   set_reg_field_value(
-   lpt_control,
-   0,
-   LOW_POWER_TILING_CONTROL,
-   LOW_POWER_TILING_NUM_BANKS);
-   break;
-   default:
-   dm_logger_write(
-   cp110->base.ctx->logger, LOG_WARNING,
-   "%s: Invalid LPT NUM_BANKS!!!",
-   __func__);
-   break;
-   }
-
-   /* The mapping is in DMIF_ADDR_CALC.
-* ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for
-* 

[PATCH 51/81] drm/amd/display: Leave all validate_ctx life cycle management to DC.

[sunpeng.li]

From: Andrey Grodzovsky 

Follow DC fix.

Change-Id: I6ceb43a7703fca170bb147106ec78b74f73cadb3
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 ---
 1 file changed, 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e5a27ab..88e177e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -653,27 +653,12 @@ dm_atomic_state_alloc(struct drm_device *dev)
return >base;
 }
 
-
-void dm_atomic_state_clear(struct drm_atomic_state *state)
-{
-   struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
-
-   if (dm_state->context) {
-   dc_resource_validate_ctx_destruct(dm_state->context);
-   dm_free(dm_state->context);
-   dm_state->context = NULL;
-   }
-
-   drm_atomic_state_default_clear(state);
-}
-
 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_user_framebuffer_create,
.output_poll_changed = amdgpu_output_poll_changed,
.atomic_check = amdgpu_dm_atomic_check,
.atomic_commit = amdgpu_dm_atomic_commit,
.atomic_state_alloc = dm_atomic_state_alloc,
-   .atomic_state_clear = dm_atomic_state_clear,
 };
 
 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = 
{
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 14/81] drm/amd/display: Add DC interface for custom CSC matrix

[sunpeng.li]

From: Yue Hin Lau 

Change-Id: Idfbcebd90fe9953f7efadb388d246c59120baea8
Signed-off-by: Yue Hin Lau 
Reviewed-by: Vitaly Prosyak 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  26 +
 drivers/gpu/drm/amd/display/dc/dc.h|   3 +
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  23 
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c   | 117 -
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h   |  76 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c |   5 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h  |   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   5 +
 8 files changed, 252 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index c113c1a..a9ddd07 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -221,6 +221,29 @@ static bool set_gamut_remap(struct dc *dc, const struct 
dc_stream *stream)
return ret;
 }
 
+static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream)
+{
+   struct core_dc *core_dc = DC_TO_CORE(dc);
+   struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
+   int i = 0;
+   bool ret = false;
+   struct pipe_ctx *pipes;
+
+   for (i = 0; i < MAX_PIPES; i++) {
+   if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
+   == core_stream) {
+
+   pipes = _dc->current_context->res_ctx.pipe_ctx[i];
+   core_dc->hwss.program_csc_matrix(pipes,
+   core_stream->public.output_color_space,
+   core_stream->public.csc_color_matrix.matrix);
+   ret = true;
+   }
+   }
+
+   return ret;
+}
+
 static void set_static_screen_events(struct dc *dc,
const struct dc_stream **stream,
int num_streams,
@@ -373,6 +396,9 @@ static void allocate_dc_stream_funcs(struct core_dc 
*core_dc)
core_dc->public.stream_funcs.set_gamut_remap =
set_gamut_remap;
 
+   core_dc->public.stream_funcs.program_csc_matrix =
+   program_csc_matrix;
+
core_dc->public.stream_funcs.set_dither_option =
set_dither_option;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 18f6858..3e2ed3d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -118,6 +118,9 @@ struct dc_stream_funcs {
bool (*set_gamut_remap)(struct dc *dc,
const struct dc_stream *stream);
 
+   bool (*program_csc_matrix)(struct dc *dc,
+   const struct dc_stream *stream);
+
void (*set_static_screen_events)(struct dc *dc,
const struct dc_stream **stream,
int num_streams,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d0bddfd..f404e4e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1623,6 +1623,28 @@ static void program_gamut_remap(struct pipe_ctx 
*pipe_ctx)
pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, );
 }
 
+
+static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
+   enum dc_color_space colorspace,
+   uint16_t *matrix)
+{
+   int i;
+   struct out_csc_color_matrix tbl_entry;
+
+   if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
+   == true) {
+   enum dc_color_space color_space =
+   pipe_ctx->stream->public.output_color_space;
+
+   //uint16_t matrix[12];
+   for (i = 0; i < 12; i++)
+   tbl_entry.regval[i] = 
pipe_ctx->stream->public.csc_color_matrix.matrix[i];
+
+   tbl_entry.color_space = color_space;
+   //tbl_entry.regval = matrix;
+   
pipe_ctx->opp->funcs->opp_set_csc_adjustment(pipe_ctx->opp, _entry);
+   }
+}
 static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 {
if (pipe_ctx->surface->public.visible)
@@ -2103,6 +2125,7 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx,
 
 static const struct hw_sequencer_funcs dcn10_funcs = {
.program_gamut_remap = program_gamut_remap,
+   .program_csc_matrix = program_csc_matrix,
.init_hw = init_hw,
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
diff --git 

[PATCH 39/81] drm/amd/display: Change how we disable pipe split

[sunpeng.li]

From: Eric Yang 

Before this change, pipe split was disabled by bumping up dpp clock
bounding box for DPM level 0 and 1, this allows validation to pass
without splitting at a lower DPM level. This change reverts this
and instead lowers display clock at DPM level 0, this forces
configurations that need pipe split at DPM level 0 to go to
DPM level 1, where they can be driven without split.

Change-Id: I252b4fcf08cfb4ddf7242fab0d7d49c57b015b7d
Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 24f8c44..3118c24 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -822,8 +822,7 @@ bool dcn_validate_bandwidth(
v->phyclk_per_state[0] = v->phyclkv_min0p65;
 
if (dc->public.debug.disable_pipe_split) {
-   v->max_dppclk[1] = v->max_dppclk_vnom0p8;
-   v->max_dppclk[0] = v->max_dppclk_vnom0p8;
+   v->max_dispclk[0] = v->max_dppclk_vmin0p65;
}
 
if (v->voltage_override == dcn_bw_v_max0p9) {
-- 
2.7.4

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[PATCH 47/81] drm/amd/display: dal1.1 ipp prog update

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: Ic61bc0018ddc6fa04c065d1520ed7912d9044fd8
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 99 +++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h |  1 +
 2 files changed, 48 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
index a09226c..4910d4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
@@ -69,7 +69,7 @@ enum dcn10_input_csc_select {
INPUT_CSC_SELECT_COMA
 };
 
-static void dcn10_program_input_csc(
+static void ippn10_program_input_csc(
struct input_pixel_processor *ipp,
enum dc_color_space color_space,
enum dcn10_input_csc_select select)
@@ -159,7 +159,7 @@ static void dcn10_program_input_csc(
 }
 
 /*program de gamma RAM B*/
-static void dcn10_ipp_program_degamma_lutb_settings(
+static void ippn10_program_degamma_lutb_settings(
struct input_pixel_processor *ipp,
const struct pwl_params *params)
 {
@@ -266,7 +266,7 @@ static void dcn10_ipp_program_degamma_lutb_settings(
 }
 
 /*program de gamma RAM A*/
-static void dcn10_ipp_program_degamma_luta_settings(
+static void ippn10_program_degamma_luta_settings(
struct input_pixel_processor *ipp,
const struct pwl_params *params)
 {
@@ -372,7 +372,7 @@ static void dcn10_ipp_program_degamma_luta_settings(
CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
 }
 
-static void ipp_power_on_degamma_lut(
+static void ippn10_power_on_degamma_lut(
struct input_pixel_processor *ipp,
bool power_on)
 {
@@ -383,7 +383,7 @@ static void ipp_power_on_degamma_lut(
 
 }
 
-static void ipp_program_degamma_lut(
+static void ippn10_program_degamma_lut(
struct input_pixel_processor *ipp,
const struct pwl_result_data *rgb,
uint32_t num,
@@ -410,25 +410,19 @@ static void ipp_program_degamma_lut(
CM_DGAM_LUT_DATA, rgb[i].delta_green_reg);
REG_SET(CM_DGAM_LUT_DATA, 0,
CM_DGAM_LUT_DATA, rgb[i].delta_blue_reg);
-
}
-
 }
 
-static void dcn10_ipp_enable_cm_block(
+static void ippn10_enable_cm_block(
struct input_pixel_processor *ipp)
 {
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
 
REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
-   if (ippn10->ipp_mask->CM_BYPASS_EN)
-   REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
-   else
-   REG_UPDATE(CM_CONTROL, CM_BYPASS, 0);
+   REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
 }
 
-
-static void dcn10_ipp_full_bypass(struct input_pixel_processor *ipp)
+static void ippn10_full_bypass(struct input_pixel_processor *ipp)
 {
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
 
@@ -450,12 +444,12 @@ static void dcn10_ipp_full_bypass(struct 
input_pixel_processor *ipp)
REG_SET(CM_IGAM_CONTROL, 0, CM_IGAM_LUT_MODE, 0);
 }
 
-static void dcn10_ipp_set_degamma(
+static void ippn10_set_degamma(
struct input_pixel_processor *ipp,
enum ipp_degamma_mode mode)
 {
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
-   dcn10_ipp_enable_cm_block(ipp);
+   ippn10_enable_cm_block(ipp);
 
switch (mode) {
case IPP_DEGAMMA_MODE_BYPASS:
@@ -474,7 +468,7 @@ static void dcn10_ipp_set_degamma(
}
 }
 
-static bool dcn10_cursor_program_control(
+static bool ippn10_cursor_program_control(
struct dcn10_ipp *ippn10,
bool pixel_data_invert,
enum dc_cursor_color_format color_format)
@@ -520,7 +514,7 @@ enum cursor_lines_per_chunk {
CURSOR_LINE_PER_CHUNK_16
 };
 
-static enum cursor_pitch dcn10_get_cursor_pitch(
+static enum cursor_pitch ippn10_get_cursor_pitch(
unsigned int pitch)
 {
enum cursor_pitch hw_pitch;
@@ -544,7 +538,7 @@ static enum cursor_pitch dcn10_get_cursor_pitch(
return hw_pitch;
 }
 
-static enum cursor_lines_per_chunk dcn10_get_lines_per_chunk(
+static enum cursor_lines_per_chunk ippn10_get_lines_per_chunk(
unsigned int cur_width,
enum dc_cursor_color_format format)
 {
@@ -565,13 +559,13 @@ static enum cursor_lines_per_chunk 
dcn10_get_lines_per_chunk(
return line_per_chunk;
 }
 
-static void dcn10_cursor_set_attributes(
+static void ippn10_cursor_set_attributes(
struct input_pixel_processor *ipp,
const struct dc_cursor_attributes *attr)
 {
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
-   enum cursor_pitch hw_pitch = 

[PATCH 55/81] drm/amd/display: change non_dpm0 state's default SR latency

[sunpeng.li]

From: Charlene Liu 

Change-Id: I007042fc257012639bab29c5df6c7c347239dd3d
Signed-off-by: Charlene Liu 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index a1eabc4..0ea0dab 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -37,8 +37,8 @@
 /* Defaults from spreadsheet rev#247 */
 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
/* latencies */
-   .sr_exit_time = 17, /*us*/
-   .sr_enter_plus_exit_time = 19, /*us*/
+   .sr_exit_time = 13, /*us*/
+   .sr_enter_plus_exit_time = 15, /*us*/
.urgent_latency = 4, /*us*/
.dram_clock_change_latency = 17, /*us*/
.write_back_latency = 12, /*us*/
-- 
2.7.4

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[PATCH 36/81] drm/amd/display: update DPM bounding box

[sunpeng.li]

From: Tony Cheng 

value based on STA  target aligned to FCLK for SS corners with 10% margin

also
- group all latency together
- group all voltage state related together

Change-Id: I16619d3d919e021c5ff233b842e62c34f20e27e3
Signed-off-by: Tony Cheng 
Reviewed-by: Eric Yang 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 71 
 1 file changed, 48 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 4486121..58a4b2e 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -36,40 +36,65 @@
 
 /* Defaults from spreadsheet rev#247 */
 const struct dcn_soc_bounding_box dcn10_soc_defaults = {
-   .sr_exit_time = 17, /*us*/ /*update based on HW Request for 
118773*/
+   /* latencies */
+   .sr_exit_time = 17, /*us*/
.sr_enter_plus_exit_time = 19, /*us*/
.urgent_latency = 4, /*us*/
+   .dram_clock_change_latency = 17, /*us*/
.write_back_latency = 12, /*us*/
.percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
-   .max_request_size = 256, /*bytes*/
-   .dcfclkv_max0p9 = 600, /*MHz*/
-   .dcfclkv_nom0p8 = 600, /*MHz*/
-   .dcfclkv_mid0p72 = 300, /*MHz*/
-   .dcfclkv_min0p65 = 300, /*MHz*/
-   .max_dispclk_vmax0p9 = 1086, /*MHz*/
-   .max_dispclk_vnom0p8 = 661, /*MHz*/
-   .max_dispclk_vmid0p72 = 608, /*MHz*/
-   .max_dispclk_vmin0p65 = 608, /*MHz*/
-   .max_dppclk_vmax0p9 = 661, /*MHz*/
-   .max_dppclk_vnom0p8 = 661, /*MHz*/
-   .max_dppclk_vmid0p72 = 435, /*MHz*/
-   .max_dppclk_vmin0p65 = 435, /*MHz*/
-   .socclk = 208, /*MHz*/
+
+   /* below default clocks derived from STA target base on
+* slow-slow corner + 10% margin with voltages aligned to FCLK.
+*
+* Use these value if fused value doesn't make sense as earlier
+* part don't have correct value fused */
+   /* default DCF CLK DPM on RV*/
+   .dcfclkv_max0p9 = 655,  /* MHz, = 3600/5.5 */
+   .dcfclkv_nom0p8 = 626,  /* MHz, = 3600/5.75 */
+   .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
+   .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
+
+   /* default DISP CLK voltage state on RV */
+   .max_dispclk_vmax0p9 = 1108,/* MHz, = 3600/3.25 */
+   .max_dispclk_vnom0p8 = 1029,/* MHz, = 3600/3.5 */
+   .max_dispclk_vmid0p72 = 960,/* MHz, = 3600/3.75 */
+   .max_dispclk_vmin0p65 = 626,/* MHz, = 3600/5.75 */
+
+   /* default DPP CLK voltage state on RV */
+   .max_dppclk_vmax0p9 = 720,  /* MHz, = 3600/5 */
+   .max_dppclk_vnom0p8 = 686,  /* MHz, = 3600/5.25 */
+   .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75 */
+   .max_dppclk_vmin0p65 = 400, /* MHz, = 3600/9 */
+
+   /* default PHY CLK voltage state on RV */
+   .phyclkv_max0p9 = 900, /*MHz*/
+   .phyclkv_nom0p8 = 847, /*MHz*/
+   .phyclkv_mid0p72 = 800, /*MHz*/
+   .phyclkv_min0p65 = 600, /*MHz*/
+
+   /* BW depend on FCLK, MCLK, # of channels */
+   /* dual channel BW */
.fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
-   .fabric_and_dram_bandwidth_vnom0p8 = 34.1f, /*GB/s*/
-   .fabric_and_dram_bandwidth_vmid0p72 = 29.8f, /*GB/s*/
+   .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/
+   .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/
.fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
-   .phyclkv_max0p9 = 810, /*MHz*/
-   .phyclkv_nom0p8 = 810, /*MHz*/
-   .phyclkv_mid0p72 = 540, /*MHz*/
-   .phyclkv_min0p65 = 540, /*MHz*/
+   /* single channel BW
+   .fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
+   .fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
+   .fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
+   .fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
+   */
+
+   .number_of_channels = 2,
+
+   .socclk = 208, /*MHz*/
.downspreading = 0.5f, /*%*/
.round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
.urgent_out_of_order_return_per_channel = 256, /*bytes*/
-   .number_of_channels = 2,
.vmm_page_size = 4096, /*bytes*/
-   

[PATCH 34/81] drm/amd/display: Remove acrtc->stream

[sunpeng.li]

From: Andrey Grodzovsky 

Remove acrtc->stream and move it into dm_crtc_state.
This allows to get rid of dm_atomic_state->dm_set.
Also reuse streams created in atomic_check during
commit.

Change-Id: I8d9868695a3a530c55e7fa934f9d5ea3800dfb8b
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  33 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 411 +++--
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h|   9 +-
 drivers/gpu/drm/amd/display/dc/dc.h|   2 -
 4 files changed, 232 insertions(+), 223 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d0651b6..e5a27ab 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -100,13 +100,16 @@ static u32 dm_vblank_get_counter(struct amdgpu_device 
*adev, int crtc)
return 0;
else {
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
+   struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
+   acrtc->base.state);
 
-   if (NULL == acrtc->stream) {
+
+   if (acrtc_state->stream == NULL) {
DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc);
return 0;
}
 
-   return dc_stream_get_vblank_counter(acrtc->stream);
+   return dc_stream_get_vblank_counter(acrtc_state->stream);
}
 }
 
@@ -119,8 +122,10 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device 
*adev, int crtc,
return -EINVAL;
else {
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
+   struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
+   acrtc->base.state);
 
-   if (NULL == acrtc->stream) {
+   if (acrtc_state->stream ==  NULL) {
DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc);
return 0;
}
@@ -129,7 +134,7 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device 
*adev, int crtc,
 * TODO rework base driver to use values directly.
 * for now parse it back into reg-format
 */
-   dc_stream_get_scanoutpos(acrtc->stream,
+   dc_stream_get_scanoutpos(acrtc_state->stream,
 _blank_start,
 _blank_end,
 _position,
@@ -652,22 +657,12 @@ dm_atomic_state_alloc(struct drm_device *dev)
 void dm_atomic_state_clear(struct drm_atomic_state *state)
 {
struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
-   int i, j;
-
-   for (i = 0; i < dm_state->set_count; i++) {
-   for (j = 0; j < dm_state->set[i].surface_count; j++) {
-   dc_surface_release(dm_state->set[i].surfaces[j]);
-   dm_state->set[i].surfaces[j] = NULL;
-   }
 
-   dc_stream_release(dm_state->set[i].stream);
-   dm_state->set[i].stream = NULL;
+   if (dm_state->context) {
+   dc_resource_validate_ctx_destruct(dm_state->context);
+   dm_free(dm_state->context);
+   dm_state->context = NULL;
}
-   dm_state->set_count = 0;
-
-   dc_resource_validate_ctx_destruct(dm_state->context);
-   dm_free(dm_state->context);
-   dm_state->context = NULL;
 
drm_atomic_state_default_clear(state);
 }
@@ -676,7 +671,7 @@ static const struct drm_mode_config_funcs 
amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_user_framebuffer_create,
.output_poll_changed = amdgpu_output_poll_changed,
.atomic_check = amdgpu_dm_atomic_check,
-   .atomic_commit = drm_atomic_helper_commit,
+   .atomic_commit = amdgpu_dm_atomic_commit,
.atomic_state_alloc = dm_atomic_state_alloc,
.atomic_state_clear = dm_atomic_state_clear,
 };
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 2a5c7b1..750e095 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -87,6 +87,7 @@ static void dm_set_cursor(
struct drm_crtc *crtc = _crtc->base;
int x, y;
int xorigin = 0, yorigin = 0;
+   struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
 
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
@@ -125,13 +126,13 @@ static void dm_set_cursor(
position.y_hotspot = yorigin;
 
if 

[PATCH 31/81] drm/amd/display: Add validate_context to atomic_state

[sunpeng.li]

From: Harry Wentland 

Change-Id: I702516607ad0682339d41bba627e7f1674d4b050
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 18 ++
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h|  2 +-
 2 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index b0734bb..396fd31 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3145,7 +3145,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
struct amdgpu_device *adev = dev->dev_private;
struct dc *dc = adev->dm.dc;
bool need_to_validate = false;
-   struct validate_context *context;
struct drm_connector *connector;
struct drm_connector_state *conn_state;
/*
@@ -3380,10 +3379,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
}
}
 
-   context = dc_get_validate_context(dc, dm_state->set, 
dm_state->set_count);
-
-   if (need_to_validate == false || dm_state->set_count == 0 || context) {
+   dm_state->context = dc_get_validate_context(dc, dm_state->set, 
dm_state->set_count);
 
+   if (need_to_validate == false || dm_state->set_count == 0 || 
dm_state->context) {
ret = 0;
/*
 * For full updates case when
@@ -3399,18 +3397,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
}
 
-   if (context) {
-   dc_resource_validate_ctx_destruct(context);
-   dm_free(context);
-   }
-
-   for (i = 0; i < dm_state->set_count; i++)
-   for (j = 0; j < dm_state->set[i].surface_count; j++)
-   dc_surface_release(dm_state->set[i].surfaces[j]);
-
-   for (i = 0; i < new_stream_count; i++)
-   dc_stream_release(new_streams[i]);
-
if (ret != 0) {
if (ret == -EDEADLK)
DRM_DEBUG_KMS("Atomic check stopped due to to 
deadlock.\n");
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
index a7adf8d..1e444cb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
@@ -55,7 +55,7 @@ struct dm_atomic_state {
 
struct dc_validation_set set[MAX_STREAMS];
int set_count;
-
+   struct validate_context *context;
 };
 
 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
-- 
2.7.4

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[PATCH 24/81] drm/amd/display: Remove SMU_INTERRUPT_CONTROL

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: Iff671ee2c27f85732763cb1293f24949883d67e3
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index 8b04996..fd6ba7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -50,7 +50,6 @@
SR(DMCU_IRAM_RD_CTRL), \
SR(DMCU_IRAM_RD_DATA), \
SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
-   SR(SMU_INTERRUPT_CONTROL), \
SRI(DIG_BE_CNTL, DIG, id), \
SRI(DIG_BE_EN_CNTL, DIG, id), \
SRI(DP_CONFIG, DP, id), \
@@ -137,7 +136,6 @@ struct dce110_link_enc_registers {
uint32_t DMCU_IRAM_RD_CTRL;
uint32_t DMCU_IRAM_RD_DATA;
uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
-   uint32_t SMU_INTERRUPT_CONTROL;
 
/* Common DP registers */
uint32_t DIG_BE_CNTL;
-- 
2.7.4

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[PATCH 60/81] drm/amd/display: change order of HUBP and MPC disable according to HW guide

[sunpeng.li]

From: Tony Cheng 

blank hubp first before disconnect MPC

Change-Id: Ibd593dead3fda16e47a79b3c20403b6904aa3981
Signed-off-by: Tony Cheng 
Reviewed-by: Eric Yang 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 +++---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c  |  4 +++-
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ac0d62c..0e90e6c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -477,9 +477,14 @@ static void reset_front_end(
if (mpcc->opp_id == 0xf)
return;
 
-   mi->funcs->dcc_control(mi, false, false);
tg->funcs->lock(tg);
 
+   mi->funcs->dcc_control(mi, false, false);
+   mi->funcs->set_blank(mi, true);
+   REG_WAIT(DCHUBP_CNTL[fe_idx],
+   HUBP_NO_OUTSTANDING_REQ, 1,
+   1, 200);
+
mpcc_cfg.opp_id = 0xf;
mpcc_cfg.top_dpp_id = 0xf;
mpcc_cfg.bot_mpcc_id = 0xf;
@@ -491,8 +496,7 @@ static void reset_front_end(
REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], 
VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 2, 20);
 
mpcc->funcs->wait_for_idle(mpcc);
-   mi->funcs->set_blank(mi, true);
-   REG_WAIT(DCHUBP_CNTL[fe_idx], HUBP_NO_OUTSTANDING_REQ, 1, 2, 
20);
+
REG_UPDATE(HUBP_CLK_CNTL[fe_idx], HUBP_CLOCK_ENABLE, 0);
REG_UPDATE(DPP_CONTROL[fe_idx], DPP_CLOCK_ENABLE, 0);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 1c9d5e9..9875d81 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -117,7 +117,9 @@ static void dcn10_mpcc_wait_idle(struct mpcc *mpcc)
 {
struct dcn10_mpcc *mpcc10 = TO_DCN10_MPCC(mpcc);
 
-   REG_WAIT(MPCC_STATUS, MPCC_BUSY, 0, 1000, 1000);
+   REG_WAIT(MPCC_STATUS,
+   MPCC_BUSY, 0,
+   1000, 1000);
 }
 
 
-- 
2.7.4

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[PATCH 72/81] drm/amd/display: Move view port registers and programming to memory input.

[sunpeng.li]

From: Vitaly Prosyak 

Change-Id: I286753b972379133fa2da57b53a39001c9cf5aa5
Signed-off-by: Vitaly Prosyak 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   | 36 -
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   | 36 -
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  2 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 37 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 36 +
 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h  |  4 +++
 6 files changed, 78 insertions(+), 73 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 85d3ca3..fff81a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -452,37 +452,6 @@ static void dpp_set_scl_filter(
}
 }
 
-static void dpp_set_viewport(
-   struct dcn10_dpp *xfm,
-   const struct rect *viewport,
-   const struct rect *viewport_c)
-{
-   REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
-   PRI_VIEWPORT_WIDTH, viewport->width,
-   PRI_VIEWPORT_HEIGHT, viewport->height);
-
-   REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
-   PRI_VIEWPORT_X_START, viewport->x,
-   PRI_VIEWPORT_Y_START, viewport->y);
-
-   /*for stereo*/
-   REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
-   SEC_VIEWPORT_WIDTH, viewport->width,
-   SEC_VIEWPORT_HEIGHT, viewport->height);
-
-   REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
-   SEC_VIEWPORT_X_START, viewport->x,
-   SEC_VIEWPORT_Y_START, viewport->y);
-
-   /* DC supports NV12 only at the moment */
-   REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
-   PRI_VIEWPORT_WIDTH_C, viewport_c->width,
-   PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
-
-   REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
-   PRI_VIEWPORT_X_START_C, viewport_c->x,
-   PRI_VIEWPORT_Y_START_C, viewport_c->y);
-}
 
 static int get_lb_depth_bpc(enum lb_pixel_depth depth)
 {
@@ -616,8 +585,6 @@ void dpp_set_scaler_auto_scale(
 
REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
 
-   dpp_set_viewport(xfm, _data->viewport, _data->viewport_c);
-
if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
return;
 
@@ -762,9 +729,6 @@ static void dpp_set_scaler_manual_scale(
/* SCL mode */
REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
 
-   /* Viewport */
-   dpp_set_viewport(xfm, _data->viewport, _data->viewport_c);
-
if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
return;
/* LB */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 9936435..c1124e9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -59,12 +59,6 @@
SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
SRI(DSCL_2TAP_CONTROL, DSCL, id), \
-   SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
-   SRI(DCSURF_PRI_VIEWPORT_START, HUBP, id), \
-   SRI(DCSURF_SEC_VIEWPORT_DIMENSION, HUBP, id), \
-   SRI(DCSURF_SEC_VIEWPORT_START, HUBP, id), \
-   SRI(DCSURF_PRI_VIEWPORT_DIMENSION_C, HUBP, id), \
-   SRI(DCSURF_PRI_VIEWPORT_START_C, HUBP, id), \
SRI(MPC_SIZE, DSCL, id), \
SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
@@ -144,18 +138,6 @@
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
-   TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, 
mask_sh),\
-   TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, 
mask_sh),\
-   TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
-   TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
-   TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, 
mask_sh),\
-   TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, 
mask_sh),\
-   TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
-   TF_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
-   TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, 
mask_sh),\
-   TF_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, 
mask_sh),\
-   

[PATCH 00/81] DC Linux Patches Jul 25, 2017

[sunpeng.li]

From: "Leo (Sunpeng) Li" 

* Start of cleanup for midlayer abstractions
* Laying down foundations for FBC
* Future-proofing of DCN functions
* Pipe splitting features for Raven
* General bug fixes for Raven

Amy Zhang (1):
  drm/amd/display: Re-enable Vsync Interrupts for Gradual Refresh Ramp

Andrey Grodzovsky (17):
  drm/amd/display: Create dm_crtc_state stubs.
  drm/amd/display: Move dm_plane_state to DAL header.
  drm/amd/display: Remove unblanaced drm_vblank_put.
  drm/amd/display: Update atomic state hooks.
  drm/amd/display: Remove acrtc->stream
  drm/amd/display: Undo dc_update_surfaces_and_stream change.
  drm/amd/display: Refactor dc_commit_streams
  drm/amd/display: Leave all validate_ctx life cycle management to DC.
  drm/amd/display: Clean dm_plane_state hooks.
  drm/amd/display: Attach surface to dm_plane_state.
  drm/amd/display: Introduce refcount for dc_validate_context
  drm/amd/display: Skip DC validation for flips and cursor.
  drm/amd/display: Release dm_state->context when state is cleared.
  drm/amd/display: dc_validate_ctx refocunt fixes.
  drm/amd/display: Preserve refcount for S3 case.
  drm/amd/display: Release cached atomic state in S3.
  drm/amd/display: Fix S3 gamma corruption.

Anthony Koo (3):
  drm/amd/display: add hyst frames for fixed refresh
  drm/amd/display: Fix MPO visual confirm
  drm/amd/display: Add regkey for DRR control for internal panel

Bhawanpreet Lakha (3):
  drm/amd/display: remove unneeded FBC hw programming code
  drm/amd/display: Connect DC resource to FBC compressor
  drm/amd/display: Set static screen register for stoney/carrizo

Charlene Liu (5):
  drm/amd/display: Enabling VSR on 4K display causes black screen
  drm/amd/display: change non_dpm0 state's default SR latency
  drm/amd/display: fix 4k@30 with 10bit deep color and avi for BT2020
  drm/amd/display: fix DVI connected to HDMI connector max tmds clock
  drm/amd/display: fix aviInfoFrame bar Info and add set_avMute

Corbin McElhanney (3):
  drm/amd/display: Add clock info struct
  drm/amd/display: Add extra mode and clock info to DTN logs
  drm/amd/display: Fix context copy memory leak

Ding Wang (1):
  drm/amd/display: link training fallback actions

Dmytro Laktyushkin (17):
  drm/amd/display: fix dcn pipe reset sequence
  drm/amd/display: enable diags compilation
  drm/amd/display: Change max OPP
  drm/amd/display: Rename DCN TG specific function prefixes to tg
  drm/amd/display: Rename DCN mem input specific function prefixes to
min.
  drm/amd/display: Rename DCN opp specific function prefixes to oppn10
  drm/amd/display: Enable ipp compilation
  drm/amd/display: Remove SMU_INTERRUPT_CONTROL
  drm/amd/display: refactor dcn10 hw_sequencer to new reg access style
  drm/amd/display: get dal1.1 to run
  drm/amd/display: minor dcn10_hwseq clean up/refactor
  drm/amd/display: dal1.1 opp prog update
  drm/amd/display: dal1.1 ipp prog update
  drm/amd/display: dal1.1 xfm prog update
  drm/amd/display: dal1.1 hwseq prog update
  drm/amd/display: add line number to reg_wait timeout print
  drm/amd/display: hwseq init sequence update

Eric Yang (7):
  drm/amd/display: move number of memory channel calc out of pplib call
  drm/amd/display: block modes that require read bw greater than 30%
  drm/amd/display: Change how we disable pipe split
  drm/amd/display: call pplib to update clocks
  drm/amd/display: fix mpo exit hang
  drm/amd/display: properly turn off unused mpc before front end
programming
  drm/amd/display: powergate fe of reused pipes to reset ttu

Harry Wentland (8):
  drm/amd/display: Make mode_config_funcs const
  drm/amd/display: Create dm_atomic_state
  drm/amd/display: Hook dm private state into atomic_check
  drm/amd/display: Add correct retain/release
  drm/amd/display: Commit validation set from state
  drm/amd/display: Add validate_context to atomic_state
  drm/amd/display: Use validate_context from atomic_check in commit
  drm/amd/display: Get freesync properties

John Wu (1):
  drm/amd/display: Fix eDP power isn't off when lid close

Ken Chalmers (1):
  drm/amd/display: RV stereo support

Leo (Sunpeng) Li (3):
  drm/amd/display: Move drm_get_vblank from legacy code
  drm/amd/display: Flattening to dc_transfer_func
  drm/amd/display: Do not release state objects on atomic check fail

Tony Cheng (5):
  drm/amd/display: update DPM bounding box
  drm/amd/display: change order of HUBP and MPC disable according to HW
guide
  drm/amd/display: avoid disabling opp clk before hubp is blanked.
  drm/amd/display: ensure OTG is locked before proceeding
  drm/amd/display: revert order change of HUBP and MPC disable

Vikrant Mhaske (1):
  drm/amd/display: Coding for backcompatible tiling support for Gfx7

Vitaly Prosyak (3):
  drm/amd/display: Fix for hdmi frame pack stereo
  drm/amd/display: Rename trasnform to dpp for dcn's
  drm/amd/display:  Move view port registers and programming to memory
input.

Yongqiang Sun (1):
  drm/amd/display: set drr during 

[PATCH 15/81] drm/amd/display: Re-enable Vsync Interrupts for Gradual Refresh Ramp

[sunpeng.li]

From: Amy Zhang 

- Make sure Vsync interrupts are disabled in static screen case
  and enabled when not to save power
- Create no_static_for_external_dp debug option

Change-Id: I29c90dcd6ea43e15e52a4dacf1e5ce91d32ac9a1
Signed-off-by: Amy Zhang 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h|  1 +
 .../drm/amd/display/modules/freesync/freesync.c| 38 --
 .../gpu/drm/amd/display/modules/inc/mod_freesync.h |  5 +++
 3 files changed, 34 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 3e2ed3d..93aff82 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -188,6 +188,7 @@ struct dc_debug {
bool disable_dmcu;
bool disable_psr;
bool force_abm_enable;
+   bool no_static_for_external_dp;
 };
 
 struct dc {
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index c7da90f..4df79f7 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -440,14 +440,11 @@ static void calc_freesync_range(struct core_freesync 
*core_freesync,
}
 
/* Determine whether BTR can be supported */
-   //if (max_frame_duration_in_ns >=
-   //  2 * min_frame_duration_in_ns)
-   //  core_freesync->map[index].caps->btr_supported = true;
-   //else
-   //  core_freesync->map[index].caps->btr_supported = false;
-
-   /* Temp, keep btr disabled */
-   core_freesync->map[index].caps->btr_supported = false;
+   if (max_frame_duration_in_ns >=
+   2 * min_frame_duration_in_ns)
+   core_freesync->map[index].caps->btr_supported = true;
+   else
+   core_freesync->map[index].caps->btr_supported = false;
 
/* Cache the time variables */
state->time.max_render_time_in_us =
@@ -882,8 +879,10 @@ void mod_freesync_update_state(struct mod_freesync 
*mod_freesync,
 * panels. Also change core variables only if there
 * is a change.
 */
-   if (dc_is_embedded_signal(
-   streams[stream_index]->sink->sink_signal) &&
+   if ((dc_is_embedded_signal(
+   streams[stream_index]->sink->sink_signal) ||
+   core_freesync->map[map_index].caps->
+   no_static_for_external_dp == false) &&
state->static_screen !=
freesync_params->enable) {
 
@@ -1035,6 +1034,25 @@ bool mod_freesync_get_user_enable(struct mod_freesync 
*mod_freesync,
return true;
 }
 
+bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync,
+   const struct dc_stream *stream,
+   bool *is_ramp_active)
+{
+   unsigned int index = 0;
+   struct core_freesync *core_freesync = NULL;
+
+   if (mod_freesync == NULL)
+   return false;
+
+   core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
+   index = map_index_from_stream(core_freesync, stream);
+
+   *is_ramp_active =
+   core_freesync->map[index].state.static_ramp.ramp_is_active;
+
+   return true;
+}
+
 bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
const struct dc_stream *streams,
unsigned int min_refresh,
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h 
b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
index f7f5a2c..eae1b34 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h
@@ -88,6 +88,7 @@ struct mod_freesync_caps {
unsigned int max_refresh_in_micro_hz;
 
bool btr_supported;
+   bool no_static_for_external_dp;
 };
 
 struct mod_freesync_params {
@@ -129,6 +130,10 @@ bool mod_freesync_get_user_enable(struct mod_freesync 
*mod_freesync,
const struct dc_stream *stream,
struct mod_freesync_user_enable *user_enable);
 
+bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync,
+   const struct dc_stream *stream,
+   bool *is_ramp_active);
+
 bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
const struct dc_stream *streams,
unsigned int min_refresh,
-- 
2.7.4

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[PATCH 27/81] drm/amd/display: Create dm_atomic_state

[sunpeng.li]

From: Harry Wentland 

We really want to use the new private_atomic_state but can't right now
as we have to maintain some backward compatibility to older kernels. For
now let's follow Intel's approach and extend the drm_atomic_state.

Change-Id: I848bda7aa11d7731684e90e0d9e88191e8db8fb2
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 37 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h|  8 +++--
 2 files changed, 41 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e856f62..1b69848 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -634,11 +634,46 @@ const struct amdgpu_ip_block_version dm_ip_block =
.funcs = _dm_funcs,
 };
 
+
+struct drm_atomic_state *
+dm_atomic_state_alloc(struct drm_device *dev)
+{
+   struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
+
+   if (!state || drm_atomic_state_init(dev, >base) < 0) {
+   kfree(state);
+   return NULL;
+   }
+
+   return >base;
+}
+
+void dm_atomic_state_clear(struct drm_atomic_state *s)
+{
+   struct dm_atomic_state *state = to_dm_atomic_state(s);
+   drm_atomic_state_default_clear(>base);
+}
+
+
+static void dm_atomic_state_free(struct drm_atomic_state *state)
+{
+   struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
+
+   drm_atomic_state_default_release(state);
+
+   kfree(dm_state);
+}
+
+
+
 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_user_framebuffer_create,
.output_poll_changed = amdgpu_output_poll_changed,
.atomic_check = amdgpu_dm_atomic_check,
-   .atomic_commit = drm_atomic_helper_commit
+   .atomic_commit = drm_atomic_helper_commit,
+   .atomic_state_alloc = dm_atomic_state_alloc,
+   .atomic_state_clear = dm_atomic_state_clear,
+   .atomic_state_free = dm_atomic_state_free,
 };
 
 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = 
{
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
index f5f4936..9ba7fdd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
@@ -27,6 +27,7 @@
 #define __AMDGPU_DM_TYPES_H__
 
 #include 
+#include 
 
 struct amdgpu_framebuffer;
 struct amdgpu_display_manager;
@@ -48,11 +49,12 @@ struct dm_crtc_state {
 
 #define to_dm_crtc_state(x)container_of(x, struct dm_crtc_state, base)
 
-struct dm_plane_state {
-   struct drm_plane_state base;
-   struct dc_surface *dc_surface;
+struct dm_atomic_state {
+   struct drm_atomic_state base;
 };
 
+#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
+
 
 /*TODO Jodan Hersen use the one in amdgpu_dm*/
 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
-- 
2.7.4

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[PATCH 49/81] drm/amd/display: dal1.1 hwseq prog update

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: I201b96af4efc95077d3cc54c6fbe810b337cf4a1
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 223bb79..4c39bf0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -64,17 +64,13 @@ static void enable_dppclk(
plane_id,
dppclk_div);
 
-   if (dppclk_div) {
-   /* 1/2 DISPCLK*/
+   if (hws->shifts->DPPCLK_RATE_CONTROL)
REG_UPDATE_2(DPP_CONTROL[plane_id],
-   DPPCLK_RATE_CONTROL, 1,
+   DPPCLK_RATE_CONTROL, dppclk_div,
DPP_CLOCK_ENABLE, 1);
-   } else {
-   /* DISPCLK */
-   REG_UPDATE_2(DPP_CONTROL[plane_id],
-   DPPCLK_RATE_CONTROL, 0,
+   else
+   REG_UPDATE(DPP_CONTROL[plane_id],
DPP_CLOCK_ENABLE, 1);
-   }
 }
 
 static void enable_power_gating_plane(
-- 
2.7.4

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[PATCH 10/81] drm/amd/display: Connect DC resource to FBC compressor

[sunpeng.li]

From: Bhawanpreet Lakha 

- Connected DC resource to FBC compressor,
- Initial Implementation of FBC for Stoney/Carrizo
- Code is currently guarded with "ENABLE_FBC" compile time flag

Change-Id: Ie5977bb58febdca4cb25206846d7e81ae528029c
Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Roman Li 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 19 ++
 .../drm/amd/display/dc/dce110/dce110_compressor.c  | 78 +++---
 .../drm/amd/display/dc/dce110/dce110_compressor.h  |  2 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 15 +
 .../drm/amd/display/dc/dce110/dce110_resource.c| 10 +++
 drivers/gpu/drm/amd/display/dc/inc/compressor.h|  6 +-
 drivers/gpu/drm/amd/display/dc/inc/core_dc.h   |  6 ++
 7 files changed, 94 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2f481ef..51e4cb3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -843,6 +843,11 @@ bool dc_enable_stereo(
int i, j;
struct pipe_ctx *pipe;
struct core_dc *core_dc = DC_TO_CORE(dc);
+
+#ifdef ENABLE_FBC
+   struct compressor *fbc_compressor = core_dc->fbc_compressor;
+#endif
+
for (i = 0; i < MAX_PIPES; i++) {
if (context != NULL)
pipe = >res_ctx.pipe_ctx[i];
@@ -854,6 +859,14 @@ bool dc_enable_stereo(
core_dc->hwss.setup_stereo(pipe, core_dc);
}
}
+
+#ifdef ENABLE_FBC
+   if (fbc_compressor != NULL &&
+   fbc_compressor->funcs->is_fbc_enabled_in_hw(core_dc->fbc_compressor,
+   >tg->inst))
+   fbc_compressor->funcs->disable_fbc(fbc_compressor);
+
+#endif
return ret;
 }
 
@@ -1232,6 +1245,12 @@ void dc_update_surfaces_and_stream(struct dc *dc,
if (!stream_status)
return; /* Cannot commit surface to stream that is not 
committed */
 
+#ifdef ENABLE_FBC
+   if (srf_updates->flip_addr) {
+   if (srf_updates->flip_addr->address.grph.addr.low_part == 0)
+   ASSERT(0);
+   }
+#endif
context = core_dc->current_context;
 
/* update current stream with the new updates */
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
index 5fe8304..1e59f4e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
@@ -175,7 +175,6 @@ void dce110_compressor_power_up_fbc(struct compressor 
*compressor)
 
 void dce110_compressor_enable_fbc(
struct compressor *compressor,
-   uint32_t paths_num,
struct compr_addr_and_pitch_params *params)
 {
struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor);
@@ -366,43 +365,6 @@ void dce110_compressor_set_fbc_invalidation_triggers(
dm_write_reg(compressor->ctx, addr, value);
 }
 
-bool dce110_compressor_construct(struct dce110_compressor *compressor,
-struct dc_context *ctx)
-{
-
-   compressor->base.options.bits.FBC_SUPPORT = true;
-
-/* for dce 11 always use one dram channel for lpt */
-   compressor->base.lpt_channels_num = 1;
-   compressor->base.options.bits.DUMMY_BACKEND = false;
-
-   /*
-* check if this system has more than 1 dram channel; if only 1 then lpt
-* should not be supported
-*/
-
-
-   compressor->base.options.bits.CLK_GATING_DISABLED = false;
-
-   compressor->base.ctx = ctx;
-   compressor->base.embedded_panel_h_size = 0;
-   compressor->base.embedded_panel_v_size = 0;
-   compressor->base.memory_bus_width = ctx->asic_id.vram_width;
-   compressor->base.allocated_size = 0;
-   compressor->base.preferred_requested_size = 0;
-   compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
-   compressor->base.options.raw = 0;
-   compressor->base.banks_num = 0;
-   compressor->base.raw_size = 0;
-   compressor->base.channel_interleave_size = 0;
-   compressor->base.dram_channels_num = 0;
-   compressor->base.lpt_channels_num = 0;
-   compressor->base.attached_inst = 0;
-   compressor->base.is_enabled = false;
-
-   return true;
-}
-
 struct compressor *dce110_compressor_create(struct dc_context *ctx)
 {
struct dce110_compressor *cp110 =
@@ -503,3 +465,43 @@ static const struct compressor_funcs 
dce110_compressor_funcs = {
 };
 
 
+bool dce110_compressor_construct(struct dce110_compressor *compressor,
+   struct dc_context *ctx)
+{
+
+   compressor->base.options.bits.FBC_SUPPORT = true;
+
+   /* for dce 11 always use one dram channel for lpt */
+   

[PATCH 25/81] drm/amd/display: Remove unblanaced drm_vblank_put.

[sunpeng.li]

From: Andrey Grodzovsky 

Since drm_vblank_get moved from this function to just
before do_flip no need to release vblank here in case of error.

Change-Id: Iedc900618da2a0c940f49fe63299c6ae3eec260d
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index fb5afba..ed48c5e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1016,8 +1016,7 @@ static int amdgpu_atomic_helper_page_flip(struct drm_crtc 
*crtc,
if (ret == -EDEADLK)
goto backoff;
 
-   if (ret)
-   drm_crtc_vblank_put(crtc);
+   drm_atomic_state_put(state);
 
return ret;
 backoff:
-- 
2.7.4

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[PATCH 05/81] drm/amd/display: Add clock info struct

[sunpeng.li]

From: Corbin McElhanney 

Change-Id: I2cca4d886b0993fc0512312c35c42d08c3ad34be
Signed-off-by: Corbin McElhanney 
Reviewed-by: Logatharshan Thothiralingam 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dm_services_types.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h 
b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
index b283045..4c04ec5 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
@@ -271,4 +271,10 @@ struct dm_pp_static_clock_info {
enum dm_pp_clocks_state max_clocks_state;
 };
 
+struct dtn_min_clk_info {
+   uint32_t disp_clk_khz;
+   uint32_t min_engine_clock_khz;
+   uint32_t min_memory_clock_khz;
+};
+
 #endif
-- 
2.7.4

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[PATCH 26/81] drm/amd/display: set drr during program timing.

[sunpeng.li]

From: Yongqiang Sun 

Change-Id: Id3b33d30fac6badc1d5b8bb0dbebfb620e7e06cd
Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../amd/display/dc/dce110/dce110_timing_generator.c | 21 +
 .../amd/display/dc/dce120/dce120_timing_generator.c | 19 ---
 .../amd/display/dc/dcn10/dcn10_timing_generator.c   |  8 
 3 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index ec59927..7f93d6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -629,6 +629,27 @@ void dce110_timing_generator_program_blanking(
CRTC_V_TOTAL);
dm_write_reg(ctx, addr, value);
 
+   /* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and
+* V_TOTAL_MIN are equal to V_TOTAL.
+*/
+   addr = CRTC_REG(mmCRTC_V_TOTAL_MAX);
+   value = dm_read_reg(ctx, addr);
+   set_reg_field_value(
+   value,
+   timing->v_total - 1,
+   CRTC_V_TOTAL_MAX,
+   CRTC_V_TOTAL_MAX);
+   dm_write_reg(ctx, addr, value);
+
+   addr = CRTC_REG(mmCRTC_V_TOTAL_MIN);
+   value = dm_read_reg(ctx, addr);
+   set_reg_field_value(
+   value,
+   timing->v_total - 1,
+   CRTC_V_TOTAL_MIN,
+   CRTC_V_TOTAL_MIN);
+   dm_write_reg(ctx, addr, value);
+
addr = CRTC_REG(mmCRTC_H_BLANK_START_END);
value = dm_read_reg(ctx, addr);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index 03b21e9..58a070d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -441,15 +441,28 @@ void dce120_timing_generator_program_blanking(
struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
 
CRTC_REG_UPDATE(
-   CRTC0_CRTC_H_TOTAL,
-   CRTC_H_TOTAL,
-   timing->h_total - 1);
+   CRTC0_CRTC_H_TOTAL,
+   CRTC_H_TOTAL,
+   timing->h_total - 1);
 
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL,
CRTC_V_TOTAL,
timing->v_total - 1);
 
+   /* In case of V_TOTAL_CONTROL is on, make sure V_TOTAL_MAX and
+* V_TOTAL_MIN are equal to V_TOTAL.
+*/
+   CRTC_REG_UPDATE(
+   CRTC0_CRTC_V_TOTAL_MAX,
+   CRTC_V_TOTAL_MAX,
+   timing->v_total - 1);
+
+   CRTC_REG_UPDATE(
+   CRTC0_CRTC_V_TOTAL_MIN,
+   CRTC_V_TOTAL_MIN,
+   timing->v_total - 1);
+
tmp1 = timing->h_total -
(h_sync_start + timing->h_border_left);
tmp2 = tmp1 + timing->h_addressable +
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 5927478..e1899f5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -177,6 +177,14 @@ static void tgn10_program_timing(
REG_SET(OTG_V_TOTAL, 0,
OTG_V_TOTAL, v_total);
 
+   /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
+* OTG_V_TOTAL_MIN are equal to V_TOTAL.
+*/
+   REG_SET(OTG_V_TOTAL_MAX, 0,
+   OTG_V_TOTAL_MAX, v_total);
+   REG_SET(OTG_V_TOTAL_MIN, 0,
+   OTG_V_TOTAL_MIN, v_total);
+
/* v_sync_start = 0, v_sync_end = v_sync_width */
v_sync_end = patched_crtc_timing.v_sync_width * interlace_factor;
 
-- 
2.7.4

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[PATCH 17/81] drm/amd/display: Coding for backcompatible tiling support for Gfx7

[sunpeng.li]

From: Vikrant Mhaske 

after the diags build error correction.

Change-Id: If851c70ecfad2ebc3dfaea6c0e772406d547d584
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 1615 +---
 1 file changed, 1060 insertions(+), 555 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
index 9e2f1bb..b7ecfad 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -1,4 +1,5 @@
-/* Copyright 2012-15 Advanced Micro Devices, Inc.
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -21,573 +22,1077 @@
  * Authors: AMD
  *
  */
+#include "dm_services.h"
+#include "dce_calcs.h"
+#include "dcn10_mem_input.h"
+#include "reg_helper.h"
+#include "basics/conversion.h"
 
-#ifndef __DC_MEM_INPUT_DCN10_H__
-#define __DC_MEM_INPUT_DCN10_H__
-
-#include "mem_input.h"
-
-#define TO_DCN10_MEM_INPUT(mi)\
-   container_of(mi, struct dcn10_mem_input, base)
-
-
-#define MI_DCN10_REG_LIST(id)\
-   SRI(DCHUBP_CNTL, HUBP, id),\
-   SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
-   SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
-   SRI(DCSURF_TILING_CONFIG, HUBP, id),\
-   SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
-   SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_SURFACE_ADDRESS, HUBPREQ, id),\
-   SRI(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
-   SRI(DCSURF_SECONDARY_SURFACE_ADDRESS, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
-   SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, HUBPREQ, id),\
-   SRI(DCSURF_SECONDARY_META_SURFACE_ADDRESS, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
-   SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
-   SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
-   SRI(HUBPRET_CONTROL, HUBPRET, id),\
-   SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
-   SRI(DCHUBP_REQ_SIZE_CONFIG, HUBP, id),\
-   SRI(DCHUBP_REQ_SIZE_CONFIG_C, HUBP, id),\
-   SRI(BLANK_OFFSET_0, HUBPREQ, id),\
-   SRI(BLANK_OFFSET_1, HUBPREQ, id),\
-   SRI(DST_DIMENSIONS, HUBPREQ, id),\
-   SRI(DST_AFTER_SCALER, HUBPREQ, id),\
-   SRI(PREFETCH_SETTINS, HUBPREQ, id),\
-   SRI(VBLANK_PARAMETERS_0, HUBPREQ, id),\
-   SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
-   SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
-   SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
-   SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
-   SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
-   SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
-   SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
-   SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
-   SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
-   SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
-   SRI(DCN_GLOBAL_TTU_CNTL, HUBPREQ, id),\
-   SRI(DCN_SURF0_TTU_CNTL0, HUBPREQ, id),\
-   SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
-   SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
-   SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, HUBPREQ, id),\
-   SRI(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, HUBPREQ, id),\
-   SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, 

[PATCH 08/81] drm/amd/display: Move dm_plane_state to DAL header.

[sunpeng.li]

From: Andrey Grodzovsky 

Change-Id: I3910605f43577f1dec99dbc50ea1ed82baf1db34
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
index 1091725..f5f4936 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
@@ -36,6 +36,11 @@ struct dc_surface;
 struct  dc_stream;
 
 
+struct dm_plane_state {
+   struct drm_plane_state base;
+   struct dc_surface *dc_surface;
+};
+
 struct dm_crtc_state {
struct drm_crtc_state base;
struct dc_stream *dc_stream;
-- 
2.7.4

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[PATCH 19/81] drm/amd/display: Set static screen register for stoney/carrizo

[sunpeng.li]

From: Bhawanpreet Lakha 

-Set CRTC_STATIC_SCREEN_EVENT for stoney/carrizo for FBC implementation
-Code is currently guarded with "ENABLE_FBC" compile time flag

Change-Id: Ia471b516b6b9fd399539be3b349c1970f19fa234
Signed-off-by: Bhawanpreet Lakha 
Reviewed-by: Roman Li 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 72d5f75..8778af7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1395,6 +1395,10 @@ static void set_static_screen_control(struct pipe_ctx 
**pipe_ctx,
if (events->cursor_update)
value |= 0x2;
 
+#ifdef ENABLE_FBC
+   value |= 0x84;
+#endif
+
for (i = 0; i < num_pipes; i++)
pipe_ctx[i]->tg->funcs->
set_static_screen_control(pipe_ctx[i]->tg, value);
-- 
2.7.4

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[PATCH 01/81] drm/amd/display: RV stereo support

[sunpeng.li]

From: Ken Chalmers 

Fix moving directly from frame packed to frame sequential mode: disable
OTG_3D_STRUCTURE_EN if the stereo mode is not frame packed.

Change-Id: I67d1a9b112f438b881104f4fe3ab1cdd41fedbdc
Signed-off-by: Ken Chalmers 
Reviewed-by: Vitaly Prosyak 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 83efbec..58fb29f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -1082,11 +1082,11 @@ static void dcn10_enable_stereo(struct timing_generator 
*tg,
REG_UPDATE(OTG_STEREO_CONTROL,
OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
 
-   if (flags->PROGRAM_STEREO && flags->FRAME_PACKED)
+   if (flags->PROGRAM_STEREO)
REG_UPDATE_3(OTG_3D_STRUCTURE_CONTROL,
-   OTG_3D_STRUCTURE_EN, 1,
-   OTG_3D_STRUCTURE_V_UPDATE_MODE, 1,
-   OTG_3D_STRUCTURE_STEREO_SEL_OVR, 1);
+   OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
+   OTG_3D_STRUCTURE_V_UPDATE_MODE, 
flags->FRAME_PACKED,
+   OTG_3D_STRUCTURE_STEREO_SEL_OVR, 
flags->FRAME_PACKED);
 
}
 
-- 
2.7.4

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[PATCH 04/81] drm/amd/display: Create dm_crtc_state stubs.

[sunpeng.li]

From: Andrey Grodzovsky 

These stubs are initial only since we need to flatten
DC objects (steran at least) to implement deep copy.

Change-Id: I6e16cddf0b937b5f078443924dab286481db2f13
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 74 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h| 10 +++
 2 files changed, 81 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index fd5d643..10ffe7f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1034,16 +1034,84 @@ static int amdgpu_atomic_helper_page_flip(struct 
drm_crtc *crtc,
goto retry;
 }
 
+static void dm_crtc_destroy_state(struct drm_crtc *crtc,
+  struct drm_crtc_state *state)
+{
+   struct dm_crtc_state *cur = to_dm_crtc_state(state);
+
+   if (cur->dc_stream) {
+   /* TODO Destroy dc_stream objects are stream object is 
flattened */
+   dm_free(cur->dc_stream);
+   } else
+   WARN_ON(1);
+
+   __drm_atomic_helper_crtc_destroy_state(state);
+
+
+   kfree(state);
+}
+
+static void dm_crtc_reset_state(struct drm_crtc *crtc)
+{
+   struct dm_crtc_state *state;
+
+   if (crtc->state)
+   dm_crtc_destroy_state(crtc, crtc->state);
+
+   state = kzalloc(sizeof(*state), GFP_KERNEL);
+   if (WARN_ON(!state))
+   return;
+
+
+   crtc->state = >base;
+   crtc->state->crtc = crtc;
+
+   state->dc_stream = dm_alloc(sizeof(*state->dc_stream));
+   WARN_ON(!state->dc_stream);
+}
+
+static struct drm_crtc_state *
+dm_crtc_duplicate_state(struct drm_crtc *crtc)
+{
+   struct dm_crtc_state *state, *cur;
+   struct dc_stream *dc_stream;
+
+   if (WARN_ON(!crtc->state))
+   return NULL;
+
+   cur = to_dm_crtc_state(crtc->state);
+   if (WARN_ON(!cur->dc_stream))
+   return NULL;
+
+   dc_stream = dm_alloc(sizeof(*dc_stream));
+   if (WARN_ON(!dc_stream))
+   return NULL;
+
+   state = dm_alloc(sizeof(*state));
+   if (WARN_ON(!state)) {
+   dm_free(dc_stream);
+   return NULL;
+   }
+
+   __drm_atomic_helper_crtc_duplicate_state(crtc, >base);
+
+   state->dc_stream = dc_stream;
+
+   /* TODO Duplicate dc_stream after objects are stream object is 
flattened */
+
+   return >base;
+}
+
 /* Implemented only the options currently availible for the driver */
 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
-   .reset = drm_atomic_helper_crtc_reset,
+   .reset = dm_crtc_reset_state,
.destroy = amdgpu_dm_crtc_destroy,
.gamma_set = drm_atomic_helper_legacy_gamma_set,
.set_config = drm_atomic_helper_set_config,
.set_property = drm_atomic_helper_crtc_set_property,
.page_flip = amdgpu_atomic_helper_page_flip,
-   .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
-   .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+   .atomic_duplicate_state = dm_crtc_duplicate_state,
+   .atomic_destroy_state = dm_crtc_destroy_state,
 };
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
index 6411dd1..1091725 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h
@@ -32,6 +32,16 @@ struct amdgpu_framebuffer;
 struct amdgpu_display_manager;
 struct dc_validation_set;
 struct dc_surface;
+/* TODO rename to dc_stream_state */
+struct  dc_stream;
+
+
+struct dm_crtc_state {
+   struct drm_crtc_state base;
+   struct dc_stream *dc_stream;
+};
+
+#define to_dm_crtc_state(x)container_of(x, struct dm_crtc_state, base)
 
 struct dm_plane_state {
struct drm_plane_state base;
-- 
2.7.4

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[PATCH 02/81] drm/amd/display: Move drm_get_vblank from legacy code

[sunpeng.li]

From: "Leo (Sunpeng) Li" 

Previously, we assumed that allow_modeset=false => page flip. This
assumption breaks when an atomic commit is submitted with allow_modeset
set to false, since the legacy flip code is never called (the legacy
code grabs the vblank reference).

Fix: Move drm_vblank_get() from amdgpu_atomic_helper_page_flip() to
amdgpu_dm_commit_surfaces().

Change-Id: Ibd429f7efb75aeef6e254e96bb88703f5b3391a0
Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Andrey Grodzovsky 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 88d4f74c..fd5d643 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -977,10 +977,6 @@ static int amdgpu_atomic_helper_page_flip(struct drm_crtc 
*crtc,
if (!state)
return -ENOMEM;
 
-   ret = drm_crtc_vblank_get(crtc);
-   if (ret)
-   return ret;
-
state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
 retry:
crtc_state = drm_atomic_get_crtc_state(state, crtc);
@@ -2551,8 +2547,6 @@ static void amdgpu_dm_commit_surfaces(struct 
drm_atomic_state *state,
if (!con_state)
continue;
 
-
-
add_surface(dm->dc, crtc, plane,
_surfaces_constructed[planes_count]);
if (dc_surfaces_constructed[planes_count] == NULL) {
@@ -2571,6 +2565,10 @@ static void amdgpu_dm_commit_surfaces(struct 
drm_atomic_state *state,
acrtc_attach->flip_flags & 
DRM_MODE_PAGE_FLIP_ASYNC ?
false : true;
 
+   /* TODO: Needs rework for multiplane flip */
+   if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+   drm_crtc_vblank_get(crtc);
+
amdgpu_dm_do_flip(
crtc,
fb,
-- 
2.7.4

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[PATCH 78/81] drm/amd/display: revert order change of HUBP and MPC disable

[sunpeng.li]

From: Tony Cheng 

- root cause was we disable opp clk in MPC disconnect
- hubp_blank is not double buffered, so we can't blank until MPC disconnect or 
we have risk of underflow

Change-Id: Ic767e4cfbdec5d68c118c3ed818c10543c771967
Signed-off-by: Tony Cheng 
Reviewed-by: Eric Yang 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h |  2 --
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 41 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c |  5 +++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h |  2 ++
 4 files changed, 32 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 7e1d46f..94d12b5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -288,7 +288,6 @@ struct dce_hwseq_registers {
HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, 
mask_sh), \
HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, 
mask_sh), \
HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, 
mask_sh), \
-   HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh), \
HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \
HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \
HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
@@ -351,7 +350,6 @@ struct dce_hwseq_registers {
 #define HWSEQ_DCN_REG_FIELD_LIST(type) \
type VUPDATE_NO_LOCK_EVENT_CLEAR; \
type VUPDATE_NO_LOCK_EVENT_OCCURRED; \
-   type HUBP_NO_OUTSTANDING_REQ; \
type HUBP_VTG_SEL; \
type HUBP_CLOCK_ENABLE; \
type DPP_CLOCK_ENABLE; \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 8284837..adf3d29 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -436,29 +436,17 @@ static void reset_back_end_for_pipe(
pipe_ctx->pipe_idx, pipe_ctx->tg->inst);
 }
 
-static void reset_front_end(
+static void plane_atomic_stop(
struct core_dc *dc,
int fe_idx)
 {
-   struct dce_hwseq *hws = dc->hwseq;
struct mpcc_cfg mpcc_cfg;
struct mem_input *mi = dc->res_pool->mis[fe_idx];
struct transform *xfm = dc->res_pool->transforms[fe_idx];
struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
struct timing_generator *tg = 
dc->res_pool->timing_generators[mpcc->opp_id];
-   unsigned int opp_id = mpcc->opp_id;
-
-   /*Already reset*/
-   if (opp_id == 0xf)
-   return;
-
-   tg->funcs->lock(tg);
 
mi->funcs->dcc_control(mi, false, false);
-   mi->funcs->set_blank(mi, true);
-   REG_WAIT(DCHUBP_CNTL[fe_idx],
-   HUBP_NO_OUTSTANDING_REQ, 1,
-   1, 200);
 
mpcc_cfg.opp_id = 0xf;
mpcc_cfg.top_dpp_id = 0xf;
@@ -466,23 +454,44 @@ static void reset_front_end(
mpcc_cfg.top_of_tree = tg->inst == mpcc->inst;
mpcc->funcs->set(mpcc, _cfg);
 
+   xfm->funcs->transform_reset(xfm);
+}
+
+static void reset_front_end(
+   struct core_dc *dc,
+   int fe_idx)
+{
+   struct dce_hwseq *hws = dc->hwseq;
+   struct mem_input *mi = dc->res_pool->mis[fe_idx];
+   struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
+   struct timing_generator *tg = 
dc->res_pool->timing_generators[mpcc->opp_id];
+   unsigned int opp_id = mpcc->opp_id;
+
+   /*Already reset*/
+   if (opp_id == 0xf)
+   return;
+
+   tg->funcs->lock(tg);
+
+   plane_atomic_stop(dc, fe_idx);
+
REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst], 
VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
tg->funcs->unlock(tg);
REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], 
VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 2, 20);
 
mpcc->funcs->wait_for_idle(mpcc);
 
+   mi->funcs->set_blank(mi, true);
+
REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
HUBP_CLOCK_ENABLE, 0);
REG_UPDATE(DPP_CONTROL[fe_idx],
DPP_CLOCK_ENABLE, 0);
 
-   if (mpcc_cfg.top_of_tree)
+   if (tg->inst == mpcc->inst)
REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
OPP_PIPE_CLOCK_EN, 0);
 
-   xfm->funcs->transform_reset(xfm);
-
dm_logger_write(dc->ctx->logger, LOG_DC,
"Reset front end %d\n",
fe_idx);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index efa02d1..8054794 100644
--- 

[PATCH 53/81] drm/amd/display: Attach surface to dm_plane_state.

[sunpeng.li]

From: Andrey Grodzovsky 

Attach surface to state.
Remove Create surface from commit.
Propogate any surface creation and initialization error back to atomic_check 
caller.
clean outdated code in check and commit.

Change-Id: I42d1dc91e152e44dafb9a2ee321af9277a0dd44d
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 348 +
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h|   2 +-
 2 files changed, 147 insertions(+), 203 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 6aefa19..32b3a39 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -300,16 +300,16 @@ static bool fill_rects_from_plane_state(
 
return true;
 }
-static bool get_fb_info(
+static int get_fb_info(
const struct amdgpu_framebuffer *amdgpu_fb,
uint64_t *tiling_flags,
uint64_t *fb_location)
 {
struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
int r = amdgpu_bo_reserve(rbo, false);
-   if (unlikely(r != 0)){
+   if (unlikely(r)) {
DRM_ERROR("Unable to reserve buffer\n");
-   return false;
+   return r;
}
 
if (fb_location)
@@ -320,9 +320,10 @@ static bool get_fb_info(
 
amdgpu_bo_unreserve(rbo);
 
-   return true;
+   return r;
 }
-static void fill_plane_attributes_from_fb(
+
+static int fill_plane_attributes_from_fb(
struct amdgpu_device *adev,
struct dc_surface *surface,
const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)
@@ -331,13 +332,16 @@ static void fill_plane_attributes_from_fb(
uint64_t fb_location = 0;
unsigned int awidth;
const struct drm_framebuffer *fb = _fb->base;
+   int ret = 0;
struct drm_format_name_buf format_name;
 
-   get_fb_info(
+   ret = get_fb_info(
amdgpu_fb,
_flags,
addReq == true ? _location:NULL);
 
+   if (ret)
+   return ret;
 
switch (fb->format->format) {
case DRM_FORMAT_C8:
@@ -367,7 +371,7 @@ static void fill_plane_attributes_from_fb(
default:
DRM_ERROR("Unsupported screen format %s\n",
  drm_get_format_name(fb->format->format, 
_name));
-   return;
+   return -EINVAL;
}
 
if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
@@ -468,23 +472,26 @@ static void fill_plane_attributes_from_fb(
surface->scaling_quality.v_taps = 0;
surface->stereo_format = PLANE_STEREO_FORMAT_NONE;
 
+   return ret;
+
 }
 
 #define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
 
-static void fill_gamma_from_crtc(
-   const struct drm_crtc *crtc,
+static void fill_gamma_from_crtc_state(
+   const struct drm_crtc_state *crtc_state,
struct dc_surface *dc_surface)
 {
int i;
struct dc_gamma *gamma;
-   struct drm_crtc_state *state = crtc->state;
-   struct drm_color_lut *lut = (struct drm_color_lut *) 
state->gamma_lut->data;
+   struct drm_color_lut *lut = (struct drm_color_lut *) 
crtc_state->gamma_lut->data;
 
gamma = dc_create_gamma();
 
-   if (gamma == NULL)
+   if (gamma == NULL) {
+   WARN_ON(1);
return;
+   }
 
for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) {
gamma->red[i] = lut[i].red;
@@ -495,27 +502,35 @@ static void fill_gamma_from_crtc(
dc_surface->gamma_correction = gamma;
 }
 
-static void fill_plane_attributes(
+static int fill_plane_attributes(
struct amdgpu_device *adev,
struct dc_surface *surface,
-   struct drm_plane_state *state, bool addrReq)
+   struct drm_plane_state *plane_state,
+   struct drm_crtc_state *crtc_state,
+   bool addrReq)
 {
const struct amdgpu_framebuffer *amdgpu_fb =
-   to_amdgpu_framebuffer(state->fb);
-   const struct drm_crtc *crtc = state->crtc;
+   to_amdgpu_framebuffer(plane_state->fb);
+   const struct drm_crtc *crtc = plane_state->crtc;
struct dc_transfer_func *input_tf;
+   int ret = 0;
 
-   fill_rects_from_plane_state(state, surface);
-   fill_plane_attributes_from_fb(
+   if (!fill_rects_from_plane_state(plane_state, surface))
+   return -EINVAL;
+
+   ret = fill_plane_attributes_from_fb(
crtc->dev->dev_private,
surface,
amdgpu_fb,
addrReq);
 
+   if (ret)
+   return ret;
+
input_tf = 

[PATCH 57/81] drm/amd/display: Skip DC validation for flips and cursor.

[sunpeng.li]

From: Andrey Grodzovsky 

Nothing to validate in DC in this case. Skip it.

Change-Id: I2e736e7c9d995a1bd702181912fd62f1e2ab4113
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Roman Li 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 35 +++---
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 32b3a39..9c08121 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1469,8 +1469,7 @@ int amdgpu_dm_connector_mode_valid(
 
if (context) {
result = MODE_OK;
-   dc_resource_validate_ctx_destruct(context);
-   dm_free(context);
+   dc_release_validate_context(context);
}
 
dc_stream_release(stream);
@@ -2766,8 +2765,8 @@ void amdgpu_dm_atomic_commit_tail(
}
}
 
-   /* DC is optimized not to do anything if 'streams' didn't change. */
-   WARN_ON(!dc_commit_context(dm->dc, dm_state->context));
+   if (dm_state->context)
+   WARN_ON(!dc_commit_context(dm->dc, dm_state->context));
 
 
list_for_each_entry(crtc, >mode_config.crtc_list, head) {
@@ -3100,9 +3099,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
/*
 * This bool will be set for true for any modeset/reset
-* or surface update which implies non fast surfae update.
+* or surface update which implies non fast surface update.
 */
-   bool aquire_global_lock = false;
+   bool lock_and_validation_needed = false;
 
ret = drm_atomic_helper_check(dev, state);
 
@@ -3190,7 +3189,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
new_acrtc_state->stream,
crtc);
 
-   aquire_global_lock = true;
+   lock_and_validation_needed = true;
 
} else if (modereset_required(crtc_state)) {
 
@@ -3204,7 +3203,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
dc_stream_release(new_acrtc_state->stream);
new_acrtc_state->stream = NULL;
 
-   aquire_global_lock = true;
+   lock_and_validation_needed = true;
}
}
 
@@ -3242,7 +3241,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
if (!is_scaling_state_different(con_new_state, con_old_state))
continue;
 
-   aquire_global_lock = true;
+   lock_and_validation_needed = true;
}
 
for_each_crtc_in_state(state, crtc, crtc_state, i) {
@@ -3292,17 +3291,11 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 new_acrtc_state->stream,
 surface);
 
-   aquire_global_lock = true;
+   lock_and_validation_needed = true;
}
}
}
 
-   dm_state->context = dc_get_validate_context(dc, set, set_count);
-   if (!dm_state->context) {
-   ret = -EINVAL;
-   goto fail_planes;
-   }
-
/*
 * For full updates case when
 * removing/adding/updating  streams on once CRTC while flipping
@@ -3312,10 +3305,18 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 * will wait for completion of any outstanding flip using DRMs
 * synchronization events.
 */
-   if (aquire_global_lock) {
+
+   if (lock_and_validation_needed) {
+
ret = do_aquire_global_lock(dev, state);
if (ret)
goto fail_planes;
+
+   dm_state->context = dc_get_validate_context(dc, set, set_count);
+   if (!dm_state->context) {
+   ret = -EINVAL;
+   goto fail_planes;
+   }
}
 
/* Must be success */
-- 
2.7.4

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[PATCH 45/81] drm/amd/display: minor dcn10_hwseq clean up/refactor

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: I6b2040078c2d94ec0604457a1376a386347b9ec0
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 49 ++
 1 file changed, 12 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 5e27523..223bb79 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -53,15 +53,6 @@
 #define FN(reg_name, field_name) \
hws->shifts->field_name, hws->masks->field_name
 
-static void disable_clocks(
-   struct dce_hwseq *hws,
-   uint8_t plane_id)
-{
-   REG_UPDATE(HUBP_CLK_CNTL[plane_id], HUBP_CLOCK_ENABLE, 0);
-
-   REG_UPDATE(DPP_CONTROL[plane_id], DPP_CLOCK_ENABLE, 0);
-}
-
 static void enable_dppclk(
struct dce_hwseq *hws,
uint8_t plane_id,
@@ -214,25 +205,6 @@ static void power_on_plane(
"Un-gated front end for pipe %d\n", plane_id);
 }
 
-/* fully check bios enabledisplaypowergating table. dal only need dce init
- * other power, clock gate register will be handle by dal itself.
- * further may be put within init_hw
- */
-static bool dcn10_enable_display_power_gating(
-   struct core_dc *dc,
-   uint8_t controller_id,
-   struct dc_bios *dcb,
-   enum pipe_gating_control power_gating)
-{
-   /* TODOFPGA */
-#if 0
-   if (power_gating != PIPE_GATING_CONTROL_ENABLE)
-   dce110_init_pte(ctx);
-#endif
-
-   return true;
-}
-
 static void bios_golden_init(struct core_dc *dc)
 {
struct dc_bios *bp = dc->ctx->dc_bios;
@@ -525,7 +497,8 @@ static void reset_front_end(
mpcc->funcs->wait_for_idle(mpcc);
mi->funcs->set_blank(mi, true);
REG_WAIT(DCHUBP_CNTL[fe_idx], HUBP_NO_OUTSTANDING_REQ, 1, 2, 
20);
-   disable_clocks(dc->hwseq, fe_idx);
+   REG_UPDATE(HUBP_CLK_CNTL[fe_idx], HUBP_CLOCK_ENABLE, 0);
+   REG_UPDATE(DPP_CONTROL[fe_idx], DPP_CLOCK_ENABLE, 0);
 
xfm->funcs->transform_reset(xfm);
 
@@ -1803,8 +1776,8 @@ static void set_plane_config(
program_gamut_remap(pipe_ctx);
 }
 
-static void dcn10_config_stereo_parameters(struct core_stream *stream,\
-   
   struct crtc_stereo_flags *flags)
+static void dcn10_config_stereo_parameters(
+   struct core_stream *stream, struct crtc_stereo_flags *flags)
 {
enum view_3d_format view_format = stream->public.view_format;
enum dc_timing_3d_format timing_3d_format =\
@@ -1840,8 +1813,7 @@ static void dcn10_config_stereo_parameters(struct 
core_stream *stream,\
return;
 }
 
-static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx,
-   struct core_dc 
*dc)
+static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc)
 {
struct crtc_stereo_flags flags = { 0 };
struct core_stream *stream = pipe_ctx->stream;
@@ -1858,11 +1830,15 @@ static void dcn10_setup_stereo(struct pipe_ctx 
*pipe_ctx,
>public.timing,
);
 
-
-
return;
 }
 
+static bool dcn10_dummy_display_power_gating(
+   struct core_dc *dc,
+   uint8_t controller_id,
+   struct dc_bios *dcb,
+   enum pipe_gating_control power_gating) {return true; }
+
 static const struct hw_sequencer_funcs dcn10_funcs = {
.program_gamut_remap = program_gamut_remap,
.program_csc_matrix = program_csc_matrix,
@@ -1881,8 +1857,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.enable_stream = dce110_enable_stream,
.disable_stream = dce110_disable_stream,
.unblank_stream = dce110_unblank_stream,
-   .enable_display_pipe_clock_gating = NULL, /* TODOFPGA */
-   .enable_display_power_gating = dcn10_enable_display_power_gating,
+   .enable_display_power_gating = dcn10_dummy_display_power_gating,
.power_down_front_end = dcn10_power_down_fe,
.power_on_front_end = dcn10_power_on_fe,
.pipe_control_lock = dcn10_pipe_control_lock,
-- 
2.7.4

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[PATCH 66/81] drm/amd/display: fix mpo exit hang

[sunpeng.li]

From: Eric Yang 

Change-Id: I163fb3501061e58c98c8ca8cbf38a086d8e3a6d6
Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c   | 17 -
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 82a96de..dbf9cea 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -500,8 +500,10 @@ static void reset_front_end(
HUBP_CLOCK_ENABLE, 0);
REG_UPDATE(DPP_CONTROL[fe_idx],
DPP_CLOCK_ENABLE, 0);
-   REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
-   OPP_PIPE_CLOCK_EN, 0);
+
+   if (mpcc_cfg.top_of_tree)
+   REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
+   OPP_PIPE_CLOCK_EN, 0);
 
xfm->funcs->transform_reset(xfm);
 
@@ -1584,7 +1586,7 @@ static void dcn10_apply_ctx_for_surface(
int i;
 
/* reset unused mpcc */
-   /*for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[i];
struct pipe_ctx *old_pipe_ctx =
>current_context->res_ctx.pipe_ctx[i];
@@ -1593,7 +1595,12 @@ static void dcn10_apply_ctx_for_surface(
|| (!pipe_ctx->stream && old_pipe_ctx->stream)) 
{
struct mpcc_cfg mpcc_cfg;
 
-   mpcc_cfg.opp_id = 0xf;
+   if (!old_pipe_ctx->top_pipe) {
+   ASSERT(0);
+   continue;
+   }
+
+   mpcc_cfg.opp_id = old_pipe_ctx->mpcc->opp_id;
mpcc_cfg.top_dpp_id = 0xf;
mpcc_cfg.bot_mpcc_id = 0xf;
mpcc_cfg.top_of_tree = !old_pipe_ctx->top_pipe;
@@ -1607,7 +1614,7 @@ static void dcn10_apply_ctx_for_surface(
"Reset mpcc for pipe %d\n",
old_pipe_ctx->pipe_idx);
}
-   }*/
+   }
 
if (!surface)
return;
-- 
2.7.4

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[PATCH 75/81] drm/amd/display: fix DVI connected to HDMI connector max tmds clock

[sunpeng.li]

From: Charlene Liu 

Change-Id: If1f43f6c7f8ed8485fcc1bda83933dedb4d76ef1
Signed-off-by: Charlene Liu 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index 812c299..5663d3d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -830,6 +830,12 @@ bool dce110_link_encoder_validate_dvi_output(
if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
return false;
 
+   /*connect DVI via adpater's HDMI connector*/
+   if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
+   connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
+   signal != SIGNAL_TYPE_HDMI_TYPE_A &&
+   crtc_timing->pix_clk_khz > TMDS_MAX_PIXEL_CLOCK)
+   return false;
if (crtc_timing->pix_clk_khz < TMDS_MIN_PIXEL_CLOCK)
return false;
 
-- 
2.7.4

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[PATCH 81/81] drm/amd/display: Do not release state objects on atomic check fail

[sunpeng.li]

From: "Leo (Sunpeng) Li" 

In any drm ioctl call, drm_atomic_state_clear() is called at the end to
destroy the states; even if atomic check fails. Therefore, releasing
states on atomic check failure is incorrect.

Change-Id: I26f9b1f244b171b71fd34e46df7ecf69c46c271d
Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Andrey Grodzovsky 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 21 ++---
 1 file changed, 6 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index cdecd2f..9908a19 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3158,7 +3158,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
conn_state = 
drm_atomic_get_connector_state(state, >base);
if (IS_ERR(conn_state)) {
ret = PTR_ERR_OR_ZERO(conn_state);
-   goto fail_crtcs;
+   goto fail;
}
 
dm_conn_state = 
to_dm_connector_state(conn_state);
@@ -3217,7 +3217,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
ret = drm_atomic_add_affected_planes(state, crtc);
if (ret)
-   goto fail_crtcs;
+   goto fail;
}
}
 
@@ -3279,7 +3279,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
crtc_state,
false);
if (ret)
-   goto fail_planes;
+   goto fail;
 
 
if (dm_plane_state->surface)
@@ -3311,13 +3311,12 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
 
ret = do_aquire_global_lock(dev, state);
if (ret)
-   goto fail_planes;
-
+   goto fail;
WARN_ON(dm_state->context);
dm_state->context = dc_get_validate_context(dc, set, set_count);
if (!dm_state->context) {
ret = -EINVAL;
-   goto fail_planes;
+   goto fail;
}
}
 
@@ -3325,15 +3324,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
WARN_ON(ret);
return ret;
 
-fail_planes:
-   for (i = 0; i < set_count; i++)
-   for (j = 0; j < set[i].surface_count; j++)
-   dc_surface_release(set[i].surfaces[j]);
-
-fail_crtcs:
-   for (i = 0; i < set_count; i++)
-   dc_stream_release(set[i].stream);
-
+fail:
if (ret == -EDEADLK)
DRM_DEBUG_KMS("Atomic check stopped due to to deadlock.\n");
else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
-- 
2.7.4

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[PATCH 68/81] drm/amd/display: Preserve refcount for S3 case.

[sunpeng.li]

From: Andrey Grodzovsky 

Curent_context is zerroed out for suspend, keep the refcount.
Minor code move in dc_commit_context_no_check

Change-Id: I45b7fa4b0a7df54f1621f6306ef9e31c9ebe25eb
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8e580ac..20f4199 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -977,10 +977,10 @@ static bool dc_commit_context_no_check(struct dc *dc, 
struct validate_context *c
 
dc_release_validate_context(core_dc->current_context);
 
-   dc_retain_validate_context(context);
-
core_dc->current_context = context;
 
+   dc_retain_validate_context(core_dc->current_context);
+
return (result == DC_OK);
 }
 
@@ -1065,8 +1065,6 @@ bool dc_commit_streams(
 
result = dc_commit_context_no_check(dc, context);
 
-   return (result == DC_OK);
-
 fail:
dc_release_validate_context(context);
 
@@ -1736,6 +1734,7 @@ void dc_set_power_state(
enum dc_acpi_cm_power_state power_state)
 {
struct core_dc *core_dc = DC_TO_CORE(dc);
+   int ref_count;
 
switch (power_state) {
case DC_ACPI_CM_POWER_STATE_D0:
@@ -1749,8 +1748,13 @@ void dc_set_power_state(
 * clean state, and dc hw programming optimizations will not
 * cause any trouble.
 */
+
+   /* Preserve refcount */
+   ref_count = core_dc->current_context->ref_count;
+   dc_resource_validate_ctx_destruct(core_dc->current_context);
memset(core_dc->current_context, 0,
sizeof(*core_dc->current_context));
+   core_dc->current_context->ref_count = ref_count;
 
break;
}
-- 
2.7.4

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[PATCH 79/81] drm/amd/display: Add regkey for DRR control for internal panel

[sunpeng.li]

From: Anthony Koo 

Also need to change default to off

Change-Id: I34f40f2a921e9b0717e5c1007e4176265a2ecda4
Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h|  1 -
 .../drm/amd/display/modules/freesync/freesync.c| 74 --
 .../gpu/drm/amd/display/modules/inc/mod_freesync.h |  1 -
 3 files changed, 40 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 6a22c91..07f064f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -188,7 +188,6 @@ struct dc_debug {
bool disable_dmcu;
bool disable_psr;
bool force_abm_enable;
-   bool no_static_for_external_dp;
 };
 
 struct dc {
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 4df79f7..a989d5d 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -43,6 +43,10 @@
 
 #define FREESYNC_REGISTRY_NAME "freesync_v1"
 
+#define FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY 
"DalFreeSyncNoStaticForExternalDp"
+
+#define FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY "DalFreeSyncNoStaticForInternal"
+
 struct gradual_static_ramp {
bool ramp_is_active;
bool ramp_direction_is_up;
@@ -114,7 +118,8 @@ struct freesync_entity {
 };
 
 struct freesync_registry_options {
-   unsigned int min_refresh_from_edid;
+   bool drr_external_supported;
+   bool drr_internal_supported;
 };
 
 struct core_freesync {
@@ -176,9 +181,19 @@ struct mod_freesync *mod_freesync_create(struct dc *dc)
NULL, NULL, 0, );
flag.save_per_edid = false;
flag.save_per_link = false;
+
if (dm_read_persistent_data(core_dc->ctx, NULL, NULL,
-   "DalDrrSupport", , sizeof(data), )) {
-   core_freesync->opts.min_refresh_from_edid = data;
+   FREESYNC_NO_STATIC_FOR_INTERNAL_REGKEY,
+   , sizeof(data), )) {
+   core_freesync->opts.drr_internal_supported =
+   (data & 1) ? false : true;
+   }
+
+   if (dm_read_persistent_data(core_dc->ctx, NULL, NULL,
+   FREESYNC_NO_STATIC_FOR_EXTERNAL_DP_REGKEY,
+   , sizeof(data), )) {
+   core_freesync->opts.drr_external_supported =
+   (data & 1) ? false : true;
}
 
return _freesync->public;
@@ -236,7 +251,7 @@ bool mod_freesync_add_stream(struct mod_freesync 
*mod_freesync,
struct core_freesync *core_freesync = NULL;
int persistent_freesync_enable = 0;
struct persistent_data_flag flag;
-   unsigned int nom_refresh_rate_micro_hz;
+   unsigned int nom_refresh_rate_uhz;
unsigned long long temp;
 
if (mod_freesync == NULL)
@@ -258,20 +273,7 @@ bool mod_freesync_add_stream(struct mod_freesync 
*mod_freesync,
temp = div_u64(temp, stream->timing.h_total);
temp = div_u64(temp, stream->timing.v_total);
 
-   nom_refresh_rate_micro_hz = (unsigned int) temp;
-
-   if (core_freesync->opts.min_refresh_from_edid != 0 &&
-   dc_is_embedded_signal(stream->sink->sink_signal)
-   && (nom_refresh_rate_micro_hz -
-   core_freesync->opts.min_refresh_from_edid *
-   100) >= 1000) {
-   caps->supported = true;
-   caps->min_refresh_in_micro_hz =
-   core_freesync->opts.min_refresh_from_edid *
-   100;
-   caps->max_refresh_in_micro_hz =
-   nom_refresh_rate_micro_hz;
-   }
+   nom_refresh_rate_uhz = (unsigned int) temp;
 
core_freesync->map[core_freesync->num_entities].stream = stream;
core_freesync->map[core_freesync->num_entities].caps = caps;
@@ -311,8 +313,8 @@ bool mod_freesync_add_stream(struct mod_freesync 
*mod_freesync,
}
 
if (caps->supported &&
-   nom_refresh_rate_micro_hz >= caps->min_refresh_in_micro_hz 
&&
-   nom_refresh_rate_micro_hz <= caps->max_refresh_in_micro_hz)
+   nom_refresh_rate_uhz >= caps->min_refresh_in_micro_hz &&
+   nom_refresh_rate_uhz <= caps->max_refresh_in_micro_hz)
core_stream->public.ignore_msa_timing_param = 1;
 
core_freesync->num_entities++;
@@ -865,6 +867,11 @@ void mod_freesync_update_state(struct mod_freesync 
*mod_freesync,
   

[PATCH 80/81] drm/amd/display: powergate fe of reused pipes to reset ttu

[sunpeng.li]

From: Eric Yang 

When we exit MPO, disconnected pipes cannot be immediately powergated
because registers are double buffered, and actual disconnection does
not happen until VUPDATE. So it is differred for many flips.
However in the case of exiting full screen, the transition from MPO
to grph only back to MPO is very fast and also involves increasing of
watermarks. Since the underlay pipe is never powergated in this
scenario, it keeps its old TTU counter, which causes allowPstateSwitch
signal to be de-asserted when compared to the new increased watermark.
Since the new pipe is not enabled yet, the signal will be continously
de-asserted and hangs SMU, who's waiting for the signal to do pstate
switching.

Change-Id: I3399a1f0feeaab090c79475b29a360f1026740c2
Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index adf3d29..6543027 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1577,6 +1577,14 @@ static void dcn10_apply_ctx_for_surface(
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[i];
struct pipe_ctx *old_pipe_ctx =
>current_context->res_ctx.pipe_ctx[i];
+   /*
+* Powergate reused pipes that are not powergated
+* fairly hacky right now, using opp_id as indicator
+*/
+   if (pipe_ctx->surface && !old_pipe_ctx->surface) {
+   if (pipe_ctx->mpcc->opp_id != 0xf)
+   dcn10_power_down_fe(dc, pipe_ctx->pipe_idx);
+   }
 
if ((!pipe_ctx->surface && old_pipe_ctx->surface)
|| (!pipe_ctx->stream && old_pipe_ctx->stream)) 
{
@@ -1588,6 +1596,7 @@ static void dcn10_apply_ctx_for_surface(
continue;
}
 
+   /* reset mpc */
mpcc_cfg.opp_id = 0xf;
mpcc_cfg.top_dpp_id = 0xf;
mpcc_cfg.bot_mpcc_id = 0xf;
-- 
2.7.4

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[PATCH 73/81] drm/amd/display: Fix S3 gamma corruption.

[sunpeng.li]

From: Andrey Grodzovsky 

On S3 resume gamma is corrupted since no gamma programming
took place.

Change-Id: I99029b281241a688635317c05aa8dc0c3cee8bdc
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 20f4199..eda36c7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1120,11 +1120,13 @@ bool dc_commit_surfaces_to_stream(
 
stream_update->src = dc_stream->src;
stream_update->dst = dc_stream->dst;
+   stream_update->out_transfer_func = dc_stream->out_transfer_func;
 
for (i = 0; i < new_surface_count; i++) {
updates[i].surface = new_surfaces[i];
updates[i].gamma =
(struct dc_gamma *)new_surfaces[i]->gamma_correction;
+   updates[i].in_transfer_func = new_surfaces[i]->in_transfer_func;
flip_addr[i].address = new_surfaces[i]->address;
flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
plane_info[i].color_space = new_surfaces[i]->color_space;
-- 
2.7.4

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[PATCH 76/81] drm/amd/display: properly turn off unused mpc before front end programming

[sunpeng.li]

From: Eric Yang 

MPCC_OPP_ID must be programmed to 0xf to properly turn off the mpcc.
However the software state of the mpcc must keep track of the opp that
the mpcc is attached to for reset to properly happen. This is kinda
hacky right now, but a good solution may involve a lot of work.

Change-Id: I98274df3226b3f9640ab7c1ab39d1944c2b3f463
Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d714422..cadc940 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1572,17 +1572,24 @@ static void dcn10_apply_ctx_for_surface(
if ((!pipe_ctx->surface && old_pipe_ctx->surface)
|| (!pipe_ctx->stream && old_pipe_ctx->stream)) 
{
struct mpcc_cfg mpcc_cfg;
+   int opp_id_cached = old_pipe_ctx->mpcc->opp_id;
 
if (!old_pipe_ctx->top_pipe) {
ASSERT(0);
continue;
}
 
-   mpcc_cfg.opp_id = old_pipe_ctx->mpcc->opp_id;
+   mpcc_cfg.opp_id = 0xf;
mpcc_cfg.top_dpp_id = 0xf;
mpcc_cfg.bot_mpcc_id = 0xf;
mpcc_cfg.top_of_tree = !old_pipe_ctx->top_pipe;
old_pipe_ctx->mpcc->funcs->set(old_pipe_ctx->mpcc, 
_cfg);
+   /*
+* the mpcc is the only thing that keeps track of the 
mpcc
+* mapping for reset front end right now. Might need 
some
+* rework.
+*/
+   old_pipe_ctx->mpcc->opp_id = opp_id_cached;
 
old_pipe_ctx->top_pipe = NULL;
old_pipe_ctx->bottom_pipe = NULL;
-- 
2.7.4

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[PATCH 48/81] drm/amd/display: dal1.1 xfm prog update

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: Ide48a560f8f76d650380e09c36518963c652
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 10 ++---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h | 43 +++---
 2 files changed, 27 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
index 398af22..59ba2d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.c
@@ -212,7 +212,7 @@ static int get_pixel_depth_val(enum lb_pixel_depth depth)
}
 }
 
-static void transform_set_lb(
+static void xfmn10_set_lb(
struct dcn10_transform *xfm,
const struct line_buffer_params *lb_params,
enum lb_memory_config mem_size_config)
@@ -622,7 +622,7 @@ void transform_set_scaler_auto_scale(
return;
 
lb_config =  find_lb_memory_config(scl_data);
-   transform_set_lb(xfm, _data->lb_params, lb_config);
+   xfmn10_set_lb(xfm, _data->lb_params, lb_config);
 
if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
return;
@@ -738,7 +738,7 @@ static void transform_set_manual_ratio_init(
 }
 
 /* Main function to program scaler and line buffer in manual scaling mode */
-static void transform_set_scaler_manual_scale(
+static void xfmn10_set_scaler_manual_scale(
struct transform *xfm_base,
const struct scaler_data *scl_data)
 {
@@ -769,7 +769,7 @@ static void transform_set_scaler_manual_scale(
return;
/* LB */
lb_config =  find_lb_memory_config(scl_data);
-   transform_set_lb(xfm, _data->lb_params, lb_config);
+   xfmn10_set_lb(xfm, _data->lb_params, lb_config);
 
if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
return;
@@ -1027,7 +1027,7 @@ static void dcn_transform_set_gamut_remap(
 static struct transform_funcs dcn10_transform_funcs = {
 
.transform_reset = transform_reset,
-   .transform_set_scaler = transform_set_scaler_manual_scale,
+   .transform_set_scaler = xfmn10_set_scaler_manual_scale,
.transform_get_optimal_number_of_taps = 
transform_get_optimal_number_of_taps,
.transform_set_gamut_remap = dcn_transform_set_gamut_remap,
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
index 880a554..8df74cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_transform.h
@@ -38,6 +38,13 @@
.field_name = reg_name ## __ ## field_name ## post_fix
 
 #define TF_REG_LIST_DCN(id) \
+   SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
+   SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
+   SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
+   SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
+   SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
+   SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
+   SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
SRI(OTG_H_BLANK, DSCL, id), \
@@ -74,13 +81,6 @@
 
 #define TF_REG_LIST_DCN10(id) \
TF_REG_LIST_DCN(id), \
-   SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
-   SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
-   SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
-   SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
-   SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
-   SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
-   SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
SRI(CM_COMA_C11_C12, CM, id),\
SRI(CM_COMA_C13_C14, CM, id),\
SRI(CM_COMA_C21_C22, CM, id),\
@@ -95,6 +95,19 @@
SRI(CM_COMB_C33_C34, CM, id)
 
 #define TF_REG_LIST_SH_MASK_DCN(mask_sh)\
+   TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
+   TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
+   TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
+   TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
+   TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
+   TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
+   TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
+   TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
+   TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
+   TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
+   TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
+   TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
+   TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\

[PATCH 22/81] drm/amd/display: Rename DCN opp specific function prefixes to oppn10

[sunpeng.li]

From: Dmytro Laktyushkin 

Also update relevant registers.

Change-Id: I188076866f25dcf652af25e5bac2f07e908fddde
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Charlene Liu 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c   | 189 ++---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h   |  79 -
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |   6 +-
 3 files changed, 138 insertions(+), 136 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index a074010..e6f2220 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -37,7 +37,7 @@
 #define CTX \
oppn10->base.ctx
 
-static void opp_set_regamma_mode(
+static void oppn10_set_regamma_mode(
struct output_pixel_processor *opp,
enum opp_regamma mode)
 {
@@ -167,7 +167,7 @@ static void set_spatial_dither(
FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
 }
 
-static void opp_program_bit_depth_reduction(
+static void oppn10_program_bit_depth_reduction(
struct output_pixel_processor *opp,
const struct bit_depth_reduction_params *params)
 {
@@ -255,7 +255,7 @@ static void opp_set_clamping(
 
 }
 
-static void opp_set_dyn_expansion(
+static void oppn10_set_dyn_expansion(
struct output_pixel_processor *opp,
enum dc_color_space color_sp,
enum dc_color_depth color_dpth,
@@ -304,7 +304,7 @@ static void opp_program_clamping_and_pixel_encoding(
set_pixel_encoding(oppn10, params);
 }
 
-static void opp_program_fmt(
+static void oppn10_program_fmt(
struct output_pixel_processor *opp,
struct bit_depth_reduction_params *fmt_bit_depth,
struct clamping_and_pixel_encoding_params *clamping)
@@ -316,7 +316,7 @@ static void opp_program_fmt(
 
/* dithering is affected by , hence should be
 * programmed afterwards */
-   opp_program_bit_depth_reduction(
+   oppn10_program_bit_depth_reduction(
opp,
fmt_bit_depth);
 
@@ -327,7 +327,7 @@ static void opp_program_fmt(
return;
 }
 
-static void opp_set_output_csc_default(
+static void oppn10_set_output_csc_default(
struct output_pixel_processor *opp,
const struct default_adjustment *default_adjust)
 {
@@ -703,7 +703,7 @@ static void opp_configure_regamma_lut(
REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0);
 }
 
-static void opp_power_on_regamma_lut(
+static void oppn10_power_on_regamma_lut(
struct output_pixel_processor *opp,
bool power_on)
 {
@@ -713,7 +713,78 @@ static void opp_power_on_regamma_lut(
 
 }
 
-void opp_set_output_csc_adjustment(
+
+static void oppn10_program_color_matrix(struct dcn10_opp *oppn10,
+   const struct out_csc_color_matrix *tbl_entry)
+{
+   uint32_t mode;
+
+   REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, );
+
+   if (tbl_entry == NULL) {
+   BREAK_TO_DEBUGGER();
+   return;
+   }
+
+
+   if (mode == 4) {
+   /*R*/
+   REG_SET_2(CM_OCSC_C11_C12, 0,
+   CM_OCSC_C11, tbl_entry->regval[0],
+   CM_OCSC_C12, tbl_entry->regval[1]);
+
+   REG_SET_2(CM_OCSC_C13_C14, 0,
+   CM_OCSC_C13, tbl_entry->regval[2],
+   CM_OCSC_C14, tbl_entry->regval[3]);
+
+   /*G*/
+   REG_SET_2(CM_OCSC_C21_C22, 0,
+   CM_OCSC_C21, tbl_entry->regval[4],
+   CM_OCSC_C22, tbl_entry->regval[5]);
+
+   REG_SET_2(CM_OCSC_C23_C24, 0,
+   CM_OCSC_C23, tbl_entry->regval[6],
+   CM_OCSC_C24, tbl_entry->regval[7]);
+
+   /*B*/
+   REG_SET_2(CM_OCSC_C31_C32, 0,
+   CM_OCSC_C31, tbl_entry->regval[8],
+   CM_OCSC_C32, tbl_entry->regval[9]);
+
+   REG_SET_2(CM_OCSC_C33_C34, 0,
+   CM_OCSC_C33, tbl_entry->regval[10],
+   CM_OCSC_C34, tbl_entry->regval[11]);
+   } else {
+   /*R*/
+   REG_SET_2(CM_COMB_C11_C12, 0,
+   CM_COMB_C11, tbl_entry->regval[0],
+   CM_COMB_C12, tbl_entry->regval[1]);
+
+   REG_SET_2(CM_COMB_C13_C14, 0,
+   CM_COMB_C13, tbl_entry->regval[2],
+   CM_COMB_C14, tbl_entry->regval[3]);
+
+   /*G*/
+   REG_SET_2(CM_COMB_C21_C22, 0,
+   CM_COMB_C21, tbl_entry->regval[4],
+   CM_COMB_C22, tbl_entry->regval[5]);
+
+   REG_SET_2(CM_COMB_C23_C24, 0,
+   CM_COMB_C23, tbl_entry->regval[6],
+

[PATCH 11/81] drm/amd/display: Add extra mode and clock info to DTN logs

[sunpeng.li]

From: Corbin McElhanney 

Adds some additional information to logs in dc_commit_streams to
better match Dal2.

Also adds a new function, dc_raw_log, that has the same
functionality as dc_conn_log, but does not attach display specific
prefixes to the log output.

Finally, adds a new DC log type, LOG_DTN, that logs to
LogMinor_DispConnect_dtn in DM. This new log type and dc_raw_log
are used to generate clock info in the logs to match Dal2.

Change-Id: I36526c471dd0bb76870a8f0f9d6456407477bea0
Signed-off-by: Corbin McElhanney 
Reviewed-by: Aric Cyr 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c  |  2 +-
 .../gpu/drm/amd/display/dc/basics/log_helpers.c| 30 +-
 drivers/gpu/drm/amd/display/dc/basics/logger.c |  6 +++--
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  7 -
 drivers/gpu/drm/amd/display/dc/dm_helpers.h|  3 ++-
 .../gpu/drm/amd/display/include/logger_interface.h |  5 
 drivers/gpu/drm/amd/display/include/logger_types.h |  1 +
 7 files changed, 48 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index dc2248c..70577ad 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -321,7 +321,7 @@ bool dm_helpers_dp_mst_send_payload_allocation(
return true;
 }
 
-bool dm_helpers_dc_conn_log(struct dc_context*ctx, const char *msg)
+bool dm_helpers_dc_conn_log(struct dc_context *ctx, struct log_entry *entry, 
enum dc_log_type event)
 {
return true;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c 
b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
index 1268be9..070ae6f 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/log_helpers.c
@@ -95,7 +95,35 @@ void dc_conn_log(struct dc_context *ctx,
dm_logger_append(, "%2.2X ", hex_data[i]);
 
dm_logger_append(, "^\n");
-   dm_helpers_dc_conn_log(ctx, entry.buf);
+   dm_helpers_dc_conn_log(ctx, , event);
+   dm_logger_close();
+
+   va_end(args);
+}
+
+void dc_raw_log(struct dc_context *ctx,
+   enum dc_log_type event,
+   const char *msg,
+   ...)
+{
+   va_list args;
+   struct log_entry entry = { 0 };
+
+   dm_logger_open(ctx->logger, , event);
+
+   va_start(args, msg);
+   entry.buf_offset += dm_log_to_buffer(
+   [entry.buf_offset],
+   LOG_MAX_LINE_SIZE - entry.buf_offset,
+   msg, args);
+
+   if (entry.buf[strlen(entry.buf) - 1] == '\n') {
+   entry.buf[strlen(entry.buf) - 1] = '\0';
+   entry.buf_offset--;
+   }
+
+   dm_logger_append(, "^\n");
+   dm_helpers_dc_conn_log(ctx, , event);
dm_logger_close();
 
va_end(args);
diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c 
b/drivers/gpu/drm/amd/display/dc/basics/logger.c
index 4be8370..0b17374 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/logger.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c
@@ -59,7 +59,8 @@ static const struct dc_log_type_info log_type_info_tbl[] = {
{LOG_EVENT_LINK_TRAINING,   "LKTN"},
{LOG_EVENT_LINK_LOSS,   "LinkLoss"},
{LOG_EVENT_UNDERFLOW,   "Underflow"},
-   {LOG_IF_TRACE,  "InterfaceTrace"}
+   {LOG_IF_TRACE,  "InterfaceTrace"},
+   {LOG_DTN,   "DTN"}
 };
 
 
@@ -84,7 +85,8 @@ static const struct dc_log_type_info log_type_info_tbl[] = {
(1 << LOG_DETECTION_DP_CAPS) | \
(1 << LOG_BACKLIGHT)) | \
(1 << LOG_I2C_AUX) | \
-   (1 << LOG_IF_TRACE) /* | \
+   (1 << LOG_IF_TRACE) | \
+   (1 << LOG_DTN) /* | \
(1 << LOG_DEBUG) | \
(1 << LOG_BIOS) | \
(1 << LOG_SURFACE) | \
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 51e4cb3..c113c1a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -944,9 +944,14 @@ bool dc_commit_streams(
dc_enable_stereo(dc, context, streams, stream_count);
}
 
-   CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
+   CONN_MSG_MODE(sink->link, "{%ux%u, %ux%u@%u, %ux%u@%uKhz}",
+   context->streams[i]->public.src.width,
+   context->streams[i]->public.src.height,

context->streams[i]->public.timing.h_addressable,

[PATCH 21/81] drm/amd/display: Rename DCN mem input specific function prefixes to min.

[sunpeng.li]

From: Dmytro Laktyushkin 

Also updated relevant registers.

Change-Id: I787f75d546b833919612fc5494c93dd281dbfcd9
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 96 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 93 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  6 +-
 3 files changed, 104 insertions(+), 91 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index a58993a..b7ecfad 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -38,7 +38,7 @@
 #define FN(reg_name, field_name) \
mi->mi_shift->field_name, mi->mi_mask->field_name
 
-static void dcn_mi_set_blank(struct mem_input *mem_input, bool blank)
+static void min10_set_blank(struct mem_input *mem_input, bool blank)
 {
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
uint32_t blank_en = blank ? 1 : 0;
@@ -48,7 +48,7 @@ static void dcn_mi_set_blank(struct mem_input *mem_input, 
bool blank)
HUBP_TTU_DISABLE, blank_en);
 }
 
-static void vready_workaround(struct mem_input *mem_input,
+static void min10_vready_workaround(struct mem_input *mem_input,
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 {
uint32_t value = 0;
@@ -71,7 +71,7 @@ static void vready_workaround(struct mem_input *mem_input,
REG_WRITE(HUBPREQ_DEBUG_DB, value);
 }
 
-static void program_tiling(
+static void min10_program_tiling(
struct dcn10_mem_input *mi,
const union dc_tiling_info *info,
const enum surface_pixel_format pixel_format)
@@ -91,7 +91,7 @@ static void program_tiling(
PIPE_ALIGNED, info->gfx9.pipe_aligned);
 }
 
-static void program_size_and_rotation(
+static void min10_program_size_and_rotation(
struct dcn10_mem_input *mi,
enum dc_rotation_angle rotation,
enum surface_pixel_format format,
@@ -153,7 +153,7 @@ static void program_size_and_rotation(
H_MIRROR_EN, mirror);
 }
 
-static void program_pixel_format(
+static void min10_program_pixel_format(
struct dcn10_mem_input *mi,
enum surface_pixel_format format)
 {
@@ -229,7 +229,7 @@ static void program_pixel_format(
/* don't see the need of program the xbar in DCN 1.0 */
 }
 
-static bool mem_input_program_surface_flip_and_addr(
+static bool min10_program_surface_flip_and_addr(
struct mem_input *mem_input,
const struct dc_plane_address *address,
bool flip_immediate)
@@ -369,7 +369,7 @@ static bool mem_input_program_surface_flip_and_addr(
return true;
 }
 
-static void dcc_control(struct mem_input *mem_input, bool enable,
+static void min10_dcc_control(struct mem_input *mem_input, bool enable,
bool independent_64b_blks)
 {
uint32_t dcc_en = enable ? 1 : 0;
@@ -381,13 +381,7 @@ static void dcc_control(struct mem_input *mem_input, bool 
enable,
PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
 }
 
-static void program_control(struct dcn10_mem_input *mi,
-   struct dc_plane_dcc_param *dcc)
-{
-   dcc_control(>base, dcc->enable, dcc->grph.independent_64b_blks);
-}
-
-static void mem_input_program_surface_config(
+static void min10_program_surface_config(
struct mem_input *mem_input,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
@@ -398,14 +392,14 @@ static void mem_input_program_surface_config(
 {
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
 
-   program_control(mi, dcc);
-   program_tiling(mi, tiling_info, format);
-   program_size_and_rotation(
+   min10_dcc_control(mem_input, dcc->enable, 
dcc->grph.independent_64b_blks);
+   min10_program_tiling(mi, tiling_info, format);
+   min10_program_size_and_rotation(
mi, rotation, format, plane_size, dcc, horizontal_mirror);
-   program_pixel_format(mi, format);
+   min10_program_pixel_format(mi, format);
 }
 
-static void program_requestor(
+static void min10_program_requestor(
struct mem_input *mem_input,
struct _vcs_dpi_display_rq_regs_st *rq_regs)
 {
@@ -440,7 +434,7 @@ static void program_requestor(
 }
 
 
-static void program_deadline(
+static void min10_program_deadline(
struct mem_input *mem_input,
struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
@@ -552,7 +546,7 @@ static void program_deadline(
ttu_attr->refcyc_per_req_delivery_pre_c);
 }
 
-static void mem_input_setup(

[PATCH 38/81] drm/amd/display: block modes that require read bw greater than 30%

[sunpeng.li]

From: Eric Yang 

Change-Id: I31d3086ac15522c9ed66e23be3d0cf6d7edf342d
Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 18 +-
 drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h   |  1 +
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 93384a3..24f8c44 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -95,6 +95,9 @@ const struct dcn_soc_bounding_box dcn10_soc_defaults = {
.vmm_page_size = 4096, /*bytes*/
.return_bus_width = 64, /*bytes*/
.max_request_size = 256, /*bytes*/
+
+   /* Depends on user class (client vs embedded, workstation, etc) 
*/
+   .percent_disp_bw_limit = 0.3f /*%*/
 };
 
 const struct dcn_ip_params dcn10_ip_defaults = {
@@ -695,6 +698,8 @@ bool dcn_validate_bandwidth(
struct dcn_bw_internal_vars *v = >dcn_bw_vars;
int i, input_idx;
int vesa_sync_start, asic_blank_end, asic_blank_start;
+   bool bw_limit_pass;
+   float bw_limit;
 
if (dcn_bw_apply_registry_override(DC_TO_CORE(>public)))
dcn_bw_sync_calcs_and_dml(DC_TO_CORE(>public));
@@ -1072,8 +1077,19 @@ bool dcn_validate_bandwidth(
dc_core->dml.soc.sr_exit_time_us = 
dc_core->dcn_soc.sr_exit_time;
}
 
+   /*
+* BW limit is set to prevent display from impacting other system 
functions
+*/
+
+   bw_limit = dc->dcn_soc.percent_disp_bw_limit * 
v->fabric_and_dram_bandwidth_vmax0p9;
+   bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
+
kernel_fpu_end();
-   return v->voltage_level != 5;
+
+   if (bw_limit_pass && v->voltage_level != 5)
+   return true;
+   else
+   return false;
 }
 
 unsigned int dcn_find_normalized_clock_vdd_Level(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h 
b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
index 499bc11..b6cc074 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h
@@ -572,6 +572,7 @@ struct dcn_soc_bounding_box {
int vmm_page_size; /*bytes*/
float dram_clock_change_latency; /*us*/
int return_bus_width; /*bytes*/
+   float percent_disp_bw_limit; /*%*/
 };
 extern const struct dcn_soc_bounding_box dcn10_soc_defaults;
 
-- 
2.7.4

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[PATCH 61/81] drm/amd/display: dc_validate_ctx refocunt fixes.

[sunpeng.li]

From: Andrey Grodzovsky 

In dc_resource_validate_ctx_copy_construct don't override dst
context refcount.

Remove extra retain to new ctx in dc_update_surfaces_and_stream

Change-Id: Ia665b3deb3c6cbe034cb31644b9a8b971d8d
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 5 +
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 +
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index e81c9d5..8e580ac 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -424,6 +424,7 @@ static void allocate_dc_stream_funcs(struct core_dc 
*core_dc)
 static void destruct(struct core_dc *dc)
 {
dc_release_validate_context(dc->current_context);
+   dc->current_context = NULL;
 
destroy_links(dc);
 
@@ -441,9 +442,6 @@ static void destruct(struct core_dc *dc)
if (dc->ctx->logger)
dal_logger_destroy(>ctx->logger);
 
-   dm_free(dc->current_context);
-   dc->current_context = NULL;
-
dm_free(dc->ctx);
dc->ctx = NULL;
 }
@@ -1656,7 +1654,6 @@ void dc_update_surfaces_and_stream(struct dc *dc,
 
if (core_dc->current_context != context) {
dc_release_validate_context(core_dc->current_context);
-   dc_retain_validate_context(context);
core_dc->current_context = context;
}
return;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index cb02c7c..a9c086a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2166,6 +2166,7 @@ void dc_resource_validate_ctx_copy_construct(
struct validate_context *dst_ctx)
 {
int i, j;
+   int ref_count = dst_ctx->ref_count;
 
*dst_ctx = *src_ctx;
 
@@ -2186,6 +2187,10 @@ void dc_resource_validate_ctx_copy_construct(
dc_surface_retain(
dst_ctx->stream_status[i].surfaces[j]);
}
+
+   /* context refcount should not be overridden */
+   dst_ctx->ref_count = ref_count;
+
 }
 
 struct clock_source *dc_resource_find_first_free_pll(
-- 
2.7.4

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[PATCH 09/81] drm/amd/display: add hyst frames for fixed refresh

[sunpeng.li]

From: Anthony Koo 

Change-Id: I084385a7647f8b602b0fa09022a21b41f72b94a4
Signed-off-by: Anthony Koo 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/modules/freesync/freesync.c| 56 ++
 1 file changed, 36 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index 7109742..c7da90f 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -37,6 +37,9 @@
 #define RENDER_TIMES_MAX_COUNT 20
 /* Threshold to exit BTR (to avoid frequent enter-exits at the lower limit) */
 #define BTR_EXIT_MARGIN 2000
+/* Number of consecutive frames to check before entering/exiting fixed 
refresh*/
+#define FIXED_REFRESH_ENTER_FRAME_COUNT 5
+#define FIXED_REFRESH_EXIT_FRAME_COUNT 5
 
 #define FREESYNC_REGISTRY_NAME "freesync_v1"
 
@@ -72,8 +75,9 @@ struct below_the_range {
 };
 
 struct fixed_refresh {
-   bool fixed_refresh_active;
-   bool program_fixed_refresh;
+   bool fixed_active;
+   bool program_fixed;
+   unsigned int frame_counter;
 };
 
 struct freesync_range {
@@ -168,8 +172,8 @@ struct mod_freesync *mod_freesync_create(struct dc *dc)
/* Create initial module folder in registry for freesync enable data */
flag.save_per_edid = true;
flag.save_per_link = false;
-   dm_write_persistent_data(core_dc->ctx, NULL, FREESYNC_REGISTRY_NAME, 
NULL, NULL,
-   0, );
+   dm_write_persistent_data(core_dc->ctx, NULL, FREESYNC_REGISTRY_NAME,
+   NULL, NULL, 0, );
flag.save_per_edid = false;
flag.save_per_link = false;
if (dm_read_persistent_data(core_dc->ctx, NULL, NULL,
@@ -422,7 +426,7 @@ static void calc_freesync_range(struct core_freesync 
*core_freesync,
min_frame_duration_in_ns) * stream->timing.pix_clk_khz),
stream->timing.h_total), 100);
 
-   /* In case of 4k free sync monitor, vmin or vmax cannot be less than 
vtotal */
+   /* vmin/vmax cannot be less than vtotal */
if (state->freesync_range.vmin < vtotal) {
/* Error of 1 is permissible */
ASSERT((state->freesync_range.vmin + 1) >= vtotal);
@@ -553,8 +557,8 @@ static void reset_freesync_state_variables(struct 
freesync_state* state)
state->btr.inserted_frame_duration_in_us = 0;
state->btr.program_btr = false;
 
-   state->fixed_refresh.fixed_refresh_active = false;
-   state->fixed_refresh.program_fixed_refresh = false;
+   state->fixed_refresh.fixed_active = false;
+   state->fixed_refresh.program_fixed = false;
 }
 /*
  * Sets freesync mode on a stream depending on current freesync state.
@@ -594,7 +598,7 @@ static bool set_freesync_on_streams(struct core_freesync 
*core_freesync,
if (core_freesync->map[map_index].user_enable.
enable_for_gaming == true &&
state->fullscreen == true &&
-   state->fixed_refresh.fixed_refresh_active == 
false) {
+   state->fixed_refresh.fixed_active == false) {
/* Enable freesync */
 
v_total_min = state->freesync_range.vmin;
@@ -1240,29 +1244,39 @@ static void update_timestamps(struct core_freesync 
*core_freesync,
state->btr.frame_counter = 0;
 
/* Exit Fixed Refresh mode */
-   } else if (state->fixed_refresh.fixed_refresh_active) {
+   } else if (state->fixed_refresh.fixed_active) {
 
-   state->fixed_refresh.program_fixed_refresh = true;
-   state->fixed_refresh.fixed_refresh_active = false;
+   state->fixed_refresh.frame_counter++;
 
+   if (state->fixed_refresh.frame_counter >
+   FIXED_REFRESH_EXIT_FRAME_COUNT) {
+   state->fixed_refresh.frame_counter = 0;
+   state->fixed_refresh.program_fixed = true;
+   state->fixed_refresh.fixed_active = false;
+   }
}
 
} else if (last_render_time_in_us > state->time.max_render_time_in_us) {
 
/* Enter Below the Range */
if (!state->btr.btr_active &&
-   
core_freesync->map[map_index].caps->btr_supported) {
+   core_freesync->map[map_index].caps->btr_supported) {
 
state->btr.program_btr = true;
state->btr.btr_active = true;
 
/* Enter Fixed Refresh mode */
-   } else if 

[PATCH 52/81] drm/amd/display: Clean dm_plane_state hooks.

[sunpeng.li]

From: Andrey Grodzovsky 

New surface is created in check only, in duplicate we just
reference exsisting surface and in destroy we release it.

Change-Id: I8a04cb7bdca9924a95929c19ad2bbbe3d80e6bd5
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 43 +++---
 1 file changed, 6 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 750e095..6aefa19 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1575,7 +1575,6 @@ const struct drm_encoder_helper_funcs 
amdgpu_dm_encoder_helper_funcs = {
 static void dm_drm_plane_reset(struct drm_plane *plane)
 {
struct dm_plane_state *amdgpu_state = NULL;
-   struct amdgpu_device *adev = plane->dev->dev_private;
 
if (plane->state)
plane->funcs->atomic_destroy_state(plane, plane->state);
@@ -1586,9 +1585,6 @@ static void dm_drm_plane_reset(struct drm_plane *plane)
plane->state = _state->base;
plane->state->plane = plane;
plane->state->rotation = DRM_ROTATE_0;
-
-   amdgpu_state->dc_surface = dc_create_surface(adev->dm.dc);
-   WARN_ON(!amdgpu_state->dc_surface);
}
else
WARN_ON(1);
@@ -1598,35 +1594,17 @@ static struct drm_plane_state *
 dm_drm_plane_duplicate_state(struct drm_plane *plane)
 {
struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
-   struct amdgpu_device *adev = plane->dev->dev_private;
 
old_dm_plane_state = to_dm_plane_state(plane->state);
dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
if (!dm_plane_state)
return NULL;
 
-   if (old_dm_plane_state->dc_surface) {
-   struct dc_surface *dc_surface = dc_create_surface(adev->dm.dc);
-   if (WARN_ON(!dc_surface))
-   return NULL;
-
-   __drm_atomic_helper_plane_duplicate_state(plane, 
_plane_state->base);
-
-   memcpy(dc_surface, old_dm_plane_state->dc_surface, 
sizeof(*dc_surface));
+   __drm_atomic_helper_plane_duplicate_state(plane, _plane_state->base);
 
-   if (old_dm_plane_state->dc_surface->gamma_correction)
-   dc_gamma_retain(dc_surface->gamma_correction);
-
-   if (old_dm_plane_state->dc_surface->in_transfer_func)
-   dc_transfer_func_retain(dc_surface->in_transfer_func);
-
-   dm_plane_state->dc_surface = dc_surface;
-
-   /*TODO Check for inferred values to be reset */
-   }
-   else {
-   WARN_ON(1);
-   return NULL;
+   if (old_dm_plane_state->dc_surface) {
+   dm_plane_state->dc_surface = old_dm_plane_state->dc_surface;
+   dc_surface_retain(dm_plane_state->dc_surface);
}
 
return _plane_state->base;
@@ -1637,17 +1615,8 @@ void dm_drm_plane_destroy_state(struct drm_plane *plane,
 {
struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
 
-   if (dm_plane_state->dc_surface) {
-   struct dc_surface *dc_surface = dm_plane_state->dc_surface;
-
-   if (dc_surface->gamma_correction)
-   dc_gamma_release(_surface->gamma_correction);
-
-   if (dc_surface->in_transfer_func)
-   dc_transfer_func_release(dc_surface->in_transfer_func);
-
-   dc_surface_release(dc_surface);
-   }
+   if (dm_plane_state->dc_surface)
+   dc_surface_release(dm_plane_state->dc_surface);
 
__drm_atomic_helper_plane_destroy_state(state);
kfree(dm_plane_state);
-- 
2.7.4

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[PATCH 20/81] drm/amd/display: Rename DCN TG specific function prefixes to tg

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: Ic6149eb2cb5bbfc33e8dc9e24c808bb7716a6715
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Charlene Liu 
Acked-by: Harry Wentland 
---
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  | 159 +
 .../amd/display/dc/dcn10/dcn10_timing_generator.h  |  53 +++
 2 files changed, 94 insertions(+), 118 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 802ace2..5927478 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -44,7 +44,7 @@
 * This is a workaround for a bug that has existed since R5xx and has not been
 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
 */
-static void tg_apply_front_porch_workaround(
+static void tgn10_apply_front_porch_workaround(
struct timing_generator *tg,
struct dc_crtc_timing *timing)
 {
@@ -57,7 +57,7 @@ static void tg_apply_front_porch_workaround(
}
 }
 
-static void dcn10_program_global_sync(
+static void tgn10_program_global_sync(
struct timing_generator *tg)
 {
struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
@@ -78,7 +78,7 @@ static void dcn10_program_global_sync(
VREADY_OFFSET, tg->dlg_otg_param.vready_offset);
 }
 
-static void dcn10_disable_stereo(struct timing_generator *tg)
+static void tgn10_disable_stereo(struct timing_generator *tg)
 {
struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
 
@@ -101,9 +101,10 @@ static void dcn10_disable_stereo(struct timing_generator 
*tg)
  * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
  * Including SYNC. Call BIOS command table to program Timings.
  */
-static void tg_program_timing_generator(
+static void tgn10_program_timing(
struct timing_generator *tg,
-   const struct dc_crtc_timing *dc_crtc_timing)
+   const struct dc_crtc_timing *dc_crtc_timing,
+   bool use_vbios)
 {
struct dc_crtc_timing patched_crtc_timing;
uint32_t vesa_sync_start;
@@ -118,11 +119,10 @@ static void tg_program_timing_generator(
uint32_t field_num = 0;
uint32_t h_div_2;
 
-
struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
 
patched_crtc_timing = *dc_crtc_timing;
-   tg_apply_front_porch_workaround(tg, _crtc_timing);
+   tgn10_apply_front_porch_workaround(tg, _crtc_timing);
 
/* Load horizontal timing */
 
@@ -253,7 +253,7 @@ static void tg_program_timing_generator(
OTG_START_POINT_CNTL, start_point,
OTG_FIELD_NUMBER_CNTL, field_num);
 
-   dcn10_program_global_sync(tg);
+   tgn10_program_global_sync(tg);
 
/* TODO
 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
@@ -273,25 +273,11 @@ static void tg_program_timing_generator(
 
 }
 
-/** tg_program_blanking
- * Only programmed part of OTG_H, OTG_V register for set_plane_config
- * Assume other OTG registers are programmed by video mode set already.
- * This function is for underlay. DCN will have new sequence.
- * This function will be removed. Need remove it from set_plane_config
- */
-
-static void tg_program_timing(struct timing_generator *tg,
-   const struct dc_crtc_timing *timing,
-   bool use_vbios)
-{
-   tg_program_timing_generator(tg, timing);
-}
-
 /**
  * unblank_crtc
  * Call ASIC Control Object to UnBlank CRTC.
  */
-static void tg_unblank_crtc(struct timing_generator *tg)
+static void tgn10_unblank_crtc(struct timing_generator *tg)
 {
struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
 
@@ -305,7 +291,7 @@ static void tg_unblank_crtc(struct timing_generator *tg)
  * Call ASIC Control Object to Blank CRTC.
  */
 
-static void tg_blank_crtc(struct timing_generator *tg)
+static void tgn10_blank_crtc(struct timing_generator *tg)
 {
struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
 
@@ -324,16 +310,16 @@ static void tg_blank_crtc(struct timing_generator *tg)
OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 0);
 }
 
-static void tg_set_blank(struct timing_generator *tg,
+static void tgn10_set_blank(struct timing_generator *tg,
bool enable_blanking)
 {
if (enable_blanking)
-   tg_blank_crtc(tg);
+   tgn10_blank_crtc(tg);
else
-   tg_unblank_crtc(tg);
+   tgn10_unblank_crtc(tg);
 }
 
-static bool tg_is_blanked(struct timing_generator *tg)
+static bool tgn10_is_blanked(struct timing_generator *tg)
 {
struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
uint32_t blank_en;
@@ -346,7 +332,7 @@ static bool tg_is_blanked(struct timing_generator *tg)
return blank_en && 

[PATCH 16/81] drm/amd/display: Enabling VSR on 4K display causes black screen

[sunpeng.li]

From: Charlene Liu 

Change-Id: I783aa77e73568c676978226f30dbecac4fe16c1f
Signed-off-by: Charlene Liu 
Reviewed-by: Anthony Koo 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index f404e4e..cc67707 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1819,7 +1819,7 @@ static void program_all_pipe_in_tree(
pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, 
!is_pipe_tree_visible(pipe_ctx));
}
 
-   if (pipe_ctx->surface->public.visible) {
+   if (pipe_ctx->surface != NULL) {
dcn10_power_on_fe(dc, pipe_ctx, context);
update_dchubp_dpp(dc, pipe_ctx, context);
}
-- 
2.7.4

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[PATCH 30/81] drm/amd/display: Commit validation set from state

[sunpeng.li]

From: Harry Wentland 

Change-Id: If474c444f6dc902b632ce068b6fac2428bac52b2
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c|  34 +++---
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 118 +
 drivers/gpu/drm/amd/display/dc/dc.h|  16 +++
 3 files changed, 152 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 13fc497..b0734bb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2681,20 +2681,22 @@ void amdgpu_dm_atomic_commit_tail(
struct drm_device *dev = state->dev;
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_display_manager *dm = >dm;
+   struct dm_atomic_state *dm_state;
uint32_t i, j;
-   uint32_t commit_streams_count = 0;
uint32_t new_crtcs_count = 0;
struct drm_crtc *crtc, *pcrtc;
struct drm_crtc_state *old_crtc_state;
-   const struct dc_stream *commit_streams[MAX_STREAMS];
struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
-   const struct dc_stream *new_stream;
+   const struct dc_stream *new_stream = NULL;
unsigned long flags;
bool wait_for_vblank = true;
struct drm_connector *connector;
struct drm_connector_state *old_conn_state;
 
drm_atomic_helper_update_legacy_modeset_state(dev, state);
+
+   dm_state = to_dm_atomic_state(state);
+
/* update changed items */
for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
struct amdgpu_crtc *acrtc;
@@ -2725,16 +2727,16 @@ void amdgpu_dm_atomic_commit_tail(
 */
 
if (modeset_required(new_state)) {
-   struct dm_connector_state *dm_state = NULL;
+   struct dm_connector_state *dm_conn_state = NULL;
new_stream = NULL;
 
if (aconnector)
-   dm_state = 
to_dm_connector_state(aconnector->base.state);
+   dm_conn_state = 
to_dm_connector_state(aconnector->base.state);
 
new_stream = create_stream_for_sink(
aconnector,
>state->mode,
-   dm_state);
+   dm_conn_state);
 
DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", 
acrtc->crtc_id, acrtc);
 
@@ -2762,6 +2764,13 @@ void amdgpu_dm_atomic_commit_tail(
if (acrtc->stream)
remove_stream(adev, acrtc);
 
+   /* TODO clean this stupid hack */
+   for (j = 0; j < dm_state->set_count; j++)
+   if (dm_state->set[j].stream->priv == acrtc) {
+   ASSERT(acrtc->stream == NULL);
+   new_stream = dm_state->set[j].stream;
+   break;
+   }
/*
 * this loop saves set mode crtcs
 * we needed to enable vblanks once all
@@ -2820,15 +2829,6 @@ void amdgpu_dm_atomic_commit_tail(
dm_error("%s: Failed to update stream scaling!\n", 
__func__);
}
 
-   list_for_each_entry(crtc, >mode_config.crtc_list, head) {
-
-   struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
-
-   if (acrtc->stream) {
-   commit_streams[commit_streams_count] = acrtc->stream;
-   ++commit_streams_count;
-   }
-   }
 
/*
 * Add streams after required streams from new and replaced streams
@@ -2857,7 +2857,8 @@ void amdgpu_dm_atomic_commit_tail(
}
 
/* DC is optimized not to do anything if 'streams' didn't change. */
-   WARN_ON(!dc_commit_streams(dm->dc, commit_streams, 
commit_streams_count));
+   WARN_ON(!dc_commit_validation_set(dm->dc, dm_state->set,
+ dm_state->set_count));
 
list_for_each_entry(crtc, >mode_config.crtc_list, head) {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
@@ -3215,6 +3216,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
}
 
new_stream = create_stream_for_sink(aconnector, 
_state->mode, dm_conn_state);
+   new_stream->priv = acrtc;
 
/*
 * we can have no stream on ACTION_SET if a display
diff --git 

[PATCH 62/81] drm/amd/display: avoid disabling opp clk before hubp is blanked.

[sunpeng.li]

From: Tony Cheng 

Change-Id: I6293b0c82073ca74fc9ace7426df291149215f90
Signed-off-by: Tony Cheng 
Reviewed-by: Eric Yang 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h |  7 +++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 18 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |  2 --
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |  8 ++--
 4 files changed, 23 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 6985a46..4da9142 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -141,6 +141,10 @@
SRII(DPP_CONTROL, DPP_TOP, 1), \
SRII(DPP_CONTROL, DPP_TOP, 2), \
SRII(DPP_CONTROL, DPP_TOP, 3), \
+   SRII(OPP_PIPE_CONTROL, OPP_PIPE, 0), \
+   SRII(OPP_PIPE_CONTROL, OPP_PIPE, 1), \
+   SRII(OPP_PIPE_CONTROL, OPP_PIPE, 2), \
+   SRII(OPP_PIPE_CONTROL, OPP_PIPE, 3), \
SR(REFCLK_CNTL), \
SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
SR(DC_IP_REQUEST_CNTL), \
@@ -188,6 +192,7 @@ struct dce_hwseq_registers {
uint32_t DCHUBP_CNTL[4];
uint32_t HUBP_CLK_CNTL[4];
uint32_t DPP_CONTROL[4];
+   uint32_t OPP_PIPE_CONTROL[4];
uint32_t REFCLK_CNTL;
uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;
uint32_t DC_IP_REQUEST_CNTL;
@@ -282,6 +287,7 @@ struct dce_hwseq_registers {
HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \
HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \
HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
+   HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\
HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 
mask_sh), \
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
@@ -346,6 +352,7 @@ struct dce_hwseq_registers {
type DPP_CLOCK_ENABLE; \
type DPPCLK_RATE_CONTROL; \
type DCHUBBUB_GLOBAL_TIMER_ENABLE; \
+   type OPP_PIPE_CLOCK_EN;\
type IP_REQUEST_EN; \
type DOMAIN0_POWER_FORCEON; \
type DOMAIN0_POWER_GATE; \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0e90e6c..18686be 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -472,9 +472,10 @@ static void reset_front_end(
struct transform *xfm = dc->res_pool->transforms[fe_idx];
struct mpcc *mpcc = dc->res_pool->mpcc[fe_idx];
struct timing_generator *tg = 
dc->res_pool->timing_generators[mpcc->opp_id];
+   unsigned int opp_id = mpcc->opp_id;
 
/*Already reset*/
-   if (mpcc->opp_id == 0xf)
+   if (opp_id == 0xf)
return;
 
tg->funcs->lock(tg);
@@ -497,8 +498,12 @@ static void reset_front_end(
 
mpcc->funcs->wait_for_idle(mpcc);
 
-   REG_UPDATE(HUBP_CLK_CNTL[fe_idx], HUBP_CLOCK_ENABLE, 0);
-   REG_UPDATE(DPP_CONTROL[fe_idx], DPP_CLOCK_ENABLE, 0);
+   REG_UPDATE(HUBP_CLK_CNTL[fe_idx],
+   HUBP_CLOCK_ENABLE, 0);
+   REG_UPDATE(DPP_CONTROL[fe_idx],
+   DPP_CLOCK_ENABLE, 0);
+   REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
+   OPP_PIPE_CLOCK_EN, 0);
 
xfm->funcs->transform_reset(xfm);
 
@@ -1211,7 +1216,12 @@ static void dcn10_power_on_fe(
pipe_ctx->pipe_idx);
 
/* enable DCFCLK current DCHUB */
-   REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx], HUBP_CLOCK_ENABLE, 1);
+   REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx],
+   HUBP_CLOCK_ENABLE, 1);
+
+   /* make sure OPP_PIPE_CLOCK_EN = 1 */
+   REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->tg->inst],
+   OPP_PIPE_CLOCK_EN, 1);
 
if (dc_surface) {
dm_logger_write(dc->ctx->logger, LOG_DC,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 9875d81..de3341d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -68,14 +68,12 @@ static void set_output_mux(struct dcn10_mpcc *mpcc10, int 
opp_id, int mpcc_id)
 {
ASSERT(mpcc10->base.opp_id == 0xf || opp_id == mpcc10->base.opp_id);
mpcc10->base.opp_id = opp_id;
-   REG_UPDATE(OPP_PIPE_CONTROL[opp_id], OPP_PIPE_CLOCK_EN, 1);
REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, mpcc_id);
 }
 
 static void reset_output_mux(struct dcn10_mpcc *mpcc10)
 {
REG_SET(MUX[mpcc10->base.opp_id], 0, MPC_OUT_MUX, 0xf);
-   

[PATCH 58/81] drm/amd/display: Release dm_state->context when state is cleared.

[sunpeng.li]

From: Andrey Grodzovsky 

Handling a use case of TEST_ONLY request from DRM where commit is
not goiing to be called. We need to release the allocated dc_validate_context
in this case.

Change-Id: I98d88703f6575a290758fa37a6b58602b5e10bb2
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 23 ++
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c|  1 +
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 88e177e..b6a04ad 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -653,12 +653,35 @@ dm_atomic_state_alloc(struct drm_device *dev)
return >base;
 }
 
+static void
+dm_atomic_state_clear(struct drm_atomic_state *state)
+{
+   struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
+
+   if (dm_state->context) {
+   dc_release_validate_context(dm_state->context);
+   dm_state->context = NULL;
+   }
+
+   drm_atomic_state_default_clear(state);
+}
+
+static void
+dm_atomic_state_alloc_free(struct drm_atomic_state *state)
+{
+   struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
+   drm_atomic_state_default_release(state);
+   kfree(dm_state);
+}
+
 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_user_framebuffer_create,
.output_poll_changed = amdgpu_output_poll_changed,
.atomic_check = amdgpu_dm_atomic_check,
.atomic_commit = amdgpu_dm_atomic_commit,
.atomic_state_alloc = dm_atomic_state_alloc,
+   .atomic_state_clear = dm_atomic_state_clear,
+   .atomic_state_free = dm_atomic_state_alloc_free
 };
 
 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = 
{
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 9c08121..15a3d01 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3312,6 +3312,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail_planes;
 
+   WARN_ON(dm_state->context);
dm_state->context = dc_get_validate_context(dc, set, set_count);
if (!dm_state->context) {
ret = -EINVAL;
-- 
2.7.4

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[PATCH 71/81] drm/amd/display: hwseq init sequence update

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: I75f76b72d998e0ee77ce22f8746be29681e60c72
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h |  8 +++-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 51 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h  |  2 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c |  1 -
 4 files changed, 20 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 4da9142..7e1d46f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -216,6 +216,11 @@ struct dce_hwseq_registers {
uint32_t DCCG_GATE_DISABLE_CNTL;
uint32_t DCCG_GATE_DISABLE_CNTL2;
uint32_t DCFCLK_CNTL;
+   uint32_t MICROSECOND_TIME_BASE_DIV;
+   uint32_t MILLISECOND_TIME_BASE_DIV;
+   uint32_t DISPCLK_FREQ_CHANGE_CNTL;
+   uint32_t RBBMIF_TIMEOUT_DIS;
+   uint32_t RBBMIF_TIMEOUT_DIS_2;
 #endif
 };
  /* set field name */
@@ -378,7 +383,8 @@ struct dce_hwseq_registers {
type DOMAIN5_PGFSM_PWR_STATUS; \
type DOMAIN6_PGFSM_PWR_STATUS; \
type DOMAIN7_PGFSM_PWR_STATUS; \
-   type DCFCLK_GATE_DIS;
+   type DCFCLK_GATE_DIS; \
+   type DCHUBBUB_GLOBAL_TIMER_REFDIV;
 #endif
 
 struct dce_hwseq_shift {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index fc46c84..eca0d53 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -24,11 +24,9 @@
  */
 
 #include "dm_services.h"
-#include "dc.h"
-#include "core_dc.h"
 #include "core_types.h"
-#include "core_status.h"
 #include "resource.h"
+#include "custom_float.h"
 #include "dcn10_hw_sequencer.h"
 #include "dce110/dce110_hw_sequencer.h"
 #include "dce/dce_hwseq.h"
@@ -39,11 +37,10 @@
 #include "timing_generator.h"
 #include "opp.h"
 #include "ipp.h"
-#include "dc_bios_types.h"
+#include "mpc.h"
 #include "raven1/DCN/dcn_1_0_offset.h"
 #include "raven1/DCN/dcn_1_0_sh_mask.h"
 #include "vega10/soc15ip.h"
-#include "custom_float.h"
 #include "reg_helper.h"
 
 #define CTX \
@@ -219,31 +216,15 @@ static void bios_golden_init(struct core_dc *dc)
}
 }
 
-/*
- * This should be done within BIOS, we are doing it for maximus only
- */
-static void dchubup_setup_timer(struct dce_hwseq *hws)
-{
-   REG_WRITE(REFCLK_CNTL, 0);
-
-   REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
-}
-
-static void init_hw(struct core_dc *dc)
+static void dcn10_init_hw(struct core_dc *dc)
 {
int i;
-   struct transform *xfm;
-   struct abm *abm;
+   struct abm *abm = dc->res_pool->abm;
struct dce_hwseq *hws = dc->hwseq;
 
-#if 1
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
-   dchubup_setup_timer(dc->hwseq);
-
-   /* TODO: dchubp_map_fb_to_mc will be moved to dchub interface
-* between dc and kmd
-*/
-   /*dchubp_map_fb_to_mc(dc->hwseq);*/
+   REG_WRITE(REFCLK_CNTL, 0);
+   REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, 
DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 
if (!dc->public.debug.disable_clock_gate) {
@@ -259,15 +240,9 @@ static void init_hw(struct core_dc *dc)
return;
}
/* end of FPGA. Below if real ASIC */
-#endif
 
bios_golden_init(dc);
 
-   for (i = 0; i < dc->res_pool->pipe_count; i++) {
-   xfm = dc->res_pool->transforms[i];
-   xfm->funcs->transform_reset(xfm);
-   }
-
for (i = 0; i < dc->link_count; i++) {
/* Power up AND update implementation according to the
 * required signal (which may be different from the
@@ -279,12 +254,12 @@ static void init_hw(struct core_dc *dc)
}
 
for (i = 0; i < dc->res_pool->pipe_count; i++) {
-   struct timing_generator *tg =
-   dc->res_pool->timing_generators[i];
-   struct mpcc *mpcc =
-   dc->res_pool->mpcc[i];
+   struct transform *xfm = dc->res_pool->transforms[i];
+   struct timing_generator *tg = 
dc->res_pool->timing_generators[i];
+   struct mpcc *mpcc = dc->res_pool->mpcc[i];
struct mpcc_cfg mpcc_cfg;
 
+   xfm->funcs->transform_reset(xfm);
mpcc_cfg.opp_id = 0xf;
mpcc_cfg.top_dpp_id = 0xf;
mpcc_cfg.bot_mpcc_id = 0xf;
@@ -305,7 +280,6 @@ static void init_hw(struct core_dc *dc)

[PATCH 65/81] drm/amd/display: ensure OTG is locked before proceeding

[sunpeng.li]

From: Tony Cheng 

also remove tg lock at init_hw as not all OTG is running

Change-Id: Ia95a2b8a603f3e6d8ddbb83c9be07d36d719270a
Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 --
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 4 
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h | 2 ++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 18686be..82a96de 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -283,13 +283,11 @@ static void init_hw(struct core_dc *dc)
dc->res_pool->mpcc[i];
struct mpcc_cfg mpcc_cfg;
 
-   tg->funcs->lock(tg);
mpcc_cfg.opp_id = 0xf;
mpcc_cfg.top_dpp_id = 0xf;
mpcc_cfg.bot_mpcc_id = 0xf;
mpcc_cfg.top_of_tree = true;
mpcc->funcs->set(mpcc, _cfg);
-   tg->funcs->unlock(tg);
 
tg->funcs->disable_vga(tg);
/* Blank controller using driver code instead of
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index e1899f5..12d7f35 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -573,6 +573,10 @@ static void tgn10_lock(struct timing_generator *tg)
OTG_MASTER_UPDATE_LOCK_SEL, tg->inst);
REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
OTG_MASTER_UPDATE_LOCK, 1);
+
+   REG_WAIT(OTG_MASTER_UPDATE_LOCK,
+   UPDATE_LOCK_STATUS, 1,
+   1, 100);
 }
 
 static void tgn10_unlock(struct timing_generator *tg)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
index e287b2b..747e821 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
@@ -140,6 +140,7 @@ struct dcn_tg_registers {
SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\
SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\
SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
+   SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, 
mask_sh),\
@@ -233,6 +234,7 @@ struct dcn_tg_registers {
type OTG_BLANK_DE_MODE;\
type OTG_CURRENT_BLANK_STATE;\
type OTG_MASTER_UPDATE_LOCK;\
+   type UPDATE_LOCK_STATUS;\
type OTG_UPDATE_PENDING;\
type OTG_MASTER_UPDATE_LOCK_SEL;\
type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\
-- 
2.7.4

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[PATCH 13/81] drm/amd/display: Change max OPP

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: I168eae802586fda2bdd0af7ab8fdc3921937a5d1
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
index fff2674..6a90a8b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
@@ -30,7 +30,7 @@
 #define TO_DCN10_MPCC(mpcc_base) \
container_of(mpcc_base, struct dcn10_mpcc, base)
 
-#define MAX_OPP 4
+#define MAX_OPP 6
 
 #define MPC_COMMON_REG_LIST_DCN1_0(inst) \
SRII(MUX, MPC_OUT, inst),\
-- 
2.7.4

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[PATCH 33/81] drm/amd/display: Update atomic state hooks.

[sunpeng.li]

From: Andrey Grodzovsky 

Reimplement atomic_state_alloc and atomic_state_clear to
release validate_ctx.

Change-Id: I57be6be9d570a90ab355731eed4defe53f3f3fcb
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 25 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c|  2 +-
 2 files changed, 11 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c2a6f2e..d0651b6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -648,33 +648,29 @@ dm_atomic_state_alloc(struct drm_device *dev)
return >base;
 }
 
-void dm_atomic_state_clear(struct drm_atomic_state *s)
-{
-   struct dm_atomic_state *state = to_dm_atomic_state(s);
-   drm_atomic_state_default_clear(>base);
-}
-
 
-static void dm_atomic_state_free(struct drm_atomic_state *state)
+void dm_atomic_state_clear(struct drm_atomic_state *state)
 {
struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
int i, j;
 
-   drm_atomic_state_default_release(state);
-
for (i = 0; i < dm_state->set_count; i++) {
for (j = 0; j < dm_state->set[i].surface_count; j++) {
dc_surface_release(dm_state->set[i].surfaces[j]);
+   dm_state->set[i].surfaces[j] = NULL;
}
-   }
 
-   for (i = 0; i < dm_state->set_count; i++)
dc_stream_release(dm_state->set[i].stream);
+   dm_state->set[i].stream = NULL;
+   }
+   dm_state->set_count = 0;
 
-   kfree(dm_state);
-}
-
+   dc_resource_validate_ctx_destruct(dm_state->context);
+   dm_free(dm_state->context);
+   dm_state->context = NULL;
 
+   drm_atomic_state_default_clear(state);
+}
 
 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_user_framebuffer_create,
@@ -683,7 +679,6 @@ static const struct drm_mode_config_funcs 
amdgpu_dm_mode_funcs = {
.atomic_commit = drm_atomic_helper_commit,
.atomic_state_alloc = dm_atomic_state_alloc,
.atomic_state_clear = dm_atomic_state_clear,
-   .atomic_state_free = dm_atomic_state_free,
 };
 
 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = 
{
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 8445337..2a5c7b1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2859,6 +2859,7 @@ void amdgpu_dm_atomic_commit_tail(
/* DC is optimized not to do anything if 'streams' didn't change. */
WARN_ON(!dc_commit_context(dm->dc, dm_state->context));
 
+
list_for_each_entry(crtc, >mode_config.crtc_list, head) {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 
@@ -3233,7 +3234,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
__func__, acrtc->base.base.id);
break;
}
-   new_stream->priv = acrtc;
 
new_streams[new_stream_count] = new_stream;
dm_state->set_count = update_in_val_sets_stream(
-- 
2.7.4

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[PATCH 74/81] drm/amd/display: link training fallback actions

[sunpeng.li]

From: Ding Wang 

Change-Id: Ic9a00fdffa1809d00a725a067ce9d97ae0df0586
Signed-off-by: Ding Wang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   | 239 +
 drivers/gpu/drm/amd/display/dc/dc.h|   2 +-
 drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h|   8 +
 .../drm/amd/display/include/link_service_types.h   |   9 +
 4 files changed, 215 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 98048fe..dd3f57f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -731,7 +731,7 @@ static enum hw_dp_training_pattern get_supported_tp(struct 
core_link *link)
return HW_DP_TRAINING_PATTERN_2;
 }
 
-static bool perform_channel_equalization_sequence(
+static enum link_training_result perform_channel_equalization_sequence(
struct core_link *link,
struct link_training_settings *lt_settings)
 {
@@ -777,19 +777,19 @@ static bool perform_channel_equalization_sequence(
 
/* 5. check CR done*/
if (!is_cr_done(lane_count, dpcd_lane_status))
-   return false;
+   return LINK_TRAINING_EQ_FAIL_CR;
 
/* 6. check CHEQ done*/
if (is_ch_eq_done(lane_count,
dpcd_lane_status,
_lane_status_updated))
-   return true;
+   return LINK_TRAINING_SUCCESS;
 
/* 7. update VS/PE/PC2 in lt_settings*/
update_drive_settings(lt_settings, req_settings);
}
 
-   return false;
+   return LINK_TRAINING_EQ_FAIL_EQ;
 
 }
 
@@ -943,18 +943,17 @@ static inline bool perform_link_training_int(
return status;
 }
 
-bool dc_link_dp_perform_link_training(
+enum link_training_result dc_link_dp_perform_link_training(
struct dc_link *link,
const struct dc_link_settings *link_setting,
bool skip_video_pattern)
 {
+   enum link_training_result status = LINK_TRAINING_SUCCESS;
struct core_link *core_link = DC_LINK_TO_CORE(link);
-   bool status;
 
char *link_rate = "Unknown";
struct link_training_settings lt_settings;
 
-   status = false;
memset(_settings, '\0', sizeof(lt_settings));
 
lt_settings.link_settings.link_rate = link_setting->link_rate;
@@ -976,16 +975,23 @@ bool dc_link_dp_perform_link_training(
 
/* 2. perform link training (set link training done
 *  to false is done as well)*/
-   if (perform_clock_recovery_sequence(core_link, _settings)) {
-
-   if (perform_channel_equalization_sequence(core_link,
-   _settings))
-   status = true;
+   if (!perform_clock_recovery_sequence(core_link, _settings)) {
+   status = LINK_TRAINING_CR_FAIL;
+   } else {
+   status = perform_channel_equalization_sequence(core_link,
+   _settings);
}
 
-   if (status || !skip_video_pattern)
-   status = perform_link_training_int(core_link,
-   _settings, status);
+   if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
+   if (!perform_link_training_int(core_link,
+   _settings,
+   status == LINK_TRAINING_SUCCESS)) {
+   /* the next link training setting in this case
+* would be the same as CR failure case.
+*/
+   status = LINK_TRAINING_CR_FAIL;
+   }
+   }
 
/* 6. print status message*/
switch (lt_settings.link_settings.link_rate) {
@@ -1013,7 +1019,9 @@ bool dc_link_dp_perform_link_training(
CONN_MSG_LT(core_link, "%sx%d %s VS=%d, PE=%d",
link_rate,
lt_settings.link_settings.lane_count,
-   status ? "pass" : "fail",
+   (status ==  LINK_TRAINING_SUCCESS) ? "pass" :
+   ((status == LINK_TRAINING_CR_FAIL) ? "CR failed" :
+   "EQ failed"),
lt_settings.lane_settings[0].VOLTAGE_SWING,
lt_settings.lane_settings[0].PRE_EMPHASIS);
 
@@ -1035,7 +1043,7 @@ bool perform_link_training_with_retries(
if (dc_link_dp_perform_link_training(
>public,
link_setting,
-   skip_video_pattern))
+   skip_video_pattern) == LINK_TRAINING_SUCCESS)
return true;
 

[PATCH 41/81] drm/amd/display: Refactor dc_commit_streams

[sunpeng.li]

From: Andrey Grodzovsky 

Change it to sue dc_commit_context. dc_commit_context
is used directly from Linux DM.

Change-Id: I1bd98f7579afe1c3859b78bf04612f81c982b200
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 99 +---
 1 file changed, 41 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2f93f0e..52077d3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -913,33 +913,22 @@ bool dc_enable_stereo(
return ret;
 }
 
-/* TODO operate on validation set (or something like it) */
-bool dc_commit_context(struct dc *dc, struct validate_context *context)
+
+/*
+ * Applies given context to HW and copy it into current context.
+ * It's up to the user to release the src context afterwards.
+ */
+static bool dc_commit_context_no_check(struct dc *dc, struct validate_context 
*context)
 {
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dc_bios *dcb = core_dc->ctx->dc_bios;
enum dc_status result = DC_ERROR_UNEXPECTED;
struct pipe_ctx *pipe;
int i, j, k, l;
+   const struct dc_stream *dc_streams[MAX_STREAMS] = {0};
 
-   if (!context)
-   dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
-   "%s: dc_commit_context with no context!\n",
-   __func__);
-
-   if (false == context_changed(core_dc, context))
-   return DC_OK;
-
-   dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
-   __func__, context->stream_count);
-
-   for (i = 0; i < context->stream_count; i++) {
-   const struct dc_stream *stream = >streams[i]->public;
-
-   dc_stream_log(stream,
-   core_dc->ctx->logger,
-   LOG_DC);
-   }
+   for (i = 0; i < context->stream_count; i++)
+   dc_streams[i] =  >streams[i]->public;
 
if (!dcb->funcs->is_accelerated_mode(dcb))
core_dc->hwss.enable_accelerated_mode(core_dc);
@@ -981,22 +970,49 @@ bool dc_commit_context(struct dc *dc, struct 
validate_context *context)
context->streams[i]->public.timing.pix_clk_khz);
}
 
+   dc_enable_stereo(dc, context, dc_streams, context->stream_count);
+
dc_resource_validate_ctx_copy_construct(context, 
core_dc->current_context);
 
return (result == DC_OK);
 }
 
+bool dc_commit_context(struct dc *dc, struct validate_context *context)
+{
+   enum dc_status result = DC_ERROR_UNEXPECTED;
+   struct core_dc *core_dc = DC_TO_CORE(dc);
+   int i;
+
+   if (false == context_changed(core_dc, context))
+   return DC_OK;
+
+   dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
+   __func__, context->stream_count);
+
+   for (i = 0; i < context->stream_count; i++) {
+   const struct dc_stream *stream = >streams[i]->public;
+
+   dc_stream_log(stream,
+   core_dc->ctx->logger,
+   LOG_DC);
+   }
+
+   result = dc_commit_context_no_check(dc, context);
+
+   return (result == DC_OK);
+}
+
+
 bool dc_commit_streams(
struct dc *dc,
const struct dc_stream *streams[],
uint8_t stream_count)
 {
struct core_dc *core_dc = DC_TO_CORE(dc);
-   struct dc_bios *dcb = core_dc->ctx->dc_bios;
enum dc_status result = DC_ERROR_UNEXPECTED;
struct validate_context *context;
struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
-   int i, j;
+   int i;
 
if (false == streams_changed(core_dc, streams, stream_count))
return DC_OK;
@@ -1039,43 +1055,10 @@ bool dc_commit_streams(
goto fail;
}
 
-   if (!dcb->funcs->is_accelerated_mode(dcb)) {
-   core_dc->hwss.enable_accelerated_mode(core_dc);
-   }
-
-   if (result == DC_OK) {
-   result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
-   }
-
-   program_timing_sync(core_dc, context);
-
-   for (i = 0; i < context->stream_count; i++) {
-   const struct core_sink *sink = context->streams[i]->sink;
-
-   for (j = 0; j < context->stream_status[i].surface_count; j++) {
-   struct core_surface *surface =
-   
DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
-
-   core_dc->hwss.apply_ctx_for_surface(core_dc, surface, 
context);
-   }
+   result = dc_commit_context_no_check(dc, context);
 
-   

[PATCH 44/81] drm/amd/display: get dal1.1 to run

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: Ieb0a201e5a902dff53a019ed61a886115eb2248c
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h   | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 761dba3..6985a46 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -275,7 +275,7 @@ struct dce_hwseq_registers {
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
-   HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, OTG0_),\
+   HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, 
mask_sh), \
HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, 
mask_sh), \
HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, 
mask_sh), \
HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh), \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index e6f2220..669ac4b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -784,7 +784,7 @@ static void oppn10_program_color_matrix(struct dcn10_opp 
*oppn10,
}
 }
 
-void oppn10_set_output_csc_adjustment(
+static void oppn10_set_output_csc_adjustment(
struct output_pixel_processor *opp,
const struct out_csc_color_matrix *tbl_entry)
 {
-- 
2.7.4

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[PATCH 32/81] drm/amd/display: Use validate_context from atomic_check in commit

[sunpeng.li]

From: Harry Wentland 

Change-Id: Ida1fba58e640e14f81a626309e8906f9d526ee75
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c| 18 --
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 71 +++---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c|  6 +-
 drivers/gpu/drm/amd/display/dc/dc.h|  5 +-
 4 files changed, 40 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 396fd31..8445337 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2771,6 +2771,7 @@ void amdgpu_dm_atomic_commit_tail(
new_stream = dm_state->set[j].stream;
break;
}
+
/*
 * this loop saves set mode crtcs
 * we needed to enable vblanks once all
@@ -2829,7 +2830,6 @@ void amdgpu_dm_atomic_commit_tail(
dm_error("%s: Failed to update stream scaling!\n", 
__func__);
}
 
-
/*
 * Add streams after required streams from new and replaced streams
 * are removed from freesync module
@@ -2857,15 +2857,19 @@ void amdgpu_dm_atomic_commit_tail(
}
 
/* DC is optimized not to do anything if 'streams' didn't change. */
-   WARN_ON(!dc_commit_validation_set(dm->dc, dm_state->set,
- dm_state->set_count));
+   WARN_ON(!dc_commit_context(dm->dc, dm_state->context));
 
list_for_each_entry(crtc, >mode_config.crtc_list, head) {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 
-   if (acrtc->stream != NULL)
-   acrtc->otg_inst =
-   
dc_stream_get_status(acrtc->stream)->primary_otg_inst;
+   if (acrtc->stream != NULL) {
+   const struct dc_stream_status *status = 
dc_stream_get_status(acrtc->stream);
+
+   if (!status)
+   DC_ERR("got no status for stream %p on 
acrtc%p\n", acrtc->stream, acrtc);
+   else
+   acrtc->otg_inst = status->primary_otg_inst;
+   }
}
 
for (i = 0; i < new_crtcs_count; i++) {
@@ -3048,6 +3052,7 @@ static uint32_t update_in_val_sets_stream(
} else {
/* update. relase old stream */
dc_stream_release(old_stream);
+
}
 
return set_count;
@@ -3228,6 +3233,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
__func__, acrtc->base.base.id);
break;
}
+   new_stream->priv = acrtc;
 
new_streams[new_stream_count] = new_stream;
dm_state->set_count = update_in_val_sets_stream(
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index b50fc0d..90a3150 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -841,18 +841,17 @@ static void program_timing_sync(
}
 }
 
-static bool set_changed(
+static bool context_changed(
struct core_dc *dc,
-   const struct dc_validation_set set[],
-   uint8_t set_count)
+   struct validate_context *context)
 {
uint8_t i;
 
-   if (set_count != dc->current_context->stream_count)
+   if (context->stream_count != dc->current_context->stream_count)
return true;
 
for (i = 0; i < dc->current_context->stream_count; i++) {
-   if (>current_context->streams[i]->public != set[i].stream)
+   if (>current_context->streams[i]->public != 
>streams[i]->public)
return true;
}
 
@@ -915,55 +914,37 @@ bool dc_enable_stereo(
 }
 
 /* TODO operate on validation set (or something like it) */
-bool dc_commit_validation_set(
-   const struct dc *dc,
-   const struct dc_validation_set set[],
-   uint8_t set_count)
+bool dc_commit_context(struct dc *dc, struct validate_context *context)
 {
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dc_bios *dcb = core_dc->ctx->dc_bios;
enum dc_status result = DC_ERROR_UNEXPECTED;
-   struct validate_context *context;
struct pipe_ctx *pipe;
int i, j, k, l;
 
-   /* TODO check validation set changed */
-   if (false == set_changed(core_dc, set, set_count))
+   if (!context)
+   

[PATCH 59/81] drm/amd/display: Fix eDP power isn't off when lid close

[sunpeng.li]

From: John Wu 

Change-Id: I7acda62e64f358f3a19040cded97e1278b98e5a5
Signed-off-by: John Wu 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 4f46ff1..0092e70 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -112,8 +112,10 @@ void dp_disable_link_phy(struct core_link *link, enum 
signal_type signal)
if (!link->wa_flags.dp_keep_receiver_powered)
dp_receiver_power_ctrl(link, false);
 
-   if (signal == SIGNAL_TYPE_EDP)
+   if (signal == SIGNAL_TYPE_EDP) {
link->link_enc->funcs->backlight_control(link->link_enc, false);
+   link->link_enc->funcs->power_control(link->link_enc, false);
+   }
 
link->link_enc->funcs->disable_output(link->link_enc, signal);
 
-- 
2.7.4

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[PATCH 03/81] drm/amd/display: Make mode_config_funcs const

[sunpeng.li]

From: Harry Wentland 

Change-Id: I33cb540471368b4013261b658770e6207870f262
Signed-off-by: Harry Wentland 
Reviewed-by: Andrey Grodzovsky 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index bd01a45..e856f62 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -634,8 +634,7 @@ const struct amdgpu_ip_block_version dm_ip_block =
.funcs = _dm_funcs,
 };
 
-/* TODO: it is temporary non-const, should fixed later */
-static struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
+static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_user_framebuffer_create,
.output_poll_changed = amdgpu_output_poll_changed,
.atomic_check = amdgpu_dm_atomic_check,
-- 
2.7.4

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[PATCH 07/81] drm/amd/display: fix dcn pipe reset sequence

[sunpeng.li]

From: Dmytro Laktyushkin 

This change fixes dcn10 front end reset sequence. Previously we
would reset front end during flip which led to issues
in certain MPO and 4k/5k scenarios. We would also never properly
power gate our front end.

Change-Id: I54d1759c8024eb150e35ee29d29f396b69668d1d
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Charlene Liu 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c|   2 +-
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  19 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  22 +-
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |   7 +
 drivers/gpu/drm/amd/display/dc/dc.h|   3 -
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  17 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 226 ++---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |  17 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h   |   4 +-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  |   6 +-
 .../amd/display/dc/dcn10/dcn10_timing_generator.h  |   4 +
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h|   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   2 +-
 13 files changed, 155 insertions(+), 175 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 10ffe7f..fb5afba 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -2544,7 +2544,7 @@ static void amdgpu_dm_do_flip(
surface_updates->flip_addr = 
 
 
-   dc_update_surfaces_for_stream(adev->dm.dc, surface_updates, 1, 
acrtc->stream);
+   dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, 
acrtc->stream, NULL);
 
DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
 __func__,
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 3ec702f..00961bc 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -511,12 +511,14 @@ static void split_stream_across_pipes(
struct pipe_ctx *primary_pipe,
struct pipe_ctx *secondary_pipe)
 {
+   int pipe_idx = secondary_pipe->pipe_idx;
+
if (!primary_pipe->surface)
return;
 
-   secondary_pipe->stream = primary_pipe->stream;
-   secondary_pipe->tg = primary_pipe->tg;
+   *secondary_pipe = *primary_pipe;
 
+   secondary_pipe->pipe_idx = pipe_idx;
secondary_pipe->mpcc = pool->mpcc[secondary_pipe->pipe_idx];
secondary_pipe->mi = pool->mis[secondary_pipe->pipe_idx];
secondary_pipe->ipp = pool->ipps[secondary_pipe->pipe_idx];
@@ -528,8 +530,6 @@ static void split_stream_across_pipes(
}
primary_pipe->bottom_pipe = secondary_pipe;
secondary_pipe->top_pipe = primary_pipe;
-   secondary_pipe->surface = primary_pipe->surface;
-   secondary_pipe->pipe_dlg_param = primary_pipe->pipe_dlg_param;
 
resource_build_scaling_params(primary_pipe);
resource_build_scaling_params(secondary_pipe);
@@ -1011,10 +1011,13 @@ bool dcn_validate_bandwidth(
dcn_bw_calc_rq_dlg_ttu(dc, v, 
hsplit_pipe);
} else if (hsplit_pipe && hsplit_pipe->surface 
== pipe->surface) {
/* merge previously split pipe */
-   if (pipe->bottom_pipe->bottom_pipe)
-   
pipe->bottom_pipe->bottom_pipe->top_pipe = pipe;
-   memset(pipe->bottom_pipe, 0, 
sizeof(*pipe->bottom_pipe));
-   pipe->bottom_pipe = 
pipe->bottom_pipe->bottom_pipe;
+   pipe->bottom_pipe = 
hsplit_pipe->bottom_pipe;
+   if (hsplit_pipe->bottom_pipe)
+   
hsplit_pipe->bottom_pipe->top_pipe = pipe;
+   hsplit_pipe->surface = NULL;
+   hsplit_pipe->stream = NULL;
+   hsplit_pipe->top_pipe = NULL;
+   hsplit_pipe->bottom_pipe = NULL;
resource_build_scaling_params(pipe);
}
/* for now important to do this after pipe 
split for building e2e params */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 18fde50..2f481ef 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -963,11 

[PATCH 64/81] drm/amd/display: Get freesync properties

[sunpeng.li]

From: Harry Wentland 

Eventually we should create proper atomic properties for freesync
but currently freesync is broken and we still have the legacy
properties. Simply return the legacy properties.

Change-Id: Ie5b8fb77e9886ef9d56b321317f78098522d52f6
Signed-off-by: Harry Wentland 
Reviewed-by: Jordan Lazare 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 15a3d01..cdecd2f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -1228,6 +1228,7 @@ int amdgpu_dm_connector_atomic_get_property(
struct dm_connector_state *dm_state =
to_dm_connector_state(state);
int ret = -EINVAL;
+   int i;
 
if (property == dev->mode_config.scaling_mode_property) {
switch (dm_state->scaling) {
@@ -1255,14 +1256,14 @@ int amdgpu_dm_connector_atomic_get_property(
} else if (property == adev->mode_info.underscan_property) {
*val = dm_state->underscan_enable;
ret = 0;
-   } else if (property == adev->mode_info.freesync_property) {
-   //TODO
-   *val = 0;
-   ret = 0;
-   } else if (property == adev->mode_info.freesync_capable_property) {
-   //TODO
-   *val = 0;
-   ret = 0;
+   } else if ((property == adev->mode_info.freesync_property) ||
+  (property == adev->mode_info.freesync_capable_property)) {
+   for (i = 0; i < connector->base.properties->count; i++) {
+   if (connector->base.properties->properties[i] == 
property) {
+   *val = connector->base.properties->values[i];
+   ret = 0;
+   }
+   }
}
return ret;
 }
-- 
2.7.4

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[PATCH 56/81] drm/amd/display: Introduce refcount for dc_validate_context

[sunpeng.li]

From: Andrey Grodzovsky 

Linux requires to be able to release allocated context
in case it was never commited.

Change-Id: I6b0faa72c995d77c0bb21ba8aabb9bdc3b0e2770
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c| 64 ++---
 drivers/gpu/drm/amd/display/dc/dc.h |  4 ++
 drivers/gpu/drm/amd/display/dc/inc/core_types.h |  2 +
 3 files changed, 54 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 4f93029..e81c9d5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -423,7 +423,7 @@ static void allocate_dc_stream_funcs(struct core_dc 
*core_dc)
 
 static void destruct(struct core_dc *dc)
 {
-   dc_resource_validate_ctx_destruct(dc->current_context);
+   dc_release_validate_context(dc->current_context);
 
destroy_links(dc);
 
@@ -467,6 +467,8 @@ static bool construct(struct core_dc *dc,
goto val_ctx_fail;
}
 
+   dc->current_context->ref_count++;
+
dc_ctx->cgs_device = init_params->cgs_device;
dc_ctx->driver_context = init_params->driver;
dc_ctx->dc = >public;
@@ -683,6 +685,8 @@ struct validate_context *dc_get_validate_context(
if (context == NULL)
goto context_alloc_fail;
 
+   ++context->ref_count;
+
if (!is_validation_required(core_dc, set, set_count)) {

dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
return context;
@@ -698,8 +702,7 @@ struct validate_context *dc_get_validate_context(
__func__,
result);
 
-   dc_resource_validate_ctx_destruct(context);
-   dm_free(context);
+   dc_release_validate_context(context);
context = NULL;
}
 
@@ -720,6 +723,8 @@ bool dc_validate_resources(
if (context == NULL)
goto context_alloc_fail;
 
+   ++context->ref_count;
+
result = core_dc->res_pool->funcs->validate_with_context(
core_dc, set, set_count, context, NULL);
 
@@ -731,8 +736,7 @@ bool dc_validate_resources(
result);
}
 
-   dc_resource_validate_ctx_destruct(context);
-   dm_free(context);
+   dc_release_validate_context(context);
context = NULL;
 
return result == DC_OK;
@@ -750,11 +754,12 @@ bool dc_validate_guaranteed(
if (context == NULL)
goto context_alloc_fail;
 
+   ++context->ref_count;
+
result = core_dc->res_pool->funcs->validate_guaranteed(
core_dc, stream, context);
 
-   dc_resource_validate_ctx_destruct(context);
-   dm_free(context);
+   dc_release_validate_context(context);
 
 context_alloc_fail:
if (result != DC_OK) {
@@ -972,8 +977,10 @@ static bool dc_commit_context_no_check(struct dc *dc, 
struct validate_context *c
 
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
-   dc_resource_validate_ctx_destruct(core_dc->current_context);
-   dm_free(core_dc->current_context);
+   dc_release_validate_context(core_dc->current_context);
+
+   dc_retain_validate_context(context);
+
core_dc->current_context = context;
 
return (result == DC_OK);
@@ -1045,6 +1052,8 @@ bool dc_commit_streams(
if (context == NULL)
goto context_alloc_fail;
 
+   ++context->ref_count;
+
result = core_dc->res_pool->funcs->validate_with_context(
core_dc, set, stream_count, context, 
core_dc->current_context);
if (result != DC_OK){
@@ -1053,7 +1062,6 @@ bool dc_commit_streams(
__func__,
result);
BREAK_TO_DEBUGGER();
-   dc_resource_validate_ctx_destruct(context);
goto fail;
}
 
@@ -1062,7 +1070,7 @@ bool dc_commit_streams(
return (result == DC_OK);
 
 fail:
-   dm_free(context);
+   dc_release_validate_context(context);
 
 context_alloc_fail:
return (result == DC_OK);
@@ -1155,6 +1163,23 @@ bool dc_commit_surfaces_to_stream(
return true;
 }
 
+void dc_retain_validate_context(struct validate_context *context)
+{
+   ASSERT(context->ref_count > 0);
+   ++context->ref_count;
+}
+
+void dc_release_validate_context(struct validate_context *context)
+{
+   ASSERT(context->ref_count > 0);
+   --context->ref_count;
+
+   if (context->ref_count == 0) {
+   dc_resource_validate_ctx_destruct(context);
+   dm_free(context);
+   }

[PATCH 43/81] drm/amd/display: Fix MPO visual confirm

[sunpeng.li]

From: Anthony Koo 

1. Need to blend non-active area to show visual confirm borders
2. Set number of Visual Confirm lines based on pipe instance
3. Set Different colors representing surface format of bottom most plan

Change-Id: I800a99f80ed2829e3e18fd8b4cb60ff9b396fd30
Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c  |  6 ---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 16 
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h   |  8 ++--
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  8 +++-
 .../drm/amd/display/dc/dce110/dce110_transform_v.c |  4 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 45 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |  5 ++-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  2 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.c | 13 ---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_transform.h |  1 +
 10 files changed, 77 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 6cd1e93..7b1f249 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -59,12 +59,6 @@ void color_space_to_black_color(
enum dc_color_space colorspace,
struct tg_color *black_color)
 {
-   if (dc->public.debug.surface_visual_confirm) {
-   *black_color =
-   black_color_format[BLACK_COLOR_FORMAT_DEBUG];
-   return;
-   }
-
switch (colorspace) {
case COLOR_SPACE_YCBCR601:
case COLOR_SPACE_YCBCR709:
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 9202bbe..cb02c7c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -399,11 +399,11 @@ static enum pixel_format 
convert_pixel_format_to_dalsurface(
break;
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
-   dal_pixel_format = PIXEL_FORMAT_420BPP12;
+   dal_pixel_format = PIXEL_FORMAT_420BPP8;
break;
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
-   dal_pixel_format = PIXEL_FORMAT_420BPP15;
+   dal_pixel_format = PIXEL_FORMAT_420BPP10;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
default:
@@ -433,8 +433,8 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
struct scaler_data *data = _ctx->scl_data;
struct rect surf_src = surface->src_rect;
struct rect clip = { 0 };
-   int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
-   || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
+   int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
+   || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
bool pri_split = pipe_ctx->bottom_pipe &&
pipe_ctx->bottom_pipe->surface == pipe_ctx->surface;
bool sec_split = pipe_ctx->top_pipe &&
@@ -637,8 +637,8 @@ static void calculate_scaling_ratios(struct pipe_ctx 
*pipe_ctx)
pipe_ctx->scl_data.ratios.horz_c = pipe_ctx->scl_data.ratios.horz;
pipe_ctx->scl_data.ratios.vert_c = pipe_ctx->scl_data.ratios.vert;
 
-   if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP12
-   || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP15) {
+   if (pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP8
+   || pipe_ctx->scl_data.format == PIXEL_FORMAT_420BPP10) {
pipe_ctx->scl_data.ratios.horz_c.value /= 2;
pipe_ctx->scl_data.ratios.vert_c.value /= 2;
}
@@ -648,8 +648,8 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx 
*pipe_ctx, struct view *r
 {
struct scaler_data *data = _ctx->scl_data;
struct rect src = pipe_ctx->surface->public.src_rect;
-   int vpc_div = (data->format == PIXEL_FORMAT_420BPP12
-   || data->format == PIXEL_FORMAT_420BPP15) ? 2 : 1;
+   int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
+   || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
 
 
if (pipe_ctx->surface->public.rotation == ROTATION_ANGLE_90 ||
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h 
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 94fb930..05f030e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -214,15 +214,15 @@ enum pixel_format {
PIXEL_FORMAT_ARGB2101010_XRBIAS,
PIXEL_FORMAT_FP16,

[PATCH 46/81] drm/amd/display: dal1.1 opp prog update

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: Ieafde1bbc30f5d4dd06136b9940d8c85d8d669f6
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
index eb99c31..de0b631 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
@@ -138,10 +138,11 @@
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \
OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 
mask_sh), \
OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 
mask_sh), \
+   OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
+   OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \
OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \
OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \
OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \
-   OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \
OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \
OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \
OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \
@@ -353,8 +354,7 @@
OPP_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \
OPP_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \
OPP_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
-   OPP_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
-   OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh)
+   OPP_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh)
 
 #define OPP_DCN10_REG_FIELD_LIST(type) \
type CM_OCSC_C11; \
-- 
2.7.4

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[PATCH 29/81] drm/amd/display: Add correct retain/release

[sunpeng.li]

From: Harry Wentland 

Needed by objs in dm_atomic_state

Change-Id: I78ccd1fba5022dd686b5df290534b86fa089e30a
Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c   | 10 ++
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c |  6 ++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1b69848..c2a6f2e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -658,9 +658,19 @@ void dm_atomic_state_clear(struct drm_atomic_state *s)
 static void dm_atomic_state_free(struct drm_atomic_state *state)
 {
struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
+   int i, j;
 
drm_atomic_state_default_release(state);
 
+   for (i = 0; i < dm_state->set_count; i++) {
+   for (j = 0; j < dm_state->set[i].surface_count; j++) {
+   dc_surface_release(dm_state->set[i].surfaces[j]);
+   }
+   }
+
+   for (i = 0; i < dm_state->set_count; i++)
+   dc_stream_release(dm_state->set[i].stream);
+
kfree(dm_state);
 }
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
index 52d1922..13fc497 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c
@@ -3038,11 +3038,15 @@ static uint32_t update_in_val_sets_stream(
}
 
val_sets[i].stream = new_stream;
+   dc_stream_retain(new_stream);
crtcs[i] = crtc;
 
if (i == set_count) {
/* nothing found. add new one to the end */
return set_count + 1;
+   } else {
+   /* update. relase old stream */
+   dc_stream_release(old_stream);
}
 
return set_count;
@@ -3064,6 +3068,7 @@ static uint32_t remove_from_val_sets(
return set_count;
}
 
+   dc_stream_release(stream);
set_count--;
 
for (; i < set_count; i++) {
@@ -3168,6 +3173,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev,
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 
if (acrtc->stream) {
+   dc_stream_retain(acrtc->stream);
dm_state->set[dm_state->set_count].stream = 
acrtc->stream;
crtc_set[dm_state->set_count] = crtc;
++dm_state->set_count;
-- 
2.7.4

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[PATCH 70/81] drm/amd/display: add line number to reg_wait timeout print

[sunpeng.li]

From: Dmytro Laktyushkin 

Change-Id: I116b51dce6e496ea5bec51131307890f64985755
Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc_helper.c  | 6 +++---
 drivers/gpu/drm/amd/display/dc/dm_services.h| 2 +-
 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c 
b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 8ed1440..87b7f6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -129,7 +129,7 @@ uint32_t generic_reg_get(const struct dc_context *ctx,
 uint32_t generic_reg_wait(const struct dc_context *ctx,
uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,
unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
-   const char *func_name)
+   const char *func_name, int line)
 {
uint32_t field_value;
uint32_t reg_val;
@@ -158,8 +158,8 @@ uint32_t generic_reg_wait(const struct dc_context *ctx,
return reg_val;
}
 
-   dm_error("REG_WAIT timeout %dus * %d tries - %s\n",
-   delay_between_poll_us, time_out_num_tries, func_name);
+   dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
+   delay_between_poll_us, time_out_num_tries, func_name, 
line);
 
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h 
b/drivers/gpu/drm/amd/display/dc/dm_services.h
index fb61e33..ea494a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -194,7 +194,7 @@ uint32_t generic_reg_update_ex(const struct dc_context *ctx,
 unsigned int generic_reg_wait(const struct dc_context *ctx,
uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,
unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
-   const char *func_name);
+   const char *func_name, int line);
 
 
 /* These macros need to be used with soc15 registers in order to retrieve
diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h 
b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
index 1828d28..77eb728 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
@@ -188,7 +188,7 @@
 #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \
generic_reg_wait(CTX, \
REG(reg_name), FN(reg_name, field), val,\
-   delay_between_poll_us, max_try, __func__)
+   delay_between_poll_us, max_try, __func__, 
__LINE__)
 
 /* macro to update (read, modify, write) register fields
  */
-- 
2.7.4

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[PATCH 50/81] drm/amd/display: Fix context copy memory leak

[sunpeng.li]

From: Corbin McElhanney 

This change corrects an error introduced in 355f123f. Instead of
using the copy constructor to assign the new context, we swap the
pointer.

Change-Id: Ic765e1ce78cd9f731486c1c44ad10c9c95f2c8ad
Signed-off-by: Corbin McElhanney 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 52077d3..4f93029 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -972,7 +972,9 @@ static bool dc_commit_context_no_check(struct dc *dc, 
struct validate_context *c
 
dc_enable_stereo(dc, context, dc_streams, context->stream_count);
 
-   dc_resource_validate_ctx_copy_construct(context, 
core_dc->current_context);
+   dc_resource_validate_ctx_destruct(core_dc->current_context);
+   dm_free(core_dc->current_context);
+   core_dc->current_context = context;
 
return (result == DC_OK);
 }
@@ -1057,9 +1059,6 @@ bool dc_commit_streams(
 
result = dc_commit_context_no_check(dc, context);
 
-   dc_resource_validate_ctx_destruct(context);
-   dm_free(context);
-
return (result == DC_OK);
 
 fail:
-- 
2.7.4

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[PATCH 63/81] drm/amd/display: fix 4k@30 with 10bit deep color and avi for BT2020

[sunpeng.li]

From: Charlene Liu 

Change-Id: I064a87f09f1254f61bde94b0546855b98f4ab211
Signed-off-by: Charlene Liu 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index a9c086a..00fed61 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1661,7 +1661,8 @@ static void set_avi_info_frame(
 
/* C0, C1 : Colorimetry */
if (color_space == COLOR_SPACE_YCBCR709 ||
-   color_space == COLOR_SPACE_YCBCR709_LIMITED)
+   color_space == COLOR_SPACE_YCBCR709_LIMITED ||
+   color_space == COLOR_SPACE_2020_YCBCR)
hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
else if (color_space == COLOR_SPACE_YCBCR601 ||
color_space == COLOR_SPACE_YCBCR601_LIMITED)
-- 
2.7.4

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[PATCH 69/81] drm/amd/display: Release cached atomic state in S3.

[sunpeng.li]

From: Andrey Grodzovsky 

Fixes memory leak.

Change-Id: I32f68c72d11695f49bb8328a11e89922818fb9fe
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b6a04ad..8377575 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -508,6 +508,7 @@ static int dm_suspend(void *handle)
 
amdgpu_dm_irq_suspend(adev);
 
+   WARN_ON(adev->dm.cached_state);
adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
 
dc_set_power_state(
@@ -607,6 +608,9 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev )
 
ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
 
+   drm_atomic_state_put(adev->dm.cached_state);
+   adev->dm.cached_state = NULL;
+
amdgpu_dm_irq_resume_late(adev);
 
return ret;
-- 
2.7.4

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Re: [PATCH] drm/amdgpu: fix spelling mistake: "suuport"-> "support"

[Alex Deucher]

On Tue, Jul 25, 2017 at 4:40 AM, Christian König
 wrote:
> Am 25.07.2017 um 00:45 schrieb Colin King:
>>
>> From: Colin Ian King 
>>
>> Trivial fix to spelling mistake in WARN_ONCE message
>>
>> Signed-off-by: Colin Ian King 

This is actually already fixed in code slated to go upstream in the next kernel.

Alex


>
>
> Reviewed-by: Christian König 
>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index 5795f81369f0..06f11e2a32af 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -1301,7 +1301,7 @@ static int amdgpu_vm_update_ptes(struct
>> amdgpu_pte_update_params *params,
>> if (params->shadow) {
>> if (WARN_ONCE(use_cpu_update,
>> -   "CPU VM update doesn't suuport shadow
>> pages"))
>> +   "CPU VM update doesn't support shadow
>> pages"))
>> return 0;
>> if (!pt->shadow)
>
>
>
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Re: [PATCH 5/8] drm/amdgpu: According hardware design revert vce and uvd doorbell assignment

[Alex Deucher]

On Tue, Jul 25, 2017 at 5:17 AM, Xiangliang.Yu  wrote:
> From: Frank Min 
>
> Now uvd doorbell is from 0xf8-0xfb and vce doorbell is from 0xfc-0xff
>
> Signed-off-by: Frank Min 
> Signed-off-by: Xiangliang.Yu 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   | 18 +-
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c |  6 --
>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c |  6 +++---
>  3 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index fe96236..d287621 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -680,15 +680,15 @@ typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
> /* overlap the doorbell assignment with VCN as they are  mutually 
> exclusive
>  * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
>  */
> -   AMDGPU_DOORBELL64_RING0_1 = 0xF8,
> -   AMDGPU_DOORBELL64_RING2_3 = 0xF9,
> -   AMDGPU_DOORBELL64_RING4_5 = 0xFA,
> -   AMDGPU_DOORBELL64_RING6_7 = 0xFB,
> -
> -   AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC,
> -   AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD,
> -   AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE,
> -   AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF,
> +   AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
> +   AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
> +   AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
> +   AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
> +
> +   AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
> +   AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
> +   AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
> +   AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
>
> AMDGPU_DOORBELL64_MAX_ASSIGNMENT  = 0xFF,
> AMDGPU_DOORBELL64_INVALID = 0x
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index ab447e8..590c3f0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -435,13 +435,15 @@ static int uvd_v7_0_sw_init(void *handle)
> return r;
> }
>
> -
> for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
> ring = >uvd.ring_enc[i];
> sprintf(ring->name, "uvd_enc%d", i);
> if (amdgpu_sriov_vf(adev)) {
> ring->use_doorbell = true;
> -   ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 
> * 2;
> +   if (i == 0)
> +   ring->doorbell_index = 
> AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
> +   else
> +   ring->doorbell_index = 
> AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;

Can you clarify the requirements?  This logic doesn't seem right.

> }
> r = amdgpu_ring_init(adev, ring, 512, >uvd.irq, 0);
> if (r)
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index 9e0050d..34c2281 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -446,11 +446,11 @@ static int vce_v4_0_sw_init(void *handle)
> /* DOORBELL only works under SRIOV */
> ring->use_doorbell = true;
> if (i == 0)
> -   ring->doorbell_index = 
> AMDGPU_DOORBELL64_RING0_1 * 2;
> +   ring->doorbell_index = 
> AMDGPU_DOORBELL64_VCE_RING0_1 * 2;
> else if (i == 1)
> -   ring->doorbell_index = 
> AMDGPU_DOORBELL64_RING2_3 * 2;
> +   ring->doorbell_index = 
> AMDGPU_DOORBELL64_VCE_RING2_3 * 2;
> else
> -   ring->doorbell_index = 
> AMDGPU_DOORBELL64_RING2_3 * 2 + 1;
> +   ring->doorbell_index = 
> AMDGPU_DOORBELL64_VCE_RING2_3 * 2 + 1;

Same here.  The one is even weirder.

Alex

> }
> r = amdgpu_ring_init(adev, ring, 512, >vce.irq, 0);
> if (r)
> --
> 2.7.4
>
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Re: [PATCH 6/6] drm/amdgpu: change gartsize default to 256MB

[Andy Furniss]

Bit late, but this causes a startup fail for me with r9 285 , nothing 
logged, just a blank screen when the driver loads.


Heads of both amd-staging-4.11 and drm-next-4.14-wip both failing.

Deucher, Alexander wrote:

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
Of Christian König
Sent: Friday, July 07, 2017 7:53 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH 6/6] drm/amdgpu: change gartsize default to 256MB

From: Christian König 

Limit the default GART size and save a lot of VRAM.

Signed-off-by: Christian König 


Patch 1-4, 6:
Reviewed-by: Alex Deucher 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +---
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  6 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c   |  9 +
  4 files changed, 10 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 94bbf71..2421b6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -76,7 +76,7 @@
   */
  extern int amdgpu_modeset;
  extern int amdgpu_vram_limit;
-extern int amdgpu_gart_size;
+extern unsigned amdgpu_gart_size;
  extern int amdgpu_gtt_size;
  extern int amdgpu_moverate;
  extern int amdgpu_benchmarking;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8ef7e5e..7a90dec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1128,13 +1128,11 @@ static void amdgpu_check_arguments(struct
amdgpu_device *adev)
amdgpu_sched_jobs =
roundup_pow_of_two(amdgpu_sched_jobs);
}

-   if (amdgpu_gart_size != -1) {
-   /* gtt size must be greater or equal to 32M */
-   if (amdgpu_gart_size < 32) {
-   dev_warn(adev->dev, "gart size (%d) too small\n",
-amdgpu_gart_size);
-   amdgpu_gart_size = -1;
-   }
+   if (amdgpu_gart_size < 32) {
+   /* gart size must be greater or equal to 32M */
+   dev_warn(adev->dev, "gart size (%d) too small\n",
+amdgpu_gart_size);
+   amdgpu_gart_size = 32;
}

if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index b7c6cee..559e092 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -74,7 +74,7 @@
  #define KMS_DRIVER_PATCHLEVEL 0

  int amdgpu_vram_limit = 0;
-int amdgpu_gart_size = -1; /* auto */
+unsigned amdgpu_gart_size = 256;
  int amdgpu_gtt_size = -1; /* auto */
  int amdgpu_moverate = -1; /* auto */
  int amdgpu_benchmarking = 0;
@@ -122,8 +122,8 @@ int amdgpu_lbpw = -1;
  MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in
megabytes");
  module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);

-MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in
megabytes (32, 64, etc., -1 = auto)");
-module_param_named(gartsize, amdgpu_gart_size, int, 0600);
+MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in
megabytes (32, 64, etc.)");
+module_param_named(gartsize, amdgpu_gart_size, uint, 0600);

  MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 =
auto)");
  module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index cb0814a..124b237 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -62,14 +62,7 @@
   */
  void amdgpu_gart_set_defaults(struct amdgpu_device *adev)
  {
-   /* unless the user had overridden it, set the gart
-* size equal to the 1024 or vram, whichever is larger.
-*/
-   if (amdgpu_gart_size == -1)
-   adev->mc.gart_size =
max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
-   adev->mc.mc_vram_size);
-   else
-   adev->mc.gart_size = (uint64_t)amdgpu_gart_size << 20;
+   adev->mc.gart_size = (uint64_t)amdgpu_gart_size << 20;
  }

  /**
--
2.7.4

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Re: [PATCH 1/8] drm/amdgpu: Clear vce ring wptr for SRIOV

[Alex Deucher]

On Tue, Jul 25, 2017 at 5:16 AM, Xiangliang.Yu  wrote:
> From: Frank Min 
>
> MMSCH FW need to get the wptr from 0 after it get the mailbox request
> from driver, since every time kick the mailbox, mmsch thinks that it
> is the first time engine start to initialize.
>
> Signed-off-by: Frank Min 
> Signed-off-by: Xiangliang.Yu 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +-
>  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +-
>  2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 987b958..e2b17cb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -685,6 +685,11 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device 
> *adev,
> /* 4, set resp to zero */
> WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
>
> +   WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
> +   adev->wb.wb[adev->uvd.ring_enc[0].wptr_offs] = 0;
> +   adev->uvd.ring_enc[0].wptr = 0;
> +   adev->uvd.ring_enc[0].wptr_old = 0;
> +
> /* 5, kick off the initialization and wait until 
> VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
> WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x1001);
>
> @@ -702,7 +707,6 @@ static int uvd_v7_0_mmsch_start(struct amdgpu_device 
> *adev,
> dev_err(adev->dev, "failed to init MMSCH, 
> mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
> return -EBUSY;
> }
> -   WDOORBELL32(adev->uvd.ring_enc[0].doorbell_index, 0);
>
> return 0;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index 1ecd6bb..9b1de6b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -173,6 +173,11 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device 
> *adev,
> /* 4, set resp to zero */
> WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);
>
> +   WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
> +   adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0;
> +   adev->vce.ring[0].wptr = 0;
> +   adev->vce.ring[0].wptr_old = 0;
> +
> /* 5, kick off the initialization and wait until 
> VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
> WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 
> 0x1001);
>
> @@ -190,7 +195,6 @@ static int vce_v4_0_mmsch_start(struct amdgpu_device 
> *adev,
> dev_err(adev->dev, "failed to init MMSCH, 
> mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
> return -EBUSY;
> }
> -   WDOORBELL32(adev->vce.ring[0].doorbell_index, 0);
>
> return 0;
>  }
> --
> 2.7.4
>
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Re: [PATCH 7/8] drm/amdgpu/uvd7: optimize uvd initialization sequence for SRIOV

[Alex Deucher]

On Tue, Jul 25, 2017 at 5:17 AM, Xiangliang.Yu  wrote:
> From: Frank Min 
>
> 1.Since in sriov there is no need of decoding, so skip the related code;
> 2.Vcpu boot up and umc enable need to take at the end of the init sequence;
>
> Signed-off-by: Frank Min 
> Signed-off-by: Xiangliang.Yu 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 58 
> +++
>  1 file changed, 11 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
> b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 590c3f0..3b64951 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -745,11 +745,9 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device 
> *adev)
> init_table += header->uvd_table_offset;
>
> ring = >uvd.ring;
> +   ring->wptr = 0;
> size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
>
> -   /* disable clock gating */
> -   MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_POWER_STATUS),
> -  
> ~UVD_POWER_STATUS__UVD_PG_MODE_MASK, 0);
> MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_STATUS),
>0x, 0x0004);
> /* mc resume*/
> @@ -786,12 +784,6 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device 
> *adev)
> MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_VCPU_CACHE_SIZE2),
> AMDGPU_UVD_STACK_SIZE + 
> (AMDGPU_UVD_SESSION_SIZE * 40));
>
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_UDEC_ADDR_CONFIG),
> -   adev->gfx.config.gb_addr_config);
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_UDEC_DB_ADDR_CONFIG),
> -   adev->gfx.config.gb_addr_config);
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_UDEC_DBW_ADDR_CONFIG),
> -   adev->gfx.config.gb_addr_config);
> MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
> /* mc resume end*/
>
> @@ -828,17 +820,6 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device 
> *adev)
>
> UVD_LMI_CTRL__REQ_MODE_MASK |
>0x0010L));
>
> -   /* disable byte swapping */
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_LMI_SWAP_CNTL), 0);
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_MP_SWAP_CNTL), 0);
> -
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_MPC_SET_MUXA0), 0x40c2040);
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_MPC_SET_MUXA1), 0x0);
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_MPC_SET_MUXB0), 0x40c2040);
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_MPC_SET_MUXB1), 0x0);
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_MPC_SET_ALU), 0);
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_MPC_SET_MUX), 0x88);
> -
> /* take all subblocks out of reset, except VCPU */
> MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_SOFT_RESET),
> 
> UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
> @@ -847,15 +828,6 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device 
> *adev)
> MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_VCPU_CNTL),
> UVD_VCPU_CNTL__CLK_EN_MASK);
>
> -   /* enable UMC */
> -   MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_LMI_CTRL2),
> -  
> ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
> -
> -   /* boot up the VCPU */
> -   MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_SOFT_RESET), 0);
> -
> -   MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_STATUS), 0x02, 0x02);
> -
> /* enable master interrupt */
> MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, 0, 
> mmUVD_MASTINT_EN),
>
> ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
> @@ -868,32 +840,24 @@ static int uvd_v7_0_sriov_start(struct amdgpu_device 
> *adev)
>