subject:"Re\: IDE knowledge anyone\?"


Hi Chuck,

Chuck Guzis  wrote:

I found the section "400 nsec delays" an interesting read,  
particularly  the bit about reading the status register five times.


http://wiki.osdev.org/ATA_PIO_Mode

--Chuck


You are completely right, but the drive is selected always as this is a
"one drive only" implementation. The same drive-selection-magic would
otherwise also apply to the "Read Sector Buffer" command which works
without any error.

Re: IDE knowledge anyone?



Oliver Lehmann  wrote:


Chuck Guzis  wrote:


On 12/11/2015 12:04 PM, Oliver Lehmann wrote:


This is the question... what is the "correct data"? Would I be able
to see the cyl/sector/head information I've set before in that
buffer? I didn't understand what the sector buffer really is by
reading the docs.


Well, ideally, this contains the data of the last sector  
transferred. It provides a sanity check on the data transfer path.


So you should be able to do a "read sector buffer" after the  
aborted "read sector" and get some clue.


I now tried something different. I issued a "format track command" and
sent 512 bytes afterwards as described in the ata spec. The drive does
not respond with an error, and when I read the sector buffer right
afterwards, it contains the exact data I transfered after I issued the
format track command.

Re: IDE knowledge anyone?


On 12/11/2015 01:26 PM, Oliver Lehmann wrote:


I now tried something different. I issued a "format track command"
and sent 512 bytes afterwards as described in the ata spec. The drive
does not respond with an error, and when I read the sector buffer
right afterwards, it contains the exact data I transfered after I
issued the format track command.



Okay, this is not getting results.  I believe that a long way back in 
the thread that you said that only one drive make+model exhibited this 
issue--other drives worked fine.


Right now, I can't find the post where you specified the drive.  Who 
knows--I might have one.


--Chuck

Re: IDE knowledge anyone?


On 12/11/2015 05:02 PM, Oliver Lehmann wrote:


Which is perfectly fine - I just want to see what is going on the
drive interface + timings - to see what is going on differently from
my implementation.



If I've got the drive and it's working, at least I've got some x86 code 
that can drive it in PIO mode.  If it works, I'll pass it along.  There 
may be a hint or two in it.


--Chuck

Re: IDE knowledge anyone?


On 12/11/2015 04:35 PM, Oliver Lehmann wrote:


Western Digital Caviar 31600 it is.

I'm waiting for a 32Port-LA (might take up to a month). When it is
there I'll continue debugging that issue and see what a MS-DOS does
different from what I do.


MS-DOS uses the native BIOS for hard disk accesses, unless you're 
running Windows 3.1 or so and use a VxD to drive the ports directly.


But, I think I've actually got one of those 1.GB Caviar drives.  I'm not 
sure if it's still operational, but I'll check my drive cabinet.


--Chuck

Re: IDE knowledge anyone?



Chuck Guzis  wrote:


On 12/11/2015 04:35 PM, Oliver Lehmann wrote:


Western Digital Caviar 31600 it is.

I'm waiting for a 32Port-LA (might take up to a month). When it is
there I'll continue debugging that issue and see what a MS-DOS does
different from what I do.


MS-DOS uses the native BIOS for hard disk accesses, unless you're  
running Windows 3.1 or so and use a VxD to drive the ports directly.


Which is perfectly fine - I just want to see what is going on the drive
interface + timings - to see what is going on differently from my
implementation.

Re: IDE knowledge anyone?


On 12/11/2015 03:45 AM, Oliver Lehmann wrote:


You are completely right, but the drive is selected always as this is
a "one drive only" implementation. The same drive-selection-magic
would otherwise also apply to the "Read Sector Buffer" command which
works without any error.


Hmmm, another piece of the puzzle perhaps.  If memory serves, "read 
sector buffer" and "identify" are two operations that are restricted to 
PIO 0 mode (I'll have to check, but I think that's true).


If you issue a "read sector buffer" right after the LBA read sector 
aborts, do you get the correct data back?


If so, I wonder if the drive is expecting that DMA mode will be used by 
default.


Just a thought.

--Chuck

Re: IDE knowledge anyone?


Hi Chuck,


Chuck Guzis  wrote:

If you issue a "read sector buffer" right after the LBA read sector  
aborts, do you get the correct data back?


This is the question... what is the "correct data"? Would I be able to
see the cyl/sector/head information I've set before in that buffer? I
didn't understand what the sector buffer really is by reading the docs.

Re: IDE knowledge anyone?


On 12/11/2015 12:04 PM, Oliver Lehmann wrote:


This is the question... what is the "correct data"? Would I be able
to see the cyl/sector/head information I've set before in that
buffer? I didn't understand what the sector buffer really is by
reading the docs.


Well, ideally, this contains the data of the last sector transferred. 
It provides a sanity check on the data transfer path.


So you should be able to do a "read sector buffer" after the aborted 
"read sector" and get some clue.


At least that's my understanding.

--Chuck

Re: IDE knowledge anyone?



Chuck Guzis  wrote:


On 12/11/2015 01:26 PM, Oliver Lehmann wrote:


I now tried something different. I issued a "format track command"
and sent 512 bytes afterwards as described in the ata spec. The drive
does not respond with an error, and when I read the sector buffer
right afterwards, it contains the exact data I transfered after I
issued the format track command.



Okay, this is not getting results.  I believe that a long way back  
in the thread that you said that only one drive make+model exhibited  
this issue--other drives worked fine.


Right now, I can't find the post where you specified the drive.  Who  
knows--I might have one.


Western Digital Caviar 31600 it is.

I'm waiting for a 32Port-LA (might take up to a month). When it is there
I'll continue debugging that issue and see what a MS-DOS does different
from what I do.

Re: IDE knowledge anyone?

2015-12-11 Thread Marc Verdiell


>> Just going by what you write...BTW, what are you using as a reference?
> I've used ftp://ftp.seagate.com/acrobat/reference/111-1c.pdf a lot.
> Also other IDE implementations on ATMegas.

Do you mind providing links to any good implementations of IDE on ATMega  you 
know of?
Marc

Re: IDE knowledge anyone?



Chuck Guzis  wrote:


On 12/11/2015 12:04 PM, Oliver Lehmann wrote:


This is the question... what is the "correct data"? Would I be able
to see the cyl/sector/head information I've set before in that
buffer? I didn't understand what the sector buffer really is by
reading the docs.


Well, ideally, this contains the data of the last sector  
transferred. It provides a sanity check on the data transfer path.


So you should be able to do a "read sector buffer" after the aborted  
"read sector" and get some clue.


OK, after I issue the read-cmd and the ABRT occured, I directly fetch
the sector buffer and it contains:

7a424c0c10e158023f001000
0e004457572d3254393839313032
3139203420202020030116003332
312e5536333744572043434131333036
48302020202020202020202020202020
20202020202020202020202020201080
002f80020200
0001406b3704
030078007800a0007800

...

7800




When I ignore the ERR-Status and read 512bytes anyhow, I'm reading
always this:

051760290510151037332e303455000d
0201251c120141123001530822015b1c
10020112110213141302271025017705
2302370e2e017c032102450824017f01
20024d0a

[...]




I've tried to read block 0, 1 and 2 - all reads are aborted, sector
buffer is always the same.

Re: IDE knowledge anyone?



Marc Verdiell  wrote:


Just going by what you write...BTW, what are you using as a reference?

I've used ftp://ftp.seagate.com/acrobat/reference/111-1c.pdf a lot.
Also other IDE implementations on ATMegas.


Do you mind providing links to any good implementations of IDE on  
ATMega  you know of?

Marc


Of course mine ;)

And http://www.opend.co.za/hardware/avride/avride.htm but I never verified
if his implementation would work with my harddisk

Re: IDE knowledge anyone?



Chuck Guzis  wrote:


On 12/10/2015 12:18 AM, Oliver Lehmann wrote:


for LBA:

while ( pata_bsy() ) {}

write_io_register ( PATA_RW_SECTOR_COUNT_REGISTER, 1 );
write_io_register ( PATA_RW_SECTOR_NUMBER_REGISTER, 0 );
write_io_register ( PATA_RW_CYLINDER_LOW_REGISTER, 0 );
write_io_register ( PATA_RW_CYLINDER_HIGH_REGISTER, 0 );
write_io_register ( PATA_RW_DEVICE_HEAD_REGISTER, 0xa0 );

write_io_register ( PATA_W_COMMAND_REGISTER, 0x21 );

while ( pata_bsy() ) {} if

 ( pata_err() ) { return; } while (

!pata_drq() ) {}


If you're using LBA, should this be the setting:

 write_io_register ( PATA_RW_DEVICE_HEAD_REGISTER, 0xe0 );

Bit 6 indicates LBA.


right - This is what I do in the code - I was writing "from memory".

Also, note that if you're using drives larger than about 120GB, the  
PATA-6 protocol comes into effect with 48-bit sector addresses.


OK - good to know. I only tested ranges 260MB - 80GB. Guess I'll just
not support it then?! How is it different regarding setting the
registers? But anyway... The host computer only supports 32bit
adressing of 512Byte Blocks. And I guess I could also use 500GB
IDE disks when using only lets say some hundrets of MB (plenty
enough - the original harddisk in the system had about 54MB)

Oliver

Re: IDE knowledge anyone?


On 12/10/2015 12:18 AM, Oliver Lehmann wrote:


for LBA:

while ( pata_bsy() ) {}

write_io_register ( PATA_RW_SECTOR_COUNT_REGISTER, 1 );
write_io_register ( PATA_RW_SECTOR_NUMBER_REGISTER, 0 );
write_io_register ( PATA_RW_CYLINDER_LOW_REGISTER, 0 );
write_io_register ( PATA_RW_CYLINDER_HIGH_REGISTER, 0 );
write_io_register ( PATA_RW_DEVICE_HEAD_REGISTER, 0xa0 );

write_io_register ( PATA_W_COMMAND_REGISTER, 0x21 );

while ( pata_bsy() ) {} if

 ( pata_err() ) { return; } while (

!pata_drq() ) {}


If you're using LBA, should this be the setting:

 write_io_register ( PATA_RW_DEVICE_HEAD_REGISTER, 0xe0 );

Bit 6 indicates LBA.

Also, note that if you're using drives larger than about 120GB, the 
PATA-6 protocol comes into effect with 48-bit sector addresses.


--Chuck

Re: IDE knowledge anyone?



Chuck Guzis  wrote:


On 12/09/2015 09:58 PM, Oliver Lehmann wrote:


And this is whst I do/did. The drive supports LBA. I also tried CHS
with it and oft course i used cyl 0, head 0 and sector 1 without
success.

I now ordered a cheap chinese LA


When you say that you get an error, exactly what is the error  
(status bytes)?   Before you issue the command, exactly what do the  
drive registers contain?


After the command is issued, The status register has the ERR bit set,
and the error register has the ABRT bit set. With drive registers you
mean sector, cylinder and so on?

for LBA:

while ( pata_bsy() ) {}

write_io_register ( PATA_RW_SECTOR_COUNT_REGISTER, 1 );
write_io_register ( PATA_RW_SECTOR_NUMBER_REGISTER, 0 );
write_io_register ( PATA_RW_CYLINDER_LOW_REGISTER, 0 );
write_io_register ( PATA_RW_CYLINDER_HIGH_REGISTER, 0 );
write_io_register ( PATA_RW_DEVICE_HEAD_REGISTER, 0xa0 );

write_io_register ( PATA_W_COMMAND_REGISTER, 0x21 );

while ( pata_bsy() ) {}
if ( pata_err() ) {
return;
}
while ( !pata_drq() ) {}

pata_bsy, _drq and _err check the status registers for the relevant
bits. pata_err returns true. right after the command was issued.

I also checked after each register set - the status is always
correct, just after the command register is set, the drive goes
from busy to 0x59 (DRQ + ERR set).

Re: IDE knowledge anyone?


On 12/10/2015 01:37 PM, Oliver Lehmann wrote:


OK - but those drives should also work on non-PATA-6 systems but
with reduced capacity - right?


As I recall (it's been at least a decade and a half), that's true--you 
just don't get the full drive.


How are you handling 16-bit data port accesses--or is this not an 8 bit 
ATMega?


Oh, the Seagate reference you furnished should work fine.

--Chuck

Re: IDE knowledge anyone?


On 12/10/2015 12:21 PM, Oliver Lehmann wrote:


right - This is what I do in the code - I was writing "from memory".


Just going by what you write...BTW, what are you using as a reference?
Seagate still has a lot of interesting stuff on their ftp.


OK - good to know. I only tested ranges 260MB - 80GB. Guess I'll
just not support it then?! How is it different regarding setting the
registers? But anyway... The host computer only supports 32bit
adressing of 512Byte Blocks. And I guess I could also use 500GB IDE
disks when using only lets say some hundrets of MB (plenty enough -
the original harddisk in the system had about 54MB)



PATA-6 is sort of a kludge supported by double-writing (MSB first) to 
each of the address registers without any intervening access to any 
other register.  Intel employs this sort of thing on their older 8-bit 
peripheral support chips.


ABRT set in the error register basically indicates that the drive  isn't 
ready or that there's something wrong with the command.  You may want to 
insert some debug code that displays exactly what's being written to the 
drive registers.


--Chuck

Re: IDE knowledge anyone?


Answering your other notes now - sorry for skipping them in my earlier
mail ;)


Chuck Guzis  wrote:


On 12/10/2015 12:21 PM, Oliver Lehmann wrote:


right - This is what I do in the code - I was writing "from memory".


Just going by what you write...BTW, what are you using as a reference?


I've used ftp://ftp.seagate.com/acrobat/reference/111-1c.pdf a lot.
Also other IDE implementations on ATMegas.



PATA-6 is sort of a kludge supported by double-writing (MSB first)  
to each of the address registers without any intervening access to  
any other register.  Intel employs this sort of thing on their older  
8-bit peripheral support chips.


OK - but those drives should also work on non-PATA-6 systems but with
reduced capacity - right?

Oliver

Re: IDE knowledge anyone?



Chuck Guzis  wrote:

ABRT set in the error register basically indicates that the drive   
isn't ready or that there's something wrong with the command.  You  
may want to insert some debug code that displays exactly what's  
being written to the drive registers.


Did that - echoed it out on serial line. But think about it - under
what circumstances I could write wrong data to the cyl/sec/head
registers that ANY other drive interprets correctly (I'm booting an OS
from other harddisks successfully)? If I would write wrong data into
those setup-registers I would also get errors from other devices,
right?
My thinking was, that the drive does not interpret the data correctly.
Things like:

1 Low-High-Switch not "clear" enough to the drive to accept the data
2 Low/High-Indicating voltage near the limits and the drive has slightly
  broken stuff so if the voltage is  neart the limit, it indicates
  "forbidden voltage"
3 I'm to fast in asserting a signal and the disk can't pick it up that
  fast.


2 -> i would have other errors as well e.g. sending identify command
also uses the same lines...
3 -> i already tried delays everywhere without success

Re: IDE knowledge anyone?

2015-12-10 Thread Jules Richardson


On 12/10/2015 03:19 PM, Oliver Lehmann wrote:

3 -> i already tried delays everywhere without success


I think you mentioned that you tried an old '486 machine and the drive was 
OK there - how hard is it to compile your code for x86 and essentially try 
testing your exact same code on the PC? It might help point the finger at 
either the software, or at it perhaps being an electronic issue.


cheers

Jules

Re: IDE knowledge anyone?

I found the section "400 nsec delays" an interesting read, particularly 
 the bit about reading the status register five times.


http://wiki.osdev.org/ATA_PIO_Mode

--Chuck

Re: IDE knowledge anyone?



Chuck Guzis  wrote:


On 12/10/2015 01:37 PM, Oliver Lehmann wrote:


OK - but those drives should also work on non-PATA-6 systems but
with reduced capacity - right?


As I recall (it's been at least a decade and a half), that's  
true--you just don't get the full drive.


More than a couple of 100 MB would not make any sense at all as there
is just not enough data to fill up the drive with on that host ;)


How are you handling 16-bit data port accesses--or is this not an 8  
bit ATMega?


normaly I would read the lower and the higher 8 bits from 2 different
ports one after each other. But as My ports are already "used up" for
other stuff, I have latches storing the higher part of th 16Bits. This
should of course not cause problems in the early stage of setting the
drive registers and issuing the command as this only happens in the
lower 8 bits.

http://www.pofo.de/P8000/notes/plaene/eigene/P8000_WDC_Emulator/P8000_WDC_Emulator_v1.2_Plan.pdf

Re: IDE knowledge anyone?

2015-12-09 Thread Joseph Lang

Since identify and read buffer return consistent data, timing would appear to 
be ok. I would change the parameters used for read. iIRC you used chs =0/0/0. 
Try chs=1/1/1 

Joe

> On Dec 8, 2015, at 4:38 PM, Oliver Lehmann  wrote:
> 
> 
> Oliver Lehmann  wrote:
> 
>> Oliver Lehmann  wrote:
>> 
>>> Toby Thain  wrote:
>>> 
> On 2015-12-08 2:16 AM, Oliver Lehmann wrote:
> Hi Warner, hi Brad,
> ...
> I don't intend to use this harddrive anyway, I just fear that I made a
> misstake in my circuit or the code and others intending to use my
> emulator also experiencing problems with their drives too.
 
 Well, it's certainly interesting. I'm curious now whether your WDC 
 AC31600H would work with my PIC code. :)
>>> 
>>> I checked it now with an old 486-DX50 EISA+VLB board (rare combination ;))
>>> with a Goldstar Prime 2 and an Acer M5105 ISA Controller. Both detect and
>>> work fine with this harddisk. No idea what mode they work but I guess it
>>> is PIO 0-whatever only - no DMA involved
>>> 
>>> Damn this drives me nuts either I accept it, or I get a logic analyzer
>>> but the cost of such a thing. :/
>> 
>> But - if the flanks or the timing would not be right - how could the IDENTIFY
>> command work without any error? If the flanks would not be straight or /RD is
>> not active long enough or whatever - shouldnt return the IDENTIFY an error as
>> well? I'd say so..
> 
> I just changed the "READ" command to a "FORMAT" command and now the drive 
> wants
> me to fill up the sector buffer (which I don't do) but at least the command is
> accepted and does not immediatly return ERR what the heck?
> 
> Read Buffer also works after the read-command-error - but now idea if the 
> buffer
> contains anything which could help me here
> 
> 7a424c0c10e158023f001000
> 0e004457572d3254393839313032
> 3139203420202020030116003332
> 312e5536333744572043434131333036
> 48302020202020202020202020202020
> 20202020202020202020202020201080
> 002f80020200
> 0001406b3704
> 030078007800a0007800
> 
> ...
> 
> 7800
> 
> No idea what this gives me the contents are reproducable
>

Re: IDE knowledge anyone?

2015-12-09 Thread Alexandre Souza

A proper HP16500C or better (series 17000) is way cheap nowadays. Myself
use a 16500C with lots of accessories (thank you, you know who you are!!!)
and a 16505A. Maybe it can help you. I don't know if there is an IDE
analyser for it (I have it for SCSI) but you can look for it. Or write a
module for it.

2015-12-08 18:44 GMT-02:00 Steven Hirsch :

> On Tue, 8 Dec 2015, Oliver Lehmann wrote:
>
> I checked it now with an old 486-DX50 EISA+VLB board (rare combination ;))
>> with a Goldstar Prime 2 and an Acer M5105 ISA Controller. Both detect and
>> work fine with this harddisk. No idea what mode they work but I guess it
>> is PIO 0-whatever only - no DMA involved
>>
>> Damn this drives me nuts either I accept it, or I get a logic analyzer
>> but the cost of such a thing. :/
>>
>
> There are some Chinese logic analyzers on eBay for well under $100. No
> idea how well they work.
>
>
> --
>

Re: IDE knowledge anyone?

2015-12-09 Thread Philip Pemberton

On 06/12/15 20:57, Oliver Lehmann wrote:
> Right after power up and after the disk got ready, I issue the IDENTIFY
> command and read the data back which works perfectly. After that I
> read sector 0 and this fails.

I thought the first valid sector on an IDE disk was sector 1, CHS 0:0:1?

-- 
Phil.
classic...@philpem.me.uk
http://www.philpem.me.uk/

Re: IDE knowledge anyone?

2015-12-09 Thread Chuck Guzis


On 12/09/2015 02:14 PM, Philip Pemberton wrote:



I thought the first valid sector on an IDE disk was sector 1, CHS
0:0:1?




Yes; it's only 0 in LBA mode.

If you'd like, I can jump in here, having done a bunch of IDE software 
back in the bad old days.


Anyone remember the glitches in the IDENTIFY command, where Maxtor got 
the word order swapped around on their 60MB drives, so that the total 
sector count was insanely (for that time anyway) high?


--Chuck

Re: IDE knowledge anyone?

2015-12-09 Thread Chuck Guzis


On 12/09/2015 09:58 PM, Oliver Lehmann wrote:


And this is whst I do/did. The drive supports LBA. I also tried CHS
with it and oft course i used cyl 0, head 0 and sector 1 without
success.

I now ordered a cheap chinese LA


When you say that you get an error, exactly what is the error (status 
bytes)?   Before you issue the command, exactly what do the drive 
registers contain?


--Chuck

Re: IDE knowledge anyone?

2015-12-09 Thread Oliver Lehmann


Chuck Guzis  wrote:


On 12/09/2015 02:14 PM, Philip Pemberton wrote:



I thought the first valid sector on an IDE disk was sector 1, CHS
0:0:1?




Yes; it's only 0 in LBA mode.



And this is whst I do/did. The drive supports LBA.
I also tried CHS with it and oft course i used cyl 0, head 0 and  
sector 1 without success.


I now ordered a cheap chinese LA

Re: IDE knowledge anyone?

2015-12-08 Thread Toby Thain


On 2015-12-08 2:16 AM, Oliver Lehmann wrote:

Hi Warner, hi Brad,
...
I don't intend to use this harddrive anyway, I just fear that I made a
misstake in my circuit or the code and others intending to use my
emulator also experiencing problems with their drives too.


Well, it's certainly interesting. I'm curious now whether your WDC 
AC31600H would work with my PIC code. :)


--Toby



Regards,
Oliver

Re: IDE knowledge anyone?

2015-12-08 Thread Oliver Lehmann



Oliver Lehmann  wrote:


Toby Thain  wrote:


On 2015-12-08 2:16 AM, Oliver Lehmann wrote:

Hi Warner, hi Brad,
...
I don't intend to use this harddrive anyway, I just fear that I made a
misstake in my circuit or the code and others intending to use my
emulator also experiencing problems with their drives too.


Well, it's certainly interesting. I'm curious now whether your WDC  
AC31600H would work with my PIC code. :)


I checked it now with an old 486-DX50 EISA+VLB board (rare combination ;))
with a Goldstar Prime 2 and an Acer M5105 ISA Controller. Both detect and
work fine with this harddisk. No idea what mode they work but I guess it
is PIO 0-whatever only - no DMA involved

Damn this drives me nuts either I accept it, or I get a logic analyzer
but the cost of such a thing. :/


But - if the flanks or the timing would not be right - how could the IDENTIFY
command work without any error? If the flanks would not be straight or /RD is
not active long enough or whatever - shouldnt return the IDENTIFY an error as
well? I'd say so..

Re: IDE knowledge anyone?

2015-12-08 Thread Steven Hirsch


On Tue, 8 Dec 2015, Oliver Lehmann wrote:


I checked it now with an old 486-DX50 EISA+VLB board (rare combination ;))
with a Goldstar Prime 2 and an Acer M5105 ISA Controller. Both detect and
work fine with this harddisk. No idea what mode they work but I guess it
is PIO 0-whatever only - no DMA involved

Damn this drives me nuts either I accept it, or I get a logic analyzer
but the cost of such a thing. :/


There are some Chinese logic analyzers on eBay for well under $100. No 
idea how well they work.



--

Re: IDE knowledge anyone?

2015-12-08 Thread Oliver Lehmann



Toby Thain  wrote:


On 2015-12-08 2:16 AM, Oliver Lehmann wrote:

Hi Warner, hi Brad,
...
I don't intend to use this harddrive anyway, I just fear that I made a
misstake in my circuit or the code and others intending to use my
emulator also experiencing problems with their drives too.


Well, it's certainly interesting. I'm curious now whether your WDC  
AC31600H would work with my PIC code. :)


I checked it now with an old 486-DX50 EISA+VLB board (rare combination ;))
with a Goldstar Prime 2 and an Acer M5105 ISA Controller. Both detect and
work fine with this harddisk. No idea what mode they work but I guess it
is PIO 0-whatever only - no DMA involved

Damn this drives me nuts either I accept it, or I get a logic analyzer
but the cost of such a thing. :/

Re: IDE knowledge anyone?

2015-12-08 Thread Oliver Lehmann



Oliver Lehmann  wrote:


Oliver Lehmann  wrote:


Toby Thain  wrote:


On 2015-12-08 2:16 AM, Oliver Lehmann wrote:

Hi Warner, hi Brad,
...
I don't intend to use this harddrive anyway, I just fear that I made a
misstake in my circuit or the code and others intending to use my
emulator also experiencing problems with their drives too.


Well, it's certainly interesting. I'm curious now whether your WDC  
AC31600H would work with my PIC code. :)


I checked it now with an old 486-DX50 EISA+VLB board (rare combination ;))
with a Goldstar Prime 2 and an Acer M5105 ISA Controller. Both detect and
work fine with this harddisk. No idea what mode they work but I guess it
is PIO 0-whatever only - no DMA involved

Damn this drives me nuts either I accept it, or I get a logic analyzer
but the cost of such a thing. :/


But - if the flanks or the timing would not be right - how could the IDENTIFY
command work without any error? If the flanks would not be straight or /RD is
not active long enough or whatever - shouldnt return the IDENTIFY an error as
well? I'd say so..


I just changed the "READ" command to a "FORMAT" command and now the  
drive wants

me to fill up the sector buffer (which I don't do) but at least the command is
accepted and does not immediatly return ERR what the heck?

Read Buffer also works after the read-command-error - but now idea if  
the buffer

contains anything which could help me here

7a424c0c10e158023f001000
0e004457572d3254393839313032
3139203420202020030116003332
312e5536333744572043434131333036
48302020202020202020202020202020
20202020202020202020202020201080
002f80020200
0001406b3704
030078007800a0007800

...

7800

No idea what this gives me the contents are reproducable

Re: IDE knowledge anyone?

Hi Warner, hi Brad,

I have an old russian 50MHz dual-beam osciloscope but without
any storage functionality. -> http://files.pofo.de/P1070427.JPG
I guess it would not be that easy to actually display the whole
communication cylce. I could see how good the flanks are, but I guess
my AVR does it quite well.

In the meantime I checked the FreeBSD ata driver as well as Linux
ata driver and I also took a look on FreeDOS. I don't see that much
differences to how I issue the Read/write commands.

This is my circuit:
http://www.pofo.de/P8000/notes/plaene/eigene/P8000_WDC_Emulator/P8000_WDC_Emulator_v1.2_Plan.pdf
It changed a bit in the meantime regarding the reset logic and I moved
2L1 from the PATA-Connector to the free AVR-Port, but nothing significantly
changed.

https://github.com/OlliL/P8000_WDC_Emulator/blob/master/P8000_WDC_Emulator/wdc_drv_pata.c

This is my ATA driver and in the directory is all the other Code for my
AVR.

I'll probably dig out my old 486 mainboard with an old ISA IDE Controller
to check if this old thing is able to work with that harddisk. All newer
stuff will do WDMA or UDMA and not PIO like I do with my AVR.

If the 486 is also able to work with that disk, I see two options...

a) get a cheap "open logic sniffer" (logic analysator) and see how good
the timing is (but as I said I added massive delays without success)

b) just accept that there is hardware around in the PC sector which works
"sometimes" ;)

I don't intend to use this harddrive anyway, I just fear that I made a
misstake in my circuit or the code and others intending to use my
emulator also experiencing problems with their drives too.

Regards,
Oliver

Re: IDE knowledge anyone?

2015-12-07 Thread Joseph Lang

Try sector count=1

Joe

> On Dec 6, 2015, at 3:57 PM, Oliver Lehmann  wrote:
> 
> Hi,
> 
> I've built a Harddisk-Controller-Emulator for my system which accesses
> a IDE (PATA) harddisk with an ATMega in PIO mode. It works like a charm
> except for one WD harddisk. The harddisk itself works fine with MS-DOS
> 6.22 and FreeBSD but refuses to work with my ATMega.
> 
> On reading or writing a sector, right after the command is issued, the
> error bit is set in the status register, and the error register indicates
> an ABRT.
> 
> # ABRT:
> # indicates the requested  command has been aborted  due to a
> # drive status error (such as not ready or write fault) or because
> # the command is invalid.
> 
> Right after power up and after the disk got ready, I issue the IDENTIFY
> command and read the data back which works perfectly. After that I
> read sector 0 and this fails.
> 
> I use LBA since the harddisk states that is supportes LBA. Nevertheless
> I also tried accessing the harddisk with CHS mode and got the same error.
> 
> I tested other harddisks which support either CHS+LBA or CHS only. All
> of them work perfectly.
> 
> 
> 
> What happens after powerup to read block 0 of the disk in LBA mode:
> 
> - Setup AVR ports and so on
> - wait until RDY gets high
> - wait until BSY gets low
> - issue a Drive/Head register Command with value 0
> - wait until BSY gets low
> - issue a Command Register Command with value 0xEC (identify device)
> - *read data*
> - process and print out data
> - wait until BSY gets low
> - issue a Sector Count register Command with value 0
> - issue a Sector Number register Command with value 0
> - issue a Cylinder Low register Command with value 0
> - issue a Cylinder High register Command with value 0
> - issue a Drive/Head register Command with 0 + 0xE0 (LBA, Drive 0)
> - issue a Command Register Command with value 0x20 (Read Sector)
> - *read data*
> 
> 
> *read data*:
> 
> - wait until BSY gets low
> - check ERR bit in the Status register <- set on cmd 0x20 here
> - wait until DRQ gets high
> - issue a Data register Command with no data
> - put /RD on low
> - read 512 bytes of data
> - put /RD on high
> - check ERR bit in the Status register
> 
> Issuing a Command works always like setting /CS0, /CS1, /DA0, /DA1,
> /DA2 to low, and then set the needed signals to high so the desired
> command is indicated.
> When data has to be transfered with this command, the lower 8 bits
> are put then onto the port, /WR is set to low afterwards, 3 nop()
> are done and /WR is set back to high.
> 
> Does anyone see an error what could make the drive behave like I said?
> 
> - ATA IDENTIFY works, and the drives data can be read
> - after a read or write sector command is issued, the status register
> directly goes 0xd0 (busy) and with the 2nd fetch 0x59 (not busy, drq
> set, err set)
> 
> Regards, Oliver

Re: IDE knowledge anyone?


Joseph Lang  wrote:


Try sector count=1


Good eyes! :)
Unfortunally it was just a type I made in the mail.

Sector count is of course 1.

Regards, Oliver

Re: IDE knowledge anyone?

2015-12-07 Thread Warner Losh

On Mon, Dec 7, 2015 at 4:35 PM, Brad Parker  wrote:

> On 12/7/15 6:52 AM, Oliver Lehmann wrote:
>
> I don't have much to offer, but I have done PIO IDE accesses on lots of
> cpu's, including small ARM cpu's.  I would put the code into a "read loop"
> and "write loop" and look at the signals with a scope. Make sure they look
> good - i.e. clean edges and the width of the assertion is "ok".  I think
> the minimum is something like 300ns (I may be wrong, that's what I
> remember).   And make sure the address is stable before you assert WE# -
> I'd check that with a scope as well.  If you don't have a scope a simple
> logic analyser will work, but a scope is better.
>
> I seem to recall some drives got unhappy if some of the signals on the IDE
> interface were not exactly right - several need to be grounded and several
> pulled up with a resistor.  You don't mention what your physical interface
> is.  If you do I can dig up my notes and tell you what I've done in the
> past (not that it's authoritative, but it's something to compare with).

One thing that's often forgotten is that some IDE drives redefine what it
means to be low-end. The literature
is littered with stories of drive 'cost reduction' that would make the
original engineers cringe: removing filtering
caps because they weren't needed, removing termination and/or specifying
higher tolerance resistor packs
(which only breaks cables at the limits of the spec), using cheaper caps
that go horrifically bad over time
(both the electrolytic well known to this forum from power supplies, to
others that were cheap because
they were defective). If drive makers could save a buck doing it, you can
be sure at least one of them
has tried with product in the market that may be causing you grief. Things
that shouldn't matter most
of the time will matter. It might even be on your board. Too-slow rise
times, etc from board layout.

tl;dr: get a scope and make sure the signals look clean and meet the
minimums in the specs
by a safe margin.

Warner

Re: IDE knowledge anyone?


And regarding timing... even this drive works without any problem:

=== P8000 WDC Emulator 0.93 ===
INFO: PATA init start
INFO: PATA disk has been found
INFO: Number of logical cylinders: 1001
INFO: Number of logical heads: 15
INFO: Number of logical sectors per logical track: 34
INFO: Serial number:   00DG169020
INFO: Firmware revision: 05.05.01
INFO: Model number: ST3290A
INFO: Capabilities:

Its releasedate should be somewhere in 1994. So it predates the drive
I have problems with for two years:

=== P8000 WDC Emulator 0.93 ===
INFO: PATA init start
INFO: PATA disk has been found
INFO: Number of logical cylinders: 3148
INFO: Number of logical heads: 16
INFO: Number of logical sectors per logical track: 63
INFO: Serial number: WD-WT2891920914
INFO: Firmware revision: 23.16U73
INFO: Model number: WDC AC31600H
INFO: Capabilities: DMA, LBA, IORDY may be disabled, IORDY, Standard  
standby Timer values,

INFO: User addressable sectors for 28-bit commands: 3173184
Single Word DMA modes: 0
Multiword Word DMA modes: 1031
PIO modes: 3
INFO: Minimum Multiword DMA cycle time per word: 120ns
INFO: Recommended Multiword DMA cycle time: 120ns
INFO: Minimum PIO transfer cycle time without flow control: 160ns
INFO: Minimum PIO cycle time with IORDY flow control: 120ns
INFO: Additional support: 0
ERROR: read error at address: 0 / errorcode is: 04

Other WD drives I own from '98 and '99 also work. Also a Samsung 560MB
drive from 1995 which is also doing LBA works fine.

Regards, Oliver


Oliver Lehmann  wrote:


Hi,

OK, i tried now to set Drive/Head first before I set all the other
registers. No success.
I then added a 10ms delay after the data is set for each register,
disable /WR and then wait another 10ms before I execute the next
register.
I also added status checks after each register setting. It stays 0x50
everytime I check it and just after I issue the command it goes to
0x59.

Feel a bit clueless here :/

Oliver


Oliver Lehmann  wrote:


Hi Toby,

Toby Thain  wrote:


I think Jon is probably on to something.

You can check out the delays in my PIO bit-banging code here:
http://www.telegraphics.com.au/svn/picide/trunk/

I tested it on a few drives & spent a lot of quality time with the  
spec...of course I can't guarantee it would work for your specific  
drive, but it might give you a clue where a delay is missing.


I think that what goes wrong in my code is the pure reading/writing
stuff since the IDENTIFY command works without any problem. So I
checked checked your ASM code for the PIC specific for that purpose.

From what I see in "ide_lbacmd" in ide.asm, you wait for BSY and DRQ
to get low, via "ide_devselect", then issue the drive+head register,
wait again for BSY and DRQ still in  "ide_devselect" . Then, back in
"ide_lbacmd" you issue the other sector/cyl/head registers. Right
after that you issue the command to execute without any further
waiting.

Now is the point where I get the error bit - so how the data is read
is probably not important here.

I'll tra to "redo" your code tonight, but beside that you issue the
drive+head first and I do just before I issue the command, I don't
see a big difference here.

I wonder if I could query the drive for the sector/cyl/head data it
works with to see if they where recieved correctly. I guess it just
gets invalid data for at least one of this so it response with ERR
for any read or write command because of "invalid addressing" (I
think).
Do you know if there is a way to find out what sector/cyl/head the
drive tried to process the command?

Regards,
Oliver

Re: IDE knowledge anyone?

2015-12-07 Thread Brad Parker


On 12/7/15 6:52 AM, Oliver Lehmann wrote:

I don't have much to offer, but I have done PIO IDE accesses on lots of 
cpu's, including small ARM cpu's.  I would put the code into a "read 
loop" and "write loop" and look at the signals with a scope. Make sure 
they look good - i.e. clean edges and the width of the assertion is 
"ok".  I think the minimum is something like 300ns (I may be wrong, 
that's what I remember).   And make sure the address is stable before 
you assert WE# - I'd check that with a scope as well.  If you don't have 
a scope a simple logic analyser will work, but a scope is better.


I seem to recall some drives got unhappy if some of the signals on the 
IDE interface were not exactly right - several need to be grounded and 
several pulled up with a resistor.  You don't mention what your physical 
interface is.  If you do I can dig up my notes and tell you what I've 
done in the past (not that it's authoritative, but it's something to 
compare with).


I'm sure you'll figure it out - just keep trying :-)

-brad

Re: IDE knowledge anyone?