from:"Freddy, Ye via Phabricator via cfe\-commits"

[PATCH] D158329: [X86] Support arch=x86-64{,-v2,-v3,-v4} for target_clones attribute

2023-08-22 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:13319
+Value *Features = Builder.CreateAlignedLoad(
+Int32Ty, Builder.CreateGEP(ATy, CpuFeatures2, Idxs),
+CharUnits::fromQuantity(4));

MaskRay wrote:
> FreddyYe wrote:
> > Will function multi version also be fixed in this patch? 
> > https://gcc.godbolt.org/z/cafhs9qbG If so, need to add test in 
> > clang/test/CodeGen/attr-target-mv.c
> The `target` attribute has strange semantics for overloading:
> ```
> int __attribute__((target("arch=skylake"))) foo(void) {return 0;}
> int __attribute__((target("arch=x86-64"))) foo(void) {return 1;}
> ```
> is not allowed in C mode of GCC.
> 
> I think such use cases are not recommended in C++.
> 
> If we don't use overloading, `int __attribute__((target("arch=x86-64"))) 
> foo(void) {return 1;}` is supported by Clang today and this patch does not 
> intend to change anything about it.
I think behavior for `target` attribute is not only overloading but also 
function multiversioning for redefined functions. And seems like C model of gcc 
haven't supported is due to it will target C23 standard: 
https://clang.llvm.org/docs/AttributeReference.html#target 
Comparing to gcc, clang misses not only `target` attribute but also other 
cpuname/feature related features for "x86-64*". See 
https://gcc.godbolt.org/z/arhne35GG (Seems gcc defined x86-64* as not only cpu 
name but also feature name.) Anyway, this patch is targeting for 
`target_clones` attribute only. So no problem here.


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[PATCH] D158329: [X86] Support arch=x86-64{,-v2,-v3,-v4} for target_clones attribute

2023-08-21 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:13317
+  continue;
+Value *Idxs[] = {Builder.getInt32(0), Builder.getInt32(i - 1)};
+Value *Features = Builder.CreateAlignedLoad(

Don't quite understand why we need to change from a i32* into <4 x i32>* and 
the first element here to be always zero.


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[PATCH] D158329: [X86] Support arch=x86-64{,-v2,-v3,-v4} for target_clones attribute

2023-08-21 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:13319
+Value *Features = Builder.CreateAlignedLoad(
+Int32Ty, Builder.CreateGEP(ATy, CpuFeatures2, Idxs),
+CharUnits::fromQuantity(4));

Will function multi version also be fixed in this patch? 
https://gcc.godbolt.org/z/cafhs9qbG If so, need to add test in 
clang/test/CodeGen/attr-target-mv.c


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[PATCH] D158329: [X86] Support arch=x86-64{,-v2,-v3,-v4} for target_clones attribute

2023-08-20 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: compiler-rt/lib/builtins/cpu_model.c:167
+  FEATURE_WP,
+  FEATURE_LZCNT = 57,
+  FEATURE_MOVBE,

` = 57` redundant


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[PATCH] D158046: [X86] Support -march=gracemont

2023-08-20 Thread Freddy, Ye via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6acff5390d05: [X86] Support -march=gracemont (authored by 
FreddyYe).

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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -36,6 +36,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=gracemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -98,6 +99,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=gracemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -430,6 +430,8 @@
   { {"arrowlake_s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
   // Lunarlake microarchitecture based processors.
   { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
+  // Gracemont microarchitecture based processors.
+  { {"gracemont"}, CK_Gracemont, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
   // Sierraforest microarchitecture based processors.
   { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
   // Grandridge microarchitecture based processors.
Index: llvm/lib/TargetParser/Host.cpp
===
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -822,6 +822,8 @@
 // Alderlake:
 case 0x97:
 case 0x9a:
+// Gracemont
+case 0xbe:
 // Raptorlake:
 case 0xb7:
 case 0xba:
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1207,6 +1207,18 @@
   list ADLFeatures =
 !listconcat(TRMFeatures, ADLAdditionalFeatures);
 
+  // Gracemont
+  list GRTTuning = [TuningMacroFusion,
+  TuningSlow3OpsLEA,
+  TuningSlowDivide32,
+  TuningSlowDivide64,
+  TuningFastScalarFSQRT,
+  TuningFastVectorFSQRT,
+  TuningFast15ByteNOP,
+  TuningFastVariablePerLaneShuffle,
+  TuningPOPCNTFalseDeps,
+  TuningInsertVZEROUPPER];
+
   // Sierraforest
   list SRFAdditionalFeatures = [FeatureCMPCCXADD,
   FeatureAVXIFMA,
@@ -1728,6 +1740,9 @@
 ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
 def : ProcModel<"alderlake", AlderlakePModel,
 ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
+// FIXME: Use

[PATCH] D158046: [X86] Support -march=gracemont

2023-08-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: clang/lib/Basic/Targets/X86.cpp:551
   case CK_Lunarlake:
+  case CK_Gracemont:
   case CK_Sierraforest:

RKSimon wrote:
> FreddyYe wrote:
> > RKSimon wrote:
> > > Why not handle this above (below tremont) as the next in the *mont series?
> > Good catch. This isn't a short story... In short words, it was to save 
> > codes in predefined-arch-macros.c.
> > If set gracemont as a series of atom processors, macros like 
> > `corei7`(predefined-arch-macros.c:2061-2062) won't be generated by 
> > `-march=gracemont`, and for history reasons, atom series processors defined 
> > some extra macros of their names, like "tremont", "goldmont", ... but these 
> > macros are not used any longer IIRC. So I decided to define gracemont as a 
> > non-atom series one.
> Hmm - how about we move it after Tremont and then add a comment explaining 
> that going forward atom/e-cores will share p-core defines? 
> ```
> case CK_Tremont:
> defineCPUMacros(Builder, "tremont");
> break;
> case CK_Gracemont:
>   // Gracemont and later atom-cores use p-core cpu macros.
>   [[fallthrough]];
> case CK_Nehalem:
>  ...
> ```
Looks good! I refined a little bit and updated.


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[PATCH] D158046: [X86] Support -march=gracemont

2023-08-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 551350.
FreddyYe marked 2 inline comments as done.
FreddyYe added a comment.

Address comment.


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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -36,6 +36,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=gracemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -98,6 +99,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=gracemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -430,6 +430,8 @@
   { {"arrowlake_s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
   // Lunarlake microarchitecture based processors.
   { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
+  // Gracemont microarchitecture based processors.
+  { {"gracemont"}, CK_Gracemont, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
   // Sierraforest microarchitecture based processors.
   { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
   // Grandridge microarchitecture based processors.
Index: llvm/lib/TargetParser/Host.cpp
===
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -822,6 +822,8 @@
 // Alderlake:
 case 0x97:
 case 0x9a:
+// Gracemont
+case 0xbe:
 // Raptorlake:
 case 0xb7:
 case 0xba:
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1200,6 +1200,18 @@
   list ADLFeatures =
 !listconcat(TRMFeatures, ADLAdditionalFeatures);
 
+  // Gracemont
+  list GRTTuning = [TuningMacroFusion,
+  TuningSlow3OpsLEA,
+  TuningSlowDivide32,
+  TuningSlowDivide64,
+  TuningFastScalarFSQRT,
+  TuningFastVectorFSQRT,
+  TuningFast15ByteNOP,
+  TuningFastVariablePerLaneShuffle,
+  TuningPOPCNTFalseDeps,
+  TuningInsertVZEROUPPER];
+
   // Sierraforest
   list SRFAdditionalFeatures = [FeatureCMPCCXADD,
   FeatureAVXIFMA,
@@ -1721,6 +1733,9 @@
 ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
 def : ProcModel<"alderlake", AlderlakePModel,
 ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
+// FIXME: Use Gracemont Schedule Model when it is ready.
+def : ProcModel<"gracemont", AlderlakePModel,

[PATCH] D158046: [X86] Support -march=gracemont

2023-08-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked an inline comment as done.
FreddyYe added inline comments.



Comment at: clang/lib/Basic/Targets/X86.cpp:551
   case CK_Lunarlake:
+  case CK_Gracemont:
   case CK_Sierraforest:

RKSimon wrote:
> Why not handle this above (below tremont) as the next in the *mont series?
Good catch. This isn't a short story... In short words, it was to save codes in 
predefined-arch-macros.c.
If set gracemont as a series of atom processors, macros like 
`corei7`(predefined-arch-macros.c:2061-2062) won't be generated by 
`-march=gracemont`, and for history reasons, atom series processors defined 
some extra macros of their names, like "tremont", "goldmont", ... but these 
macros are not used any longer IIRC. So I decided to define gracemont as a 
non-atom series one.


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[PATCH] D158046: [X86] Support -march=gracemont

2023-08-15 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe created this revision.
Herald added subscribers: Enna1, pengfei, hiraditya.
Herald added a project: All.
FreddyYe requested review of this revision.
Herald added projects: clang, Sanitizers, LLVM.
Herald added subscribers: llvm-commits, Sanitizers, cfe-commits.

gracemont has some different tuning features from alderlake.


Repository:
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https://reviews.llvm.org/D158046

Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -36,6 +36,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=gracemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -98,6 +99,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=gracemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -430,6 +430,8 @@
   { {"arrowlake_s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
   // Lunarlake microarchitecture based processors.
   { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
+  // Gracemont microarchitecture based processors.
+  { {"gracemont"}, CK_Gracemont, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
   // Sierraforest microarchitecture based processors.
   { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
   // Grandridge microarchitecture based processors.
Index: llvm/lib/TargetParser/Host.cpp
===
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -822,6 +822,8 @@
 // Alderlake:
 case 0x97:
 case 0x9a:
+// Gracemont
+case 0xbe:
 // Raptorlake:
 case 0xb7:
 case 0xba:
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1200,6 +1200,18 @@
   list ADLFeatures =
 !listconcat(TRMFeatures, ADLAdditionalFeatures);
 
+  // Gracemont
+  list GRTTuning = [TuningMacroFusion,
+  TuningSlow3OpsLEA,
+  TuningSlowDivide32,
+  TuningSlowDivide64,
+  TuningFastScalarFSQRT,
+  TuningFastVectorFSQRT,
+  TuningFast15ByteNOP,
+  TuningFastVariablePerLaneShuffle,
+  TuningPOPCNTFalseDeps,
+  TuningInsertVZEROUPPER];
+
   // Sierraforest
   list SRFAdditionalFeatures = [FeatureCMPCCXADD,
   FeatureAVXIFMA,
@@ -1721,6 +1733,9 @@
 ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
 def : ProcModel<"alderlake", AlderlakePModel,
 ProcessorFeatures.ADLFeatures,

[PATCH] D156239: [X86] Support -march=arrowlake, arrowlake-s, lunarlake

2023-07-28 Thread Freddy, Ye via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc9d92e66387b: [X86] Support 
-march=arrowlake,arrowlake-s,lunarlake (authored by FreddyYe).

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  https://reviews.llvm.org/D156239/new/

https://reviews.llvm.org/D156239

Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -32,6 +32,10 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -90,6 +94,10 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -237,6 +237,8 @@
 FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
 constexpr FeatureBitset FeaturesGrandridge =
 FeaturesSierraforest | FeatureRAOINT;
+constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest |
+FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
 
 // Geode Processor.
 constexpr FeatureBitset FeaturesGeode =
@@ -422,6 +424,12 @@
   { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
   // Meteorlake microarchitecture based processors.
   { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
+  // Arrowlake microarchitecture based processors.
+  { {"arrowlake"}, CK_Arrowlake, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
+  { {"arrowlake-s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, '\0', false },
+  { {"arrowlake_s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
+  // Lunarlake microarchitecture based processors.
+  { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
   // Sierraforest microarchitecture based processors.
   { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
   // Grandridge microarchitecture based processors.
Index:

[PATCH] D156239: [X86] Support -march=arrowlake, arrowlake-s, lunarlake

2023-07-27 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 544625.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156239/new/

https://reviews.llvm.org/D156239

Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -32,6 +32,10 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -90,6 +94,10 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -237,6 +237,8 @@
 FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
 constexpr FeatureBitset FeaturesGrandridge =
 FeaturesSierraforest | FeatureRAOINT;
+constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest |
+FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
 
 // Geode Processor.
 constexpr FeatureBitset FeaturesGeode =
@@ -422,6 +424,12 @@
   { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
   // Meteorlake microarchitecture based processors.
   { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
+  // Arrowlake microarchitecture based processors.
+  { {"arrowlake"}, CK_Arrowlake, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
+  { {"arrowlake-s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, '\0', false },
+  { {"arrowlake_s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
+  // Lunarlake microarchitecture based processors.
+  { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
   // Sierraforest microarchitecture based processors.
   { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
   // Grandridge microarchitecture based processors.
Index: llvm/lib/TargetParser/Host.cpp
===
---

[PATCH] D156239: [X86] Support -march=arrowlake, arrowlake-s, lunarlake

2023-07-27 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added a comment.

ping


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[PATCH] D156239: [X86] Support -march=arrowlake, arrowlake-s, lunarlake

2023-07-27 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added a comment.

ping


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[PATCH] D156239: [X86] Support -march=arrowlake, arrowlake-s, lunarlake

2023-07-26 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 544314.
FreddyYe marked 2 inline comments as done.
FreddyYe added a comment.

address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156239/new/

https://reviews.llvm.org/D156239

Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -32,6 +32,10 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -90,6 +94,10 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -237,6 +237,8 @@
 FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
 constexpr FeatureBitset FeaturesGrandridge =
 FeaturesSierraforest | FeatureRAOINT;
+constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest |
+FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
 
 // Geode Processor.
 constexpr FeatureBitset FeaturesGeode =
@@ -422,6 +424,12 @@
   { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
   // Meteorlake microarchitecture based processors.
   { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
+  // Arrowlake microarchitecture based processors.
+  { {"arrowlake"}, CK_Arrowlake, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
+  { {"arrowlake-s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, '\0', false },
+  { {"arrowlake_s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
+  // Lunarlake microarchitecture based processors.
+  { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
   // Sierraforest microarchitecture based processors.
   { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
   // Grandridge microarchitecture based processors.
Index: llvm/lib/TargetParser/Host.cpp
===
---

[PATCH] D156239: [X86] Support -march=arrowlake, arrowlake-s, lunarlake

2023-07-26 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked 3 inline comments as done.
FreddyYe added inline comments.



Comment at: llvm/test/CodeGen/X86/cpus-intel.ll:37
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake-s 
2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake_s 
2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lunarlake 
2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty

RKSimon wrote:
> FreddyYe wrote:
> > RKSimon wrote:
> > > duplicate?
> > No, it is `-` vs `_`
> Got it - does that mean we should have added "graniterapids_d" as well?
Right! I realized that's a missing when I added here. But it may introduce 
conflict here so I prefer to add it in later patch.


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[PATCH] D156239: [X86] Support -march=arrowlake, arrowlake-s, lunarlake

2023-07-26 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked 2 inline comments as done.
FreddyYe added inline comments.



Comment at: llvm/test/CodeGen/X86/cpus-intel.ll:37
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake-s 
2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake_s 
2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lunarlake 
2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty

RKSimon wrote:
> duplicate?
No, it is `-` vs `_`



Comment at: llvm/test/CodeGen/X86/cpus-intel.ll:99
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake-s 
2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake_s 
2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lunarlake 
2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty

RKSimon wrote:
> duplicate?
Same above.


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[PATCH] D156239: [X86] Support -march=arrowlake, arrowlake-s, lunarlake

2023-07-25 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 544159.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

Address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156239/new/

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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -32,6 +32,10 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -90,6 +94,10 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -237,6 +237,8 @@
 FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
 constexpr FeatureBitset FeaturesGrandridge =
 FeaturesSierraforest | FeatureRAOINT;
+constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest |
+FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
 
 // Geode Processor.
 constexpr FeatureBitset FeaturesGeode =
@@ -422,6 +424,12 @@
   { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
   // Meteorlake microarchitecture based processors.
   { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
+  // Arrowlake microarchitecture based processors.
+  { {"arrowlake"}, CK_Arrowlake, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
+  { {"arrowlake-s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, '\0', false },
+  { {"arrowlake_s"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
+  // Lunarlake microarchitecture based processors.
+  { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
   // Sierraforest microarchitecture based processors.
   { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
   // Grandridge microarchitecture based processors.
Index: llvm/lib/TargetParser/Host.cpp
===
---

[PATCH] D156239: [X86] Support -march=arrowlake, arrowlake-s, lunarlake

2023-07-25 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe created this revision.
Herald added subscribers: Enna1, pengfei, hiraditya.
Herald added a project: All.
FreddyYe requested review of this revision.
Herald added projects: clang, Sanitizers, LLVM.
Herald added subscribers: llvm-commits, Sanitizers, cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156239

Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -32,6 +32,10 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -90,6 +94,10 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake-s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=arrowlake_s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lunarlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -237,6 +237,8 @@
 FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
 constexpr FeatureBitset FeaturesGrandridge =
 FeaturesSierraforest | FeatureRAOINT;
+constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest |
+FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
 
 // Geode Processor.
 constexpr FeatureBitset FeaturesGeode =
@@ -422,6 +424,12 @@
   { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
   // Meteorlake microarchitecture based processors.
   { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
+  // Arrowlake microarchitecture based processors.
+  { {"arrowlake"}, CK_Arrowlake, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
+  { {"arrowlake-s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, '\0', false },
+  { {"arrowlake_s"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
+  // Lunarlake microarchitecture based processors.
+  { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
   // Sierraforest microarchitecture based processors.
   { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
   // Grandridge microarchitecture based processors.
Index: llvm/lib/TargetParser/Host.cpp

[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-24 Thread Freddy, Ye via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6d23a3faa4e6: [X86] Support -march=graniterapids-d and 
update -march=graniterapids (authored by FreddyYe).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155798/new/

https://reviews.llvm.org/D155798

Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -30,6 +30,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -88,6 +89,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -210,8 +210,7 @@
 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
 FeatureWAITPKG;
 constexpr FeatureBitset FeaturesGraniteRapids =
-FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI |
-FeatureAMX_COMPLEX;
+FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
@@ -429,6 +428,9 @@
   { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p', false },
   // Granite Rapids microarchitecture based processors.
   { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false },
+  // Granite Rapids D microarchitecture based processors.
+  { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, '\0', false },
+  { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
   // Emerald Rapids microarchitecture based processors.
   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
   // Knights Landing processor.
Index: llvm/lib/TargetParser/Host.cpp
===
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -833,13 +833,19 @@
   break;
 
 // Graniterapids:
-case 0xae:
 case 0xad:
   CPU = "graniterapids";
   *Type = X86::INTEL_COREI7;
   *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
   break;
 
+// Granite Rapids D:
+case 0xae:
+  CPU = "graniterapids-d";
+  *Type = X86::INTEL_COREI7;
+  *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
+  break;
+
 // Icelake Xeon:
 case 0x6a:
 case 0x6c:
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1078,11 +1078,15 @@
 
   // Graniterapids
   list GNRAdditionalFeatures =

[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-24 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 543826.
FreddyYe added a comment.

rebase and fix typo


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155798/new/

https://reviews.llvm.org/D155798

Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -30,6 +30,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -88,6 +89,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -210,8 +210,7 @@
 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
 FeatureWAITPKG;
 constexpr FeatureBitset FeaturesGraniteRapids =
-FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI |
-FeatureAMX_COMPLEX;
+FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
@@ -429,6 +428,9 @@
   { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p', false },
   // Granite Rapids microarchitecture based processors.
   { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false },
+  // Granite Rapids D microarchitecture based processors.
+  { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, '\0', false },
+  { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
   // Emerald Rapids microarchitecture based processors.
   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
   // Knights Landing processor.
Index: llvm/lib/TargetParser/Host.cpp
===
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -833,13 +833,19 @@
   break;
 
 // Graniterapids:
-case 0xae:
 case 0xad:
   CPU = "graniterapids";
   *Type = X86::INTEL_COREI7;
   *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
   break;
 
+// Granite Rapids D:
+case 0xae:
+  CPU = "graniterapids-d";
+  *Type = X86::INTEL_COREI7;
+  *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
+  break;
+
 // Icelake Xeon:
 case 0x6a:
 case 0x6c:
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1078,11 +1078,15 @@
 
   // Graniterapids
   list GNRAdditionalFeatures = [FeatureAMXFP16,
-  FeaturePREFETCHI,
-  FeatureAMXCOMPLEX];
+

[PATCH] D155784: [X86] Update features for sierraforest, grandridge

2023-07-24 Thread Freddy, Ye via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5cc4b1059b28: [X86] Update features for sierraforest, 
grandridge (authored by FreddyYe).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155784/new/

https://reviews.llvm.org/D155784

Files:
  clang/test/Preprocessor/predefined-arch-macros.c
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/X86TargetParser.cpp

Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -234,8 +234,8 @@
 FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
 FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
 constexpr FeatureBitset FeaturesSierraforest =
-FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA |
-FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
+FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
+FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
 constexpr FeatureBitset FeaturesGrandridge =
 FeaturesSierraforest | FeatureRAOINT;
 
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1200,6 +1200,8 @@
   list SRFAdditionalFeatures = [FeatureCMPCCXADD,
   FeatureAVXIFMA,
   FeatureAVXNECONVERT,
+  FeatureENQCMD,
+  FeatureUINTR,
   FeatureAVXVNNIINT8];
   list SRFFeatures =
 !listconcat(ADLFeatures, SRFAdditionalFeatures);
Index: clang/test/Preprocessor/predefined-arch-macros.c
===
--- clang/test/Preprocessor/predefined-arch-macros.c
+++ clang/test/Preprocessor/predefined-arch-macros.c
@@ -2455,6 +2455,9 @@
 // RUN: %clang -march=sierraforest -m32 -E -dM %s -o - 2>&1 \
 // RUN: --target=i386 \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
+// RUN: %clang -march=grandridge -m32 -E -dM %s -o - 2>&1 \
+// RUN: --target=i386 \
+// RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M32,CHECK_GRR_M32
 // CHECK_SRF_M32: #define __ADX__ 1
 // CHECK_SRF_M32: #define __AES__ 1
 // CHECK_SRF_M32: #define __AVX2__ 1
@@ -2470,6 +2473,7 @@
 // CHECK_SRF_M32: #define __CLFLUSHOPT__ 1
 // CHECK_SRF_M32: #define __CLWB__ 1
 // CHECK_SRF_M32: #define __CMPCCXADD__ 1
+// CHECK_SRF_M32: #define __ENQCMD__ 1
 // CHECK_SRF_M32: #define __F16C__ 1
 // CHECK_SRF_M32: #define __FMA__ 1
 // CHECK_SRF_M32: #define __FSGSBASE__ 1
@@ -2489,6 +2493,8 @@
 // CHECK_SRF_M32: #define __POPCNT__ 1
 // CHECK_SRF_M32: #define __PRFCHW__ 1
 // CHECK_SRF_M32: #define __PTWRITE__ 1
+// CHECK_SRF_M32-NOT: #define __RAOINT__ 1
+// CHECK_GRR_M32: #define __RAOINT__ 1
 // CHECK_SRF_M32: #define __RDPID__ 1
 // CHECK_SRF_M32: #define __RDRND__ 1
 // CHECK_SRF_M32: #define __RDSEED__ 1
@@ -2503,6 +2509,7 @@
 // CHECK_SRF_M32: #define __SSE_MATH__ 1
 // CHECK_SRF_M32: #define __SSE__ 1
 // CHECK_SRF_M32: #define __SSSE3__ 1
+// CHECK_SRF_M32: #define __UINTR__ 1
 // CHECK_SRF_M32: #define __VAES__ 1
 // CHECK_SRF_M32: #define __VPCLMULQDQ__ 1
 // CHECK_SRF_M32: #define __WAITPKG__ 1
@@ -2521,6 +2528,9 @@
 // RUN: %clang -march=sierraforest -m64 -E -dM %s -o - 2>&1 \
 // RUN: --target=i386 \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
+// RUN: %clang -march=grandridge -m64 -E -dM %s -o - 2>&1 \
+// RUN: --target=i386 \
+// RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M64,CHECK_GRR_M64
 // CHECK_SRF_M64: #define __ADX__ 1
 // CHECK_SRF_M64: #define __AES__ 1
 // CHECK_SRF_M64: #define __AVX2__ 1
@@ -2536,6 +2546,7 @@
 // CHECK_SRF_M64: #define __CLFLUSHOPT__ 1
 // CHECK_SRF_M64: #define __CLWB__ 1
 // CHECK_SRF_M64: #define __CMPCCXADD__ 1
+// CHECK_SRF_M64: #define __ENQCMD__ 1
 // CHECK_SRF_M64: #define __F16C__ 1
 // CHECK_SRF_M64: #define __FMA__ 1
 // CHECK_SRF_M64: #define __FSGSBASE__ 1
@@ -2555,6 +2566,8 @@
 // CHECK_SRF_M64: #define __POPCNT__ 1
 // CHECK_SRF_M64: #define __PRFCHW__ 1
 // CHECK_SRF_M64: #define __PTWRITE__ 1
+// CHECK_SRF_M64-NOT: #define __RAOINT__ 1
+// CHECK_GRR_M64: #define __RAOINT__ 1
 // CHECK_SRF_M64: #define __RDPID__ 1
 // CHECK_SRF_M64: #define __RDRND__ 1
 // CHECK_SRF_M64: #define __RDSEED__ 1
@@ -2570,6 +2583,7 @@
 // CHECK_SRF_M64: #define __SSE_MATH__ 1
 // CHECK_SRF_M64: #define __SSE__ 1
 // CHECK_SRF_M64: #define __SSSE3__ 1
+// CHECK_SRF_M64: #define __UINTR__ 1
 // CHECK_SRF_M64: #define __VAES__ 1
 // CHECK_SRF_M64: #define __VPCLMULQDQ__ 1
 // CHECK_SRF_M64: #define __WAITPKG__ 1
@@

[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-24 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 543797.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -30,6 +30,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -88,6 +89,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -210,8 +210,7 @@
 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
 FeatureWAITPKG;
 constexpr FeatureBitset FeaturesGraniteRapids =
-FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI |
-FeatureAMX_COMPLEX;
+FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
@@ -429,6 +428,9 @@
   { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p', false },
   // Granite Rapids microarchitecture based processors.
   { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false },
+  // Granite Rapids D microarchitecture based processors.
+  { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, '\0', false },
+  { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
   // Emerald Rapids microarchitecture based processors.
   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
   // Knights Landing processor.
Index: llvm/lib/TargetParser/Host.cpp
===
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -833,13 +833,19 @@
   break;
 
 // Graniterapids:
-case 0xae:
 case 0xad:
   CPU = "graniterapids";
   *Type = X86::INTEL_COREI7;
   *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
   break;
 
+// Granite Rapids D:
+case 0xae:
+  CPU = "graniterapids-d";
+  *Type = X86::INTEL_COREI7;
+  *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
+  break;
+
 // Icelake Xeon:
 case 0x6a:
 case 0x6c:
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1078,11 +1078,15 @@
 
   // Graniterapids
   list GNRAdditionalFeatures = [FeatureAMXFP16,
-  FeaturePREFETCHI,
-

[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-24 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added a comment.

ping


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[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-23 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 543344.
FreddyYe added a comment.

Update cpu_specific required features.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D155798

Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -30,6 +30,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -88,6 +89,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -210,8 +210,7 @@
 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
 FeatureWAITPKG;
 constexpr FeatureBitset FeaturesGraniteRapids =
-FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI |
-FeatureAMX_COMPLEX;
+FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
@@ -428,7 +427,10 @@
   // Grandridge microarchitecture based processors.
   { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p', false },
   // Granite Rapids microarchitecture based processors.
-  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false },
+  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids , 'n', false },
+  // Granite Rapids D microarchitecture based processors.
+  { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, '\0', false },
+  { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
   // Emerald Rapids microarchitecture based processors.
   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
   // Knights Landing processor.
Index: llvm/lib/TargetParser/Host.cpp
===
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -833,13 +833,19 @@
   break;
 
 // Graniterapids:
-case 0xae:
 case 0xad:
   CPU = "graniterapids";
   *Type = X86::INTEL_COREI7;
   *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
   break;
 
+// Granite Rapids D:
+case 0xae:
+  CPU = "graniterapids-d";
+  *Type = X86::INTEL_COREI7;
+  *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
+  break;
+
 // Icelake Xeon:
 case 0x6a:
 case 0x6c:
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1078,11 +1078,15 @@
 
   // Graniterapids
   list GNRAdditionalFeatures

[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-23 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:1082
   FeaturePREFETCHI,
-  FeatureSHA512,
   FeatureAMXCOMPLEX];
   list GNRFeatures =

FreddyYe wrote:
> RKSimon wrote:
> > RKSimon wrote:
> > > If this was incorrect it needs to be removed in its own patch
> > Doesn't the FeatureAMXCOMPLEX need to be on GNRDAdditionalFeatures and 
> > removed from GNRAdditionalFeatures?
> Right. Fixed in 
> https://github.com/llvm/llvm-project/commit/5533fc10219747d1b312f8057edfb10d4d0fcd77
Sorry for mess here. Addressed.


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[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-23 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 543342.
FreddyYe marked 3 inline comments as done.
FreddyYe added a comment.

Rebase and address comments.


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -30,6 +30,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -88,6 +89,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -210,8 +210,7 @@
 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
 FeatureWAITPKG;
 constexpr FeatureBitset FeaturesGraniteRapids =
-FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI |
-FeatureAMX_COMPLEX;
+FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
@@ -428,7 +427,10 @@
   // Grandridge microarchitecture based processors.
   { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p', false },
   // Granite Rapids microarchitecture based processors.
-  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false },
+  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids , 'n', false },
+  // Granite Rapids D microarchitecture based processors.
+  { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', false },
+  { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
   // Emerald Rapids microarchitecture based processors.
   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
   // Knights Landing processor.
Index: llvm/lib/TargetParser/Host.cpp
===
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -833,13 +833,19 @@
   break;
 
 // Graniterapids:
-case 0xae:
 case 0xad:
   CPU = "graniterapids";
   *Type = X86::INTEL_COREI7;
   *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
   break;
 
+// Granite Rapids D:
+case 0xae:
+  CPU = "graniterapids-d";
+  *Type = X86::INTEL_COREI7;
+  *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
+  break;
+
 // Icelake Xeon:
 case 0x6a:
 case 0x6c:
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1078,11 +1078,15 @@
 
   //

[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-23 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked 2 inline comments as done.
FreddyYe added inline comments.



Comment at: llvm/lib/Target/X86/X86.td:1082
   FeaturePREFETCHI,
-  FeatureSHA512,
   FeatureAMXCOMPLEX];

RKSimon wrote:
> RKSimon wrote:
> > If this was incorrect it needs to be removed in its own patch
> Doesn't the FeatureAMXCOMPLEX need to be on GNRDAdditionalFeatures and 
> removed from GNRAdditionalFeatures?
Right. Fixed in 
https://github.com/llvm/llvm-project/commit/5533fc10219747d1b312f8057edfb10d4d0fcd77


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[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-20 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked 2 inline comments as done.
FreddyYe added inline comments.



Comment at: clang/test/Preprocessor/predefined-arch-macros.c:1925
 // CHECK_GNR_M64: #define __AMX_BF16__ 1
-// CHECK_GNR_M64: #define __AMX_COMPLEX__ 1
+// CHECK_GNR_M64-NOT: #define __AMX_COMPLEX__ 1
+// CHECK_GNRD_M64: #define __AMX_COMPLEX__ 1

pengfei wrote:
> FreddyYe wrote:
> > RKSimon wrote:
> > > Won't this fail on the graniterapids-d run?
> > Whops, I didn't realize this problem before! But it indeed doesn't fail. 
> > Need to figure out why...
> I'm guessing when using multi prefixes, it will try to match with the second 
> one if the first failed. It's common and easy to understand for positive 
> check but a bit confusing for negative one.
I did some experiments and arrived at same guessing. It indeed worked here for 
graniterapids-d and checked each `#define` for it.


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[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-20 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked an inline comment as done.
FreddyYe added inline comments.



Comment at: clang/test/Preprocessor/predefined-arch-macros.c:1925
 // CHECK_GNR_M64: #define __AMX_BF16__ 1
-// CHECK_GNR_M64: #define __AMX_COMPLEX__ 1
+// CHECK_GNR_M64-NOT: #define __AMX_COMPLEX__ 1
+// CHECK_GNRD_M64: #define __AMX_COMPLEX__ 1

RKSimon wrote:
> Won't this fail on the graniterapids-d run?
Whops, I didn't realize this problem before! But it indeed doesn't fail. Need 
to figure out why...


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[PATCH] D155784: [X86] Update features for sierraforest, grandridge

2023-07-20 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 542476.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D155784

Files:
  clang/test/Preprocessor/predefined-arch-macros.c
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/X86TargetParser.cpp

Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -234,8 +234,8 @@
 FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
 FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
 constexpr FeatureBitset FeaturesSierraforest =
-FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA |
-FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
+FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
+FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
 constexpr FeatureBitset FeaturesGrandridge =
 FeaturesSierraforest | FeatureRAOINT;
 
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1201,6 +1201,8 @@
   list SRFAdditionalFeatures = [FeatureCMPCCXADD,
   FeatureAVXIFMA,
   FeatureAVXNECONVERT,
+  FeatureENQCMD,
+  FeatureUINTR,
   FeatureAVXVNNIINT8];
   list SRFFeatures =
 !listconcat(ADLFeatures, SRFAdditionalFeatures);
Index: clang/test/Preprocessor/predefined-arch-macros.c
===
--- clang/test/Preprocessor/predefined-arch-macros.c
+++ clang/test/Preprocessor/predefined-arch-macros.c
@@ -2455,6 +2455,9 @@
 // RUN: %clang -march=sierraforest -m32 -E -dM %s -o - 2>&1 \
 // RUN: --target=i386 \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
+// RUN: %clang -march=grandridge -m32 -E -dM %s -o - 2>&1 \
+// RUN: --target=i386 \
+// RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M32,CHECK_GRR_M32
 // CHECK_SRF_M32: #define __ADX__ 1
 // CHECK_SRF_M32: #define __AES__ 1
 // CHECK_SRF_M32: #define __AVX2__ 1
@@ -2470,6 +2473,7 @@
 // CHECK_SRF_M32: #define __CLFLUSHOPT__ 1
 // CHECK_SRF_M32: #define __CLWB__ 1
 // CHECK_SRF_M32: #define __CMPCCXADD__ 1
+// CHECK_SRF_M32: #define __ENQCMD__ 1
 // CHECK_SRF_M32: #define __F16C__ 1
 // CHECK_SRF_M32: #define __FMA__ 1
 // CHECK_SRF_M32: #define __FSGSBASE__ 1
@@ -2489,6 +2493,8 @@
 // CHECK_SRF_M32: #define __POPCNT__ 1
 // CHECK_SRF_M32: #define __PRFCHW__ 1
 // CHECK_SRF_M32: #define __PTWRITE__ 1
+// CHECK_SRF_M32-NOT: #define __RAOINT__ 1
+// CHECK_GRR_M32: #define __RAOINT__ 1
 // CHECK_SRF_M32: #define __RDPID__ 1
 // CHECK_SRF_M32: #define __RDRND__ 1
 // CHECK_SRF_M32: #define __RDSEED__ 1
@@ -2503,6 +2509,7 @@
 // CHECK_SRF_M32: #define __SSE_MATH__ 1
 // CHECK_SRF_M32: #define __SSE__ 1
 // CHECK_SRF_M32: #define __SSSE3__ 1
+// CHECK_SRF_M32: #define __UINTR__ 1
 // CHECK_SRF_M32: #define __VAES__ 1
 // CHECK_SRF_M32: #define __VPCLMULQDQ__ 1
 // CHECK_SRF_M32: #define __WAITPKG__ 1
@@ -2521,6 +2528,9 @@
 // RUN: %clang -march=sierraforest -m64 -E -dM %s -o - 2>&1 \
 // RUN: --target=i386 \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
+// RUN: %clang -march=grandridge -m64 -E -dM %s -o - 2>&1 \
+// RUN: --target=i386 \
+// RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M64,CHECK_GRR_M64
 // CHECK_SRF_M64: #define __ADX__ 1
 // CHECK_SRF_M64: #define __AES__ 1
 // CHECK_SRF_M64: #define __AVX2__ 1
@@ -2536,6 +2546,7 @@
 // CHECK_SRF_M64: #define __CLFLUSHOPT__ 1
 // CHECK_SRF_M64: #define __CLWB__ 1
 // CHECK_SRF_M64: #define __CMPCCXADD__ 1
+// CHECK_SRF_M64: #define __ENQCMD__ 1
 // CHECK_SRF_M64: #define __F16C__ 1
 // CHECK_SRF_M64: #define __FMA__ 1
 // CHECK_SRF_M64: #define __FSGSBASE__ 1
@@ -2555,6 +2566,8 @@
 // CHECK_SRF_M64: #define __POPCNT__ 1
 // CHECK_SRF_M64: #define __PRFCHW__ 1
 // CHECK_SRF_M64: #define __PTWRITE__ 1
+// CHECK_SRF_M64-NOT: #define __RAOINT__ 1
+// CHECK_GRR_M64: #define __RAOINT__ 1
 // CHECK_SRF_M64: #define __RDPID__ 1
 // CHECK_SRF_M64: #define __RDRND__ 1
 // CHECK_SRF_M64: #define __RDSEED__ 1
@@ -2570,6 +2583,7 @@
 // CHECK_SRF_M64: #define __SSE_MATH__ 1
 // CHECK_SRF_M64: #define __SSE__ 1
 // CHECK_SRF_M64: #define __SSSE3__ 1
+// CHECK_SRF_M64: #define __UINTR__ 1
 // CHECK_SRF_M64: #define __VAES__ 1
 // CHECK_SRF_M64: #define __VPCLMULQDQ__ 1
 // CHECK_SRF_M64: #define __WAITPKG__ 1
@@ -2586,142 +2600,6 @@
 // CHECK_SRF_M64: #define __x86_64 1
 // CHECK_SRF_M64: #define __x86_64__ 1
 
-//

[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-20 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 542446.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155798/new/

https://reviews.llvm.org/D155798

Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -30,6 +30,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -88,6 +89,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -210,8 +210,7 @@
 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
 FeatureWAITPKG;
 constexpr FeatureBitset FeaturesGraniteRapids =
-FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI |
-FeatureAMX_COMPLEX;
+FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
@@ -428,7 +427,10 @@
   // Grandridge microarchitecture based processors.
   { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p', false },
   // Granite Rapids microarchitecture based processors.
-  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false },
+  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids , 'n', false },
+  // Granite Rapids D microarchitecture based processors.
+  { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', false },
+  { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
   // Emerald Rapids microarchitecture based processors.
   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
   // Knights Landing processor.
Index: llvm/lib/TargetParser/Host.cpp
===
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -833,13 +833,19 @@
   break;
 
 // Graniterapids:
-case 0xae:
 case 0xad:
   CPU = "graniterapids";
   *Type = X86::INTEL_COREI7;
   *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
   break;
 
+// Granite Rapids D:
+case 0xae:
+  CPU = "graniterapids-d";
+  *Type = X86::INTEL_COREI7;
+  *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
+  break;
+
 // Icelake Xeon:
 case 0x6a:
 case 0x6c:
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1079,11 +1079,16 @@
   // Graniterapids
   list

[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-20 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: clang/test/Preprocessor/predefined-arch-macros.c:1922
+// RUN: --target=x86_64 \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_GNRD_M64
 // CHECK_GNR_M64: #define __AES__ 1

RKSimon wrote:
> Maybe create a common CHECK_GNR_BASE prefix that you can check 
> graniterapids/graniterapids-d against - currently graniterapids-d is barely 
> testing anything
Oh, it should be `-check-prefixes=CHECK_GNR_M64,CHECK_GNRD_M64`
I did this before, like: 
https://github.com/llvm/llvm-project/blob/a2160dd34d56ea5440cbb805657bfee0e2228073/clang/test/Preprocessor/predefined-arch-macros.c#L370


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[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-20 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 542360.
FreddyYe added a comment.

add clang releasenote


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155798/new/

https://reviews.llvm.org/D155798

Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -30,6 +30,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -88,6 +89,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -210,8 +210,7 @@
 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
 FeatureWAITPKG;
 constexpr FeatureBitset FeaturesGraniteRapids =
-FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI |
-FeatureAMX_COMPLEX;
+FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
@@ -428,7 +427,10 @@
   // Grandridge microarchitecture based processors.
   { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p', false },
   // Granite Rapids microarchitecture based processors.
-  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false },
+  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids , 'n', false },
+  // Granite Rapids D microarchitecture based processors.
+  { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', false },
+  { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
   // Emerald Rapids microarchitecture based processors.
   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
   // Knights Landing processor.
Index: llvm/lib/TargetParser/Host.cpp
===
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -833,13 +833,19 @@
   break;
 
 // Graniterapids:
-case 0xae:
 case 0xad:
   CPU = "graniterapids";
   *Type = X86::INTEL_COREI7;
   *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
   break;
 
+// Granite Rapids D:
+case 0xae:
+  CPU = "graniterapids-d";
+  *Type = X86::INTEL_COREI7;
+  *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
+  break;
+
 // Icelake Xeon:
 case 0x6a:
 case 0x6c:
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1079,11 +1079,16 @@
   // Graniterapids
   list GNRAdditionalFeatures = [FeatureAMXFP16,

[PATCH] D155798: [X86] Support -march=graniterapids-d and update -march=graniterapids

2023-07-20 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe created this revision.
Herald added subscribers: Enna1, pengfei, hiraditya.
Herald added a project: All.
FreddyYe requested review of this revision.
Herald added projects: clang, Sanitizers, LLVM.
Herald added subscribers: llvm-commits, Sanitizers, cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155798

Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-target-mv.c
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -30,6 +30,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=emeraldrapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -88,6 +89,7 @@
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sierraforest 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=grandridge 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=graniterapids-d 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -210,8 +210,7 @@
 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
 FeatureWAITPKG;
 constexpr FeatureBitset FeaturesGraniteRapids =
-FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI |
-FeatureAMX_COMPLEX;
+FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
@@ -428,7 +427,10 @@
   // Grandridge microarchitecture based processors.
   { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p', false },
   // Granite Rapids microarchitecture based processors.
-  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false },
+  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids , 'n', false },
+  // Granite Rapids D microarchitecture based processors.
+  { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', false },
+  { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
   // Emerald Rapids microarchitecture based processors.
   { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
   // Knights Landing processor.
Index: llvm/lib/TargetParser/Host.cpp
===
--- llvm/lib/TargetParser/Host.cpp
+++ llvm/lib/TargetParser/Host.cpp
@@ -833,13 +833,19 @@
   break;
 
 // Graniterapids:
-case 0xae:
 case 0xad:
   CPU = "graniterapids";
   *Type = X86::INTEL_COREI7;
   *Subtype = X86::INTEL_COREI7_GRANITERAPIDS;
   break;
 
+// Granite Rapids D:
+case 0xae:
+  CPU = "graniterapids-d";
+  *Type = X86::INTEL_COREI7;
+  *Subtype = X86::INTEL_COREI7_GRANITERAPIDS_D;
+  break;
+
 // Icelake Xeon:
 case 0x6a:
 case 0x6c:
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1079,11

[PATCH] D155784: [X86] Update features for sierraforest, grandridge

2023-07-20 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe created this revision.
Herald added subscribers: pengfei, hiraditya.
Herald added a project: All.
FreddyYe requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155784

Files:
  clang/test/Preprocessor/predefined-arch-macros.c
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/X86TargetParser.cpp

Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -234,8 +234,8 @@
 FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
 FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
 constexpr FeatureBitset FeaturesSierraforest =
-FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA |
-FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
+FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
+FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
 constexpr FeatureBitset FeaturesGrandridge =
 FeaturesSierraforest | FeatureRAOINT;
 
Index: llvm/lib/Target/X86/X86.td
===
--- llvm/lib/Target/X86/X86.td
+++ llvm/lib/Target/X86/X86.td
@@ -1201,6 +1201,8 @@
   list SRFAdditionalFeatures = [FeatureCMPCCXADD,
   FeatureAVXIFMA,
   FeatureAVXNECONVERT,
+  FeatureENQCMD,
+  FeatureUINTR,
   FeatureAVXVNNIINT8];
   list SRFFeatures =
 !listconcat(ADLFeatures, SRFAdditionalFeatures);
Index: clang/test/Preprocessor/predefined-arch-macros.c
===
--- clang/test/Preprocessor/predefined-arch-macros.c
+++ clang/test/Preprocessor/predefined-arch-macros.c
@@ -2455,6 +2455,9 @@
 // RUN: %clang -march=sierraforest -m32 -E -dM %s -o - 2>&1 \
 // RUN: --target=i386 \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M32
+// RUN: %clang -march=grandridge -m32 -E -dM %s -o - 2>&1 \
+// RUN: --target=i386 \
+// RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M32,CHECK_GRR_M32
 // CHECK_SRF_M32: #define __ADX__ 1
 // CHECK_SRF_M32: #define __AES__ 1
 // CHECK_SRF_M32: #define __AVX2__ 1
@@ -2470,6 +2473,7 @@
 // CHECK_SRF_M32: #define __CLFLUSHOPT__ 1
 // CHECK_SRF_M32: #define __CLWB__ 1
 // CHECK_SRF_M32: #define __CMPCCXADD__ 1
+// CHECK_SRF_M32: #define __ENQCMD__ 1
 // CHECK_SRF_M32: #define __F16C__ 1
 // CHECK_SRF_M32: #define __FMA__ 1
 // CHECK_SRF_M32: #define __FSGSBASE__ 1
@@ -2489,6 +2493,7 @@
 // CHECK_SRF_M32: #define __POPCNT__ 1
 // CHECK_SRF_M32: #define __PRFCHW__ 1
 // CHECK_SRF_M32: #define __PTWRITE__ 1
+// CHECK_GRR_M32: #define __RAOINT__ 1
 // CHECK_SRF_M32: #define __RDPID__ 1
 // CHECK_SRF_M32: #define __RDRND__ 1
 // CHECK_SRF_M32: #define __RDSEED__ 1
@@ -2503,6 +2508,7 @@
 // CHECK_SRF_M32: #define __SSE_MATH__ 1
 // CHECK_SRF_M32: #define __SSE__ 1
 // CHECK_SRF_M32: #define __SSSE3__ 1
+// CHECK_SRF_M32: #define __UINTR__ 1
 // CHECK_SRF_M32: #define __VAES__ 1
 // CHECK_SRF_M32: #define __VPCLMULQDQ__ 1
 // CHECK_SRF_M32: #define __WAITPKG__ 1
@@ -2521,6 +2527,9 @@
 // RUN: %clang -march=sierraforest -m64 -E -dM %s -o - 2>&1 \
 // RUN: --target=i386 \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SRF_M64
+// RUN: %clang -march=grandridge -m64 -E -dM %s -o - 2>&1 \
+// RUN: --target=i386 \
+// RUN:   | FileCheck -match-full-lines %s -check-prefixes=CHECK_SRF_M64,CHECK_GRR_M64
 // CHECK_SRF_M64: #define __ADX__ 1
 // CHECK_SRF_M64: #define __AES__ 1
 // CHECK_SRF_M64: #define __AVX2__ 1
@@ -2536,6 +2545,7 @@
 // CHECK_SRF_M64: #define __CLFLUSHOPT__ 1
 // CHECK_SRF_M64: #define __CLWB__ 1
 // CHECK_SRF_M64: #define __CMPCCXADD__ 1
+// CHECK_SRF_M64: #define __ENQCMD__ 1
 // CHECK_SRF_M64: #define __F16C__ 1
 // CHECK_SRF_M64: #define __FMA__ 1
 // CHECK_SRF_M64: #define __FSGSBASE__ 1
@@ -2555,6 +2565,7 @@
 // CHECK_SRF_M64: #define __POPCNT__ 1
 // CHECK_SRF_M64: #define __PRFCHW__ 1
 // CHECK_SRF_M64: #define __PTWRITE__ 1
+// CHECK_GRR_M64: #define __RAOINT__ 1
 // CHECK_SRF_M64: #define __RDPID__ 1
 // CHECK_SRF_M64: #define __RDRND__ 1
 // CHECK_SRF_M64: #define __RDSEED__ 1
@@ -2570,6 +2581,7 @@
 // CHECK_SRF_M64: #define __SSE_MATH__ 1
 // CHECK_SRF_M64: #define __SSE__ 1
 // CHECK_SRF_M64: #define __SSSE3__ 1
+// CHECK_SRF_M64: #define __UINTR__ 1
 // CHECK_SRF_M64: #define __VAES__ 1
 // CHECK_SRF_M64: #define __VPCLMULQDQ__ 1
 // CHECK_SRF_M64: #define __WAITPKG__ 1
@@ -2586,142 +2598,6 @@
 // CHECK_SRF_M64: #define __x86_64 1
 // CHECK_SRF_M64: #define __x86_64__ 1
 
-// RUN: %clang -march=grandridge -m32 -E -dM %s -o -

[PATCH] D155148: [X86] Add SM4 instructions.

2023-07-19 Thread Freddy, Ye via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG049d6a3f428e: [X86] Add SM4 instructions. (authored by 
FreddyYe).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155148/new/

https://reviews.llvm.org/D155148

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm4intrin.h
  clang/test/CodeGen/X86/sm4-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm4-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm4-32.txt
  llvm/test/MC/Disassembler/X86/sm4-64.txt
  llvm/test/MC/X86/sm4-32-att.s
  llvm/test/MC/X86/sm4-32-intel.s
  llvm/test/MC/X86/sm4-64-att.s
  llvm/test/MC/X86/sm4-64-intel.s
  llvm/test/TableGen/x86-fold-tables.inc

Index: llvm/test/TableGen/x86-fold-tables.inc
===
--- llvm/test/TableGen/x86-fold-tables.inc
+++ llvm/test/TableGen/x86-fold-tables.inc
@@ -3169,6 +3169,10 @@
   {X86::VSHUFPSZ256rri, X86::VSHUFPSZ256rmi, 0},
   {X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0},
   {X86::VSHUFPSrri, X86::VSHUFPSrmi, 0},
+  {X86::VSM4KEY4Yrr, X86::VSM4KEY4Yrm, 0},
+  {X86::VSM4KEY4rr, X86::VSM4KEY4rm, 0},
+  {X86::VSM4RNDS4Yrr, X86::VSM4RNDS4Yrm, 0},
+  {X86::VSM4RNDS4rr, X86::VSM4RNDS4rm, 0},
   {X86::VSQRTPDZ128rkz, X86::VSQRTPDZ128mkz, 0},
   {X86::VSQRTPDZ256rkz, X86::VSQRTPDZ256mkz, 0},
   {X86::VSQRTPDZrkz, X86::VSQRTPDZmkz, 0},
Index: llvm/test/MC/X86/sm4-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm4-64-intel.s
@@ -0,0 +1,114 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm4key4 ymm12, ymm13, ymm4
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xe4]
+  vsm4key4 ymm12, ymm13, ymm4
+
+// CHECK: vsm4key4 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xe4]
+  vsm4key4 xmm12, xmm13, xmm4
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x16,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x16,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff]
+  vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa1,0xe0,0x0f,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa2,0x00,0xf0,0xff,0xff]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x12,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x12,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK:

[PATCH] D155148: [X86] Add SM4 instructions.

2023-07-19 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 542305.
FreddyYe added a comment.

rebase and fix lit fail


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155148/new/

https://reviews.llvm.org/D155148

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm4intrin.h
  clang/test/CodeGen/X86/sm4-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm4-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm4-32.txt
  llvm/test/MC/Disassembler/X86/sm4-64.txt
  llvm/test/MC/X86/sm4-32-att.s
  llvm/test/MC/X86/sm4-32-intel.s
  llvm/test/MC/X86/sm4-64-att.s
  llvm/test/MC/X86/sm4-64-intel.s
  llvm/test/TableGen/x86-fold-tables.inc

Index: llvm/test/TableGen/x86-fold-tables.inc
===
--- llvm/test/TableGen/x86-fold-tables.inc
+++ llvm/test/TableGen/x86-fold-tables.inc
@@ -3169,6 +3169,10 @@
   {X86::VSHUFPSZ256rri, X86::VSHUFPSZ256rmi, 0},
   {X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0},
   {X86::VSHUFPSrri, X86::VSHUFPSrmi, 0},
+  {X86::VSM4KEY4Yrr, X86::VSM4KEY4Yrm, 0},
+  {X86::VSM4KEY4rr, X86::VSM4KEY4rm, 0},
+  {X86::VSM4RNDS4Yrr, X86::VSM4RNDS4Yrm, 0},
+  {X86::VSM4RNDS4rr, X86::VSM4RNDS4rm, 0},
   {X86::VSQRTPDZ128rkz, X86::VSQRTPDZ128mkz, 0},
   {X86::VSQRTPDZ256rkz, X86::VSQRTPDZ256mkz, 0},
   {X86::VSQRTPDZrkz, X86::VSQRTPDZmkz, 0},
Index: llvm/test/MC/X86/sm4-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm4-64-intel.s
@@ -0,0 +1,114 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm4key4 ymm12, ymm13, ymm4
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xe4]
+  vsm4key4 ymm12, ymm13, ymm4
+
+// CHECK: vsm4key4 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xe4]
+  vsm4key4 xmm12, xmm13, xmm4
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x16,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x16,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff]
+  vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa1,0xe0,0x0f,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa2,0x00,0xf0,0xff,0xff]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x12,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x12,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymm4
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xe4]
+  vsm4rnds4 ymm12, ymm13, ymm4
+
+//

[PATCH] D155145: [X86] Add AVX-VNNI-INT16 instructions.

2023-07-19 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added a comment.

ping... Anyone help accept?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155145/new/

https://reviews.llvm.org/D155145

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[PATCH] D155147: [X86] Add SM3 instructions.

2023-07-19 Thread Freddy, Ye via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc6f66de21af0: [X86] Add SM3 instructions. (authored by 
FreddyYe).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155147/new/

https://reviews.llvm.org/D155147

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s
  llvm/test/TableGen/x86-fold-tables.inc

Index: llvm/test/TableGen/x86-fold-tables.inc
===
--- llvm/test/TableGen/x86-fold-tables.inc
+++ llvm/test/TableGen/x86-fold-tables.inc
@@ -4800,6 +4800,9 @@
   {X86::VSHUFPSZ128rrikz, X86::VSHUFPSZ128rmikz, 0},
   {X86::VSHUFPSZ256rrikz, X86::VSHUFPSZ256rmikz, 0},
   {X86::VSHUFPSZrrikz, X86::VSHUFPSZrmikz, 0},
+  {X86::VSM3MSG1rr, X86::VSM3MSG1rm, 0},
+  {X86::VSM3MSG2rr, X86::VSM3MSG2rm, 0},
+  {X86::VSM3RNDS2rr, X86::VSM3RNDS2rm, 0},
   {X86::VSQRTPDZ128rk, X86::VSQRTPDZ128mk, 0},
   {X86::VSQRTPDZ256rk, X86::VSQRTPDZ256mk, 0},
   {X86::VSQRTPDZrk, X86::VSQRTPDZmk, 0},
Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
+  vsm3msg1 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
+  vsm3msg2 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr

[PATCH] D155147: [X86] Add SM3 instructions.

2023-07-19 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 542274.
FreddyYe added a comment.

rebase and fix lit fail


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155147/new/

https://reviews.llvm.org/D155147

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s
  llvm/test/TableGen/x86-fold-tables.inc

Index: llvm/test/TableGen/x86-fold-tables.inc
===
--- llvm/test/TableGen/x86-fold-tables.inc
+++ llvm/test/TableGen/x86-fold-tables.inc
@@ -4800,6 +4800,9 @@
   {X86::VSHUFPSZ128rrikz, X86::VSHUFPSZ128rmikz, 0},
   {X86::VSHUFPSZ256rrikz, X86::VSHUFPSZ256rmikz, 0},
   {X86::VSHUFPSZrrikz, X86::VSHUFPSZrmikz, 0},
+  {X86::VSM3MSG1rr, X86::VSM3MSG1rm, 0},
+  {X86::VSM3MSG2rr, X86::VSM3MSG2rm, 0},
+  {X86::VSM3RNDS2rr, X86::VSM3RNDS2rm, 0},
   {X86::VSQRTPDZ128rk, X86::VSQRTPDZ128mk, 0},
   {X86::VSQRTPDZ256rk, X86::VSQRTPDZ256mk, 0},
   {X86::VSQRTPDZrk, X86::VSQRTPDZmk, 0},
Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
+  vsm3msg1 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
+  vsm3msg2 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmm4, 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
+

[PATCH] D155146: [X86] Add SHA512 instructions.

2023-07-19 Thread Freddy, Ye via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGfc3b7874b6c9: [X86] Add SHA512 instructions. (authored by 
FreddyYe).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512-32.txt
  llvm/test/MC/Disassembler/X86/sha512-64.txt
  llvm/test/MC/X86/sha512-32-att.s
  llvm/test/MC/X86/sha512-32-intel.s
  llvm/test/MC/X86/sha512-64-att.s
  llvm/test/MC/X86/sha512-64-intel.s

Index: llvm/test/MC/X86/sha512-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-64-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsha512msg1 ymm12, xmm3
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3]
+  vsha512msg1 ymm12, xmm3
+
+// CHECK: vsha512msg2 ymm12, ymm3
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3]
+  vsha512msg2 ymm12, ymm3
+
+// CHECK: vsha512rnds2 ymm12, ymm3, xmm4
+// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4]
+  vsha512rnds2 ymm12, ymm3, xmm4
+
Index: llvm/test/MC/X86/sha512-64-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-64-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK: vsha512msg1 %xmm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3]
+  vsha512msg1 %xmm3, %ymm12
+
+// CHECK: vsha512msg2 %ymm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3]
+  vsha512msg2 %ymm3, %ymm12
+
+// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4]
+  vsha512rnds2 %xmm4, %ymm3, %ymm12
+
Index: llvm/test/MC/X86/sha512-32-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-32-intel.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-32-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-32-att.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512-64.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512-64.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   vsha512msg1 %xmm3, %ymm12
+# INTEL: vsha512msg1 ymm12, xmm3
+0xc4,0x62,0x7f,0xcc,0xe3
+
+# ATT:   vsha512msg2 %ymm3, %ymm12
+# INTEL: vsha512msg2 ymm12, ymm3
+0xc4,0x62,0x7f,0xcd,0xe3
+
+# ATT:   vsha512rnds2 %xmm4, %ymm3, %ymm12
+# INTEL: vsha512rnds2 ymm12, ymm3, xmm4
+0xc4,0x62,0x67,0xcb,0xe4
+
Index: llvm/test/MC/Disassembler/X86/sha512-32.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512-32.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 |

[PATCH] D155146: [X86] Add SHA512 instructions.

2023-07-19 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 542267.
FreddyYe added a comment.

rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512-32.txt
  llvm/test/MC/Disassembler/X86/sha512-64.txt
  llvm/test/MC/X86/sha512-32-att.s
  llvm/test/MC/X86/sha512-32-intel.s
  llvm/test/MC/X86/sha512-64-att.s
  llvm/test/MC/X86/sha512-64-intel.s

Index: llvm/test/MC/X86/sha512-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-64-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsha512msg1 ymm12, xmm3
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3]
+  vsha512msg1 ymm12, xmm3
+
+// CHECK: vsha512msg2 ymm12, ymm3
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3]
+  vsha512msg2 ymm12, ymm3
+
+// CHECK: vsha512rnds2 ymm12, ymm3, xmm4
+// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4]
+  vsha512rnds2 ymm12, ymm3, xmm4
+
Index: llvm/test/MC/X86/sha512-64-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-64-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK: vsha512msg1 %xmm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3]
+  vsha512msg1 %xmm3, %ymm12
+
+// CHECK: vsha512msg2 %ymm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3]
+  vsha512msg2 %ymm3, %ymm12
+
+// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4]
+  vsha512rnds2 %xmm4, %ymm3, %ymm12
+
Index: llvm/test/MC/X86/sha512-32-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-32-intel.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-32-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-32-att.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512-64.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512-64.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   vsha512msg1 %xmm3, %ymm12
+# INTEL: vsha512msg1 ymm12, xmm3
+0xc4,0x62,0x7f,0xcc,0xe3
+
+# ATT:   vsha512msg2 %ymm3, %ymm12
+# INTEL: vsha512msg2 ymm12, ymm3
+0xc4,0x62,0x7f,0xcd,0xe3
+
+# ATT:   vsha512rnds2 %xmm4, %ymm3, %ymm12
+# INTEL: vsha512rnds2 ymm12, ymm3, xmm4
+0xc4,0x62,0x67,0xcb,0xe4
+
Index: llvm/test/MC/Disassembler/X86/sha512-32.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512-32.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+#

[PATCH] D155147: [X86] Add SM3 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541824.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155147/new/

https://reviews.llvm.org/D155147

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s

Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
+  vsm3msg1 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
+  vsm3msg2 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmm4, 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmm4, 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b]
+

[PATCH] D155147: [X86] Add SM3 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541815.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

Address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155147/new/

https://reviews.llvm.org/D155147

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s

Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
+  vsm3msg1 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
+  vsm3msg2 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmm4, 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmm4, 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b]
+

[PATCH] D155146: [X86] Add SHA512 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked 3 inline comments as done.
FreddyYe added a comment.

I think we can discuss this issue first in https://reviews.llvm.org/D155662


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

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[PATCH] D155146: [X86] Add SHA512 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541793.
FreddyYe added a comment.

Add missing doxygen


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512-32.txt
  llvm/test/MC/Disassembler/X86/sha512-64.txt
  llvm/test/MC/X86/sha512-32-att.s
  llvm/test/MC/X86/sha512-32-intel.s
  llvm/test/MC/X86/sha512-64-att.s
  llvm/test/MC/X86/sha512-64-intel.s

Index: llvm/test/MC/X86/sha512-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-64-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsha512msg1 ymm12, xmm3
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3]
+  vsha512msg1 ymm12, xmm3
+
+// CHECK: vsha512msg2 ymm12, ymm3
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3]
+  vsha512msg2 ymm12, ymm3
+
+// CHECK: vsha512rnds2 ymm12, ymm3, xmm4
+// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4]
+  vsha512rnds2 ymm12, ymm3, xmm4
+
Index: llvm/test/MC/X86/sha512-64-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-64-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK: vsha512msg1 %xmm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3]
+  vsha512msg1 %xmm3, %ymm12
+
+// CHECK: vsha512msg2 %ymm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3]
+  vsha512msg2 %ymm3, %ymm12
+
+// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4]
+  vsha512rnds2 %xmm4, %ymm3, %ymm12
+
Index: llvm/test/MC/X86/sha512-32-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-32-intel.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-32-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-32-att.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512-64.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512-64.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   vsha512msg1 %xmm3, %ymm12
+# INTEL: vsha512msg1 ymm12, xmm3
+0xc4,0x62,0x7f,0xcc,0xe3
+
+# ATT:   vsha512msg2 %ymm3, %ymm12
+# INTEL: vsha512msg2 ymm12, ymm3
+0xc4,0x62,0x7f,0xcd,0xe3
+
+# ATT:   vsha512rnds2 %xmm4, %ymm3, %ymm12
+# INTEL: vsha512rnds2 ymm12, ymm3, xmm4
+0xc4,0x62,0x67,0xcb,0xe4
+
Index: llvm/test/MC/Disassembler/X86/sha512-32.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512-32.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s

[PATCH] D155147: [X86] Add SM3 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: clang/lib/Headers/sm3intrin.h:230
+/// \endcode
+#define _mm_sm3rnds2_epi32(A, B, C, D) 
\
+  (__m128i) __builtin_ia32_vsm3rnds2((__v4su)A, (__v4su)B, (__v4su)C, (int)D)

pengfei wrote:
> Missing `__` for variables.
MACROs prefer no __ for prefix and the operation defines A, B, C, ... So I used 
another naming convention in doxygen for parameters.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D155147: [X86] Add SM3 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541792.
FreddyYe marked 5 inline comments as done.
FreddyYe added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155147/new/

https://reviews.llvm.org/D155147

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s

Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
+  vsm3msg1 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
+  vsm3msg2 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmm4, 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmm4, 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b]
+

[PATCH] D155148: [X86] Add SM4 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541787.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

Address comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155148/new/

https://reviews.llvm.org/D155148

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm4intrin.h
  clang/test/CodeGen/X86/sm4-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm4-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm4-32.txt
  llvm/test/MC/Disassembler/X86/sm4-64.txt
  llvm/test/MC/X86/sm4-32-att.s
  llvm/test/MC/X86/sm4-32-intel.s
  llvm/test/MC/X86/sm4-64-att.s
  llvm/test/MC/X86/sm4-64-intel.s

Index: llvm/test/MC/X86/sm4-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm4-64-intel.s
@@ -0,0 +1,114 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm4key4 ymm12, ymm13, ymm4
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xe4]
+  vsm4key4 ymm12, ymm13, ymm4
+
+// CHECK: vsm4key4 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xe4]
+  vsm4key4 xmm12, xmm13, xmm4
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x16,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x16,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff]
+  vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa1,0xe0,0x0f,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa2,0x00,0xf0,0xff,0xff]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x12,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x12,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymm4
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xe4]
+  vsm4rnds4 ymm12, ymm13, ymm4
+
+// CHECK: vsm4rnds4 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xe4]
+  vsm4rnds4 xmm12, xmm13, xmm4
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x17,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4rnds4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x17,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4rnds4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0x25,0x00,0x00,0x00,0x00]
+

[PATCH] D155146: [X86] Add SHA512 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541503.
FreddyYe added a comment.

Remove -x86-asm-syntax=intel


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512-32.txt
  llvm/test/MC/Disassembler/X86/sha512-64.txt
  llvm/test/MC/X86/sha512-32-att.s
  llvm/test/MC/X86/sha512-32-intel.s
  llvm/test/MC/X86/sha512-64-att.s
  llvm/test/MC/X86/sha512-64-intel.s

Index: llvm/test/MC/X86/sha512-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-64-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsha512msg1 ymm12, xmm3
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3]
+  vsha512msg1 ymm12, xmm3
+
+// CHECK: vsha512msg2 ymm12, ymm3
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3]
+  vsha512msg2 ymm12, ymm3
+
+// CHECK: vsha512rnds2 ymm12, ymm3, xmm4
+// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4]
+  vsha512rnds2 ymm12, ymm3, xmm4
+
Index: llvm/test/MC/X86/sha512-64-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-64-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK: vsha512msg1 %xmm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3]
+  vsha512msg1 %xmm3, %ymm12
+
+// CHECK: vsha512msg2 %ymm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3]
+  vsha512msg2 %ymm3, %ymm12
+
+// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4]
+  vsha512rnds2 %xmm4, %ymm3, %ymm12
+
Index: llvm/test/MC/X86/sha512-32-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-32-intel.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-32-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-32-att.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512-64.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512-64.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   vsha512msg1 %xmm3, %ymm12
+# INTEL: vsha512msg1 ymm12, xmm3
+0xc4,0x62,0x7f,0xcc,0xe3
+
+# ATT:   vsha512msg2 %ymm3, %ymm12
+# INTEL: vsha512msg2 ymm12, ymm3
+0xc4,0x62,0x7f,0xcd,0xe3
+
+# ATT:   vsha512rnds2 %xmm4, %ymm3, %ymm12
+# INTEL: vsha512rnds2 ymm12, ymm3, xmm4
+0xc4,0x62,0x67,0xcb,0xe4
+
Index: llvm/test/MC/Disassembler/X86/sha512-32.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512-32.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s

[PATCH] D155146: [X86] Add SHA512 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541502.
FreddyYe added a comment.

Split assembly tests and cover more registers.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512-32.txt
  llvm/test/MC/Disassembler/X86/sha512-64.txt
  llvm/test/MC/X86/sha512-32-att.s
  llvm/test/MC/X86/sha512-32-intel.s
  llvm/test/MC/X86/sha512-64-att.s
  llvm/test/MC/X86/sha512-64-intel.s

Index: llvm/test/MC/X86/sha512-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-64-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsha512msg1 ymm12, xmm3
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3]
+  vsha512msg1 ymm12, xmm3
+
+// CHECK: vsha512msg2 ymm12, ymm3
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3]
+  vsha512msg2 ymm12, ymm3
+
+// CHECK: vsha512rnds2 ymm12, ymm3, xmm4
+// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4]
+  vsha512rnds2 ymm12, ymm3, xmm4
+
Index: llvm/test/MC/X86/sha512-64-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-64-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK: vsha512msg1 %xmm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcc,0xe3]
+  vsha512msg1 %xmm3, %ymm12
+
+// CHECK: vsha512msg2 %ymm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x7f,0xcd,0xe3]
+  vsha512msg2 %ymm3, %ymm12
+
+// CHECK: vsha512rnds2 %xmm4, %ymm3, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x67,0xcb,0xe4]
+  vsha512rnds2 %xmm4, %ymm3, %ymm12
+
Index: llvm/test/MC/X86/sha512-32-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-32-intel.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-32-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-32-att.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512-64.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512-64.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   vsha512msg1 %xmm3, %ymm12
+# INTEL: vsha512msg1 ymm12, xmm3
+0xc4,0x62,0x7f,0xcc,0xe3
+
+# ATT:   vsha512msg2 %ymm3, %ymm12
+# INTEL: vsha512msg2 ymm12, ymm3
+0xc4,0x62,0x7f,0xcd,0xe3
+
+# ATT:   vsha512rnds2 %xmm4, %ymm3, %ymm12
+# INTEL: vsha512rnds2 ymm12, ymm3, xmm4
+0xc4,0x62,0x67,0xcb,0xe4
+
Index: llvm/test/MC/Disassembler/X86/sha512-32.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512-32.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386

[PATCH] D155148: [X86] Add SM4 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541496.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155148/new/

https://reviews.llvm.org/D155148

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm4intrin.h
  clang/test/CodeGen/X86/sm4-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm4-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm4-32.txt
  llvm/test/MC/Disassembler/X86/sm4-64.txt
  llvm/test/MC/X86/sm4-32-att.s
  llvm/test/MC/X86/sm4-32-intel.s
  llvm/test/MC/X86/sm4-64-att.s
  llvm/test/MC/X86/sm4-64-intel.s

Index: llvm/test/MC/X86/sm4-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm4-64-intel.s
@@ -0,0 +1,114 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm4key4 ymm12, ymm13, ymm4
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xe4]
+  vsm4key4 ymm12, ymm13, ymm4
+
+// CHECK: vsm4key4 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xe4]
+  vsm4key4 xmm12, xmm13, xmm4
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x16,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x16,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff]
+  vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa1,0xe0,0x0f,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa2,0x00,0xf0,0xff,0xff]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x12,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x12,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymm4
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xe4]
+  vsm4rnds4 ymm12, ymm13, ymm4
+
+// CHECK: vsm4rnds4 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xe4]
+  vsm4rnds4 xmm12, xmm13, xmm4
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x17,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4rnds4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x17,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4rnds4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0x25,0x00,0x00,0x00,0x00]
+

[PATCH] D155147: [X86] Add SM3 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541495.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155147/new/

https://reviews.llvm.org/D155147

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s

Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
+  vsm3msg1 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
+  vsm3msg2 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmm4, 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmm4, 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b]
+

[PATCH] D155146: [X86] Add SHA512 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541392.
FreddyYe marked 2 inline comments as done.
FreddyYe added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512.txt
  llvm/test/MC/X86/sha512-att.s
  llvm/test/MC/X86/sha512-intel.s

Index: llvm/test/MC/X86/sha512-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512.txt
@@ -0,0 +1,17 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:vsha512msg1 %xmm3, %ymm2
+# INTEL:  vsha512msg1 ymm2, xmm3
+0xc4,0xe2,0x7f,0xcc,0xd3
+
+# ATT:vsha512msg2 %ymm3, %ymm2
+# INTEL:  vsha512msg2 ymm2, ymm3
+0xc4,0xe2,0x7f,0xcd,0xd3
+
+# ATT:vsha512rnds2 %xmm4, %ymm3, %ymm2
+# INTEL:  vsha512rnds2 ymm2, ymm3, xmm4
+0xc4,0xe2,0x67,0xcb,0xd4
+
Index: llvm/test/CodeGen/X86/sha512-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/sha512-intrinsics.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s
+
+define <4 x i64> @test_int_x86_vsha512msg1(<4 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg1:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg1 %xmm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcc,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+
+define <4 x i64> @test_int_x86_vsha512msg2(<4 x i64> %A, <4 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg2:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg2 %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcd,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x

[PATCH] D155148: [X86] Add SM4 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541373.
FreddyYe marked 3 inline comments as done.
FreddyYe added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155148/new/

https://reviews.llvm.org/D155148

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm4intrin.h
  clang/test/CodeGen/X86/sm4-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm4-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm4-32.txt
  llvm/test/MC/Disassembler/X86/sm4-64.txt
  llvm/test/MC/X86/sm4-32-att.s
  llvm/test/MC/X86/sm4-32-intel.s
  llvm/test/MC/X86/sm4-64-att.s
  llvm/test/MC/X86/sm4-64-intel.s

Index: llvm/test/MC/X86/sm4-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm4-64-intel.s
@@ -0,0 +1,114 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm4key4 ymm12, ymm13, ymm4
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xe4]
+  vsm4key4 ymm12, ymm13, ymm4
+
+// CHECK: vsm4key4 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xe4]
+  vsm4key4 xmm12, xmm13, xmm4
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x16,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x16,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff]
+  vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa1,0xe0,0x0f,0x00,0x00]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa2,0x00,0xf0,0xff,0xff]
+  vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x12,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x12,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymm4
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xe4]
+  vsm4rnds4 ymm12, ymm13, ymm4
+
+// CHECK: vsm4rnds4 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xe4]
+  vsm4rnds4 xmm12, xmm13, xmm4
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x17,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm4rnds4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x17,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm4rnds4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0x25,0x00,0x00,0x00,0x00]
+

[PATCH] D155147: [X86] Add SM3 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541343.
FreddyYe added a comment.

Refine doxygen


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155147/new/

https://reviews.llvm.org/D155147

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s

Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
+  vsm3msg1 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
+  vsm3msg2 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmm4, 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmm4, 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+
+//

[PATCH] D155147: [X86] Add SM3 instructions.

2023-07-18 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 541340.
FreddyYe marked 2 inline comments as done.
FreddyYe added a comment.

Address commments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155147/new/

https://reviews.llvm.org/D155147

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s

Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xe4]
+  vsm3msg1 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x10,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x10,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x10,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg1 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xe4]
+  vsm3msg2 xmm12, xmm13, xmm4
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x11,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x11,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x25,0x00,0x00,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa1,0xf0,0x07,0x00,0x00]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x11,0xda,0xa2,0x00,0xf8,0xff,0xff]
+  vsm3msg2 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmm4, 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0xe4,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmm4, 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0x23,0x11,0xde,0xa4,0xf5,0x00,0x00,0x00,0x10,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0x43,0x11,0xde,0xa4,0x80,0x23,0x01,0x00,0x00,0x7b]
+  vsm3rnds2 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK: vsm3rnds2 xmm12, xmm13, xmmword ptr [rip], 123
+// CHECK: encoding: [0xc4,0x63,0x11,0xde,0x25,0x00,0x00,0x00,0x00,0x7b]
+

[PATCH] D155148: Add SM4 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: clang/test/CodeGen/X86/sm4-builtins.c:5
+#include 
+#include 
+

RKSimon wrote:
> what is stddef.h needed for?
Good catch! probably be copy paste error.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155148/new/

https://reviews.llvm.org/D155148

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[PATCH] D155146: Add SHA512 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 540951.
FreddyYe added a comment.

Remove #include 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512.txt
  llvm/test/MC/X86/sha512-att.s
  llvm/test/MC/X86/sha512-intel.s

Index: llvm/test/MC/X86/sha512-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512.txt
@@ -0,0 +1,17 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:vsha512msg1 %xmm3, %ymm2
+# INTEL:  vsha512msg1 ymm2, xmm3
+0xc4,0xe2,0x7f,0xcc,0xd3
+
+# ATT:vsha512msg2 %ymm3, %ymm2
+# INTEL:  vsha512msg2 ymm2, ymm3
+0xc4,0xe2,0x7f,0xcd,0xd3
+
+# ATT:vsha512rnds2 %xmm4, %ymm3, %ymm2
+# INTEL:  vsha512rnds2 ymm2, ymm3, xmm4
+0xc4,0xe2,0x67,0xcb,0xd4
+
Index: llvm/test/CodeGen/X86/sha512-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/sha512-intrinsics.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s
+
+define <4 x i64> @test_int_x86_vsha512msg1(<4 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg1:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg1 %xmm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcc,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+
+define <4 x i64> @test_int_x86_vsha512msg2(<4 x i64> %A, <4 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg2:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg2 %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcd,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+
+define <4 x i64>

[PATCH] D155148: Add SM4 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 540950.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

Remove #include 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155148/new/

https://reviews.llvm.org/D155148

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm4intrin.h
  clang/test/CodeGen/X86/sm4-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm4-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm4-32.txt
  llvm/test/MC/Disassembler/X86/sm4-64.txt
  llvm/test/MC/X86/sm4-32-att.s
  llvm/test/MC/X86/sm4-32-intel.s
  llvm/test/MC/X86/sm4-64-att.s
  llvm/test/MC/X86/sm4-64-intel.s

Index: llvm/test/MC/X86/sm4-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm4-64-intel.s
@@ -0,0 +1,113 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymm4
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0xd4]
+   vsm4key4 ymm2, ymm3, ymm4
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0xd4]
+   vsm4key4 xmm2, xmm3, xmm4
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x66,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm4key4 ymm2, ymm3, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x66,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm4key4 ymm2, ymm3, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm4key4 ymm2, ymm3, ymmword ptr [rip]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [2*rbp - 1024]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff]
+   vsm4key4 ymm2, ymm3, ymmword ptr [2*rbp - 1024]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [rcx + 4064]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x91,0xe0,0x0f,0x00,0x00]
+   vsm4key4 ymm2, ymm3, ymmword ptr [rcx + 4064]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [rdx - 4096]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x92,0x00,0xf0,0xff,0xff]
+   vsm4key4 ymm2, ymm3, ymmword ptr [rdx - 4096]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x62,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm4key4 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x62,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm4key4 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm4key4 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm4key4 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm4key4 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm4key4 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm4rnds4 ymm2, ymm3, ymm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0xd4]
+   vsm4rnds4 ymm2, ymm3, ymm4
+
+// CHECK:  vsm4rnds4 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0xd4]
+   vsm4rnds4 xmm2, xmm3, xmm4
+
+// CHECK:  vsm4rnds4 ymm2, ymm3, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x67,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm4rnds4 ymm2, ymm3, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm4rnds4 ymm2, ymm3, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x67,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm4rnds4 ymm2, ymm3, ymmword ptr [r8 + 4*rax + 291]
+
+//

[PATCH] D155147: Add SM3 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 540949.
FreddyYe added a comment.

Remove #include 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155147/new/

https://reviews.llvm.org/D155147

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s

Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+   vsm3msg1 xmm2, xmm3, xmm4
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x60,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x60,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+   vsm3msg2 xmm2, xmm3, xmm4
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x61,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x61,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmm4, 123
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0xa3,0x61,0xde,0x94,0xf5,0x00,0x00,0x00,0x10,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0xc3,0x61,0xde,0x94,0x80,0x23,0x01,0x00,0x00,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmmword ptr [rip], 123
+// CHECK:

[PATCH] D155146: Add SHA512 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 540909.
FreddyYe added a comment.

Remove `-check-prefix=CHECK`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512.txt
  llvm/test/MC/X86/sha512-att.s
  llvm/test/MC/X86/sha512-intel.s

Index: llvm/test/MC/X86/sha512-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512.txt
@@ -0,0 +1,17 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:vsha512msg1 %xmm3, %ymm2
+# INTEL:  vsha512msg1 ymm2, xmm3
+0xc4,0xe2,0x7f,0xcc,0xd3
+
+# ATT:vsha512msg2 %ymm3, %ymm2
+# INTEL:  vsha512msg2 ymm2, ymm3
+0xc4,0xe2,0x7f,0xcd,0xd3
+
+# ATT:vsha512rnds2 %xmm4, %ymm3, %ymm2
+# INTEL:  vsha512rnds2 ymm2, ymm3, xmm4
+0xc4,0xe2,0x67,0xcb,0xd4
+
Index: llvm/test/CodeGen/X86/sha512-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/sha512-intrinsics.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s
+
+define <4 x i64> @test_int_x86_vsha512msg1(<4 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg1:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg1 %xmm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcc,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+
+define <4 x i64> @test_int_x86_vsha512msg2(<4 x i64> %A, <4 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg2:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg2 %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcd,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+
+define <4 x i64>

[PATCH] D155148: Add SM4 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 540900.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155148/new/

https://reviews.llvm.org/D155148

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm4intrin.h
  clang/test/CodeGen/X86/sm4-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm4-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm4-32.txt
  llvm/test/MC/Disassembler/X86/sm4-64.txt
  llvm/test/MC/X86/sm4-32-att.s
  llvm/test/MC/X86/sm4-32-intel.s
  llvm/test/MC/X86/sm4-64-att.s
  llvm/test/MC/X86/sm4-64-intel.s

Index: llvm/test/MC/X86/sm4-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm4-64-intel.s
@@ -0,0 +1,113 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymm4
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0xd4]
+   vsm4key4 ymm2, ymm3, ymm4
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0xd4]
+   vsm4key4 xmm2, xmm3, xmm4
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x66,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm4key4 ymm2, ymm3, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x66,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm4key4 ymm2, ymm3, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm4key4 ymm2, ymm3, ymmword ptr [rip]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [2*rbp - 1024]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff]
+   vsm4key4 ymm2, ymm3, ymmword ptr [2*rbp - 1024]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [rcx + 4064]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x91,0xe0,0x0f,0x00,0x00]
+   vsm4key4 ymm2, ymm3, ymmword ptr [rcx + 4064]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [rdx - 4096]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x92,0x00,0xf0,0xff,0xff]
+   vsm4key4 ymm2, ymm3, ymmword ptr [rdx - 4096]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x62,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm4key4 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x62,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm4key4 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm4key4 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm4key4 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm4key4 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm4key4 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm4rnds4 ymm2, ymm3, ymm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0xd4]
+   vsm4rnds4 ymm2, ymm3, ymm4
+
+// CHECK:  vsm4rnds4 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0xd4]
+   vsm4rnds4 xmm2, xmm3, xmm4
+
+// CHECK:  vsm4rnds4 ymm2, ymm3, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x67,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm4rnds4 ymm2, ymm3, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm4rnds4 ymm2, ymm3, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x67,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm4rnds4 ymm2, ymm3, ymmword ptr [r8 + 4*rax + 291]
+
+//

[PATCH] D155148: Add SM4 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked 4 inline comments as done.
FreddyYe added inline comments.



Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8308
+RC:$src2))]>,
+  Sched<[WriteVecIMul]>;
+def rm : I<0xda, MRMSrcMem, (outs RC:$dst),

skan wrote:
> From the description, it seems that `WriteVecIMul` is not the right schedule?
Added FIXME.


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[PATCH] D155147: Add SM3 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8331
+VR128:$src2, (loadv4i32 addr:$src3), timm:$src4))]>,
+  Sched<[WriteVecIMul]>;
+  }

skan wrote:
> Is the schedule appropriate?
I referred to SHA1MSG1's, any good ideas? I'll add a FIXME first here.



Comment at: llvm/test/MC/Disassembler/X86/sm3-64.txt:4
+
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s 
--check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel 
--output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL

pengfei wrote:
> We can merge 64-bit tests into 32-bit ones. The same below.
Due to these instructions support  rm form, hard to merge here?


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[PATCH] D155146: Add SHA512 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 540893.
FreddyYe added a comment.

Added FIXME for schedule


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512.txt
  llvm/test/MC/X86/sha512-att.s
  llvm/test/MC/X86/sha512-intel.s

Index: llvm/test/MC/X86/sha512-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512.txt
@@ -0,0 +1,17 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:vsha512msg1 %xmm3, %ymm2
+# INTEL:  vsha512msg1 ymm2, xmm3
+0xc4,0xe2,0x7f,0xcc,0xd3
+
+# ATT:vsha512msg2 %ymm3, %ymm2
+# INTEL:  vsha512msg2 ymm2, ymm3
+0xc4,0xe2,0x7f,0xcd,0xd3
+
+# ATT:vsha512rnds2 %xmm4, %ymm3, %ymm2
+# INTEL:  vsha512rnds2 ymm2, ymm3, xmm4
+0xc4,0xe2,0x67,0xcb,0xd4
+
Index: llvm/test/CodeGen/X86/sha512-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/sha512-intrinsics.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s -check-prefixes=CHECK
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s -check-prefixes=CHECK
+
+define <4 x i64> @test_int_x86_vsha512msg1(<4 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg1:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg1 %xmm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcc,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+
+define <4 x i64> @test_int_x86_vsha512msg2(<4 x i64> %A, <4 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg2:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg2 %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcd,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg2(<4 x i64>

[PATCH] D155147: Add SM3 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 540892.
FreddyYe marked 5 inline comments as done.
FreddyYe added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155147/new/

https://reviews.llvm.org/D155147

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s

Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+   vsm3msg1 xmm2, xmm3, xmm4
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x60,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x60,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+   vsm3msg2 xmm2, xmm3, xmm4
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x61,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x61,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmm4, 123
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0xa3,0x61,0xde,0x94,0xf5,0x00,0x00,0x00,0x10,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291], 123
+// CHECK: encoding: [0xc4,0xc3,0x61,0xde,0x94,0x80,0x23,0x01,0x00,0x00,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291], 123
+
+// CHECK:  vsm3rnds2

[PATCH] D155146: Add SHA512 instructions.

2023-07-17 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 540885.
FreddyYe marked 15 inline comments as done.
FreddyYe added a comment.

Address comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155146/new/

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512.txt
  llvm/test/MC/X86/sha512-att.s
  llvm/test/MC/X86/sha512-intel.s

Index: llvm/test/MC/X86/sha512-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-att.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512.txt
@@ -0,0 +1,17 @@
+# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:vsha512msg1 %xmm3, %ymm2
+# INTEL:  vsha512msg1 ymm2, xmm3
+0xc4,0xe2,0x7f,0xcc,0xd3
+
+# ATT:vsha512msg2 %ymm3, %ymm2
+# INTEL:  vsha512msg2 ymm2, ymm3
+0xc4,0xe2,0x7f,0xcd,0xd3
+
+# ATT:vsha512rnds2 %xmm4, %ymm3, %ymm2
+# INTEL:  vsha512rnds2 ymm2, ymm3, xmm4
+0xc4,0xe2,0x67,0xcb,0xd4
+
Index: llvm/test/CodeGen/X86/sha512-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/sha512-intrinsics.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s -check-prefixes=CHECK
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sha512 | FileCheck %s -check-prefixes=CHECK
+
+define <4 x i64> @test_int_x86_vsha512msg1(<4 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg1:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg1 %xmm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcc,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %A, <2 x i64> %B)
+
+define <4 x i64> @test_int_x86_vsha512msg2(<4 x i64> %A, <4 x i64> %B) {
+; CHECK-LABEL: test_int_x86_vsha512msg2:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:vsha512msg2 %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xcd,0xc1]
+; CHECK-NEXT:ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %A, <4 x i64> %B)
+  ret <4 x i64> %ret
+}
+declare <4 x

[PATCH] D155145: Add AVX-VNNI-INT16 instructions.

2023-07-13 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: llvm/test/CodeGen/X86/avxvnniint16-intrinsics.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown 
--show-mc-encoding -mattr=+avx2,+avxvnniint16 | FileCheck %s 
--check-prefixes=X64
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown 
--show-mc-encoding -mattr=+avx2,+avxvnniint16 | FileCheck %s 
--check-prefixes=X86

pengfei wrote:
> `X64,CHECK`
This couldn't help merging the CHECKs here. Do we need it?



Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155145/new/

https://reviews.llvm.org/D155145

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[PATCH] D155148: Add SM4 instructions.

2023-07-12 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe created this revision.
Herald added subscribers: pengfei, hiraditya.
Herald added a project: All.
FreddyYe requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

For more details about these instructions, please refer to the latest ISE 
document: 
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155148

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm4intrin.h
  clang/test/CodeGen/X86/sm4-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm4-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm4-32.txt
  llvm/test/MC/Disassembler/X86/sm4-64.txt
  llvm/test/MC/X86/sm4-32-att.s
  llvm/test/MC/X86/sm4-32-intel.s
  llvm/test/MC/X86/sm4-64-att.s
  llvm/test/MC/X86/sm4-64-intel.s

Index: llvm/test/MC/X86/sm4-64-intel.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm4-64-intel.s
@@ -0,0 +1,113 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymm4
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0xd4]
+   vsm4key4 ymm2, ymm3, ymm4
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0xd4]
+   vsm4key4 xmm2, xmm3, xmm4
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x66,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm4key4 ymm2, ymm3, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x66,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm4key4 ymm2, ymm3, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm4key4 ymm2, ymm3, ymmword ptr [rip]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [2*rbp - 1024]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff]
+   vsm4key4 ymm2, ymm3, ymmword ptr [2*rbp - 1024]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [rcx + 4064]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x91,0xe0,0x0f,0x00,0x00]
+   vsm4key4 ymm2, ymm3, ymmword ptr [rcx + 4064]
+
+// CHECK:  vsm4key4 ymm2, ymm3, ymmword ptr [rdx - 4096]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x92,0x00,0xf0,0xff,0xff]
+   vsm4key4 ymm2, ymm3, ymmword ptr [rdx - 4096]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x62,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm4key4 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x62,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm4key4 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm4key4 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm4key4 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm4key4 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm4key4 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm4key4 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm4rnds4 ymm2, ymm3, ymm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0xd4]
+   vsm4rnds4 ymm2, ymm3, ymm4
+
+// CHECK:  vsm4rnds4 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0xd4]
+   vsm4rnds4 xmm2, xmm3, xmm4
+
+// CHECK:  vsm4rnds4 ymm2, ymm3, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x67,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm4rnds4 ymm2, ymm3,

[PATCH] D155147: Add SM3 instructions.

2023-07-12 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe created this revision.
Herald added subscribers: pengfei, hiraditya.
Herald added a project: All.
FreddyYe requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

For more details about these instructions, please refer to the latest ISE 
document: 
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155147

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sm3intrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/X86/sm3-builtins.c
  clang/test/CodeGen/X86/sm3-error.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sm3-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sm3-32.txt
  llvm/test/MC/Disassembler/X86/sm3-64.txt
  llvm/test/MC/X86/sm3-att-32.s
  llvm/test/MC/X86/sm3-att-64.s
  llvm/test/MC/X86/sm3-intel-32.s
  llvm/test/MC/X86/sm3-intel-64.s

Index: llvm/test/MC/X86/sm3-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sm3-intel-64.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0xd4]
+   vsm3msg1 xmm2, xmm3, xmm4
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x60,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x60,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x60,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm3msg1 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0xd4]
+   vsm3msg2 xmm2, xmm3, xmm4
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0xa2,0x61,0xda,0x94,0xf5,0x00,0x00,0x00,0x10]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0xc2,0x61,0xda,0x94,0x80,0x23,0x01,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x15,0x00,0x00,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rip]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [2*rbp - 512]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x91,0xf0,0x07,0x00,0x00]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rcx + 2032]
+
+// CHECK:  vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x61,0xda,0x92,0x00,0xf8,0xff,0xff]
+   vsm3msg2 xmm2, xmm3, xmmword ptr [rdx - 2048]
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmm4, 123
+// CHECK: encoding: [0xc4,0xe3,0x61,0xde,0xd4,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmm4, 123
+
+// CHECK:  vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+// CHECK: encoding: [0xc4,0xa3,0x61,0xde,0x94,0xf5,0x00,0x00,0x00,0x10,0x7b]
+   vsm3rnds2 xmm2, xmm3, xmmword ptr [rbp + 8*r14 + 268435456], 123
+
+//

[PATCH] D155146: Add SHA512 instructions.

2023-07-12 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe created this revision.
Herald added subscribers: pengfei, hiraditya.
Herald added a project: All.
FreddyYe requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

For more details about this instruction, please refer to the latest ISE 
document: 
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155146

Files:
  clang/docs/ReleaseNotes.rst
  clang/include/clang/Basic/BuiltinsX86.def
  clang/include/clang/Driver/Options.td
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/immintrin.h
  clang/lib/Headers/sha512intrin.h
  clang/test/CodeGen/X86/sha512-builtins.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/Driver/x86-target-features.c
  clang/test/Preprocessor/x86_target_features.c
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/TargetParser/Host.cpp
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/sha512-intrinsics.ll
  llvm/test/MC/Disassembler/X86/sha512-32.txt
  llvm/test/MC/Disassembler/X86/sha512-64.txt
  llvm/test/MC/X86/sha512-att-32.s
  llvm/test/MC/X86/sha512-att-64.s
  llvm/test/MC/X86/sha512-intel-32.s
  llvm/test/MC/X86/sha512-intel-64.s

Index: llvm/test/MC/X86/sha512-intel-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel-64.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-intel-32.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-intel-32.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 ymm2, xmm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 ymm2, xmm3
+
+// CHECK:  vsha512msg2 ymm2, ymm3
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 ymm2, ymm3
+
+// CHECK:  vsha512rnds2 ymm2, ymm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 ymm2, ymm3, xmm4
Index: llvm/test/MC/X86/sha512-att-64.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att-64.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/X86/sha512-att-32.s
===
--- /dev/null
+++ llvm/test/MC/X86/sha512-att-32.s
@@ -0,0 +1,13 @@
+// RUN: llvm-mc -triple i686 --show-encoding %s | FileCheck %s
+
+// CHECK:  vsha512msg1 %xmm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcc,0xd3]
+   vsha512msg1 %xmm3, %ymm2
+
+// CHECK:  vsha512msg2 %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x7f,0xcd,0xd3]
+   vsha512msg2 %ymm3, %ymm2
+
+// CHECK:  vsha512rnds2 %xmm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xcb,0xd4]
+   vsha512rnds2 %xmm4, %ymm3, %ymm2
Index: llvm/test/MC/Disassembler/X86/sha512-64.txt
===
--- /dev/null
+++ llvm/test/MC/Disassembler/X86/sha512-64.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:vsha512msg1 %xmm3, %ymm2
+# INTEL:  vsha512msg1 ymm2, xmm3
+0xc4,0xe2,0x7f,0xcc,0xd3
+
+# ATT:vsha512msg2 %ymm3, %ymm2
+# INTEL:  vsha512msg2 ymm2, ymm3
+0xc4,0xe2,0x7f,0xcd,0xd3
+
+# ATT:vsha512rnds2 %xmm4, %ymm3, %ymm2
+# INTEL:  vsha512rnds2 ymm2, ymm3, xmm4

[PATCH] D154493: [X86] Support some Intel CPUs for cpu_specific/dispatch feature

2023-07-06 Thread Freddy, Ye via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa10dccf2712f: [X86] Support some Intel CPUs for 
cpu_specific/dispatch feature (authored by FreddyYe).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154493/new/

https://reviews.llvm.org/D154493

Files:
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  llvm/lib/TargetParser/X86TargetParser.cpp

Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -333,48 +333,48 @@
   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
   { {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true },
   // i686-generation processors, P6 / Pentium M microarchitecture based.
-  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
+  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', false },
   { {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true },
   { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
-  { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, '\0', false },
+  { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', false },
   { {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true },
-  { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, '\0', false },
-  { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, '\0', false },
+  { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
+  { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
   { {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
   { {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
   { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false },
   { {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true },
   { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false },
-  { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, '\0', false },
+  { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, 'L', false },
   // Netburst microarchitecture based processors.
-  { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, '\0', false },
-  { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, '\0', false },
+  { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
+  { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
   { {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true },
   { {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true },
-  { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, '\0', false },
-  { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, '\0', false },
+  { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', false },
+  { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, 'L', false },
   // Core microarchitecture based processors.
-  { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, '\0', false },
+  { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, 'M', false },
   { {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true },
-  { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, '\0', false },
+  { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', false },
   { {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true },
   // Atom processors
-  { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, '\0', false },
+  { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
   { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
-  { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, '\0', false },
-  { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, '\0', false },
+  { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
+  { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
   { {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true },
   { {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true },
   { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false },
   { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false },
-  { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', true },
-  { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, '\0', false },
+  { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, 'd', true },
+  { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, 'd', false },
   // Nehalem microarchitecture based processors.
-  { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, '\0', false },
+  { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
   { {"core_i7_sse4_2"},

[PATCH] D154493: [X86] Support some Intel CPUs for cpu_specific/dispatch feature

2023-07-06 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 537980.
FreddyYe added a comment.

Tune test as well.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154493/new/

https://reviews.llvm.org/D154493

Files:
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  llvm/lib/TargetParser/X86TargetParser.cpp

Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -333,48 +333,48 @@
   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
   { {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true },
   // i686-generation processors, P6 / Pentium M microarchitecture based.
-  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
+  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', false },
   { {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true },
   { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
-  { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, '\0', false },
+  { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', false },
   { {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true },
-  { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, '\0', false },
-  { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, '\0', false },
+  { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
+  { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
   { {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
   { {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
   { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false },
   { {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true },
   { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false },
-  { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, '\0', false },
+  { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, 'L', false },
   // Netburst microarchitecture based processors.
-  { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, '\0', false },
-  { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, '\0', false },
+  { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
+  { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
   { {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true },
   { {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true },
-  { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, '\0', false },
-  { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, '\0', false },
+  { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', false },
+  { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, 'L', false },
   // Core microarchitecture based processors.
-  { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, '\0', false },
+  { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, 'M', false },
   { {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true },
-  { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, '\0', false },
+  { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', false },
   { {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true },
   // Atom processors
-  { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, '\0', false },
+  { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
   { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
-  { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, '\0', false },
-  { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, '\0', false },
+  { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
+  { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
   { {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true },
   { {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true },
   { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false },
   { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false },
-  { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', true },
-  { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, '\0', false },
+  { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, 'd', true },
+  { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, 'd', false },
   // Nehalem microarchitecture based processors.
-  { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, '\0', false },
+  { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
   { {"core_i7_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', true },
-  { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, '\0', false },
+  { {"corei7"},

[PATCH] D154493: [X86] Support some Intel CPUs for cpu_specific/dispatch feature

2023-07-06 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: llvm/lib/TargetParser/X86TargetParser.cpp:419
   // Sapphire Rapids microarchitecture based processors.
-  { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, 
FeaturesSapphireRapids, '\0', false },
+  { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, 
FeaturesSapphireRapids, 'n', false },
   // Alderlake microarchitecture based processors.

SPR has AVX512BF16 comparing to icelake-server, which is a X86_FEATURE_COMPAT 
feature.


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[PATCH] D154493: [X86] Support some Intel CPUs for cpu_specific/dispatch feature

2023-07-06 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 537957.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

Tuned some manglings. SPR should create a new mangling for its feature list.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154493/new/

https://reviews.llvm.org/D154493

Files:
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  llvm/lib/TargetParser/X86TargetParser.cpp

Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -333,48 +333,48 @@
   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
   { {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true },
   // i686-generation processors, P6 / Pentium M microarchitecture based.
-  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
+  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', false },
   { {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true },
   { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
-  { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, '\0', false },
+  { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', false },
   { {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true },
-  { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, '\0', false },
-  { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, '\0', false },
+  { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
+  { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
   { {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
   { {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
   { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false },
   { {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true },
   { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false },
-  { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, '\0', false },
+  { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, 'L', false },
   // Netburst microarchitecture based processors.
-  { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, '\0', false },
-  { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, '\0', false },
+  { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
+  { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
   { {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true },
   { {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true },
-  { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, '\0', false },
-  { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, '\0', false },
+  { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', false },
+  { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, 'L', false },
   // Core microarchitecture based processors.
-  { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, '\0', false },
+  { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, 'M', false },
   { {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true },
-  { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, '\0', false },
+  { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', false },
   { {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true },
   // Atom processors
-  { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, '\0', false },
+  { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
   { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
-  { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, '\0', false },
-  { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, '\0', false },
+  { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
+  { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
   { {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true },
   { {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true },
   { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false },
   { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false },
-  { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', true },
-  { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, '\0', false },
+  { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, 'd', true },
+  { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, 'd', false },
   // Nehalem microarchitecture based processors.
-  { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, '\0', false },
+  { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
   { {"core_i7_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', true

[PATCH] D154493: [X86] Support some Intel CPUs for cpu_specific/dispatch feature

2023-07-05 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked an inline comment as done.
FreddyYe added inline comments.



Comment at: llvm/lib/TargetParser/X86TargetParser.cpp:333
   { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B, 'B', false },
   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
   { {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true },

RKSimon wrote:
> add this as well?
cpu names contain '-' are not supported for cpu_specific/dispatch feature since 
'-' is not an identifier character. The solution here is creating a new name 
with '_' replacing and set the OnlyForCPUDispatchSpecific as `true`, like 
`icelake-client`, `icelake-server` and `goldmont-plus`


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[PATCH] D154493: [X86] Support some Intel CPUs for cpu_specific/dispatch feature

2023-07-05 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe created this revision.
Herald added a subscriber: hiraditya.
Herald added a project: All.
FreddyYe requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154493

Files:
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  llvm/lib/TargetParser/X86TargetParser.cpp

Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -333,48 +333,48 @@
   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
   { {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true },
   // i686-generation processors, P6 / Pentium M microarchitecture based.
-  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
+  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', false },
   { {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true },
   { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
-  { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, '\0', false },
+  { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', false },
   { {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true },
-  { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, '\0', false },
-  { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, '\0', false },
+  { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
+  { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
   { {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
   { {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
   { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false },
   { {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true },
   { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false },
-  { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, '\0', false },
+  { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, 'L', false },
   // Netburst microarchitecture based processors.
-  { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, '\0', false },
-  { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, '\0', false },
+  { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
+  { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
   { {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true },
   { {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true },
-  { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, '\0', false },
-  { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, '\0', false },
+  { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', false },
+  { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, 'L', false },
   // Core microarchitecture based processors.
-  { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, '\0', false },
+  { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, 'M', false },
   { {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true },
-  { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, '\0', false },
+  { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', false },
   { {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true },
   // Atom processors
-  { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, '\0', false },
+  { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
   { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
-  { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, '\0', false },
-  { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, '\0', false },
+  { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
+  { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
   { {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true },
   { {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true },
   { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false },
   { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false },
-  { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', true },
-  { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, '\0', false },
+  { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, 'd', true },
+  { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, 'd', false },
   // Nehalem microarchitecture based processors.
-  { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, '\0', false },
+  { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
   { {"core_i7_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', true },
-  { {"corei7"}, CK_Nehalem,

[PATCH] D151696: [X86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-07-05 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added a comment.

Thank so much on all your comments/review to make this happen. Cheers~!


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[PATCH] D151696: [X86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-07-05 Thread Freddy, Ye via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG7717c0071d7c: [X86] Remove CPU_SPECIFIC* MACROs and add 
getCPUDispatchMangling (authored by FreddyYe).

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/test/CodeGen/attr-cpuspecific-avx-abi.c
  clang/test/CodeGen/attr-cpuspecific.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -6,16 +6,24 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i586 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-mmx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_mmx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i686 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentiumpro 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_pro 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_ii 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_iii 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_iii_no_xmm_regs 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_4_sse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=raptorlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=meteorlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -26,26 +34,39 @@
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core_2_duo_ssse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o

[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-07-04 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 537065.
FreddyYe marked 2 inline comments as done.
FreddyYe added a comment.

Add comments about Mangling and OnlyForCPUDispatchSpecific,
and remove the supporting more/new CPU names for cpu_specific/dispatch feature.


Repository:
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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/test/CodeGen/attr-cpuspecific-avx-abi.c
  clang/test/CodeGen/attr-cpuspecific.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -6,16 +6,24 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i586 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-mmx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_mmx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i686 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentiumpro 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_pro 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_ii 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_iii 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_iii_no_xmm_regs 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_4_sse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=raptorlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=meteorlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -26,26 +34,39 @@
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core_2_duo_ssse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s

[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-07-03 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked an inline comment as done.
FreddyYe added inline comments.



Comment at: clang/test/CodeGen/attr-cpuspecific-cpus.c:40
 ATTR(cpu_specific(knm)) void CPU(void){}
+ATTR(cpu_specific(cascadelake)) void CPU(void){}
+ATTR(cpu_specific(cooperlake)) void CPU(void){}

In this patch, I additionally supported some intel new CPU's _cpu_specific 
feature by creating a new mangling or copy some old ones (which means aliasing 
certain cpu). Maybe I should do this in a following patch?



Comment at: llvm/lib/TargetParser/X86TargetParser.cpp:378
+  { {"core_3rd_gen_avx"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', 
true },
+  { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, '\0', false 
},
   // Haswell microarchitecture based processors.

RKSimon wrote:
> I'm still not clear on what determines the mangling mode and cpu dispatch 
> flag for cpu targets are supposedly the same? For example, none of these 
> ivybridge equivalent configs have the same values.
I assign them by following orders:
1. Copy the mangling from the original CPU_SPEICIFC MACRO.
2. If there's no way to copy, assign to '\0' by default, which means doesn't 
support __cpu_specific/dispatch feature.
3. If cpu name contain ''-', assign the mangling as '\0', too. Because '-' 
cannot be correctly identified in _cpu_specific/dispatch().
4. set OnlyForCPUDispatch flag as `true` if this cpu name was not listed here, 
which means it doesn't support -march, -mtune and so on. This flag makes this 
cpu name only support __cpu_dispatch/specific feature. E.g. core_3rd_gen_avx, 
core_4rd_gen_avx., ... And normally, these names are very old. So supporting 
them with -march=, -mtune= is not easy for now. And notice that new cpu names 
shouldn't set this flag as `true` since they should both support -march= and 
__cpu_specific/dispatch feature by default.



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[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-07-03 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added a comment.

gentle ping. If no objections, I'll merge this tomorrow.


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[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-07-02 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 536645.
FreddyYe marked an inline comment as done.
FreddyYe added a comment.

Rebase, especially for D151696 


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/test/CodeGen/attr-cpuspecific-avx-abi.c
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-cpuspecific.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -6,16 +6,24 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i586 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-mmx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_mmx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i686 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentiumpro 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_pro 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_ii 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_iii 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_iii_no_xmm_regs 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_4_sse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=raptorlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=meteorlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -26,26 +34,39 @@
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core_2_duo_ssse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null

[PATCH] D154209: [X86] Add missing features for ivybridge, sandybridge and knl in X86TargetParser.def.

2023-07-02 Thread Freddy, Ye via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb026c9eb1051: [X86] Add missing features for ivybridge, 
sandybridge and knl in… (authored by FreddyYe).

Repository:
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Files:
  clang/test/CodeGen/attr-cpuspecific.c
  llvm/include/llvm/TargetParser/X86TargetParser.def


Index: llvm/include/llvm/TargetParser/X86TargetParser.def
===
--- llvm/include/llvm/TargetParser/X86TargetParser.def
+++ llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -262,9 +262,9 @@
 CPU_SPECIFIC("core_aes_pclmulqdq", "westmere", 'Q', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt")
 CPU_SPECIFIC("atom_sse4_2_movbe", "silvermont", 'd', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt")
 CPU_SPECIFIC("goldmont", "goldmont", 'i', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt")
-CPU_SPECIFIC("sandybridge", "sandybridge", 'R', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+avx")
+CPU_SPECIFIC("sandybridge", "sandybridge", 'R', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+avx,+pclmul")
 CPU_SPECIFIC_ALIAS("core_2nd_gen_avx", "sandybridge", "sandybridge")
-CPU_SPECIFIC("ivybridge", "ivybridge", 'S', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+f16c,+avx")
+CPU_SPECIFIC("ivybridge", "ivybridge", 'S', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+f16c,+avx,+pclmul")
 CPU_SPECIFIC_ALIAS("core_3rd_gen_avx", "ivybridge", "ivybridge")
 CPU_SPECIFIC("haswell", "haswell", 'V', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2")
 CPU_SPECIFIC_ALIAS("core_4th_gen_avx", "haswell", "haswell")
@@ -272,7 +272,7 @@
 CPU_SPECIFIC("broadwell", "broadwell", 'X', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx")
 CPU_SPECIFIC_ALIAS("core_5th_gen_avx", "broadwell", "broadwell")
 CPU_SPECIFIC("core_5th_gen_avx_tsx", "broadwell", 'Y', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx")
-CPU_SPECIFIC("knl", "knl", 'Z', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512f,+adx,+avx512er,+avx512pf,+avx512cd")
+CPU_SPECIFIC("knl", "knl", 'Z', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512f,+adx,+avx512er,+avx512pf,+avx512cd,+pclmul,+bmi2,+aes")
 CPU_SPECIFIC_ALIAS("mic_avx512", "knl", "knl")
 CPU_SPECIFIC("skylake", "skylake", 'b', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx,+mpx")
 CPU_SPECIFIC( "skylake_avx512", "skylake-avx512", 'a', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512dq,+avx512f,+adx,+avx512cd,+avx512bw,+avx512vl,+clwb")
Index: clang/test/CodeGen/attr-cpuspecific.c
===
--- clang/test/CodeGen/attr-cpuspecific.c
+++ clang/test/CodeGen/attr-cpuspecific.c
@@ -44,8 +44,8 @@
 // LINUX: define weak_odr ptr @SingleVersion.resolver()
 // LINUX: call void @__cpu_indicator_init
 // LINUX: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 1023
-// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 1023
+// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 525311
+// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 525311
 // LINUX: ret ptr @SingleVersion.S
 // LINUX: call void @llvm.trap
 // LINUX: unreachable
@@ -53,8 +53,8 @@
 // WINDOWS: define weak_odr dso_local void @SingleVersion() comdat
 // WINDOWS: call void @__cpu_indicator_init()
 // WINDOWS: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// WINDOWS: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 1023
-// WINDOWS: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 1023
+// WINDOWS: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 525311
+// WINDOWS: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 525311
 // WINDOWS: call void @SingleVersion.S()
 // WINDOWS-NEXT: ret void
 // WINDOWS: call void @llvm.trap
@@ -74,8 +74,8 @@
 // LINUX: define weak_odr ptr @TwoVersions.resolver()
 // LINUX: call void @__cpu_indicator_init
 // LINUX: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 58836991
-// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 58836991

[PATCH] D154209: [X86] Add missing features for ivybridge, sandybridge and knl in X86TargetParser.def.

2023-07-01 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added a comment.

In D154209#4466304 , @RKSimon wrote:

> LGTM - but it would be good to fix silvermont / westmere cases as well with 
> suitable test coverage

Thanks review! After D151696  landed, they 
can be both fixed and there will be more tests cover such missing like 
clang/test/Preprocessor/predefined-arch-macros.c. And about cpu_specific test 
coverage, I'll consider a way to refine.

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[PATCH] D154209: [X86] Add missing features for ivybridge, sandybridge and knl in X86TargetParser.def.

2023-06-30 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 536495.
FreddyYe marked 2 inline comments as done.
FreddyYe added a comment.

Address comment, thanks review!


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Files:
  clang/test/CodeGen/attr-cpuspecific.c
  llvm/include/llvm/TargetParser/X86TargetParser.def


Index: llvm/include/llvm/TargetParser/X86TargetParser.def
===
--- llvm/include/llvm/TargetParser/X86TargetParser.def
+++ llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -262,9 +262,9 @@
 CPU_SPECIFIC("core_aes_pclmulqdq", "westmere", 'Q', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt")
 CPU_SPECIFIC("atom_sse4_2_movbe", "silvermont", 'd', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt")
 CPU_SPECIFIC("goldmont", "goldmont", 'i', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt")
-CPU_SPECIFIC("sandybridge", "sandybridge", 'R', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+avx")
+CPU_SPECIFIC("sandybridge", "sandybridge", 'R', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+avx,+pclmul")
 CPU_SPECIFIC_ALIAS("core_2nd_gen_avx", "sandybridge", "sandybridge")
-CPU_SPECIFIC("ivybridge", "ivybridge", 'S', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+f16c,+avx")
+CPU_SPECIFIC("ivybridge", "ivybridge", 'S', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+f16c,+avx,+pclmul")
 CPU_SPECIFIC_ALIAS("core_3rd_gen_avx", "ivybridge", "ivybridge")
 CPU_SPECIFIC("haswell", "haswell", 'V', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2")
 CPU_SPECIFIC_ALIAS("core_4th_gen_avx", "haswell", "haswell")
@@ -272,7 +272,7 @@
 CPU_SPECIFIC("broadwell", "broadwell", 'X', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx")
 CPU_SPECIFIC_ALIAS("core_5th_gen_avx", "broadwell", "broadwell")
 CPU_SPECIFIC("core_5th_gen_avx_tsx", "broadwell", 'Y', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx")
-CPU_SPECIFIC("knl", "knl", 'Z', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512f,+adx,+avx512er,+avx512pf,+avx512cd")
+CPU_SPECIFIC("knl", "knl", 'Z', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512f,+adx,+avx512er,+avx512pf,+avx512cd,+pclmul,+bmi2,+aes")
 CPU_SPECIFIC_ALIAS("mic_avx512", "knl", "knl")
 CPU_SPECIFIC("skylake", "skylake", 'b', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx,+mpx")
 CPU_SPECIFIC( "skylake_avx512", "skylake-avx512", 'a', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512dq,+avx512f,+adx,+avx512cd,+avx512bw,+avx512vl,+clwb")
Index: clang/test/CodeGen/attr-cpuspecific.c
===
--- clang/test/CodeGen/attr-cpuspecific.c
+++ clang/test/CodeGen/attr-cpuspecific.c
@@ -44,8 +44,8 @@
 // LINUX: define weak_odr ptr @SingleVersion.resolver()
 // LINUX: call void @__cpu_indicator_init
 // LINUX: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 1023
-// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 1023
+// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 525311
+// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 525311
 // LINUX: ret ptr @SingleVersion.S
 // LINUX: call void @llvm.trap
 // LINUX: unreachable
@@ -53,8 +53,8 @@
 // WINDOWS: define weak_odr dso_local void @SingleVersion() comdat
 // WINDOWS: call void @__cpu_indicator_init()
 // WINDOWS: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// WINDOWS: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 1023
-// WINDOWS: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 1023
+// WINDOWS: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 525311
+// WINDOWS: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 525311
 // WINDOWS: call void @SingleVersion.S()
 // WINDOWS-NEXT: ret void
 // WINDOWS: call void @llvm.trap
@@ -74,8 +74,8 @@
 // LINUX: define weak_odr ptr @TwoVersions.resolver()
 // LINUX: call void @__cpu_indicator_init
 // LINUX: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 58836991
-// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 58836991
+// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 59754495
+// LINUX: %[[FEAT_CHECK:.+]] = icmp eq

[PATCH] D154209: [X86] Add missing features for ivybridge, sandybridge and knl in X86TargetParser.def.

2023-06-30 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked an inline comment as done.
FreddyYe added inline comments.



Comment at: llvm/include/llvm/TargetParser/X86TargetParser.def:262
 CPU_SPECIFIC("core_i7_sse4_2", "nehalem", 'P', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt")
 CPU_SPECIFIC("core_aes_pclmulqdq", "westmere", 'Q', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt")
 CPU_SPECIFIC("atom_sse4_2_movbe", "silvermont", 'd', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt")

RKSimon wrote:
> In X86.td westmere and silvermont also have FeaturePCLMUL
Yeah, that's what I wanted to mean. The miss for these two are also true, but 
no tests influenced yet.


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[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-06-30 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked an inline comment as done.
FreddyYe added inline comments.



Comment at: clang/test/CodeGen/attr-cpuspecific.c:47
 // LINUX: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 1023
-// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 1023
+// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 525311
+// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 525311

RKSimon wrote:
> FreddyYe wrote:
> > RKSimon wrote:
> > > FreddyYe wrote:
> > > > This value change is because the feature list of ivybridge described in 
> > > > X86TargetParser.def before missed feature "pclmul".
> > > Pull out an ivybridge fix into its own patch?
> > Emmm. Seems like a good idea. How about I change these two CPU's old 
> > feature list only? Since the successors of them will also have this issue, 
> > but no tests influenced.
> Sure, a single patch with multiple cpus' fixups is fine
Done in https://reviews.llvm.org/D154209


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[PATCH] D154209: [X86] Add missing features for ivybridge, sandybridge and knl in X86TargetParser.def.

2023-06-30 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe created this revision.
Herald added a project: All.
FreddyYe requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This is also a pre-commit change for D151696 


Repository:
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https://reviews.llvm.org/D154209

Files:
  clang/test/CodeGen/attr-cpuspecific.c
  llvm/include/llvm/TargetParser/X86TargetParser.def


Index: llvm/include/llvm/TargetParser/X86TargetParser.def
===
--- llvm/include/llvm/TargetParser/X86TargetParser.def
+++ llvm/include/llvm/TargetParser/X86TargetParser.def
@@ -262,9 +262,9 @@
 CPU_SPECIFIC("core_aes_pclmulqdq", "westmere", 'Q', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt")
 CPU_SPECIFIC("atom_sse4_2_movbe", "silvermont", 'd', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt")
 CPU_SPECIFIC("goldmont", "goldmont", 'i', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt")
-CPU_SPECIFIC("sandybridge", "sandybridge", 'R', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+avx")
+CPU_SPECIFIC("sandybridge", "sandybridge", 'R', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+avx,+pclmul")
 CPU_SPECIFIC_ALIAS("core_2nd_gen_avx", "sandybridge", "sandybridge")
-CPU_SPECIFIC("ivybridge", "ivybridge", 'S', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+f16c,+avx")
+CPU_SPECIFIC("ivybridge", "ivybridge", 'S', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+f16c,+avx,+pclmul")
 CPU_SPECIFIC_ALIAS("core_3rd_gen_avx", "ivybridge", "ivybridge")
 CPU_SPECIFIC("haswell", "haswell", 'V', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2")
 CPU_SPECIFIC_ALIAS("core_4th_gen_avx", "haswell", "haswell")
@@ -272,7 +272,7 @@
 CPU_SPECIFIC("broadwell", "broadwell", 'X', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx")
 CPU_SPECIFIC_ALIAS("core_5th_gen_avx", "broadwell", "broadwell")
 CPU_SPECIFIC("core_5th_gen_avx_tsx", "broadwell", 'Y', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx")
-CPU_SPECIFIC("knl", "knl", 'Z', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512f,+adx,+avx512er,+avx512pf,+avx512cd")
+CPU_SPECIFIC("knl", "knl", 'Z', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512f,+adx,+avx512er,+avx512pf,+avx512cd,,+pclmul,+bmi2,+aes")
 CPU_SPECIFIC_ALIAS("mic_avx512", "knl", "knl")
 CPU_SPECIFIC("skylake", "skylake", 'b', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx,+mpx")
 CPU_SPECIFIC( "skylake_avx512", "skylake-avx512", 'a', 
"+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512dq,+avx512f,+adx,+avx512cd,+avx512bw,+avx512vl,+clwb")
Index: clang/test/CodeGen/attr-cpuspecific.c
===
--- clang/test/CodeGen/attr-cpuspecific.c
+++ clang/test/CodeGen/attr-cpuspecific.c
@@ -44,8 +44,8 @@
 // LINUX: define weak_odr ptr @SingleVersion.resolver()
 // LINUX: call void @__cpu_indicator_init
 // LINUX: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 1023
-// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 1023
+// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 525311
+// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 525311
 // LINUX: ret ptr @SingleVersion.S
 // LINUX: call void @llvm.trap
 // LINUX: unreachable
@@ -53,8 +53,8 @@
 // WINDOWS: define weak_odr dso_local void @SingleVersion() comdat
 // WINDOWS: call void @__cpu_indicator_init()
 // WINDOWS: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// WINDOWS: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 1023
-// WINDOWS: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 1023
+// WINDOWS: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 525311
+// WINDOWS: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 525311
 // WINDOWS: call void @SingleVersion.S()
 // WINDOWS-NEXT: ret void
 // WINDOWS: call void @llvm.trap
@@ -74,8 +74,8 @@
 // LINUX: define weak_odr ptr @TwoVersions.resolver()
 // LINUX: call void @__cpu_indicator_init
 // LINUX: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 58836991
-// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 58836991
+// LINUX: %[[FEAT_JOIN:.+]] = and i32

[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-06-30 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added inline comments.



Comment at: clang/test/CodeGen/attr-cpuspecific.c:47
 // LINUX: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 1023
-// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 1023
+// LINUX: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 525311
+// LINUX: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 525311

RKSimon wrote:
> FreddyYe wrote:
> > This value change is because the feature list of ivybridge described in 
> > X86TargetParser.def before missed feature "pclmul".
> Pull out an ivybridge fix into its own patch?
Emmm. Seems like a good idea. How about I change these two CPU's old feature 
list only? Since the successors of them will also have this issue, but no tests 
influenced.


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[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-06-29 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 536118.
FreddyYe added a comment.

changes according to the new RULE3, pls review again.


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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/test/CodeGen/attr-cpuspecific-avx-abi.c
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-cpuspecific.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -6,16 +6,24 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i586 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-mmx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_mmx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i686 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentiumpro 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_pro 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_ii 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_iii 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_iii_no_xmm_regs 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_4_sse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=raptorlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=meteorlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -26,26 +34,39 @@
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core_2_duo_ssse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core_2_duo_sse4_1 2>&1 | FileCheck

[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-06-29 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe updated this revision to Diff 536116.
FreddyYe added a comment.

Rebase for D154181 


Repository:
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Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/lib/Basic/Targets/X86.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/test/CodeGen/attr-cpuspecific-avx-abi.c
  clang/test/CodeGen/attr-cpuspecific-cpus.c
  clang/test/CodeGen/attr-cpuspecific.c
  llvm/include/llvm/TargetParser/X86TargetParser.def
  llvm/include/llvm/TargetParser/X86TargetParser.h
  llvm/lib/Target/X86/X86.td
  llvm/lib/TargetParser/X86TargetParser.cpp
  llvm/test/CodeGen/X86/cpus-intel.ll

Index: llvm/test/CodeGen/X86/cpus-intel.ll
===
--- llvm/test/CodeGen/X86/cpus-intel.ll
+++ llvm/test/CodeGen/X86/cpus-intel.ll
@@ -6,16 +6,24 @@
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i586 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-mmx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_mmx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=i686 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentiumpro 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_pro 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_ii 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_iii 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_iii_no_xmm_regs 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_4 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=pentium_4_sse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=raptorlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=i686-unknown-unknown -mcpu=meteorlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
@@ -26,26 +34,39 @@
 
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=nocona 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core_2_duo_ssse3 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=penryn 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=core_2_duo_sse4_1 2>&1 | FileCheck

[PATCH] D154181: [x86] Add missing FeatureCMOV in frontend targets.

2023-06-29 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added a comment.

Thanks review!


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[PATCH] D154181: [x86] Add missing FeatureCMOV in frontend targets.

2023-06-29 Thread Freddy, Ye via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa9256a2e0450: [x86] Add missing FeatureCMOV in frontend 
targets. (authored by FreddyYe).

Repository:
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CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D154181

Files:
  clang/test/CodeGen/attr-target-clones.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/CodeGen/attr-target-x87-softfp.c
  clang/test/CodeGen/tune-cpu.c
  llvm/lib/TargetParser/X86TargetParser.cpp


Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -126,7 +126,7 @@
 
 // Pentium 2 and 3.
 constexpr FeatureBitset FeaturesPentium2 =
-FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
+FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR | FeatureCMOV;
 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
 
 // Pentium 4 CPUs
@@ -321,8 +321,8 @@
   { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
   // i686-generation processors, P6 / Pentium M microarchitecture based.
-  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
-  { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
+  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | 
FeatureCMPXCHG8B },
+  { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B },
   { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
   { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
   { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
Index: clang/test/CodeGen/tune-cpu.c
===
--- clang/test/CodeGen/tune-cpu.c
+++ clang/test/CodeGen/tune-cpu.c
@@ -3,4 +3,4 @@
 int baz(int a) { return 4; }
 
 // CHECK: baz{{.*}} #0
-// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cx8,+x87" 
"tune-cpu"="nehalem"
+// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" 
"tune-cpu"="nehalem"
Index: clang/test/CodeGen/attr-target-x87-softfp.c
===
--- clang/test/CodeGen/attr-target-x87-softfp.c
+++ clang/test/CodeGen/attr-target-x87-softfp.c
@@ -7,10 +7,10 @@
 // CHECK: foo{{.*}} #0
 // CHECK: bar{{.*}} #1
 
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87"
+// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87"
 // HARD-NOT: "use-soft-float"
 // SOFT: "use-soft-float"="true"
 
-// CHECK: #1 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,-x87"
+// CHECK: #1 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,-x87"
 // HARD-NOT: "use-soft-float"
 // SOFT: "use-soft-float"="true"
Index: clang/test/CodeGen/attr-target-x86.c
===
--- clang/test/CodeGen/attr-target-x86.c
+++ clang/test/CodeGen/attr-target-x86.c
@@ -51,22 +51,22 @@
 // CHECK: lake{{.*}} #7
 // CHECK: use_before_def{{.*}} #7
 // CHECK: walrus{{.*}} #8
-// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cx8,+x87" 
"tune-cpu"="i686"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
+// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" 
"tune-cpu"="i686"
+// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
 // CHECK-NOT: tune-cpu
-// CHECK: #2 = {{.*}}"target-cpu"="i686" 
"target-features"="+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop"
 "tune-cpu"="i686"
-// CHECK: #3 = {{.*}}"target-cpu"="i686" 
"target-features"="+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
 "tune-cpu"="i686"
-// CHECK: #4 = {{.*}}"target-cpu"="i686"

[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-06-29 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added a comment.

> Yes, it looks like it would be best to split off and commit some of the fixes 
> (cmov / the isa changes causing the attr-cpuspecific.c diffs etc.) first, 
> before this refactor patch.

Done in https://reviews.llvm.org/D154181


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[PATCH] D154181: [x86] Add missing FeatureCMOV in frontend targets.

2023-06-29 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe created this revision.
Herald added subscribers: pengfei, hiraditya.
Herald added a project: All.
FreddyYe requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

The missing info is gathered from X86.td.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D154181

Files:
  clang/test/CodeGen/attr-target-clones.c
  clang/test/CodeGen/attr-target-x86.c
  clang/test/CodeGen/attr-target-x87-softfp.c
  clang/test/CodeGen/tune-cpu.c
  llvm/lib/TargetParser/X86TargetParser.cpp


Index: llvm/lib/TargetParser/X86TargetParser.cpp
===
--- llvm/lib/TargetParser/X86TargetParser.cpp
+++ llvm/lib/TargetParser/X86TargetParser.cpp
@@ -126,7 +126,7 @@
 
 // Pentium 2 and 3.
 constexpr FeatureBitset FeaturesPentium2 =
-FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
+FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR | FeatureCMOV;
 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE;
 
 // Pentium 4 CPUs
@@ -321,8 +321,8 @@
   { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
   { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
   // i686-generation processors, P6 / Pentium M microarchitecture based.
-  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
-  { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
+  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | 
FeatureCMPXCHG8B },
+  { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B },
   { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
   { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
   { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
Index: clang/test/CodeGen/tune-cpu.c
===
--- clang/test/CodeGen/tune-cpu.c
+++ clang/test/CodeGen/tune-cpu.c
@@ -3,4 +3,4 @@
 int baz(int a) { return 4; }
 
 // CHECK: baz{{.*}} #0
-// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cx8,+x87" 
"tune-cpu"="nehalem"
+// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" 
"tune-cpu"="nehalem"
Index: clang/test/CodeGen/attr-target-x87-softfp.c
===
--- clang/test/CodeGen/attr-target-x87-softfp.c
+++ clang/test/CodeGen/attr-target-x87-softfp.c
@@ -7,10 +7,10 @@
 // CHECK: foo{{.*}} #0
 // CHECK: bar{{.*}} #1
 
-// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87"
+// CHECK: #0 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87"
 // HARD-NOT: "use-soft-float"
 // SOFT: "use-soft-float"="true"
 
-// CHECK: #1 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,-x87"
+// CHECK: #1 = {{.*}}"target-cpu"="x86-64" 
"target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,-x87"
 // HARD-NOT: "use-soft-float"
 // SOFT: "use-soft-float"="true"
Index: clang/test/CodeGen/attr-target-x86.c
===
--- clang/test/CodeGen/attr-target-x86.c
+++ clang/test/CodeGen/attr-target-x86.c
@@ -51,22 +51,22 @@
 // CHECK: lake{{.*}} #7
 // CHECK: use_before_def{{.*}} #7
 // CHECK: walrus{{.*}} #8
-// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cx8,+x87" 
"tune-cpu"="i686"
-// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
+// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" 
"tune-cpu"="i686"
+// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" 
"target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
 // CHECK-NOT: tune-cpu
-// CHECK: #2 = {{.*}}"target-cpu"="i686" 
"target-features"="+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop"
 "tune-cpu"="i686"
-// CHECK: #3 = {{.*}}"target-cpu"="i686" 
"target-features"="+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
 "tune-cpu"="i686"
-// CHECK: #4 = {{.*}}"target-cpu"="i686" 
"target-features"="+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop"

[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-06-29 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe added a comment.

In D151696#4458435 , @pengfei wrote:

> I have some concerns for RULE 3, especially `core_aes_pclmulqdq -> westmere` 
> and `atom_sse4_2_movbe -> silvermont`.
> Sometimes, we have minor feature differences in the same generation targets. 
> I guess that's why we use `arch_feature` naming like core_2_duo_ssse3. 
> Merging them into the same generation or the next generation might corrup the 
> intention here. But I'm not expert in CPUDispatch, and I don't see any 
> existing tests for them, so I won't block the patch since it's an improvement 
> in general.
> Please wait a few days for other reviewers' opinions.

You are right. For historical reasons, I can't find which product each cpu name 
string points to actually. From the old feature list in X86TargetParser.def, 
these three cpu names even share a same feature list:

  atom_sse4_2
  core_i7_sse4_2
  core_aes_pclmulqdq

"core_5th_gen_avx_tsx"  is also same as "broadwell". So I have a new proposal 
for RULE3, which can be considered to be more conservative:

  pentium_4_sse3 -> prescott (FeatureSSE3)
  First introduce FeatureSSE4_1 like prescott
  core_2_duo_ssse3 -> core2 (FeatureSSSE3)
  First introduce FeatureSSE4_1 like core2
  core_2_duo_sse4_1 -> penryn (FeatureSSE4_1)
  First introduce FeatureSSE4_1 like penryn
  atom_sse4_2 -> nehalem (FeatureSSE4_2)
  First introduce FeatureSSE4_2 like nehalem
  core_i7_sse4_2 -> nehalem (FeatureSSE4_2)
  First introduce FeatureSSE4_2 like nehalem
  core_aes_pclmulqdq -> nehalem (FeatureSSE4_2)
  First introduce FeatureSSE4_2 like nehalem
  core_5th_gen_avx_tsx -> broadwell 
  Same feature list as broadwell

Meanwhile, the fact above won't affect code changes in X86.td. I'll still 
define these new cpu names with the TUNE_NAME info in original source.


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[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-06-29 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked an inline comment as done.
FreddyYe added a comment.

In D151696#4458443 , @pengfei wrote:

> It looks to me the failed unit tests might be related to this patch, please 
> take a look.

This is due to FeatureCMOV adding. Should I split into another review?


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[PATCH] D151696: [x86] Remove CPU_SPECIFIC* MACROs and add getCPUDispatchMangling

2023-06-29 Thread Freddy, Ye via Phabricator via cfe-commits

FreddyYe marked an inline comment as done.
FreddyYe added inline comments.



Comment at: clang/test/CodeGen/attr-cpuspecific.c:56
 // WINDOWS: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32, 
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// WINDOWS: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 1023
-// WINDOWS: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 1023
+// WINDOWS: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 525311
+// WINDOWS: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 525311

pengfei wrote:
> FreddyYe wrote:
> > This value change is because the feature list of knl described in 
> > X86TargetParser.def before missed feature "bmi2" and "aes".
> The comment is for TwoVersions?
Yes. Sorry for wrong point.


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