[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

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Comment at: clang/test/CodeGen/RISCV/abi-empty-structs.c:21-22
 
 // Fields containing empty structs or unions are ignored when flattening
 // structs for the hard FP ABIs, even in C++.
-// FIXME: This isn't currently respected.

Shouldn't you mention the array exception here? (which you now cover in 
`test_s7` and `test_s8`).


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[PATCH] D145164: [clang][RISCV] Enable -fasynchronous-unwind-tables by default on Linux

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luismarques added a comment.

From Kito's comment in D144174 : 
https://github.com/gcc-mirror/gcc/commit/3cd08f7168c196d7a481b9ed9f4289fd1f14eea8


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[PATCH] D131141: [RISCV] Add MC support of RISCV Zcb Extension

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luismarques accepted this revision.
luismarques added a comment.

LGTM, with some in-line caveats.




Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZc.td:1
+//===-- RISCVInstrInfoZc.td - RISC-V 'Zc' instructions -*- tablegen 
-*-===//
+//

`Zc` -> `Zc*`



Comment at: llvm/test/MC/RISCV/rv32zcb-valid.s:21
+# CHECK-ASM: encoding: [0x61,0x9c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zcb' (Shortened 
format for basic bit manipulation instructions){{$}}
+c.zext.b s0

Still has the old message phrasing with the "shortened".


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[PATCH] D131141: [RISCV] Add MC support of RISCV Zcb Extension

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luismarques added a comment.

Possibly we want to add this change to the release notes?




Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:304-308
+   "'Zcb' (Shortened format for basic bit manipulation 
instructions)", 
+   [FeatureExtZca]>;
+def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
+ AssemblerPredicate<(all_of FeatureExtZcb),
+ "'Zcb' (Shortened format for basic bit 
manipulation instructions)">;

Is there any particular reason why this is described as a "shortened format" 
instead of the more common "compressed"?



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZc.td:9-10
+///
+/// This file describes the RISC-V instructions from the 'Zc' Code-size 
+/// reduction extension, version 0.70.4.
+/// This version is still experimental as the 'Zc' extension hasn't been

Ditto "Code-size reduction" -> "compressed"?


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[PATCH] D142326: [clang][RISCV][test] Add test cases for empty structs and the FP calling conventions

[Luís Marques via Phabricator via cfe-commits]

luismarques added inline comments.



Comment at: clang/test/CodeGen/RISCV/abi-empty-structs.c:1
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --function-signature --full-function-signature --filter "^define 
|^entry:"
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f 
-emit-llvm %s -o - \

Assume you updated this test with the not yet committed 
`--full-function-signature` option and forgot to remove that before updating 
the patch?
Please also check if the newly added `%s` below are supposed to be there.


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[PATCH] D142373: [Utils] Add --full-function-signature to update_cc_test_checks.py to match return type as well as args

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luismarques added a comment.

I'm probably not the best person to review this but, for what it's worth, it 
LGTM.


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[PATCH] D142373: [Utils] Add --full-function-signature to update_cc_test_checks.py to match return type as well as args

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luismarques added a comment.

Do we actually want to include the `dso_local` in the full signature?


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[PATCH] D142326: [clang][RISCV][test] Add test cases for empty structs and the FP calling conventions

[Luís Marques via Phabricator via cfe-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM but others should also chime in.




Comment at: clang/test/CodeGen/RISCV/abi-empty-structs.c:101
+
+struct s5 { struct empty e[1]; float f; };
+

Should we also test a case with an array size 0 like `ct s { struct empty e[0]; 
float f; };`? I think that's a GNU extension and I don't expect the result to 
be different but...



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[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

[Luís Marques via Phabricator via cfe-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGMT.




Comment at: clang/lib/CodeGen/TargetInfo.cpp:591
   if (isa(RT->getDecl()) &&
-  (WasArray || !FD->hasAttr()))
+  (WasArray || (!FD->hasAttr() && !AsIfNoUniqueAddr)))
 return false;

Nit: the `!AsIfNoUniqueAddr` condition could be tested before the 
`!FD->hasAttr()` condition, and I imagine that would be 
slightly cheaper for the `AsIfNoUniqueAddr = true` case?


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[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

Regarding the overkill of "RISCVInstrInfoZawrs.td", how about having a 
"RISCVInstrInfoExtra.td" (or "RISCVInstrInfoExt.td") as a grab bag for 
everything that doesn't merit its own .td file?

I think this is fine regarding the versioning issue. Seems to only be missing 
the actual instruction tests, otherwise LGTM.


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[PATCH] D132192: [RISCV] Add '32bit' feature to rv32 only builtins.

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

Overall LGTM.

I have one concern, though. The old error message was more user friendly. 
Referring to RV32 as an extension is... weird. You're already massaging the 
error with the `OF = "RV64"` / `OF = "RV32"`. Can't you special case this 
feature check error handling to make it print something more like the 
`err_32_bit_builtin_64_bit_tgt` message, "this builtin is only available on 
32-bit targets"? (if so, the same goes for the 64-bit case).

Also, arguably this could be two separate patches, but maybe it's not worth 
splitting...?




Comment at: clang/lib/Sema/SemaChecking.cpp:4359
-return Diag(TheCall->getCallee()->getBeginLoc(),
-diag::err_32_bit_builtin_64_bit_tgt);
-

That tablegen def is still being used for X86. Maybe you could make a similar 
patch for X86?


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[PATCH] D122370: Split up large test files under clang/test/CodeGen/RISCV

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luismarques added a comment.

What's the timeout value that is being exceeded?


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

Assuming this will be merged soon, do you want to submit a backport request for 
the 14.0 branch?


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[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

I think this would benefit from increased test coverage, namely to show that 
the mattr command-line options are properly handled. Some possible ideas:

- Tests with the correct extension versions (maybe add a test file that 
exercises the version for all extensions).
- Tests that show an error message with unsupported versions.
- A test that shows that something like mattr=+m,+m2p1 is allowed (or not).

Nit: fix the lint / no new line warnings.


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[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

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luismarques added a comment.

> enable 'm' extension with passing mattr=+m After this patch, it would be 
> -mattr=+m2p0.

It's not obvious to me that support for extension versions should mean or has 
to mean that we always explicitly specify the version. Why can't we keep 
supporting the option `mattr=+m`, which would be mapped to `mattr=+m,+m2p0`, or 
whatever the current default `m` version happens to be?


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[PATCH] D110669: [RISCV] Update Zba, Zbb, Zbc, and Zbs version from 0.93 to 1.0.

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luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D109727: [Driver] Remove unneeded *-suse-* triples

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

In D109727#3004125 , @MaskRay wrote:

> The code change of D74399  should be 
> reverted. The test can stay, but I won't think we need too many 
> riscv64-$distro-linux-gnu tests.

Makes sense. Do you want to update this patch to also remove that?


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[PATCH] D109727: [Driver] Remove unneeded *-suse-* triples

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luismarques added a comment.

Regarding D74399 , cmake on a fedora RISC-V 
host still detects a generic triple:

  -- LLVM host triple: riscv64-unknown-linux-gnu
  -- LLVM default target triple: riscv64-unknown-linux-gnu

as opposed to the `gcc -dumpmachine` triple of `riscv64-redhat-linux` (with the 
vendor and no `-gnu` suffix), needed for a working toolchain. (I don't know if 
that cmake behaviour is uncommon or not).

Are you saying that it's fine for D74399  to 
remain because of that, or does your argument also imply that D74399 
 should be reverted? Would the answer change 
if cmake started detecting the "proper" triple? (and what would the deprecation 
path for that be, if any?).




Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:2108-2113
+  "x86_64-linux-gnu", "x86_64-unknown-linux-gnu",
+  "x86_64-pc-linux-gnu",  "x86_64-redhat-linux6E",
+  "x86_64-redhat-linux",  "x86_64-manbo-linux-gnu",
+  "x86_64-linux-gnu", "x86_64-slackware-linux",
+  "x86_64-unknown-linux", "x86_64-amazon-linux",
+  "x86_64-linux-android"};

Ugh, these lines with multiple entries make mentally parsing the diff rather 
annoying.


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[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

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luismarques added a comment.

I was trying to put this patch through its paces but it no longer applies. Can 
you please rebase it? It seems this is nearly there.


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[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

[Luís Marques via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG34e055d33e37: [Clang][RISCV] Implement getConstraintRegister 
for RISC-V (authored by luismarques).

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  clang/test/Sema/inline-asm-validate-riscv.c


Index: clang/test/Sema/inline-asm-validate-riscv.c
===
--- clang/test/Sema/inline-asm-validate-riscv.c
+++ clang/test/Sema/inline-asm-validate-riscv.c
@@ -21,3 +21,11 @@
   asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of 
range for constraint 'K'}}
   asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of 
range for constraint 'K'}}
 }
+
+void test_clobber_conflict(void) {
+  register long x10 asm("x10");
+  asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm 
clobber list}}
+  asm volatile("" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm 
clobber list}}
+  asm volatile("" : "=r"(x10) :: "x10"); // expected-error {{conflicts with 
asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "a0"); // expected-error {{conflicts with asm 
clobber list}}
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -82,6 +82,11 @@
 
   const char *getClobbers() const override { return ""; }
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   ArrayRef getGCCRegNames() const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {


Index: clang/test/Sema/inline-asm-validate-riscv.c
===
--- clang/test/Sema/inline-asm-validate-riscv.c
+++ clang/test/Sema/inline-asm-validate-riscv.c
@@ -21,3 +21,11 @@
   asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'K'}}
   asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of range for constraint 'K'}}
 }
+
+void test_clobber_conflict(void) {
+  register long x10 asm("x10");
+  asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "a0"); // expected-error {{conflicts with asm clobber list}}
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -82,6 +82,11 @@
 
   const char *getClobbers() const override { return ""; }
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   ArrayRef getGCCRegNames() const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
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[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

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Comment at: clang/test/Sema/inline-asm-validate-riscv.c:27-28
+  register long x10 asm("x10");
+  asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm 
clobber list}}
+  asm volatile("" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm 
clobber list}}
+  asm volatile("" : "=r"(x10) :: "x10"); // expected-error {{conflicts with 
asm clobber list}}

I don't really understand the point of erroring-out in these two cases where 
the register is an input and is also clobbered. In fact, I've run into a case 
where that would be useful and accurately reflected the situation. But GCC's 
documentation explicitly prohibits that. I'm not sure if there's a fundamental 
reason for that, or if it's just an implementation quirk.


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[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

[Luís Marques via Phabricator via cfe-commits]

luismarques updated this revision to Diff 368323.
luismarques added a comment.

Nit: remove nop.


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  clang/test/Sema/inline-asm-validate-riscv.c


Index: clang/test/Sema/inline-asm-validate-riscv.c
===
--- clang/test/Sema/inline-asm-validate-riscv.c
+++ clang/test/Sema/inline-asm-validate-riscv.c
@@ -21,3 +21,11 @@
   asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of 
range for constraint 'K'}}
   asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of 
range for constraint 'K'}}
 }
+
+void test_clobber_conflict(void) {
+  register long x10 asm("x10");
+  asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm 
clobber list}}
+  asm volatile("" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm 
clobber list}}
+  asm volatile("" : "=r"(x10) :: "x10"); // expected-error {{conflicts with 
asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "a0"); // expected-error {{conflicts with asm 
clobber list}}
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -82,6 +82,11 @@
 
   const char *getClobbers() const override { return ""; }
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   ArrayRef getGCCRegNames() const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {


Index: clang/test/Sema/inline-asm-validate-riscv.c
===
--- clang/test/Sema/inline-asm-validate-riscv.c
+++ clang/test/Sema/inline-asm-validate-riscv.c
@@ -21,3 +21,11 @@
   asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'K'}}
   asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of range for constraint 'K'}}
 }
+
+void test_clobber_conflict(void) {
+  register long x10 asm("x10");
+  asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "a0"); // expected-error {{conflicts with asm clobber list}}
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -82,6 +82,11 @@
 
   const char *getClobbers() const override { return ""; }
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   ArrayRef getGCCRegNames() const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
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[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

[Luís Marques via Phabricator via cfe-commits]

luismarques created this revision.
luismarques added reviewers: asb, thopre.
Herald added subscribers: vkmr, frasercrmck, evandro, apazos, sameer.abuasal, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, 
sabuasal, simoncook, johnrusso, rbar.
luismarques requested review of this revision.
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Herald added a project: clang.

The getConstraintRegister method is used by semantic checking of inline 
assembly statements in order to diagnose conflicts between clobber list and 
input/output lists. By overriding getConstraintRegister we get those 
diagnostics and we match RISC-V GCC's behavior. The implementation is trivial 
due to the lack of single-register RISC-V-specific constraints.


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Files:
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Sema/inline-asm-validate-riscv.c


Index: clang/test/Sema/inline-asm-validate-riscv.c
===
--- clang/test/Sema/inline-asm-validate-riscv.c
+++ clang/test/Sema/inline-asm-validate-riscv.c
@@ -21,3 +21,11 @@
   asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of 
range for constraint 'K'}}
   asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of 
range for constraint 'K'}}
 }
+
+void test_clobber_conflict(void) {
+  register long x10 asm("x10");
+  asm volatile("nop" :: "r"(x10) : "x10"); // expected-error {{conflicts with 
asm clobber list}}
+  asm volatile("nop" :: "r"(x10) : "a0"); // expected-error {{conflicts with 
asm clobber list}}
+  asm volatile("nop" : "=r"(x10) :: "x10"); // expected-error {{conflicts with 
asm clobber list}}
+  asm volatile("nop" : "=r"(x10) :: "a0"); // expected-error {{conflicts with 
asm clobber list}}
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -82,6 +82,11 @@
 
   const char *getClobbers() const override { return ""; }
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   ArrayRef getGCCRegNames() const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {


Index: clang/test/Sema/inline-asm-validate-riscv.c
===
--- clang/test/Sema/inline-asm-validate-riscv.c
+++ clang/test/Sema/inline-asm-validate-riscv.c
@@ -21,3 +21,11 @@
   asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'K'}}
   asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of range for constraint 'K'}}
 }
+
+void test_clobber_conflict(void) {
+  register long x10 asm("x10");
+  asm volatile("nop" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("nop" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("nop" : "=r"(x10) :: "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("nop" : "=r"(x10) :: "a0"); // expected-error {{conflicts with asm clobber list}}
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -82,6 +82,11 @@
 
   const char *getClobbers() const override { return ""; }
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   ArrayRef getGCCRegNames() const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
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[PATCH] D106888: [RISC-V] Implement jump tables for CFI-icall

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

In D106888#2954788 , @twd2 wrote:

> Hi, you can check here: 
> https://buildkite.com/llvm-project/premerge-checks/builds/49755#814fd222-2e5a-4400-824d-d1a1f1293c01
> The clang-tidy failed due to the invalid case style for variable 
> 'kRISCVJumpTableEntrySize'.

We can ignore the lint check failure. The new constant follows the same style 
as the existing ones.


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[PATCH] D106888: [RISC-V] Implement jump tables for CFI-icall

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

In D106888#2954425 , @asb wrote:

> Is it possible to write a test case for this?

Good question. I had checked that the AArch64 implementation had included a 
test, but I think that was only for new target-specific stuff, which doesn't 
apply here. So I was assuming the answer was no, but it would be good to get 
confirmation. I was also confused by the comment about "the build failure", 
since this applied cleanly and built OK for me when I looked at it.


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[PATCH] D106701: [clang] Add -falign-loops=N where N is a power of 2

[Luís Marques via Phabricator via cfe-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

Still LGTM.

BTW, I liked that in the old version the help string included "In GCC =0 is the 
same as =1".


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[PATCH] D106701: [clang] Add -falign-loops=N where N is a power of 2

[Luís Marques via Phabricator via cfe-commits]

luismarques added inline comments.



Comment at: llvm/test/CodeGen/RISCV/loop-alignment.ll:3-4
+; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
+; RUN: llc < %s -mtriple=riscv64 -align-loops=16 | FileCheck %s 
-check-prefix=ALIGN_16
+; RUN: llc < %s -mtriple=riscv64 -align-loops=32 | FileCheck %s 
-check-prefix=ALIGN_32
+

MaskRay wrote:
> jrtc27 wrote:
> > MaskRay wrote:
> > > jrtc27 wrote:
> > > > MaskRay wrote:
> > > > > luismarques wrote:
> > > > > > Nit: it's a convention of the RISC-V backend codegen tests to wrap 
> > > > > > the RUN lines.
> > > > > only 86 columns. compiler-rt is even transiting to 100 column.
> > > > compiler-rt is not the RISC-V backend :)
> > > Wrapping lines here just makes the code less readable.
> > That's your personal opinion, which I disagree with, and it's not true if 
> > your terminal isn't wide enough. Going against existing convention in the 
> > backend tests should only be done with very good reason, and personal 
> > opinion is not that.
> Lines longer than 80-column (in this case just 86) are pretty common among 
> tests. I really hope test/CodeGen/RISCV/ can be more tolerant on this matter.
> 
> Even the Linux scripts/checkpatch.pl has increased the limit to 100 because 
> in many cases wrapping lines for strict 80-conformance just harms readability.
> 
> Of course I don't want to waste time arguing on this matter. So if this turns 
> out to be an issue for RISC-V folks, I'll update it to save my time.
> Of course I don't want to waste time arguing on this matter. So if this turns 
> out to be an issue for RISC-V folks, I'll update it to save my time.

Personally, I don't particularly care. I don't know if @asb has strong feelings 
about this. If you think it would be beneficial to relax this convention please 
raise the issue on llvm-dev. Let's not keep discussing this in every patch 
touching RISC-V :-)


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[PATCH] D106701: [clang] Add -falign-loops=N where N is a power of 2

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

LGTM. I'll let someone familiar with the old option explicitly approve it.




Comment at: clang/test/Driver/falign-loops.c:6-7
+// RUN: %clang -### -falign-loops=5 %s 2>&1 | FileCheck %s 
--check-prefix=CHECK-5
+// RUN: %clang -### -falign-loops=8 %s 2>&1 | FileCheck %s 
--check-prefix=CHECK-8
+// RUN: %clang -### -falign-loops=65537 %s 2>&1 | FileCheck %s 
--check-prefix=CHECK-65537
+// RUN: %clang -### -falign-loops=a %s 2>&1 | FileCheck %s 
--check-prefix=CHECK-ERR-A

I would generally expect to see the `<= x` bound tested with `x` and `x+1`, not 
just `x+1`.



Comment at: llvm/test/CodeGen/RISCV/loop-alignment.ll:3-4
+; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
+; RUN: llc < %s -mtriple=riscv64 -align-loops=16 | FileCheck %s 
-check-prefix=ALIGN_16
+; RUN: llc < %s -mtriple=riscv64 -align-loops=32 | FileCheck %s 
-check-prefix=ALIGN_32
+

Nit: it's a convention of the RISC-V backend codegen tests to wrap the RUN 
lines.


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[PATCH] D105690: [RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change

[Luís Marques via Phabricator via cfe-commits]

luismarques added inline comments.



Comment at: llvm/test/CodeGen/RISCV/rvv/vfredusum-rv32.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh 
-verify-machineinstrs \

frasercrmck wrote:
> Just to check - was this renaming done with `git mv`? Phabricator suggests 
> that `vfredsum-rv32.ll` was deleted and this was added, which would be worse 
> for the git history. It might be a phabricator quirk, though.
AFAIK `git mv` doesn't do anything in particular to track renames. File renames 
are automatically detected based on the added and removed content, which means 
that if there are also changes to the content that detection might fail, and 
here the instruction renames did cause a lot of changes.


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[PATCH] D105254: [RISCV] Support machine constraint "S"

[Luís Marques via Phabricator via cfe-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

In D105254#2852489 , @luismarques 
wrote:

> Makes sense. Let's wait for the GCC Bugzilla feedback.

With 'S' now documented on the GNU side, I think this can be merged.

Would we keep this constraint forever regardless of how discussions of [1] 
might evolve?

[1] https://github.com/riscv/riscv-elf-psabi-doc/issues/197


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[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

This patch is nearly there! Just address the remaining review comments and it 
LGTM.

BTW, please mark all addressed inline comments as done. I think a few were 
missed, and it's helpful for a large patch like this.




Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:953-956
+static MCRegister convertGPRToGPRPair(MCRegister Reg) {
+  assert(isGPRPair(Reg) && "Invalid register");
+  return (Reg - RISCV::X0) / 2 + RISCV::X0_ZERO;
+}

Nitpicking: perhaps this could use better terminology. You're asserting that 
`Reg` is a GPRPair, and then you convert `Reg` to a GPRPair, but the return 
value would fail an assert of `isGPRPair`...



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69
 
+def sub_lo : SubRegIndex<32>;
+def sub_hi : SubRegIndex<32, 32>;

jrtc27 wrote:
> This assumes RV32, and is not clear it applies to register pairs
What's the best way to address this?



Comment at: llvm/test/MC/RISCV/rv32zpsfoperand-invalid.s:6-9
+# Paired register operand
+
+# CHECK-ERROR: error: invalid operand for instruction
+smal a0, a1, a2

It would be nice to have a more specific error message, indicating the need for 
an even register operand. But not a deal-breaker, IMO.


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[PATCH] D98113: [Driver] Also search FilePaths for compiler-rt before falling back

[Luís Marques via Phabricator via cfe-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

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luismarques added inline comments.



Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:1
+//===-- RISCVArchStringParser.h - RISCV Arch String Parser --*- C++ 
-*-===//
+//

Incorrect header name.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:24-38
+// Represents the major and version number components of a RISC-V extension
+struct RISCVExtensionVersion {
+  unsigned Major;
+  unsigned Minor;
+};
+
+struct RISCVSupportedExtensionInfo {

Use `///` to add to the generated documentation?



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:112
+
+// Helper function for fiilter SupportedExtensionInfos by name.
+static auto filterSupportedExtensionInfosByName(StringRef ExtName) {

fiilter -> filtering



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:190-191
+  if (Pos == StringRef::npos)
+// If got an unknown extension letter, then give it an alphabetical
+// order, but after all known standard extension.
+Rank = AllStdExts.size() + (Ext - 'a');

got -> we got. extension -> extensions.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:235
+// Compare function for extension.
+// Only compare the extension name, ignore version comparesion.
+bool RISCVISAInfo::compareExtension(const std::string ,

comparesion -> comparison.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:260
+
+  // If the rank is same, it must be sorted by lexical order.
+  return LHS < RHS;

lexicographic order


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[PATCH] D105254: [RISCV] Support machine constraint "S"

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luismarques added a comment.

Makes sense. Let's wait for the GCC Bugzilla feedback.


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[PATCH] D103878: [clang][RISCV][test] Add more tests of the -mabi and -march options

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

In D103878#2807118 , @benshi001 wrote:

> 1. there is no tests for mabi=ilp32e, and my patch covers that.
> 2. the tests in riscv-abi.c will show default abi changes for special archs, 
> especially for the arch with F but without D extension, in the future.
> 3. the tests in riscv-arch.c will show default arch changes for abi=ilp32, 
> which is rv32imacfd now, and it is better to be rv32imac. for abi=ilp32f it 
> is better arch=imacf than current imacfd.

That sounds like a good description to add to the patch summary / commit 
message!


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[PATCH] D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

In D102839#2784275 , @ksyx wrote:

> Thanks for mentioning that! Now, I changed the effect of `no-div` option into 
> choosing a proper extension and implemented the `Zmmul` subextension. Is this 
> solution acceptable or are there anything need further changes?

It seems like the community is quickly converging on just using the ISA string 
with Zmmul, and not using no-div. While being compatible with the GNU tools is 
nice, if they are planning on dropping support for no-div soonish then we 
probably shouldn't add support for it. IMO, Zmmul should be a separate patch 
and presumably (at the moment) be gated by `-menable-experimental-extensions`.


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[PATCH] D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

In D102839#2783636 , @ksyx wrote:

> So it seems the better way to do this would definitely by adding a 
> subextension as the spec had changed. But I'd like  also to ask how will GCC 
> deal with this option, and should we make this option an alias to turn off M 
> extension and turn on ZMMul extension?

Regarding "turn off M extension", see Krste's comment in the PR:

> I think -mno-div is OK as a compiler option, but it's meaning is for the 
> compiler not to generate divide instructions, not to indicate what the ISA 
> is. So for example, -mno-div should not set ELF flags in binary to indicate 
> ISA doesn't have divide - it should simply not generate divide instructions.


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[PATCH] D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

In D102839#2782557 , @kito-cheng 
wrote:

> We have Zmmul extension in the ISA spec now, that's equivalent to `-mno-div` 
> , so I suggest we should go forward to implement that extension rather than 
> `-mno-div`.
> https://github.com/riscv/riscv-isa-manual/pull/648

Thanks for bringing that to our attention, Kito. I had missed that recent PR 
and its discussion.
If the GNU ecosystem intends to move away from `-mno-div` soonish then Zmmul is 
for sure the way to go. I don't see enough benefit for LLVM to add a stop-gap 
compatibility option.


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[PATCH] D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division

[Luís Marques via Phabricator via cfe-commits]

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Comment at: clang/include/clang/Driver/Options.td:3149-3152
+def mno_div : Flag<["-"], "mno-div">, Group,
+  HelpText<"Disable hardware integral division instructions in M extension">;
+def mdiv : Flag<["-"], "mdiv">, Group,
+  HelpText<"Enable hardware integral division instructions in M extension">;

Remove the redundant "hardware".

BTW, is "integral" actually correct, or should it be "integer division"?



Comment at: clang/lib/Basic/Targets/RISCV.h:49
   bool HasZvlsseg = false;
+  bool DisableHardwareIntDiv = false;
 

`DisableHardwareIntDiv` -> `DisableIntDiv`

Also, in general it would be best for the feature to be positive rather than 
negative, but I'm not sure whether it makes sense to make an exception here, 
since the option that toggles the feature is also negative.



Comment at: clang/test/Driver/riscv-no-div.c:1-17
+// RUN: %clang -target riscv32-unknown-elf %s -mno-div -S -o - 2>&1 \
+// RUN:   | not FileCheck -check-prefix=CHECK-NOERROR %s
+
+// RUN: %clang -target riscv64-unknown-elf %s -mno-div -S -o - 2>&1 \
+// RUN:   | not FileCheck -check-prefix=CHECK-NOERROR %s
+
+// RUN: %clang -target riscv32-unknown-elf %s -mno-div -S -o - 2>&1 \

Is `not FileCheck` the only way to check these do not occur?



Comment at: clang/test/Driver/riscv-no-div.c:33-35
+  // CHECK-DIV: div{{w?}} a{{[0-9]}}, a{{[0-9]}}, a{{[0-9]}}
+  // CHECK-REM: rem{{w?}} a{{[0-9]}}, a{{[0-9]}}, a{{[0-9]}}
+  // CHECK-MUL: mul{{w?}} a{{[0-9]}}, a{{[0-9]}}, a{{[0-9]}}

Should we be checking the actual instructions in a Clang test?



Comment at: llvm/test/CodeGen/RISCV/no-div.ll:29-31
+; This test makes sure even when both M extension no-div option enabled,
+; the compile would not fail. Instead, it will use a fallback solution like
+; calling builtin library functions.

I'm not sure it makes sense to refer to the possibility of the compilation 
failing. It's just that we shouldn't emit divide instructions.



Comment at: llvm/test/CodeGen/RISCV/no-div.ll:34-44
+; CHECK-UDIV: divu{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, 
{{[as]}}{{[0-9]}}
+  %1 = udiv i32 %a, %b
+; CHECK-DIV: div{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}
+  %2 = sdiv i32 %a, %1
+; CHECK-MUL: mul{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}
+  %3 = mul i32 %b, %2
+; CHECK-UREM: remu{{w?}} {{[as]}}{{[0-9]}}, {{[as]}}{{[0-9]}}, 
{{[as]}}{{[0-9]}}

@jrtc27 should we use update_llc_test_checks.py instead here?


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[PATCH] D101876: [clang] Support -fpic -fno-semantic-interposition for RISCV

[Luís Marques via Phabricator via cfe-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D99108: [RISCV] Add XFAIL riscv32 for known issue with the old pass manager

[Luís Marques via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa8cf32baf57d: [RISCV] Add XFAIL riscv32 for known issue with 
the old pass manager (authored by luismarques).

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Files:
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Index: clang/test/CodeGen/sanitize-coverage-old-pm.c
===
--- clang/test/CodeGen/sanitize-coverage-old-pm.c
+++ clang/test/CodeGen/sanitize-coverage-old-pm.c
@@ -7,6 +7,8 @@
 //
 // Host armv7 is currently unsupported: 
https://bugs.llvm.org/show_bug.cgi?id=46117
 // XFAIL: armv7, thumbv7
+// The same issue also occurs on a riscv32 host.
+// XFAIL: riscv32
 
 int x[10];
 


Index: clang/test/CodeGen/sanitize-coverage-old-pm.c
===
--- clang/test/CodeGen/sanitize-coverage-old-pm.c
+++ clang/test/CodeGen/sanitize-coverage-old-pm.c
@@ -7,6 +7,8 @@
 //
 // Host armv7 is currently unsupported: https://bugs.llvm.org/show_bug.cgi?id=46117
 // XFAIL: armv7, thumbv7
+// The same issue also occurs on a riscv32 host.
+// XFAIL: riscv32
 
 int x[10];
 
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[PATCH] D99108: [RISCV] Add XFAIL riscv32 for known issue with the old pass manager

[Luís Marques via Phabricator via cfe-commits]

luismarques created this revision.
luismarques added a reviewer: asb.
Herald added subscribers: vkmr, evandro, sameer.abuasal, s.egerton, Jim, benna, 
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See D80668  and rG7b4832648a63 
 for 
details of the issue.


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Files:
  clang/test/CodeGen/sanitize-coverage-old-pm.c


Index: clang/test/CodeGen/sanitize-coverage-old-pm.c
===
--- clang/test/CodeGen/sanitize-coverage-old-pm.c
+++ clang/test/CodeGen/sanitize-coverage-old-pm.c
@@ -7,6 +7,8 @@
 //
 // Host armv7 is currently unsupported: 
https://bugs.llvm.org/show_bug.cgi?id=46117
 // XFAIL: armv7, thumbv7
+// The same issue also occurs on a riscv32 host.
+// XFAIL: riscv32
 
 int x[10];
 


Index: clang/test/CodeGen/sanitize-coverage-old-pm.c
===
--- clang/test/CodeGen/sanitize-coverage-old-pm.c
+++ clang/test/CodeGen/sanitize-coverage-old-pm.c
@@ -7,6 +7,8 @@
 //
 // Host armv7 is currently unsupported: https://bugs.llvm.org/show_bug.cgi?id=46117
 // XFAIL: armv7, thumbv7
+// The same issue also occurs on a riscv32 host.
+// XFAIL: riscv32
 
 int x[10];
 
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[PATCH] D98113: [Driver] Also search FilePaths for compiler-rt before falling back

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

I just looked at this again and I don't have the full context in my mind right 
now but won't the test just exercise the BareMetal toolchain and not your 
changes?


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[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

This still doesn't report that the multilib configuration came from GCC when it 
succeeds, does it? I suppose that's not a deal-breaker, but it would be nice to 
have. Would it be difficult to implement?

Regarding the Windows test issue, aren't there other test cases in similar 
situations that managed to sort that out?




Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1659
+  for (StringRef Line : Lines) {
+if (Line.trim().empty())
+  continue;

I was actually thinking something along the lines of `Line = Line.trim();`, so 
that the rest of the parsing code would also benefit from having any extraneous 
whitespace removed and thus be more robust. Or does this mutate the argument?



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1742
+  if (RC != 0) {
+MultilibErrorMessages = "Read GCC multilib configureation failed due to "
+"non-zero return code";

configureation -> configuration. Also, the user won't know what the "non-zero 
return code" refers to. How about something like "Failed to execute  in 
an attempt to obtain the multilib configuration from GCC"?


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[PATCH] D98113: [Driver] Also search FilePaths for compiler-rt before falling back

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

This makes sense to me but I'm not quite sure about the implications, 
especially when we consider compatibility. I think we need more eyes on this 
patch.


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[PATCH] D98610: [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'

[Luís Marques via Phabricator via cfe-commits]

luismarques added inline comments.



Comment at: llvm/test/CodeGen/RISCV/patchable-function-entry.ll:1-3
+;; Test the function attribute "patchable-function-entry".
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefixes=CHECK,32
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefixes=CHECK,64

jrtc27 wrote:
> Please match the style of the other tests: 
> - update_llc_test_checks.py
> - RV32I/RV32IC/RV64I/RV64IC
> Please match the style of the other tests: 
> - update_llc_test_checks.py

I was going to comment on that but I was unsure it applied here, given that 
this test was running more than just `llc`. The other RISC-V CodeGen tests we 
have with objdump don't use the update script IIRC. (And these manual tests 
were neatly written and much more condensed that the sprawling output of the 
auto updated checks). But I agree that in general using the script is the way 
to go for the RISC-V tests.


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[PATCH] D97916: [Driver][RISCV] Support parsing multi-lib config from GCC.

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

This patch seems to be in pretty good shape now.

One thing that might be useful (important?) to add is additional diagnostics 
when run in verbose mode. Currently `clang -v` will indicate that it found the 
GCC installation and will list the multilibs but there will be no indication 
that the multilib list came from GCC. Also, if things like the `ExecuteAndWait` 
(in `getRISCVMultilibFromGCC`) fail shouldn't we print some kind of diagnostic, 
at least in verbose mode? Otherwise when problems occur it might be tricky to 
figure out what's going on.




Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:726
+StringRef riscv::getRISCVCodeModel(const llvm::opt::ArgList ) {
+  // Default code model is small(medlow).
+  StringRef CodeModel;

Nitpicking suggestion: `\\ Default code model is 'small' (what GCC calls 
'medlow').`



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1657
+  for (StringRef Line : Lines) {
+if (Line.empty())
+  continue;

Maybe trim whitespace before checking for empty lines, for extra robustness?



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[PATCH] D98610: [RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'

[Luís Marques via Phabricator via cfe-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

Overall LGTM.
I just don't understand what you mean with "1-byte NOPs" in the patchable 
prefix case. Regular NOPs are emitted. Please clarify the comment/patch as 
needed.


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[PATCH] D97896: [Clang][RISCV][RFC] Add byval parameter attribute?

[Luís Marques via Phabricator via cfe-commits]

luismarques created this revision.
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Should we add the `byval` parameter attribute to struct parameters?

Pros:

- Improves optimizations;
- Used by MSan instrumentation pass (without it a test will fail).

Cons:

- ?

An example of an optimization without `byval` and with `byval`:

  $ cat test.c
  struct S { char c[32]; };
  void foo(struct S s) {
  s.c[0] = 42;
  }
  $ clang --target=riscv64-linux -O2 -S -o- test.c

Without `byval`:

  foo:
  addia1, zero, 42
  sb  a1, 0(a0)
  ret

With `byval`:

  foo:
  ret

I'm not sure what the impact would be of also adding the attribute to vector 
parameters, so this patch doesn't do so.


Repository:
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Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/RISCV/riscv32-ilp32-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-abi.c
  clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
  clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c

Index: clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
===
--- clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
+++ clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
@@ -240,7 +240,7 @@
 
 struct int_double_int_s { int a; double b; int c; };
 
-// CHECK: define{{.*}} void @f_int_double_int_s_arg(%struct.int_double_int_s* %a)
+// CHECK: define{{.*}} void @f_int_double_int_s_arg(%struct.int_double_int_s* byval(%struct.int_double_int_s) align 8 %a)
 void f_int_double_int_s_arg(struct int_double_int_s a) {}
 
 // CHECK: define{{.*}} void @f_ret_int_double_int_s(%struct.int_double_int_s* noalias sret(%struct.int_double_int_s) align 8 %agg.result)
Index: clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
===
--- clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
+++ clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
@@ -159,7 +159,7 @@
   int64_t a, b, c, d;
 };
 
-// CHECK-LABEL: define{{.*}} void @f_agg_large(%struct.large* %x)
+// CHECK-LABEL: define{{.*}} void @f_agg_large(%struct.large* byval(%struct.large) align 8 %x)
 void f_agg_large(struct large x) {
   x.a = x.b + x.c + x.d;
 }
@@ -186,7 +186,7 @@
 // Scalars passed on the stack should not have signext/zeroext attributes
 // (they are anyext).
 
-// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i64 %a.coerce, [2 x i64] %b.coerce, i128 %c.coerce, %struct.large* %d, i8 zeroext %e, i8 signext %f, i8 %g, i8 %h)
+// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i64 %a.coerce, [2 x i64] %b.coerce, i128 %c.coerce, %struct.large* byval(%struct.large) align 8 %d, i8 zeroext %e, i8 signext %f, i8 %g, i8 %h)
 int f_scalar_stack_1(struct tiny a, struct small b, struct small_aligned c,
  struct large d, uint8_t e, int8_t f, uint8_t g, int8_t h) {
   return g + h;
@@ -217,7 +217,7 @@
 
 // CHECK-LABEL: define{{.*}} void @f_va_caller()
 void f_va_caller() {
-  // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i64 3, double 4.00e+00, double 5.00e+00, i64 {{%.*}}, [2 x i64] {{%.*}}, i128 {{%.*}}, %struct.large* {{%.*}})
+  // CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i64 3, double 4.00e+00, double 5.00e+00, i64 {{%.*}}, [2 x i64] {{%.*}}, i128 {{%.*}}, %struct.large* byval(%struct.large) align 8 {{%.*}})
   f_va_callee(1, 2, 3LL, 4.0f, 5.0, (struct tiny){6, 7, 8, 9},
   (struct small){10, NULL}, (struct small_aligned){11},
   (struct large){12, 13, 14, 15});
Index: clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
===
--- clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
+++ clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
@@ -109,7 +109,7 @@
   return (struct float_int32_s){1.0, 2};
 }
 
-// CHECK: define{{.*}} void @f_float_int64_s_arg(%struct.float_int64_s* %a)
+// CHECK: define{{.*}} void @f_float_int64_s_arg(%struct.float_int64_s* byval(%struct.float_int64_s) align 8 %a)
 void f_float_int64_s_arg(struct float_int64_s a) {}
 
 // CHECK: define{{.*}} void @f_ret_float_int64_s(%struct.float_int64_s* noalias sret(%struct.float_int64_s) align 8 %agg.result)
@@ -233,7 +233,7 @@
 
 struct 

[PATCH] D92403: [LSan][RISCV] Enable LSan for RISCV64

[Luís Marques via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2de4f19ecdb2: [LSan][RISCV] Enable LSan for RISCV64 
(authored by luismarques).

Repository:
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Files:
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/fsanitize.c
  compiler-rt/cmake/config-ix.cmake
  compiler-rt/lib/lsan/lsan_allocator.h
  compiler-rt/lib/lsan/lsan_common.h
  compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
  compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
  compiler-rt/test/asan/lit.cfg.py
  compiler-rt/test/lsan/TestCases/use_registers.cpp
  compiler-rt/test/lsan/lit.common.cfg.py
  compiler-rt/test/sanitizer_common/print_address.h

Index: compiler-rt/test/sanitizer_common/print_address.h
===
--- compiler-rt/test/sanitizer_common/print_address.h
+++ compiler-rt/test/sanitizer_common/print_address.h
@@ -8,7 +8,7 @@
   while (n--) {
 void *p = va_arg(ap, void *);
 #if defined(__x86_64__) || defined(__aarch64__) || defined(__powerpc64__) || \
-defined(__s390x__)
+defined(__s390x__) || (defined(__riscv) && __riscv_xlen == 64)
 // On FreeBSD, the %p conversion specifier works as 0x%x and thus does not
 // match to the format used in the diagnotic message.
 fprintf(stderr, "0x%012lx ", (unsigned long) p);
Index: compiler-rt/test/lsan/lit.common.cfg.py
===
--- compiler-rt/test/lsan/lit.common.cfg.py
+++ compiler-rt/test/lsan/lit.common.cfg.py
@@ -76,7 +76,7 @@
 # LeakSanitizer tests are currently supported on
 # Android{aarch64, x86, x86_64}, x86-64 Linux, PowerPC64 Linux, arm Linux, mips64 Linux, s390x Linux and x86_64 Darwin.
 supported_android = config.android and config.target_arch in ['x86_64', 'i386', 'aarch64'] and 'android-thread-properties-api' in config.available_features
-supported_linux = (not config.android) and config.host_os == 'Linux' and config.host_arch in ['x86_64', 'ppc64', 'ppc64le', 'mips64', 'arm', 'armhf', 'armv7l', 's390x']
+supported_linux = (not config.android) and config.host_os == 'Linux' and config.host_arch in ['x86_64', 'ppc64', 'ppc64le', 'mips64', 'riscv64', 'arm', 'armhf', 'armv7l', 's390x']
 supported_darwin = config.host_os == 'Darwin' and config.target_arch in ['x86_64']
 supported_netbsd = config.host_os == 'NetBSD' and config.target_arch in ['x86_64', 'i386']
 if not (supported_android or supported_linux or supported_darwin or supported_netbsd):
Index: compiler-rt/test/lsan/TestCases/use_registers.cpp
===
--- compiler-rt/test/lsan/TestCases/use_registers.cpp
+++ compiler-rt/test/lsan/TestCases/use_registers.cpp
@@ -50,6 +50,10 @@
   asm("lgr %%r10, %0"
   :
   : "r"(p));
+#elif defined(__riscv)
+  asm("mv s11, %0"
+  :
+  : "r"(p));
 #else
 #error "Test is not supported on this architecture."
 #endif
Index: compiler-rt/test/asan/lit.cfg.py
===
--- compiler-rt/test/asan/lit.cfg.py
+++ compiler-rt/test/asan/lit.cfg.py
@@ -210,7 +210,7 @@
 
 # Turn on leak detection on 64-bit Linux.
 leak_detection_android = config.android and 'android-thread-properties-api' in config.available_features and (config.target_arch in ['x86_64', 'i386', 'i686', 'aarch64'])
-leak_detection_linux = (config.host_os == 'Linux') and (not config.android) and (config.target_arch in ['x86_64', 'i386'])
+leak_detection_linux = (config.host_os == 'Linux') and (not config.android) and (config.target_arch in ['x86_64', 'i386', 'riscv64'])
 leak_detection_mac = (config.host_os == 'Darwin') and (config.target_arch == 'x86_64')
 leak_detection_netbsd = (config.host_os == 'NetBSD') and (config.target_arch in ['x86_64', 'i386'])
 if leak_detection_android or leak_detection_linux or leak_detection_mac or leak_detection_netbsd:
Index: compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
===
--- compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
+++ compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
@@ -486,7 +486,7 @@
   (!SI_FREEBSD && !SI_MAC && !SI_NETBSD && SI_NOT_RTEMS)
 #define SANITIZER_INTERCEPT___LIBC_MEMALIGN SI_GLIBC
 #define SANITIZER_INTERCEPT_PVALLOC (SI_GLIBC || SI_ANDROID)
-#define SANITIZER_INTERCEPT_CFREE SI_GLIBC
+#define SANITIZER_INTERCEPT_CFREE (SI_GLIBC && !SANITIZER_RISCV64)
 #define SANITIZER_INTERCEPT_REALLOCARRAY SI_POSIX
 #define SANITIZER_INTERCEPT_ALIGNED_ALLOC (!SI_MAC && SI_NOT_RTEMS)
 #define SANITIZER_INTERCEPT_MALLOC_USABLE_SIZE (!SI_MAC && !SI_NETBSD)
Index: compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp

[PATCH] D92403: [LSan][RISCV] Enable LSan for RISCV64

[Luís Marques via Phabricator via cfe-commits]

luismarques updated this revision to Diff 320375.
luismarques added a comment.
Herald added a subscriber: vkmr.

Rebase and address formatting issues.


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  clang/test/Driver/fsanitize.c
  compiler-rt/cmake/config-ix.cmake
  compiler-rt/lib/lsan/lsan_allocator.h
  compiler-rt/lib/lsan/lsan_common.h
  compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
  compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
  compiler-rt/test/asan/lit.cfg.py
  compiler-rt/test/lsan/TestCases/use_registers.cpp
  compiler-rt/test/lsan/lit.common.cfg.py
  compiler-rt/test/sanitizer_common/print_address.h

Index: compiler-rt/test/sanitizer_common/print_address.h
===
--- compiler-rt/test/sanitizer_common/print_address.h
+++ compiler-rt/test/sanitizer_common/print_address.h
@@ -8,7 +8,7 @@
   while (n--) {
 void *p = va_arg(ap, void *);
 #if defined(__x86_64__) || defined(__aarch64__) || defined(__powerpc64__) || \
-defined(__s390x__)
+defined(__s390x__) || (defined(__riscv) && __riscv_xlen == 64)
 // On FreeBSD, the %p conversion specifier works as 0x%x and thus does not
 // match to the format used in the diagnotic message.
 fprintf(stderr, "0x%012lx ", (unsigned long) p);
Index: compiler-rt/test/lsan/lit.common.cfg.py
===
--- compiler-rt/test/lsan/lit.common.cfg.py
+++ compiler-rt/test/lsan/lit.common.cfg.py
@@ -76,7 +76,7 @@
 # LeakSanitizer tests are currently supported on
 # Android{aarch64, x86, x86_64}, x86-64 Linux, PowerPC64 Linux, arm Linux, mips64 Linux, s390x Linux and x86_64 Darwin.
 supported_android = config.android and config.target_arch in ['x86_64', 'i386', 'aarch64'] and 'android-thread-properties-api' in config.available_features
-supported_linux = (not config.android) and config.host_os == 'Linux' and config.host_arch in ['x86_64', 'ppc64', 'ppc64le', 'mips64', 'arm', 'armhf', 'armv7l', 's390x']
+supported_linux = (not config.android) and config.host_os == 'Linux' and config.host_arch in ['x86_64', 'ppc64', 'ppc64le', 'mips64', 'riscv64', 'arm', 'armhf', 'armv7l', 's390x']
 supported_darwin = config.host_os == 'Darwin' and config.target_arch in ['x86_64']
 supported_netbsd = config.host_os == 'NetBSD' and config.target_arch in ['x86_64', 'i386']
 if not (supported_android or supported_linux or supported_darwin or supported_netbsd):
Index: compiler-rt/test/lsan/TestCases/use_registers.cpp
===
--- compiler-rt/test/lsan/TestCases/use_registers.cpp
+++ compiler-rt/test/lsan/TestCases/use_registers.cpp
@@ -50,6 +50,10 @@
   asm("lgr %%r10, %0"
   :
   : "r"(p));
+#elif defined(__riscv)
+  asm("mv s11, %0"
+  :
+  : "r"(p));
 #else
 #error "Test is not supported on this architecture."
 #endif
Index: compiler-rt/test/asan/lit.cfg.py
===
--- compiler-rt/test/asan/lit.cfg.py
+++ compiler-rt/test/asan/lit.cfg.py
@@ -210,7 +210,7 @@
 
 # Turn on leak detection on 64-bit Linux.
 leak_detection_android = config.android and 'android-thread-properties-api' in config.available_features and (config.target_arch in ['x86_64', 'i386', 'i686', 'aarch64'])
-leak_detection_linux = (config.host_os == 'Linux') and (not config.android) and (config.target_arch in ['x86_64', 'i386'])
+leak_detection_linux = (config.host_os == 'Linux') and (not config.android) and (config.target_arch in ['x86_64', 'i386', 'riscv64'])
 leak_detection_mac = (config.host_os == 'Darwin') and (config.target_arch == 'x86_64')
 leak_detection_netbsd = (config.host_os == 'NetBSD') and (config.target_arch in ['x86_64', 'i386'])
 if leak_detection_android or leak_detection_linux or leak_detection_mac or leak_detection_netbsd:
Index: compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
===
--- compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
+++ compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
@@ -486,7 +486,7 @@
   (!SI_FREEBSD && !SI_MAC && !SI_NETBSD && SI_NOT_RTEMS)
 #define SANITIZER_INTERCEPT___LIBC_MEMALIGN SI_GLIBC
 #define SANITIZER_INTERCEPT_PVALLOC (SI_GLIBC || SI_ANDROID)
-#define SANITIZER_INTERCEPT_CFREE SI_GLIBC
+#define SANITIZER_INTERCEPT_CFREE (SI_GLIBC && !SANITIZER_RISCV64)
 #define SANITIZER_INTERCEPT_REALLOCARRAY SI_POSIX
 #define SANITIZER_INTERCEPT_ALIGNED_ALLOC (!SI_MAC && SI_NOT_RTEMS)
 #define SANITIZER_INTERCEPT_MALLOC_USABLE_SIZE (!SI_MAC && !SI_NETBSD)
Index: compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
===
--- compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
+++ 

[PATCH] D91278: [Clang][CodeGen][RISCV] Fix hard float ABI for struct with empty struct and complex

[Luís Marques via Phabricator via cfe-commits]

luismarques updated this revision to Diff 309991.
luismarques added a comment.

Add float Complex case, for regression test completeness.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91278/new/

https://reviews.llvm.org/D91278

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp


Index: clang/test/CodeGen/riscv32-ilp32d-abi.cpp
===
--- clang/test/CodeGen/riscv32-ilp32d-abi.cpp
+++ clang/test/CodeGen/riscv32-ilp32d-abi.cpp
@@ -32,3 +32,19 @@
 double f_empty_double_float(empty_double_float a) {
 return a.g;
 }
+
+struct empty_complex_f { struct {}; float _Complex fc; };
+
+// CHECK: define float @_Z17f_empty_complex_f15empty_complex_f(float %0, float 
%1)
+// CHECK: { [4 x i8], float, float }
+float f_empty_complex_f(empty_complex_f a) {
+return __imag__ a.fc;
+}
+
+struct empty_complex_d { struct {}; double _Complex fc; };
+
+// CHECK: define double @_Z17f_empty_complex_d15empty_complex_d(double %0, 
double %1)
+// CHECK: { [8 x i8], double, double }
+double f_empty_complex_d(empty_complex_d a) {
+return __imag__ a.fc;
+}
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10469,7 +10469,6 @@
   return false;
 Field1Ty = CGT.ConvertType(EltTy);
 Field1Off = CurOff;
-assert(CurOff.isZero() && "Unexpected offset for first field");
 Field2Ty = Field1Ty;
 Field2Off = Field1Off + getContext().getTypeSizeInChars(EltTy);
 return true;


Index: clang/test/CodeGen/riscv32-ilp32d-abi.cpp
===
--- clang/test/CodeGen/riscv32-ilp32d-abi.cpp
+++ clang/test/CodeGen/riscv32-ilp32d-abi.cpp
@@ -32,3 +32,19 @@
 double f_empty_double_float(empty_double_float a) {
 return a.g;
 }
+
+struct empty_complex_f { struct {}; float _Complex fc; };
+
+// CHECK: define float @_Z17f_empty_complex_f15empty_complex_f(float %0, float %1)
+// CHECK: { [4 x i8], float, float }
+float f_empty_complex_f(empty_complex_f a) {
+return __imag__ a.fc;
+}
+
+struct empty_complex_d { struct {}; double _Complex fc; };
+
+// CHECK: define double @_Z17f_empty_complex_d15empty_complex_d(double %0, double %1)
+// CHECK: { [8 x i8], double, double }
+double f_empty_complex_d(empty_complex_d a) {
+return __imag__ a.fc;
+}
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10469,7 +10469,6 @@
   return false;
 Field1Ty = CGT.ConvertType(EltTy);
 Field1Off = CurOff;
-assert(CurOff.isZero() && "Unexpected offset for first field");
 Field2Ty = Field1Ty;
 Field2Off = Field1Off + getContext().getTypeSizeInChars(EltTy);
 return true;
___
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[PATCH] D91270: [Clang][CodeGen][RISCV] Fix hard float ABI test cases with empty struct

[Luís Marques via Phabricator via cfe-commits]

luismarques updated this revision to Diff 309981.
luismarques added a comment.

Address review feedback.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91270/new/

https://reviews.llvm.org/D91270

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp


Index: clang/test/CodeGen/riscv32-ilp32d-abi.cpp
===
--- clang/test/CodeGen/riscv32-ilp32d-abi.cpp
+++ clang/test/CodeGen/riscv32-ilp32d-abi.cpp
@@ -4,8 +4,7 @@
 struct empty_float2 { struct {}; float f; float g; };
 
 // CHECK: define float @_Z14f_empty_float212empty_float2(float %0, float %1)
-// FIXME: Extraneous padding before the second float
-// CHECK: { [4 x i8], float, [4 x i8], float }
+// CHECK: { [4 x i8], float, float }
 float f_empty_float2(empty_float2 a) {
 return a.g;
 }
@@ -13,8 +12,7 @@
 struct empty_double2 { struct {}; double f; double g; };
 
 // CHECK: define double @_Z15f_empty_double213empty_double2(double %0, double 
%1)
-// FIXME: Extraneous padding before the second double
-// CHECK: { [8 x i8], double, [8 x i8], double }
+// CHECK: { [8 x i8], double, double }
 double f_empty_double2(empty_double2 a) {
 return a.g;
 }
@@ -30,8 +28,7 @@
 struct empty_double_float { struct {}; double f; float g; };
 
 // CHECK: define double @_Z20f_empty_double_float18empty_double_float(double 
%0, float %1)
-// FIXME: Extraneous padding before the float
-// CHECK: { [8 x i8], double, [8 x i8], float }
+// CHECK: { [8 x i8], double, float }
 double f_empty_double_float(empty_double_float a) {
 return a.g;
 }
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10564,7 +10564,7 @@
 NeededArgFPRs++;
   else if (Field2Ty)
 NeededArgGPRs++;
-  return IsCandidate;
+  return true;
 }
 
 // Call getCoerceAndExpand for the two-element flattened struct described by
@@ -10590,15 +10590,15 @@
 
   CharUnits Field2Align =
   CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(Field2Ty));
-  CharUnits Field1Size =
+  CharUnits Field1End = Field1Off +
   CharUnits::fromQuantity(getDataLayout().getTypeStoreSize(Field1Ty));
-  CharUnits Field2OffNoPadNoPack = Field1Size.alignTo(Field2Align);
+  CharUnits Field2OffNoPadNoPack = Field1End.alignTo(Field2Align);
 
   CharUnits Padding = CharUnits::Zero();
   if (Field2Off > Field2OffNoPadNoPack)
 Padding = Field2Off - Field2OffNoPadNoPack;
-  else if (Field2Off != Field2Align && Field2Off > Field1Size)
-Padding = Field2Off - Field1Size;
+  else if (Field2Off != Field2Align && Field2Off > Field1End)
+Padding = Field2Off - Field1End;
 
   bool IsPacked = !Field2Off.isMultipleOf(Field2Align);
 


Index: clang/test/CodeGen/riscv32-ilp32d-abi.cpp
===
--- clang/test/CodeGen/riscv32-ilp32d-abi.cpp
+++ clang/test/CodeGen/riscv32-ilp32d-abi.cpp
@@ -4,8 +4,7 @@
 struct empty_float2 { struct {}; float f; float g; };
 
 // CHECK: define float @_Z14f_empty_float212empty_float2(float %0, float %1)
-// FIXME: Extraneous padding before the second float
-// CHECK: { [4 x i8], float, [4 x i8], float }
+// CHECK: { [4 x i8], float, float }
 float f_empty_float2(empty_float2 a) {
 return a.g;
 }
@@ -13,8 +12,7 @@
 struct empty_double2 { struct {}; double f; double g; };
 
 // CHECK: define double @_Z15f_empty_double213empty_double2(double %0, double %1)
-// FIXME: Extraneous padding before the second double
-// CHECK: { [8 x i8], double, [8 x i8], double }
+// CHECK: { [8 x i8], double, double }
 double f_empty_double2(empty_double2 a) {
 return a.g;
 }
@@ -30,8 +28,7 @@
 struct empty_double_float { struct {}; double f; float g; };
 
 // CHECK: define double @_Z20f_empty_double_float18empty_double_float(double %0, float %1)
-// FIXME: Extraneous padding before the float
-// CHECK: { [8 x i8], double, [8 x i8], float }
+// CHECK: { [8 x i8], double, float }
 double f_empty_double_float(empty_double_float a) {
 return a.g;
 }
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10564,7 +10564,7 @@
 NeededArgFPRs++;
   else if (Field2Ty)
 NeededArgGPRs++;
-  return IsCandidate;
+  return true;
 }
 
 // Call getCoerceAndExpand for the two-element flattened struct described by
@@ -10590,15 +10590,15 @@
 
   CharUnits Field2Align =
   CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(Field2Ty));
-  CharUnits Field1Size =
+  CharUnits Field1End = Field1Off +
   CharUnits::fromQuantity(getDataLayout().getTypeStoreSize(Field1Ty));
-  CharUnits Field2OffNoPadNoPack = Field1Size.alignTo(Field2Align);
+  CharUnits Field2OffNoPadNoPack = Field1End.alignTo(Field2Align);
 
   CharUnits Padding = 

[PATCH] D92403: [LSan][RISCV] Enable LSan for RISCV64

[Luís Marques via Phabricator via cfe-commits]

luismarques updated this revision to Diff 308737.
luismarques added a comment.

Fix formatting.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92403/new/

https://reviews.llvm.org/D92403

Files:
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/fsanitize.c
  compiler-rt/cmake/config-ix.cmake
  compiler-rt/lib/lsan/lsan_allocator.h
  compiler-rt/lib/lsan/lsan_common.h
  compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
  compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
  compiler-rt/test/asan/lit.cfg.py
  compiler-rt/test/lsan/TestCases/use_registers.cpp
  compiler-rt/test/lsan/lit.common.cfg.py
  compiler-rt/test/sanitizer_common/print_address.h

Index: compiler-rt/test/sanitizer_common/print_address.h
===
--- compiler-rt/test/sanitizer_common/print_address.h
+++ compiler-rt/test/sanitizer_common/print_address.h
@@ -8,7 +8,7 @@
   while (n--) {
 void *p = va_arg(ap, void *);
 #if defined(__x86_64__) || defined(__aarch64__) || defined(__powerpc64__) || \
-defined(__s390x__)
+defined(__s390x__) || (defined(__riscv) && (__riscv_xlen == 64))
 // On FreeBSD, the %p conversion specifier works as 0x%x and thus does not
 // match to the format used in the diagnotic message.
 fprintf(stderr, "0x%012lx ", (unsigned long) p);
Index: compiler-rt/test/lsan/lit.common.cfg.py
===
--- compiler-rt/test/lsan/lit.common.cfg.py
+++ compiler-rt/test/lsan/lit.common.cfg.py
@@ -76,7 +76,7 @@
 # LeakSanitizer tests are currently supported on
 # Android{aarch64, x86, x86_64}, x86-64 Linux, PowerPC64 Linux, arm Linux, mips64 Linux, s390x Linux and x86_64 Darwin.
 supported_android = config.android and config.target_arch in ['x86_64', 'i386', 'aarch64'] and 'android-thread-properties-api' in config.available_features
-supported_linux = (not config.android) and config.host_os == 'Linux' and config.host_arch in ['x86_64', 'ppc64', 'ppc64le', 'mips64', 'arm', 'armhf', 'armv7l', 's390x']
+supported_linux = (not config.android) and config.host_os == 'Linux' and config.host_arch in ['x86_64', 'ppc64', 'ppc64le', 'mips64', 'riscv64', 'arm', 'armhf', 'armv7l', 's390x']
 supported_darwin = config.host_os == 'Darwin' and config.target_arch in ['x86_64']
 supported_netbsd = config.host_os == 'NetBSD' and config.target_arch in ['x86_64', 'i386']
 if not (supported_android or supported_linux or supported_darwin or supported_netbsd):
Index: compiler-rt/test/lsan/TestCases/use_registers.cpp
===
--- compiler-rt/test/lsan/TestCases/use_registers.cpp
+++ compiler-rt/test/lsan/TestCases/use_registers.cpp
@@ -50,6 +50,10 @@
   asm("lgr %%r10, %0"
   :
   : "r"(p));
+#elif defined(__riscv)
+  asm("mv s11, %0"
+  :
+  : "r"(p));
 #else
 #error "Test is not supported on this architecture."
 #endif
Index: compiler-rt/test/asan/lit.cfg.py
===
--- compiler-rt/test/asan/lit.cfg.py
+++ compiler-rt/test/asan/lit.cfg.py
@@ -210,7 +210,7 @@
 
 # Turn on leak detection on 64-bit Linux.
 leak_detection_android = config.android and 'android-thread-properties-api' in config.available_features and (config.target_arch in ['x86_64', 'i386', 'i686', 'aarch64'])
-leak_detection_linux = (config.host_os == 'Linux') and (not config.android) and (config.target_arch in ['x86_64', 'i386'])
+leak_detection_linux = (config.host_os == 'Linux') and (not config.android) and (config.target_arch in ['x86_64', 'i386', 'riscv64'])
 leak_detection_mac = (config.host_os == 'Darwin') and (config.target_arch == 'x86_64')
 leak_detection_netbsd = (config.host_os == 'NetBSD') and (config.target_arch in ['x86_64', 'i386'])
 if leak_detection_android or leak_detection_linux or leak_detection_mac or leak_detection_netbsd:
Index: compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
===
--- compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
+++ compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
@@ -492,7 +492,7 @@
!SI_SOLARIS)  // NOLINT
 #define SANITIZER_INTERCEPT_CFREE\
   (!SI_FREEBSD && !SI_MAC && !SI_NETBSD && SI_NOT_FUCHSIA && SI_NOT_RTEMS && \
-   !SI_SOLARIS && !SANITIZER_ANDROID)  // NOLINT
+   !SI_SOLARIS && !SANITIZER_ANDROID && !SANITIZER_RISCV64)  // NOLINT
 #define SANITIZER_INTERCEPT_REALLOCARRAY SI_POSIX
 #define SANITIZER_INTERCEPT_ALIGNED_ALLOC (!SI_MAC && SI_NOT_RTEMS)
 #define SANITIZER_INTERCEPT_MALLOC_USABLE_SIZE (!SI_MAC && !SI_NETBSD)
Index: compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
===
--- compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
+++ 

[PATCH] D92403: [LSan][RISCV] Enable LSan for RISCV64

[Luís Marques via Phabricator via cfe-commits]

luismarques created this revision.
luismarques added reviewers: asb, lenary, vitalybuka, eugenis, EccoTheDolphin.
Herald added subscribers: Sanitizers, cfe-commits, NickHung, evandro, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, PkmX, rogfer01, shiva0217, 
kito-cheng, simoncook, fedor.sergeev, mgorny.
Herald added projects: clang, Sanitizers.
luismarques requested review of this revision.

Fixes the broken RISCV64 implementation of `internal_clone` and adds RISCV64 
support for LSan.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92403

Files:
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/fsanitize.c
  compiler-rt/cmake/config-ix.cmake
  compiler-rt/lib/lsan/lsan_allocator.h
  compiler-rt/lib/lsan/lsan_common.h
  compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
  compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
  compiler-rt/test/asan/lit.cfg.py
  compiler-rt/test/lsan/TestCases/use_registers.cpp
  compiler-rt/test/lsan/lit.common.cfg.py
  compiler-rt/test/sanitizer_common/print_address.h

Index: compiler-rt/test/sanitizer_common/print_address.h
===
--- compiler-rt/test/sanitizer_common/print_address.h
+++ compiler-rt/test/sanitizer_common/print_address.h
@@ -8,7 +8,7 @@
   while (n--) {
 void *p = va_arg(ap, void *);
 #if defined(__x86_64__) || defined(__aarch64__) || defined(__powerpc64__) || \
-defined(__s390x__)
+defined(__s390x__) || (defined(__riscv) && (__riscv_xlen == 64))
 // On FreeBSD, the %p conversion specifier works as 0x%x and thus does not
 // match to the format used in the diagnotic message.
 fprintf(stderr, "0x%012lx ", (unsigned long) p);
Index: compiler-rt/test/lsan/lit.common.cfg.py
===
--- compiler-rt/test/lsan/lit.common.cfg.py
+++ compiler-rt/test/lsan/lit.common.cfg.py
@@ -76,7 +76,7 @@
 # LeakSanitizer tests are currently supported on
 # Android{aarch64, x86, x86_64}, x86-64 Linux, PowerPC64 Linux, arm Linux, mips64 Linux, s390x Linux and x86_64 Darwin.
 supported_android = config.android and config.target_arch in ['x86_64', 'i386', 'aarch64'] and 'android-thread-properties-api' in config.available_features
-supported_linux = (not config.android) and config.host_os == 'Linux' and config.host_arch in ['x86_64', 'ppc64', 'ppc64le', 'mips64', 'arm', 'armhf', 'armv7l', 's390x']
+supported_linux = (not config.android) and config.host_os == 'Linux' and config.host_arch in ['x86_64', 'ppc64', 'ppc64le', 'mips64', 'riscv64', 'arm', 'armhf', 'armv7l', 's390x']
 supported_darwin = config.host_os == 'Darwin' and config.target_arch in ['x86_64']
 supported_netbsd = config.host_os == 'NetBSD' and config.target_arch in ['x86_64', 'i386']
 if not (supported_android or supported_linux or supported_darwin or supported_netbsd):
Index: compiler-rt/test/lsan/TestCases/use_registers.cpp
===
--- compiler-rt/test/lsan/TestCases/use_registers.cpp
+++ compiler-rt/test/lsan/TestCases/use_registers.cpp
@@ -50,6 +50,10 @@
   asm("lgr %%r10, %0"
   :
   : "r"(p));
+#elif defined(__riscv)
+  asm("mv s11, %0"
+  :
+  : "r"(p));
 #else
 #error "Test is not supported on this architecture."
 #endif
Index: compiler-rt/test/asan/lit.cfg.py
===
--- compiler-rt/test/asan/lit.cfg.py
+++ compiler-rt/test/asan/lit.cfg.py
@@ -210,7 +210,7 @@
 
 # Turn on leak detection on 64-bit Linux.
 leak_detection_android = config.android and 'android-thread-properties-api' in config.available_features and (config.target_arch in ['x86_64', 'i386', 'i686', 'aarch64'])
-leak_detection_linux = (config.host_os == 'Linux') and (not config.android) and (config.target_arch in ['x86_64', 'i386'])
+leak_detection_linux = (config.host_os == 'Linux') and (not config.android) and (config.target_arch in ['x86_64', 'i386', 'riscv64'])
 leak_detection_mac = (config.host_os == 'Darwin') and (config.target_arch == 'x86_64')
 leak_detection_netbsd = (config.host_os == 'NetBSD') and (config.target_arch in ['x86_64', 'i386'])
 if leak_detection_android or leak_detection_linux or leak_detection_mac or leak_detection_netbsd:
Index: compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
===
--- compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
+++ compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
@@ -492,7 +492,7 @@
!SI_SOLARIS)  // NOLINT
 #define SANITIZER_INTERCEPT_CFREE\
   (!SI_FREEBSD && !SI_MAC && !SI_NETBSD && SI_NOT_FUCHSIA && SI_NOT_RTEMS && \
-   !SI_SOLARIS && !SANITIZER_ANDROID)  // NOLINT
+   !SI_SOLARIS && !SANITIZER_ANDROID && !SANITIZER_RISCV64)  // NOLINT
 #define SANITIZER_INTERCEPT_REALLOCARRAY SI_POSIX
 #define 

[PATCH] D91784: [RISCV] Set __GCC_HAVE_SYNC_COMPARE_AND_SWAP_x defines

[Luís Marques via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG28de0fb4863a: [RISCV] Set __GCC_HAVE_SYNC_COMPARE_AND_SWAP_x 
defines (authored by luismarques).

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Basic/Targets/RISCV.cpp


Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -115,8 +115,14 @@
 Builder.defineMacro("__riscv_muldiv");
   }
 
-  if (HasA)
+  if (HasA) {
 Builder.defineMacro("__riscv_atomic");
+Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
+Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
+Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
+if (Is64Bit)
+  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
+  }
 
   if (HasF || HasD) {
 Builder.defineMacro("__riscv_flen", HasD ? "64" : "32");


Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -115,8 +115,14 @@
 Builder.defineMacro("__riscv_muldiv");
   }
 
-  if (HasA)
+  if (HasA) {
 Builder.defineMacro("__riscv_atomic");
+Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
+Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
+Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
+if (Is64Bit)
+  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
+  }
 
   if (HasF || HasD) {
 Builder.defineMacro("__riscv_flen", HasD ? "64" : "32");
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[PATCH] D91315: [RISCV] Handle zfh in the arch string.

[Luís Marques via Phabricator via cfe-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D91278: [Clang][CodeGen][RISCV] Fix hard float ABI for struct with empty struct and complex

[Luís Marques via Phabricator via cfe-commits]

luismarques updated this revision to Diff 304554.
luismarques added a comment.

Fix bad test.


Repository:
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Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp


Index: clang/test/CodeGen/riscv32-ilp32d-abi.cpp
===
--- clang/test/CodeGen/riscv32-ilp32d-abi.cpp
+++ clang/test/CodeGen/riscv32-ilp32d-abi.cpp
@@ -32,3 +32,11 @@
 double f_empty_double_float(empty_double_float a) {
 return a.g;
 }
+
+struct empty_complex { struct {}; double _Complex fc; };
+
+// CHECK: define double @_Z15f_empty_complex13empty_complex(double %0, double 
%1)
+// CHECK: { [8 x i8], double, double }
+double f_empty_complex(empty_complex a) {
+return __imag__ a.fc;
+}
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10479,7 +10479,6 @@
   return false;
 Field1Ty = CGT.ConvertType(EltTy);
 Field1Off = CurOff;
-assert(CurOff.isZero() && "Unexpected offset for first field");
 Field2Ty = Field1Ty;
 Field2Off = Field1Off + getContext().getTypeSizeInChars(EltTy);
 return true;


Index: clang/test/CodeGen/riscv32-ilp32d-abi.cpp
===
--- clang/test/CodeGen/riscv32-ilp32d-abi.cpp
+++ clang/test/CodeGen/riscv32-ilp32d-abi.cpp
@@ -32,3 +32,11 @@
 double f_empty_double_float(empty_double_float a) {
 return a.g;
 }
+
+struct empty_complex { struct {}; double _Complex fc; };
+
+// CHECK: define double @_Z15f_empty_complex13empty_complex(double %0, double %1)
+// CHECK: { [8 x i8], double, double }
+double f_empty_complex(empty_complex a) {
+return __imag__ a.fc;
+}
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10479,7 +10479,6 @@
   return false;
 Field1Ty = CGT.ConvertType(EltTy);
 Field1Off = CurOff;
-assert(CurOff.isZero() && "Unexpected offset for first field");
 Field2Ty = Field1Ty;
 Field2Off = Field1Off + getContext().getTypeSizeInChars(EltTy);
 return true;
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[PATCH] D91278: [Clang][CodeGen][RISCV] Fix hard float ABI for struct with empty struct and complex

[Luís Marques via Phabricator via cfe-commits]

luismarques created this revision.
luismarques added reviewers: asb, lenary, rjmccall, efriedma.
Herald added subscribers: cfe-commits, frasercrmck, NickHung, evandro, apazos, 
sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar.
Herald added a project: clang.
luismarques requested review of this revision.

Fixes bug 44904.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91278

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp


Index: clang/test/CodeGen/riscv32-ilp32d-abi.cpp
===
--- clang/test/CodeGen/riscv32-ilp32d-abi.cpp
+++ clang/test/CodeGen/riscv32-ilp32d-abi.cpp
@@ -32,3 +32,11 @@
 double f_empty_double_float(empty_double_float a) {
 return a.g;
 }
+
+struct empty_complex { struct {}; double _Complex fc; };
+
+// CHECK: define double @_Z20f_empty_double_float13empty_complex(double %0, 
double %1)
+// CHECK: { [8 x i8], double, double }
+double f_empty_double_float(empty_complex a) {
+return __imag__ a.fc;
+}
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10479,7 +10479,6 @@
   return false;
 Field1Ty = CGT.ConvertType(EltTy);
 Field1Off = CurOff;
-assert(CurOff.isZero() && "Unexpected offset for first field");
 Field2Ty = Field1Ty;
 Field2Off = Field1Off + getContext().getTypeSizeInChars(EltTy);
 return true;


Index: clang/test/CodeGen/riscv32-ilp32d-abi.cpp
===
--- clang/test/CodeGen/riscv32-ilp32d-abi.cpp
+++ clang/test/CodeGen/riscv32-ilp32d-abi.cpp
@@ -32,3 +32,11 @@
 double f_empty_double_float(empty_double_float a) {
 return a.g;
 }
+
+struct empty_complex { struct {}; double _Complex fc; };
+
+// CHECK: define double @_Z20f_empty_double_float13empty_complex(double %0, double %1)
+// CHECK: { [8 x i8], double, double }
+double f_empty_double_float(empty_complex a) {
+return __imag__ a.fc;
+}
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10479,7 +10479,6 @@
   return false;
 Field1Ty = CGT.ConvertType(EltTy);
 Field1Off = CurOff;
-assert(CurOff.isZero() && "Unexpected offset for first field");
 Field2Ty = Field1Ty;
 Field2Off = Field1Off + getContext().getTypeSizeInChars(EltTy);
 return true;
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[PATCH] D91270: [Clang][CodeGen][RISCV] Fix hard float ABI test cases with empty struct

[Luís Marques via Phabricator via cfe-commits]

luismarques created this revision.
luismarques added reviewers: asb, lenary, rjmccall, efriedma.
Herald added subscribers: cfe-commits, frasercrmck, NickHung, evandro, apazos, 
sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar.
Herald added a project: clang.
luismarques requested review of this revision.

The code seemed not to account for the field 1 offset. This patch hopefully 
fixes that issue.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91270

Files:
  clang/lib/CodeGen/TargetInfo.cpp
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp


Index: clang/test/CodeGen/riscv32-ilp32d-abi.cpp
===
--- clang/test/CodeGen/riscv32-ilp32d-abi.cpp
+++ clang/test/CodeGen/riscv32-ilp32d-abi.cpp
@@ -4,8 +4,7 @@
 struct empty_float2 { struct {}; float f; float g; };
 
 // CHECK: define float @_Z14f_empty_float212empty_float2(float %0, float %1)
-// FIXME: Extraneous padding before the second float
-// CHECK: { [4 x i8], float, [4 x i8], float }
+// CHECK: { [4 x i8], float, float }
 float f_empty_float2(empty_float2 a) {
 return a.g;
 }
@@ -13,8 +12,7 @@
 struct empty_double2 { struct {}; double f; double g; };
 
 // CHECK: define double @_Z15f_empty_double213empty_double2(double %0, double 
%1)
-// FIXME: Extraneous padding before the second double
-// CHECK: { [8 x i8], double, [8 x i8], double }
+// CHECK: { [8 x i8], double, double }
 double f_empty_double2(empty_double2 a) {
 return a.g;
 }
@@ -30,8 +28,7 @@
 struct empty_double_float { struct {}; double f; float g; };
 
 // CHECK: define double @_Z20f_empty_double_float18empty_double_float(double 
%0, float %1)
-// FIXME: Extraneous padding before the float
-// CHECK: { [8 x i8], double, [8 x i8], float }
+// CHECK: { [8 x i8], double, float }
 double f_empty_double_float(empty_double_float a) {
 return a.g;
 }
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10574,7 +10574,7 @@
 NeededArgFPRs++;
   else if (Field2Ty)
 NeededArgGPRs++;
-  return IsCandidate;
+  return true;
 }
 
 // Call getCoerceAndExpand for the two-element flattened struct described by
@@ -10600,15 +10600,16 @@
 
   CharUnits Field2Align =
   CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(Field2Ty));
-  CharUnits Field1Size =
-  CharUnits::fromQuantity(getDataLayout().getTypeStoreSize(Field1Ty));
-  CharUnits Field2OffNoPadNoPack = Field1Size.alignTo(Field2Align);
+  CharUnits Field1EffectiveSize =
+  CharUnits::fromQuantity(getDataLayout().getTypeStoreSize(Field1Ty)) +
+  Field1Off;
+  CharUnits Field2OffNoPadNoPack = Field1EffectiveSize.alignTo(Field2Align);
 
   CharUnits Padding = CharUnits::Zero();
   if (Field2Off > Field2OffNoPadNoPack)
 Padding = Field2Off - Field2OffNoPadNoPack;
-  else if (Field2Off != Field2Align && Field2Off > Field1Size)
-Padding = Field2Off - Field1Size;
+  else if (Field2Off != Field2Align && Field2Off > Field1EffectiveSize)
+Padding = Field2Off - Field1EffectiveSize;
 
   bool IsPacked = !Field2Off.isMultipleOf(Field2Align);
 


Index: clang/test/CodeGen/riscv32-ilp32d-abi.cpp
===
--- clang/test/CodeGen/riscv32-ilp32d-abi.cpp
+++ clang/test/CodeGen/riscv32-ilp32d-abi.cpp
@@ -4,8 +4,7 @@
 struct empty_float2 { struct {}; float f; float g; };
 
 // CHECK: define float @_Z14f_empty_float212empty_float2(float %0, float %1)
-// FIXME: Extraneous padding before the second float
-// CHECK: { [4 x i8], float, [4 x i8], float }
+// CHECK: { [4 x i8], float, float }
 float f_empty_float2(empty_float2 a) {
 return a.g;
 }
@@ -13,8 +12,7 @@
 struct empty_double2 { struct {}; double f; double g; };
 
 // CHECK: define double @_Z15f_empty_double213empty_double2(double %0, double %1)
-// FIXME: Extraneous padding before the second double
-// CHECK: { [8 x i8], double, [8 x i8], double }
+// CHECK: { [8 x i8], double, double }
 double f_empty_double2(empty_double2 a) {
 return a.g;
 }
@@ -30,8 +28,7 @@
 struct empty_double_float { struct {}; double f; float g; };
 
 // CHECK: define double @_Z20f_empty_double_float18empty_double_float(double %0, float %1)
-// FIXME: Extraneous padding before the float
-// CHECK: { [8 x i8], double, [8 x i8], float }
+// CHECK: { [8 x i8], double, float }
 double f_empty_double_float(empty_double_float a) {
 return a.g;
 }
Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10574,7 +10574,7 @@
 NeededArgFPRs++;
   else if (Field2Ty)
 NeededArgGPRs++;
-  return IsCandidate;
+  return true;
 }
 
 

[PATCH] D91269: [Clang][CodeGen][RISCV] Add hard float ABI tests with empty struct

[Luís Marques via Phabricator via cfe-commits]

luismarques created this revision.
luismarques added reviewers: asb, lenary, rjmccall, efriedma.
Herald added subscribers: cfe-commits, frasercrmck, NickHung, evandro, apazos, 
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brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar.
Herald added a project: clang.
luismarques requested review of this revision.

This patch adds tests that showcase a behavior that is currently buggy.
Fix in a follow-up patch.


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Files:
  clang/test/CodeGen/riscv32-ilp32d-abi.cpp


Index: clang/test/CodeGen/riscv32-ilp32d-abi.cpp
===
--- /dev/null
+++ clang/test/CodeGen/riscv32-ilp32d-abi.cpp
@@ -0,0 +1,37 @@
+// RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-abi ilp32d \
+// RUN: -Wno-missing-declarations -emit-llvm %s -o - | FileCheck %s
+
+struct empty_float2 { struct {}; float f; float g; };
+
+// CHECK: define float @_Z14f_empty_float212empty_float2(float %0, float %1)
+// FIXME: Extraneous padding before the second float
+// CHECK: { [4 x i8], float, [4 x i8], float }
+float f_empty_float2(empty_float2 a) {
+return a.g;
+}
+
+struct empty_double2 { struct {}; double f; double g; };
+
+// CHECK: define double @_Z15f_empty_double213empty_double2(double %0, double 
%1)
+// FIXME: Extraneous padding before the second double
+// CHECK: { [8 x i8], double, [8 x i8], double }
+double f_empty_double2(empty_double2 a) {
+return a.g;
+}
+
+struct empty_float_double { struct {}; float f; double g; };
+
+// CHECK: define double @_Z20f_empty_float_double18empty_float_double(float 
%0, double %1)
+// CHECK: { [4 x i8], float, double }
+double f_empty_float_double(empty_float_double a) {
+return a.g;
+}
+
+struct empty_double_float { struct {}; double f; float g; };
+
+// CHECK: define double @_Z20f_empty_double_float18empty_double_float(double 
%0, float %1)
+// FIXME: Extraneous padding before the float
+// CHECK: { [8 x i8], double, [8 x i8], float }
+double f_empty_double_float(empty_double_float a) {
+return a.g;
+}


Index: clang/test/CodeGen/riscv32-ilp32d-abi.cpp
===
--- /dev/null
+++ clang/test/CodeGen/riscv32-ilp32d-abi.cpp
@@ -0,0 +1,37 @@
+// RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-abi ilp32d \
+// RUN: -Wno-missing-declarations -emit-llvm %s -o - | FileCheck %s
+
+struct empty_float2 { struct {}; float f; float g; };
+
+// CHECK: define float @_Z14f_empty_float212empty_float2(float %0, float %1)
+// FIXME: Extraneous padding before the second float
+// CHECK: { [4 x i8], float, [4 x i8], float }
+float f_empty_float2(empty_float2 a) {
+return a.g;
+}
+
+struct empty_double2 { struct {}; double f; double g; };
+
+// CHECK: define double @_Z15f_empty_double213empty_double2(double %0, double %1)
+// FIXME: Extraneous padding before the second double
+// CHECK: { [8 x i8], double, [8 x i8], double }
+double f_empty_double2(empty_double2 a) {
+return a.g;
+}
+
+struct empty_float_double { struct {}; float f; double g; };
+
+// CHECK: define double @_Z20f_empty_float_double18empty_float_double(float %0, double %1)
+// CHECK: { [4 x i8], float, double }
+double f_empty_float_double(empty_float_double a) {
+return a.g;
+}
+
+struct empty_double_float { struct {}; double f; float g; };
+
+// CHECK: define double @_Z20f_empty_double_float18empty_double_float(double %0, float %1)
+// FIXME: Extraneous padding before the float
+// CHECK: { [8 x i8], double, [8 x i8], float }
+double f_empty_double_float(empty_double_float a) {
+return a.g;
+}
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[PATCH] D89025: [RISCV] Add -mtune support

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

In D89025#2324334 , @khchen wrote:

> RISCV supports `-mcpu` with default empty arch to align gcc's `-mtune` 
> behavior since clang didn't support `-mtune` before. But now clang has 
> `-mtune`, is it a good idea to remove those options? (ex. `rocket-rv32/rv64`, 
> `sifive-7-rv32/64`)

If possible that would good, since -mcpu is deprecated (for e.g. x86_64) or 
unsupported in GCC (for e.g. RISC-V). So doing that would further align Clang 
with GCC. But I wonder if this might be too problematic, in terms of 
compatibility.


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[PATCH] D89025: [RISCV] Add -mtune support

[Luís Marques via Phabricator via cfe-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM, but I would like other people to also review this, if possible.
(Just be sure to check/fix the clang-format warnings and the inline comments).




Comment at: clang/test/Driver/riscv-cpus.c:29
+
+// Check mtune alias CPU has resolve to the right CPU according XLEN.
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck 
-check-prefix=MTUNE-GENERIC-32 %s

Nit: resolve -> resolved.



Comment at: clang/test/Driver/riscv-cpus.c:82
+// Check interaction between mcpu and mtune.
+//
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 
-mtune=sifive-e76 | FileCheck -check-prefix=MTUNE-E31-MCPU-E76 %s

khchen wrote:
> maybe we can describe what is expected interaction behavior somewhere.
+1



Comment at: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp:201
   const RISCVTargetMachine  = static_cast(TM);
-  const RISCVSubtarget STI(TT, CPU, FS, /*ABIName=*/"", RTM);
+  /* TuneCPU don't impact emission for ELF attributes, ELF attribute only
+ care about arch related features, so we can set TuneCPU as CPU.  */

Nit: don't -> doesn't; for -> of; attribute -> attributes.


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[PATCH] D79770: [RISCV] Fix passing two floating-point values in complex separately by two GPRs on RV64

[Luís Marques via Phabricator via cfe-commits]

luismarques added inline comments.



Comment at: clang/lib/CodeGen/TargetInfo.cpp:10241-10242
   // Pass floating point values via FPRs if possible.
-  if (IsFixed && Ty->isFloatingType() && FLen >= Size && ArgFPRsLeft) {
+  if (IsFixed && Ty->isFloatingType() && !Ty->isComplexType() &&
+  FLen >= Size && ArgFPRsLeft) {
 ArgFPRsLeft--;

Do you have tests that show the impact of the added `FLen >= Size && 
ArgFPRsLeft` conditions for other values besides complex floats?


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[PATCH] D75061: [RISCV] Fix sysroot tests without GCC on RISC-V hosts with GCC

[Luís Marques via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG91f7f0d8e3ef: [RISCV] Fix sysroot tests without GCC on 
RISC-V hosts with GCC (authored by luismarques).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75061/new/

https://reviews.llvm.org/D75061

Files:
  clang/test/Driver/riscv32-toolchain-extra.c
  clang/test/Driver/riscv64-toolchain-extra.c


Index: clang/test/Driver/riscv64-toolchain-extra.c
===
--- clang/test/Driver/riscv64-toolchain-extra.c
+++ clang/test/Driver/riscv64-toolchain-extra.c
@@ -19,6 +19,7 @@
 // RUN: ln -s %S/Inputs/basic_riscv64_nogcc_tree/bin/riscv64-unknown-elf-ld 
%T/testroot-riscv64-baremetal-nogcc/bin/riscv64-unknown-elf-ld
 // RUN: ln -s %S/Inputs/basic_riscv64_nogcc_tree/riscv64-unknown-elf 
%T/testroot-riscv64-baremetal-nogcc/riscv64-unknown-elf
 // RUN: %T/testroot-riscv64-baremetal-nogcc/bin/clang %s -### 
-no-canonical-prefixes \
+// RUN:--gcc-toolchain=%T/testroot-riscv64-baremetal-nogcc/invalid \
 // RUN:-target riscv64-unknown-elf --rtlib=platform 2>&1 \
 // RUN:| FileCheck -check-prefix=C-RV64-BAREMETAL-LP64-NOGCC %s
 
Index: clang/test/Driver/riscv32-toolchain-extra.c
===
--- clang/test/Driver/riscv32-toolchain-extra.c
+++ clang/test/Driver/riscv32-toolchain-extra.c
@@ -19,6 +19,7 @@
 // RUN: ln -s %S/Inputs/basic_riscv32_nogcc_tree/bin/riscv32-unknown-elf-ld 
%T/testroot-riscv32-baremetal-nogcc/bin/riscv32-unknown-elf-ld
 // RUN: ln -s %S/Inputs/basic_riscv32_nogcc_tree/riscv32-unknown-elf 
%T/testroot-riscv32-baremetal-nogcc/riscv32-unknown-elf
 // RUN: %T/testroot-riscv32-baremetal-nogcc/bin/clang %s -### 
-no-canonical-prefixes \
+// RUN:--gcc-toolchain=%T/testroot-riscv32-baremetal-nogcc/invalid \
 // RUN:-target riscv32-unknown-elf --rtlib=platform 2>&1 \
 // RUN:| FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32-NOGCC %s
 


Index: clang/test/Driver/riscv64-toolchain-extra.c
===
--- clang/test/Driver/riscv64-toolchain-extra.c
+++ clang/test/Driver/riscv64-toolchain-extra.c
@@ -19,6 +19,7 @@
 // RUN: ln -s %S/Inputs/basic_riscv64_nogcc_tree/bin/riscv64-unknown-elf-ld %T/testroot-riscv64-baremetal-nogcc/bin/riscv64-unknown-elf-ld
 // RUN: ln -s %S/Inputs/basic_riscv64_nogcc_tree/riscv64-unknown-elf %T/testroot-riscv64-baremetal-nogcc/riscv64-unknown-elf
 // RUN: %T/testroot-riscv64-baremetal-nogcc/bin/clang %s -### -no-canonical-prefixes \
+// RUN:--gcc-toolchain=%T/testroot-riscv64-baremetal-nogcc/invalid \
 // RUN:-target riscv64-unknown-elf --rtlib=platform 2>&1 \
 // RUN:| FileCheck -check-prefix=C-RV64-BAREMETAL-LP64-NOGCC %s
 
Index: clang/test/Driver/riscv32-toolchain-extra.c
===
--- clang/test/Driver/riscv32-toolchain-extra.c
+++ clang/test/Driver/riscv32-toolchain-extra.c
@@ -19,6 +19,7 @@
 // RUN: ln -s %S/Inputs/basic_riscv32_nogcc_tree/bin/riscv32-unknown-elf-ld %T/testroot-riscv32-baremetal-nogcc/bin/riscv32-unknown-elf-ld
 // RUN: ln -s %S/Inputs/basic_riscv32_nogcc_tree/riscv32-unknown-elf %T/testroot-riscv32-baremetal-nogcc/riscv32-unknown-elf
 // RUN: %T/testroot-riscv32-baremetal-nogcc/bin/clang %s -### -no-canonical-prefixes \
+// RUN:--gcc-toolchain=%T/testroot-riscv32-baremetal-nogcc/invalid \
 // RUN:-target riscv32-unknown-elf --rtlib=platform 2>&1 \
 // RUN:| FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32-NOGCC %s
 
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[PATCH] D75061: [RISCV] Fix sysroot tests without GCC on RISC-V hosts with GCC

[Luís Marques via Phabricator via cfe-commits]

luismarques created this revision.
luismarques added reviewers: edward-jones, lenary.
Herald added subscribers: cfe-commits, evandro, apazos, sameer.abuasal, pzheng, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, 
MartinMosbeck, rogfer01, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, 
sabuasal, simoncook, johnrusso, rbar, asb.
Herald added a project: clang.

D68391  added tests that check scenarios where 
no RISC-V GCC toolchain is supposed to be detected. When running the tests on 
RISC-V hosts the system's GCC toolchain will be detected, and the tests will 
fail. This patch adds a `--gcc-toolchain` option pointing to a path where no 
GCC toolchain is present, ensuring that the tests are run under the expected 
conditions, and therefore are able to pass in all test environments.

(I had also explored the option of checking if the found GCC toolchain actually 
matched the exact requested triple, but there seems to be no good way of doing 
that, and the test would still fail if such an exact match happened to be found 
anyway).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75061

Files:
  clang/test/Driver/riscv32-toolchain-extra.c
  clang/test/Driver/riscv64-toolchain-extra.c


Index: clang/test/Driver/riscv64-toolchain-extra.c
===
--- clang/test/Driver/riscv64-toolchain-extra.c
+++ clang/test/Driver/riscv64-toolchain-extra.c
@@ -19,6 +19,7 @@
 // RUN: ln -s %S/Inputs/basic_riscv64_nogcc_tree/bin/riscv64-unknown-elf-ld 
%T/testroot-riscv64-baremetal-nogcc/bin/riscv64-unknown-elf-ld
 // RUN: ln -s %S/Inputs/basic_riscv64_nogcc_tree/riscv64-unknown-elf 
%T/testroot-riscv64-baremetal-nogcc/riscv64-unknown-elf
 // RUN: %T/testroot-riscv64-baremetal-nogcc/bin/clang %s -### 
-no-canonical-prefixes \
+// RUN:--gcc-toolchain=%T/testroot-riscv64-baremetal-nogcc/invalid \
 // RUN:-target riscv64-unknown-elf --rtlib=platform 2>&1 \
 // RUN:| FileCheck -check-prefix=C-RV64-BAREMETAL-LP64-NOGCC %s
 
Index: clang/test/Driver/riscv32-toolchain-extra.c
===
--- clang/test/Driver/riscv32-toolchain-extra.c
+++ clang/test/Driver/riscv32-toolchain-extra.c
@@ -19,6 +19,7 @@
 // RUN: ln -s %S/Inputs/basic_riscv32_nogcc_tree/bin/riscv32-unknown-elf-ld 
%T/testroot-riscv32-baremetal-nogcc/bin/riscv32-unknown-elf-ld
 // RUN: ln -s %S/Inputs/basic_riscv32_nogcc_tree/riscv32-unknown-elf 
%T/testroot-riscv32-baremetal-nogcc/riscv32-unknown-elf
 // RUN: %T/testroot-riscv32-baremetal-nogcc/bin/clang %s -### 
-no-canonical-prefixes \
+// RUN:--gcc-toolchain=%T/testroot-riscv32-baremetal-nogcc/invalid \
 // RUN:-target riscv32-unknown-elf --rtlib=platform 2>&1 \
 // RUN:| FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32-NOGCC %s
 


Index: clang/test/Driver/riscv64-toolchain-extra.c
===
--- clang/test/Driver/riscv64-toolchain-extra.c
+++ clang/test/Driver/riscv64-toolchain-extra.c
@@ -19,6 +19,7 @@
 // RUN: ln -s %S/Inputs/basic_riscv64_nogcc_tree/bin/riscv64-unknown-elf-ld %T/testroot-riscv64-baremetal-nogcc/bin/riscv64-unknown-elf-ld
 // RUN: ln -s %S/Inputs/basic_riscv64_nogcc_tree/riscv64-unknown-elf %T/testroot-riscv64-baremetal-nogcc/riscv64-unknown-elf
 // RUN: %T/testroot-riscv64-baremetal-nogcc/bin/clang %s -### -no-canonical-prefixes \
+// RUN:--gcc-toolchain=%T/testroot-riscv64-baremetal-nogcc/invalid \
 // RUN:-target riscv64-unknown-elf --rtlib=platform 2>&1 \
 // RUN:| FileCheck -check-prefix=C-RV64-BAREMETAL-LP64-NOGCC %s
 
Index: clang/test/Driver/riscv32-toolchain-extra.c
===
--- clang/test/Driver/riscv32-toolchain-extra.c
+++ clang/test/Driver/riscv32-toolchain-extra.c
@@ -19,6 +19,7 @@
 // RUN: ln -s %S/Inputs/basic_riscv32_nogcc_tree/bin/riscv32-unknown-elf-ld %T/testroot-riscv32-baremetal-nogcc/bin/riscv32-unknown-elf-ld
 // RUN: ln -s %S/Inputs/basic_riscv32_nogcc_tree/riscv32-unknown-elf %T/testroot-riscv32-baremetal-nogcc/riscv32-unknown-elf
 // RUN: %T/testroot-riscv32-baremetal-nogcc/bin/clang %s -### -no-canonical-prefixes \
+// RUN:--gcc-toolchain=%T/testroot-riscv32-baremetal-nogcc/invalid \
 // RUN:-target riscv32-unknown-elf --rtlib=platform 2>&1 \
 // RUN:| FileCheck -check-prefix=C-RV32-BAREMETAL-ILP32-NOGCC %s
 
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[PATCH] D74847: [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V

[Luís Marques via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG0781e93a6eaa: [CodeGen][RISCV] Fix 
clang/test/CodeGen/atomic_ops.c for RISC-V (authored by luismarques).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74847/new/

https://reviews.llvm.org/D74847

Files:
  clang/test/CodeGen/atomic_ops.c


Index: clang/test/CodeGen/atomic_ops.c
===
--- clang/test/CodeGen/atomic_ops.c
+++ clang/test/CodeGen/atomic_ops.c
@@ -1,7 +1,7 @@
-// XFAIL: hexagon,sparc
-//(due to not having native load atomic support)
-// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -triple mips-linux-gnu -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64 -emit-llvm %s \
+// RUN:   -o - | FileCheck -check-prefixes=CHECK,NATIVE %s
+// RUN: %clang_cc1 -triple riscv32 -target-feature -a -emit-llvm %s \
+// RUN:   -o - | FileCheck -check-prefixes=CHECK,LIBCALL %s
 
 void foo(int x)
 {
@@ -9,32 +9,47 @@
   _Atomic(short) j = 0;
   // Check that multiply / divides on atomics produce a cmpxchg loop
   i *= 2;
-  // CHECK: mul nsw i32
-  // CHECK: {{(cmpxchg i32*|i1 @__atomic_compare_exchange\(i32 4,)}}
+  // NATIVE: mul nsw i32
+  // NATIVE: cmpxchg i32*
+  // LIBCALL: mul nsw i32
+  // LIBCALL: i1 @__atomic_compare_exchange(i32 4,
   i /= 2;
-  // CHECK: sdiv i32
-  // CHECK: {{(cmpxchg i32*|i1 @__atomic_compare_exchange\(i32 4, )}}
+  // NATIVE: sdiv i32
+  // NATIVE: cmpxchg i32*
+  // LIBCALL: sdiv i32
+  // LIBCALL: i1 @__atomic_compare_exchange(i32 4,
   j /= x;
-  // CHECK: sdiv i32
-  // CHECK: {{(cmpxchg i16*|i1 @__atomic_compare_exchange\(i32 2, )}}
+  // NATIVE: sdiv i32
+  // NATIVE: cmpxchg i16*
+  // LIBCALL: sdiv i32
+  // LIBCALL: i1 @__atomic_compare_exchange(i32 2,
 
 }
 
 extern _Atomic _Bool b;
 
 _Bool bar() {
-// CHECK-LABEL: @bar
-// CHECK: %[[load:.*]] = load atomic i8, i8* @b seq_cst
-// CHECK: %[[tobool:.*]] = trunc i8 %[[load]] to i1
-// CHECK: ret i1 %[[tobool]]
+// NATIVE-LABEL: @bar
+// NATIVE: %[[load:.*]] = load atomic i8, i8* @b seq_cst
+// NATIVE: %[[tobool:.*]] = trunc i8 %[[load]] to i1
+// NATIVE: ret i1 %[[tobool]]
+// LIBCALL-LABEL: @bar
+// LIBCALL: call void @__atomic_load(i32 1, i8* @b, i8* %atomic-temp, i32 5)
+// LIBCALL: %[[load:.*]] = load i8, i8* %atomic-temp
+// LIBCALL: %[[tobool:.*]] = trunc i8 %[[load]] to i1
+// LIBCALL: ret i1 %[[tobool]]
+
   return b;
 }
 
 extern _Atomic(_Complex int) x;
 
 void baz(int y) {
-// CHECK-LABEL: @baz
-// CHECK: {{store atomic|call void @__atomic_store}}
+// NATIVE-LABEL: @baz
+// NATIVE: store atomic
+// LIBCALL-LABEL: @baz
+// LIBCALL: call void @__atomic_store
+
   x += y;
 }
 
@@ -84,9 +99,11 @@
 }
 
 _Atomic(int) compound_mul(_Atomic(int) in) {
-// CHECK-LABEL: @compound_mul
-// CHECK: cmpxchg i32* {{%.*}}, i32 {{%.*}}, i32 [[NEW:%.*]] seq_cst seq_cst
-// CHECK: ret i32 [[NEW]]
+// NATIVE-LABEL: @compound_mul
+// NATIVE: cmpxchg i32* {{%.*}}, i32 {{%.*}}, i32 [[NEW:%.*]] seq_cst seq_cst
+// NATIVE: ret i32 [[NEW]]
+// LIBCALL-LABEL: @compound_mul
+// LIBCALL: i1 @__atomic_compare_exchange(i32 4,
 
   return (in *= 5);
 }


Index: clang/test/CodeGen/atomic_ops.c
===
--- clang/test/CodeGen/atomic_ops.c
+++ clang/test/CodeGen/atomic_ops.c
@@ -1,7 +1,7 @@
-// XFAIL: hexagon,sparc
-//(due to not having native load atomic support)
-// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -triple mips-linux-gnu -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64 -emit-llvm %s \
+// RUN:   -o - | FileCheck -check-prefixes=CHECK,NATIVE %s
+// RUN: %clang_cc1 -triple riscv32 -target-feature -a -emit-llvm %s \
+// RUN:   -o - | FileCheck -check-prefixes=CHECK,LIBCALL %s
 
 void foo(int x)
 {
@@ -9,32 +9,47 @@
   _Atomic(short) j = 0;
   // Check that multiply / divides on atomics produce a cmpxchg loop
   i *= 2;
-  // CHECK: mul nsw i32
-  // CHECK: {{(cmpxchg i32*|i1 @__atomic_compare_exchange\(i32 4,)}}
+  // NATIVE: mul nsw i32
+  // NATIVE: cmpxchg i32*
+  // LIBCALL: mul nsw i32
+  // LIBCALL: i1 @__atomic_compare_exchange(i32 4,
   i /= 2;
-  // CHECK: sdiv i32
-  // CHECK: {{(cmpxchg i32*|i1 @__atomic_compare_exchange\(i32 4, )}}
+  // NATIVE: sdiv i32
+  // NATIVE: cmpxchg i32*
+  // LIBCALL: sdiv i32
+  // LIBCALL: i1 @__atomic_compare_exchange(i32 4,
   j /= x;
-  // CHECK: sdiv i32
-  // CHECK: {{(cmpxchg i16*|i1 @__atomic_compare_exchange\(i32 2, )}}
+  // NATIVE: sdiv i32
+  // NATIVE: cmpxchg i16*
+  // LIBCALL: sdiv i32
+  // LIBCALL: i1 @__atomic_compare_exchange(i32 2,
 
 }
 
 extern _Atomic _Bool b;
 
 _Bool bar() {
-// CHECK-LABEL: @bar
-// CHECK: %[[load:.*]] = load atomic i8, i8* @b seq_cst
-// CHECK: %[[tobool:.*]] = trunc i8 %[[load]] to i1
-// CHECK: ret i1 %[[tobool]]
+// NATIVE-LABEL: @bar
+// NATIVE: %[[load:.*]] = load atomic i8, i8* @b seq_cst

[PATCH] D74847: [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V

[Luís Marques via Phabricator via cfe-commits]

luismarques updated this revision to Diff 245881.
luismarques edited the summary of this revision.
luismarques added a comment.
Herald added a subscriber: fedor.sergeev.

As suggested by @efriedma, the patch was reworked to have one target with 
native atomics, and one without. No RUN run with a default target remains.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74847/new/

https://reviews.llvm.org/D74847

Files:
  clang/test/CodeGen/atomic_ops.c


Index: clang/test/CodeGen/atomic_ops.c
===
--- clang/test/CodeGen/atomic_ops.c
+++ clang/test/CodeGen/atomic_ops.c
@@ -1,7 +1,7 @@
-// XFAIL: hexagon,sparc
-//(due to not having native load atomic support)
-// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -triple mips-linux-gnu -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64 -emit-llvm %s \
+// RUN:   -o - | FileCheck -check-prefixes=CHECK,NATIVE %s
+// RUN: %clang_cc1 -triple riscv32 -target-feature -a -emit-llvm %s \
+// RUN:   -o - | FileCheck -check-prefixes=CHECK,LIBCALL %s
 
 void foo(int x)
 {
@@ -9,32 +9,47 @@
   _Atomic(short) j = 0;
   // Check that multiply / divides on atomics produce a cmpxchg loop
   i *= 2;
-  // CHECK: mul nsw i32
-  // CHECK: {{(cmpxchg i32*|i1 @__atomic_compare_exchange\(i32 4,)}}
+  // NATIVE: mul nsw i32
+  // NATIVE: cmpxchg i32*
+  // LIBCALL: mul nsw i32
+  // LIBCALL: i1 @__atomic_compare_exchange(i32 4,
   i /= 2;
-  // CHECK: sdiv i32
-  // CHECK: {{(cmpxchg i32*|i1 @__atomic_compare_exchange\(i32 4, )}}
+  // NATIVE: sdiv i32
+  // NATIVE: cmpxchg i32*
+  // LIBCALL: sdiv i32
+  // LIBCALL: i1 @__atomic_compare_exchange(i32 4,
   j /= x;
-  // CHECK: sdiv i32
-  // CHECK: {{(cmpxchg i16*|i1 @__atomic_compare_exchange\(i32 2, )}}
+  // NATIVE: sdiv i32
+  // NATIVE: cmpxchg i16*
+  // LIBCALL: sdiv i32
+  // LIBCALL: i1 @__atomic_compare_exchange(i32 2,
 
 }
 
 extern _Atomic _Bool b;
 
 _Bool bar() {
-// CHECK-LABEL: @bar
-// CHECK: %[[load:.*]] = load atomic i8, i8* @b seq_cst
-// CHECK: %[[tobool:.*]] = trunc i8 %[[load]] to i1
-// CHECK: ret i1 %[[tobool]]
+// NATIVE-LABEL: @bar
+// NATIVE: %[[load:.*]] = load atomic i8, i8* @b seq_cst
+// NATIVE: %[[tobool:.*]] = trunc i8 %[[load]] to i1
+// NATIVE: ret i1 %[[tobool]]
+// LIBCALL-LABEL: @bar
+// LIBCALL: call void @__atomic_load(i32 1, i8* @b, i8* %atomic-temp, i32 5)
+// LIBCALL: %[[load:.*]] = load i8, i8* %atomic-temp
+// LIBCALL: %[[tobool:.*]] = trunc i8 %[[load]] to i1
+// LIBCALL: ret i1 %[[tobool]]
+
   return b;
 }
 
 extern _Atomic(_Complex int) x;
 
 void baz(int y) {
-// CHECK-LABEL: @baz
-// CHECK: {{store atomic|call void @__atomic_store}}
+// NATIVE-LABEL: @baz
+// NATIVE: store atomic
+// LIBCALL-LABEL: @baz
+// LIBCALL: call void @__atomic_store
+
   x += y;
 }
 
@@ -84,9 +99,11 @@
 }
 
 _Atomic(int) compound_mul(_Atomic(int) in) {
-// CHECK-LABEL: @compound_mul
-// CHECK: cmpxchg i32* {{%.*}}, i32 {{%.*}}, i32 [[NEW:%.*]] seq_cst seq_cst
-// CHECK: ret i32 [[NEW]]
+// NATIVE-LABEL: @compound_mul
+// NATIVE: cmpxchg i32* {{%.*}}, i32 {{%.*}}, i32 [[NEW:%.*]] seq_cst seq_cst
+// NATIVE: ret i32 [[NEW]]
+// LIBCALL-LABEL: @compound_mul
+// LIBCALL: i1 @__atomic_compare_exchange(i32 4,
 
   return (in *= 5);
 }


Index: clang/test/CodeGen/atomic_ops.c
===
--- clang/test/CodeGen/atomic_ops.c
+++ clang/test/CodeGen/atomic_ops.c
@@ -1,7 +1,7 @@
-// XFAIL: hexagon,sparc
-//(due to not having native load atomic support)
-// RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -triple mips-linux-gnu -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64 -emit-llvm %s \
+// RUN:   -o - | FileCheck -check-prefixes=CHECK,NATIVE %s
+// RUN: %clang_cc1 -triple riscv32 -target-feature -a -emit-llvm %s \
+// RUN:   -o - | FileCheck -check-prefixes=CHECK,LIBCALL %s
 
 void foo(int x)
 {
@@ -9,32 +9,47 @@
   _Atomic(short) j = 0;
   // Check that multiply / divides on atomics produce a cmpxchg loop
   i *= 2;
-  // CHECK: mul nsw i32
-  // CHECK: {{(cmpxchg i32*|i1 @__atomic_compare_exchange\(i32 4,)}}
+  // NATIVE: mul nsw i32
+  // NATIVE: cmpxchg i32*
+  // LIBCALL: mul nsw i32
+  // LIBCALL: i1 @__atomic_compare_exchange(i32 4,
   i /= 2;
-  // CHECK: sdiv i32
-  // CHECK: {{(cmpxchg i32*|i1 @__atomic_compare_exchange\(i32 4, )}}
+  // NATIVE: sdiv i32
+  // NATIVE: cmpxchg i32*
+  // LIBCALL: sdiv i32
+  // LIBCALL: i1 @__atomic_compare_exchange(i32 4,
   j /= x;
-  // CHECK: sdiv i32
-  // CHECK: {{(cmpxchg i16*|i1 @__atomic_compare_exchange\(i32 2, )}}
+  // NATIVE: sdiv i32
+  // NATIVE: cmpxchg i16*
+  // LIBCALL: sdiv i32
+  // LIBCALL: i1 @__atomic_compare_exchange(i32 2,
 
 }
 
 extern _Atomic _Bool b;
 
 _Bool bar() {
-// CHECK-LABEL: @bar
-// CHECK: %[[load:.*]] = load atomic i8, i8* @b seq_cst
-// CHECK: %[[tobool:.*]] = trunc i8 

[PATCH] D74847: [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

In D74847#1883028 , @efriedma wrote:

> I'm not really a big fan of running tests with the host target triple, 
> anyway; it seems to create work with almost no benefit.  I'd be happy to just 
> run the test with one target that has native atomics, and one target that 
> doesn't.  (The relevant code is all target-independent, aside from the atomic 
> widths, so we aren't really gaining anything by testing more targets.)


That sounds fine to me. I might need to rewrite the tests with two different 
prefixes though (e.g. `NATIVE-` vs `LIBCALL-`), since I can't see how to mix 
substitution blocks with regex alternatives. For instance, we have this:

  // CHECK: %[[load:.*]] = {{load atomic i8, i8\* @b seq_cst|}}

You need to add an alternative for an `__atomic_load` libcall instead of the 
`load atomic`, but then the "assignment" to `%atomic-temp` moves to the right, 
as an out argument, so you'd need the variable capture to move to inside the 
regex, which I don't think is supported.
Is that OK, using different prefixes? Arguably that's a better test anyway, 
since you can then check your expectation that certain targets triples match 
certain alternative matches.


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[PATCH] D74847: [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V

[Luís Marques via Phabricator via cfe-commits]

luismarques created this revision.
luismarques added reviewers: jyknight, eli.friedman, lenary.
Herald added subscribers: cfe-commits, evandro, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, PkmX, jfb, rkruppe, rogfer01, shiva0217, kito-cheng, simoncook.
Herald added a project: clang.

By default the RISC-V target doesn't have the atomics standard extension 
enabled. The first RUN line in `clang/test/CodeGen/atomic_ops.c` doesn't 
specify a target triple, which means that on RISC-V Linux hosts it will target 
RISC-V, but because we use clang cc1 we don't get the toolchain driver 
functionality to automatically turn on the extensions implied by the target 
triple (riscv64-linux includes atomics). This causes the test to fail on RISC-V 
hosts.

I waffled a bit regarding the best way to fix this. In the end I decided to 1) 
use XFAIL to blacklist RISC-V hosts and 2) add explicitly run lines for 
riscv32/64, with the atomics extension enabled. With that choice we 
//effectively// don't do the test on RISC-V hosts, but still get to test those 
two RISC-V targets on other hosts.

An alternative approach would be to eliminate the first RUN line and explicitly 
list all of the target triples we want to test. But looking at the other clang 
tests, there doesn't seem to be any test that comprehensively lists all of the 
targets, and it wasn't quite clear which should be listed on this test. Running 
clang with the non-cc1 interface would also be an option, but in principle that 
could still fail in some hypothetical scenarios, and the tests seem to prefer 
to use cc1.

(It's a shame that XFAIL necessarily means blacklisting host triples, and not 
target triples. That doesn't interact very well with cross-compilers.)


Repository:
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https://reviews.llvm.org/D74847

Files:
  clang/test/CodeGen/atomic_ops.c


Index: clang/test/CodeGen/atomic_ops.c
===
--- clang/test/CodeGen/atomic_ops.c
+++ clang/test/CodeGen/atomic_ops.c
@@ -1,7 +1,13 @@
 // XFAIL: hexagon,sparc
 //(due to not having native load atomic support)
+// XFAIL: riscv
+//(due to requiring an explicit -target-feature +a)
 // RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s
 // RUN: %clang_cc1 -triple mips-linux-gnu -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +a -emit-llvm %s \
+// RUN:   -o - | FileCheck %s
+// RUN: %clang_cc1 -triple riscv32 -target-feature +a -emit-llvm %s \
+// RUN:   -o - | FileCheck %s
 
 void foo(int x)
 {


Index: clang/test/CodeGen/atomic_ops.c
===
--- clang/test/CodeGen/atomic_ops.c
+++ clang/test/CodeGen/atomic_ops.c
@@ -1,7 +1,13 @@
 // XFAIL: hexagon,sparc
 //(due to not having native load atomic support)
+// XFAIL: riscv
+//(due to requiring an explicit -target-feature +a)
 // RUN: %clang_cc1 -emit-llvm %s -o - | FileCheck %s
 // RUN: %clang_cc1 -triple mips-linux-gnu -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +a -emit-llvm %s \
+// RUN:   -o - | FileCheck %s
+// RUN: %clang_cc1 -triple riscv32 -target-feature +a -emit-llvm %s \
+// RUN:   -o - | FileCheck %s
 
 void foo(int x)
 {
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[PATCH] D69869: [clang-tools-extra] fix the check for if '-latomic' is necessary

[Luís Marques via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1d40c4150630: [clang-tools-extra] fix the check for if 
-latomic is necessary (authored by gokturk, committed by 
luismarques).

Repository:
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Files:
  clang-tools-extra/clangd/CMakeLists.txt


Index: clang-tools-extra/clangd/CMakeLists.txt
===
--- clang-tools-extra/clangd/CMakeLists.txt
+++ clang-tools-extra/clangd/CMakeLists.txt
@@ -30,7 +30,7 @@
 endif()
 
 set(CLANGD_ATOMIC_LIB "")
-if(NOT HAVE_CXX_ATOMICS64_WITHOUT_LIB)
+if(NOT HAVE_CXX_ATOMICS_WITHOUT_LIB OR NOT HAVE_CXX_ATOMICS64_WITHOUT_LIB)
   list(APPEND CLANGD_ATOMIC_LIB "atomic")
 endif()
 


Index: clang-tools-extra/clangd/CMakeLists.txt
===
--- clang-tools-extra/clangd/CMakeLists.txt
+++ clang-tools-extra/clangd/CMakeLists.txt
@@ -30,7 +30,7 @@
 endif()
 
 set(CLANGD_ATOMIC_LIB "")
-if(NOT HAVE_CXX_ATOMICS64_WITHOUT_LIB)
+if(NOT HAVE_CXX_ATOMICS_WITHOUT_LIB OR NOT HAVE_CXX_ATOMICS64_WITHOUT_LIB)
   list(APPEND CLANGD_ATOMIC_LIB "atomic")
 endif()
 
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[PATCH] D69869: [clang-tools-extra] fix the check for if '-latomic' is necessary

[Luís Marques via Phabricator via cfe-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

Whether or not GCC behaves the way it should behave regarding atomics, this 
seems like a sensible patch to make things work given the current situation.
LGTM.


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[PATCH] D74399: [Driver][RISCV] Add RedHat Linux RISC-V triple

[Luís Marques via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG9816e726e747: [Driver][RISCV] Add RedHat Linux RISC-V triple 
(authored by luismarques).
Herald added a subscriber: jrtc27.

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  
clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib/gcc/riscv64-redhat-linux/9/crtbegin.o
  
clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib/gcc/riscv64-redhat-linux/9/crtend.o
  
clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib/gcc/riscv64-redhat-linux/9/crti.o
  
clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib/gcc/riscv64-redhat-linux/9/crtn.o
  clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib64/crt1.o
  clang/test/Driver/linux-ld.c


Index: clang/test/Driver/linux-ld.c
===
--- clang/test/Driver/linux-ld.c
+++ clang/test/Driver/linux-ld.c
@@ -769,6 +769,21 @@
 // CHECK-FEDORA-21-AARCH64: 
"{{.*}}/usr/lib/gcc/aarch64-redhat-linux/4.9.0{{/|}}crtend.o"
 // CHECK-FEDORA-21-AARCH64: 
"{{.*}}/usr/lib/gcc/aarch64-redhat-linux/4.9.0/../../../../lib64{{/|}}crtn.o"
 //
+// Check Fedora 31 on riscv64.
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=riscv64-redhat-linux -rtlib=platform \
+// RUN: --gcc-toolchain="" \
+// RUN: --sysroot=%S/Inputs/fedora_31_riscv64_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-FEDORA-31-RISCV64 %s
+// CHECK-FEDORA-31-RISCV64: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64{{/|}}crt1.o"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crti.o"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtbegin.o"
+// CHECK-FEDORA-31-RISCV64: "-L[[SYSROOT]]/usr/lib/gcc/riscv64-redhat-linux/9"
+// CHECK-FEDORA-31-RISCV64: 
"-L[[SYSROOT]]/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtend.o"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtn.o"
+//
 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
 // RUN: --target=arm-unknown-linux-gnueabi -rtlib=platform \
 // RUN: --gcc-toolchain="" \
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2090,6 +2090,7 @@
   static const char *const RISCV64Triples[] = {"riscv64-unknown-linux-gnu",
"riscv64-linux-gnu",
"riscv64-unknown-elf",
+   "riscv64-redhat-linux",
"riscv64-suse-linux"};
 
   static const char *const SPARCv8LibDirs[] = {"/lib32", "/lib"};


Index: clang/test/Driver/linux-ld.c
===
--- clang/test/Driver/linux-ld.c
+++ clang/test/Driver/linux-ld.c
@@ -769,6 +769,21 @@
 // CHECK-FEDORA-21-AARCH64: "{{.*}}/usr/lib/gcc/aarch64-redhat-linux/4.9.0{{/|}}crtend.o"
 // CHECK-FEDORA-21-AARCH64: "{{.*}}/usr/lib/gcc/aarch64-redhat-linux/4.9.0/../../../../lib64{{/|}}crtn.o"
 //
+// Check Fedora 31 on riscv64.
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=riscv64-redhat-linux -rtlib=platform \
+// RUN: --gcc-toolchain="" \
+// RUN: --sysroot=%S/Inputs/fedora_31_riscv64_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-FEDORA-31-RISCV64 %s
+// CHECK-FEDORA-31-RISCV64: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64{{/|}}crt1.o"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crti.o"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtbegin.o"
+// CHECK-FEDORA-31-RISCV64: "-L[[SYSROOT]]/usr/lib/gcc/riscv64-redhat-linux/9"
+// CHECK-FEDORA-31-RISCV64: "-L[[SYSROOT]]/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtend.o"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtn.o"
+//
 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
 // RUN: --target=arm-unknown-linux-gnueabi -rtlib=platform \
 // RUN: --gcc-toolchain="" \
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2090,6 +2090,7 @@
   static const char *const 

[PATCH] D74399: [Driver][RISCV] Add RedHat Linux RISC-V triple

[Luís Marques via Phabricator via cfe-commits]

luismarques updated this revision to Diff 244211.
luismarques added a comment.

Correct paths.


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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  
clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib/gcc/riscv64-redhat-linux/9/crtbegin.o
  
clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib/gcc/riscv64-redhat-linux/9/crtend.o
  
clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib/gcc/riscv64-redhat-linux/9/crti.o
  
clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib/gcc/riscv64-redhat-linux/9/crtn.o
  clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib64/crt1.o
  clang/test/Driver/linux-ld.c


Index: clang/test/Driver/linux-ld.c
===
--- clang/test/Driver/linux-ld.c
+++ clang/test/Driver/linux-ld.c
@@ -769,6 +769,21 @@
 // CHECK-FEDORA-21-AARCH64: 
"{{.*}}/usr/lib/gcc/aarch64-redhat-linux/4.9.0{{/|}}crtend.o"
 // CHECK-FEDORA-21-AARCH64: 
"{{.*}}/usr/lib/gcc/aarch64-redhat-linux/4.9.0/../../../../lib64{{/|}}crtn.o"
 //
+// Check Fedora 31 on riscv64.
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=riscv64-redhat-linux -rtlib=platform \
+// RUN: --gcc-toolchain="" \
+// RUN: --sysroot=%S/Inputs/fedora_31_riscv64_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-FEDORA-31-RISCV64 %s
+// CHECK-FEDORA-31-RISCV64: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64{{/|}}crt1.o"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crti.o"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtbegin.o"
+// CHECK-FEDORA-31-RISCV64: "-L[[SYSROOT]]/usr/lib/gcc/riscv64-redhat-linux/9"
+// CHECK-FEDORA-31-RISCV64: 
"-L[[SYSROOT]]/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtend.o"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtn.o"
+//
 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
 // RUN: --target=arm-unknown-linux-gnueabi -rtlib=platform \
 // RUN: --gcc-toolchain="" \
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2090,6 +2090,7 @@
   static const char *const RISCV64Triples[] = {"riscv64-unknown-linux-gnu",
"riscv64-linux-gnu",
"riscv64-unknown-elf",
+   "riscv64-redhat-linux",
"riscv64-suse-linux"};
 
   static const char *const SPARCv8LibDirs[] = {"/lib32", "/lib"};


Index: clang/test/Driver/linux-ld.c
===
--- clang/test/Driver/linux-ld.c
+++ clang/test/Driver/linux-ld.c
@@ -769,6 +769,21 @@
 // CHECK-FEDORA-21-AARCH64: "{{.*}}/usr/lib/gcc/aarch64-redhat-linux/4.9.0{{/|}}crtend.o"
 // CHECK-FEDORA-21-AARCH64: "{{.*}}/usr/lib/gcc/aarch64-redhat-linux/4.9.0/../../../../lib64{{/|}}crtn.o"
 //
+// Check Fedora 31 on riscv64.
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=riscv64-redhat-linux -rtlib=platform \
+// RUN: --gcc-toolchain="" \
+// RUN: --sysroot=%S/Inputs/fedora_31_riscv64_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-FEDORA-31-RISCV64 %s
+// CHECK-FEDORA-31-RISCV64: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64{{/|}}crt1.o"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crti.o"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtbegin.o"
+// CHECK-FEDORA-31-RISCV64: "-L[[SYSROOT]]/usr/lib/gcc/riscv64-redhat-linux/9"
+// CHECK-FEDORA-31-RISCV64: "-L[[SYSROOT]]/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtend.o"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtn.o"
+//
 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
 // RUN: --target=arm-unknown-linux-gnueabi -rtlib=platform \
 // RUN: --gcc-toolchain="" \
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2090,6 +2090,7 @@
   static const char *const RISCV64Triples[] = {"riscv64-unknown-linux-gnu",
"riscv64-linux-gnu",

[PATCH] D74399: [Driver][RISCV] Add RedHat Linux RISC-V triple

[Luís Marques via Phabricator via cfe-commits]

luismarques updated this revision to Diff 244187.
luismarques added a comment.
Herald added subscribers: apazos, pzheng, jocewei, the_o, brucehoult, 
MartinMosbeck, edward-jones, zzheng, niosHD, sabuasal, johnrusso, rbar.

Adds a test (using the RISC-V Fedora 31 paths).


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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  
clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib/gcc/riscv64-redhat-linux/9/crtbegin.o
  
clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib/gcc/riscv64-redhat-linux/9/crtend.o
  clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib64/crt1.o
  clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib64/crti.o
  clang/test/Driver/Inputs/fedora_31_riscv64_tree/usr/lib64/crtn.o
  clang/test/Driver/linux-ld.c


Index: clang/test/Driver/linux-ld.c
===
--- clang/test/Driver/linux-ld.c
+++ clang/test/Driver/linux-ld.c
@@ -769,6 +769,21 @@
 // CHECK-FEDORA-21-AARCH64: 
"{{.*}}/usr/lib/gcc/aarch64-redhat-linux/4.9.0{{/|}}crtend.o"
 // CHECK-FEDORA-21-AARCH64: 
"{{.*}}/usr/lib/gcc/aarch64-redhat-linux/4.9.0/../../../../lib64{{/|}}crtn.o"
 //
+// Check Fedora 31 on riscv64.
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=riscv64-redhat-linux -rtlib=platform \
+// RUN: --gcc-toolchain="" \
+// RUN: --sysroot=%S/Inputs/fedora_31_riscv64_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-FEDORA-31-RISCV64 %s
+// CHECK-FEDORA-31-RISCV64: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64{{/|}}crt1.o"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64{{/|}}crti.o"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtbegin.o"
+// CHECK-FEDORA-31-RISCV64: "-L[[SYSROOT]]/usr/lib/gcc/riscv64-redhat-linux/9"
+// CHECK-FEDORA-31-RISCV64: 
"-L[[SYSROOT]]/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtend.o"
+// CHECK-FEDORA-31-RISCV64: 
"{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64{{/|}}crtn.o"
+//
 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
 // RUN: --target=arm-unknown-linux-gnueabi -rtlib=platform \
 // RUN: --gcc-toolchain="" \
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2090,6 +2090,7 @@
   static const char *const RISCV64Triples[] = {"riscv64-unknown-linux-gnu",
"riscv64-linux-gnu",
"riscv64-unknown-elf",
+   "riscv64-redhat-linux",
"riscv64-suse-linux"};
 
   static const char *const SPARCv8LibDirs[] = {"/lib32", "/lib"};


Index: clang/test/Driver/linux-ld.c
===
--- clang/test/Driver/linux-ld.c
+++ clang/test/Driver/linux-ld.c
@@ -769,6 +769,21 @@
 // CHECK-FEDORA-21-AARCH64: "{{.*}}/usr/lib/gcc/aarch64-redhat-linux/4.9.0{{/|}}crtend.o"
 // CHECK-FEDORA-21-AARCH64: "{{.*}}/usr/lib/gcc/aarch64-redhat-linux/4.9.0/../../../../lib64{{/|}}crtn.o"
 //
+// Check Fedora 31 on riscv64.
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=riscv64-redhat-linux -rtlib=platform \
+// RUN: --gcc-toolchain="" \
+// RUN: --sysroot=%S/Inputs/fedora_31_riscv64_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-FEDORA-31-RISCV64 %s
+// CHECK-FEDORA-31-RISCV64: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64{{/|}}crt1.o"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64{{/|}}crti.o"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtbegin.o"
+// CHECK-FEDORA-31-RISCV64: "-L[[SYSROOT]]/usr/lib/gcc/riscv64-redhat-linux/9"
+// CHECK-FEDORA-31-RISCV64: "-L[[SYSROOT]]/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9{{/|}}crtend.o"
+// CHECK-FEDORA-31-RISCV64: "{{.*}}/usr/lib/gcc/riscv64-redhat-linux/9/../../../../lib64{{/|}}crtn.o"
+//
 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
 // RUN: --target=arm-unknown-linux-gnueabi -rtlib=platform \
 // RUN: --gcc-toolchain="" \
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2090,6 +2090,7 @@
   

[PATCH] D74399: [Driver][RISCV] Add RedHat Linux RISC-V triple

[Luís Marques via Phabricator via cfe-commits]

luismarques created this revision.
luismarques added reviewers: lenary, asb, dlj.
Herald added subscribers: cfe-commits, evandro, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, PkmX, rkruppe, rogfer01, shiva0217, kito-cheng, simoncook.
Herald added a project: clang.

Adds the RedHat Linux triple to the list of 64-bit RISC-V triples. Without this 
the gcc libraries wouldn't be found by clang on a redhat/fedora system, as the 
search list included `/usr/lib/gcc/riscv64-redhat-linux-gnu` but the correct 
path didn't include the `-gnu` suffix.


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Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2090,6 +2090,7 @@
   static const char *const RISCV64Triples[] = {"riscv64-unknown-linux-gnu",
"riscv64-linux-gnu",
"riscv64-unknown-elf",
+   "riscv64-redhat-linux",
"riscv64-suse-linux"};
 
   static const char *const SPARCv8LibDirs[] = {"/lib32", "/lib"};


Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2090,6 +2090,7 @@
   static const char *const RISCV64Triples[] = {"riscv64-unknown-linux-gnu",
"riscv64-linux-gnu",
"riscv64-unknown-elf",
+   "riscv64-redhat-linux",
"riscv64-suse-linux"};
 
   static const char *const SPARCv8LibDirs[] = {"/lib32", "/lib"};
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[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

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luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

[Luís Marques via Phabricator via cfe-commits]

luismarques added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVCallingConv.td:36
+// The only physical register that isn't saved is x2 (SP), which is used by the
+// processor when the interrupt happens.
+

Nitpick: "the interrupt happens" -> "an interrupt happens" (or, even better, 
"is serviced").



Comment at: llvm/test/CodeGen/RISCV/calling-conv-ilp32e-double-bug.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -target-abi ilp32e -mattr=+f -verify-machineinstrs 
< %s

It would be good to describe in a comment what the bug is.


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[PATCH] D69383: [RISCV] Match GCC `-march`/`-mabi` driver defaults

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luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

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luismarques added a comment.

@simoncook: your commit doesn't include handling the case of TLS lowering when 
`-ffixed-x4` is used.


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[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

[Luís Marques via Phabricator via cfe-commits]

luismarques requested changes to this revision.
luismarques added inline comments.
This revision now requires changes to proceed.



Comment at: libunwind/include/__libunwind_config.h:26
 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 63
 

The highest dwarf register number is 64, the Alternate Frame Return Column. See 
https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#dwarf-register-numbers-


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[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

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Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:97
   RISCVABI::ABI getTargetABI() const { return TargetABI; }
+  bool isRegisterReservedByUser(size_t i) const {
+return UserReservedRegister[i];

This should take a `Register` argument instead.


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[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

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Comment at: libunwind/src/Registers.hpp:3545
+  void  setSP(uint64_t value) { _registers[2] = value; }
+  uint64_t  getIP() const { return _registers[1]; }
+  void  setIP(uint64_t value) { _registers[1] = value; }

`x1` is the return address. Is this the the `IP` to which we unwind to? How do 
we get the original `ra` value at that unwind point?
I vaguely recall seeing this IP/x1 pattern in another unwind library, so it's 
probably correct, but it would be good to confirm and document such details.



Comment at: libunwind/src/Registers.hpp:3756
+inline double Registers_riscv::getFloatRegister(int regNum) const {
+#ifdef __riscv_float_abi_double
+  assert(validFloatRegister(regNum));

luismarques wrote:
> lenary wrote:
> > mhorne wrote:
> > > lenary wrote:
> > > > Is this an ABI or an architecture issue? I'm not sure what other 
> > > > libunwind "backends" do for similar cases.
> > > > 
> > > > The difference is, if I compile libunwind with `-march=rv64g 
> > > > -mabi=lp64`, `__riscv_float_abi_double` is not defined (because you're 
> > > > using a soft-float ABI), but `__riscv_flen == 64` (because the machine 
> > > > does have hardware floating-point registers).
> > > > 
> > > > I'm not sure what the intended behaviour of libunwind is in this case.
> > > > 
> > > > `__riscv_float_abi_double` implies `__riscv_flen >= 64`.
> > > An ABI issue, in my opinion. The unwind frame will always contain space 
> > > for the float registers, but accessing them should be disallowed for 
> > > soft-float configurations as the intent of soft-float is that the FPRs 
> > > will not be used at all. I'd say there is precedent for this in the MIPS 
> > > implementation, since it checks for `defined(__mips_hard_float) && 
> > > __mips_fpr == 64`.
> > I had a discussion with @asb about this. The ISA vs ABI issue in RISC-V is 
> > complex. The TL;DR is we both think you need to be using `__riscv_flen == 
> > 64` here.
> > 
> > The reason for this is that if you compile with `-march=rv64imfd` but 
> > `-mabi=lp64`, the architecture still has floating point registers, it just 
> > does not use the floating-point calling convention. This means there are 
> > still `D`-extension instructions in the stream of instructions, just that 
> > "No floating-point registers, if present, are preserved across calls." (see 
> > [[ 
> > https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#integer-calling-convention
> >  | psABI Integer Calling Convention ]]) This effectively means that with 
> > this combination, `f0-f31` are treated exactly the same as `t0-t6`, and so 
> > should be able to be restored when unwinding. It is not necessarily the 
> > case that with a soft float ABI, `f0-f31` are not used at all. This is 
> > similar to ARM's `soft` vs `softfp` calling conventions.
> > 
> > The expectation is that if you are compiling your programs with a specific 
> > `-march`, then you should be compiling your runtime libraries with the same 
> > `-march`. Eventually there should be enough details in the ELF file to 
> > allow you to ensure both `-march` and `-mabi` match when linking programs, 
> > but support for this is not widespread.
> A soft-float *ABI* doesn't mean that FPRs aren't used at all, it means that 
> floating-point arguments aren't passed in the floating-point registers. From 
> a quick Google search I got the impression that `__mips_hard_float` was used 
> for a mips softfloat target (i.e. without hardware floating-point support, 
> not for a soft-float ABI), so that's probably not a comparable example.
I just saw @lenary's reply. I agree with his more detailed analysis.


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[PATCH] D68362: [libunwind][RISCV] Add 64-bit RISC-V support

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luismarques added inline comments.



Comment at: libunwind/src/Registers.hpp:3756
+inline double Registers_riscv::getFloatRegister(int regNum) const {
+#ifdef __riscv_float_abi_double
+  assert(validFloatRegister(regNum));

lenary wrote:
> mhorne wrote:
> > lenary wrote:
> > > Is this an ABI or an architecture issue? I'm not sure what other 
> > > libunwind "backends" do for similar cases.
> > > 
> > > The difference is, if I compile libunwind with `-march=rv64g -mabi=lp64`, 
> > > `__riscv_float_abi_double` is not defined (because you're using a 
> > > soft-float ABI), but `__riscv_flen == 64` (because the machine does have 
> > > hardware floating-point registers).
> > > 
> > > I'm not sure what the intended behaviour of libunwind is in this case.
> > > 
> > > `__riscv_float_abi_double` implies `__riscv_flen >= 64`.
> > An ABI issue, in my opinion. The unwind frame will always contain space for 
> > the float registers, but accessing them should be disallowed for soft-float 
> > configurations as the intent of soft-float is that the FPRs will not be 
> > used at all. I'd say there is precedent for this in the MIPS 
> > implementation, since it checks for `defined(__mips_hard_float) && 
> > __mips_fpr == 64`.
> I had a discussion with @asb about this. The ISA vs ABI issue in RISC-V is 
> complex. The TL;DR is we both think you need to be using `__riscv_flen == 64` 
> here.
> 
> The reason for this is that if you compile with `-march=rv64imfd` but 
> `-mabi=lp64`, the architecture still has floating point registers, it just 
> does not use the floating-point calling convention. This means there are 
> still `D`-extension instructions in the stream of instructions, just that "No 
> floating-point registers, if present, are preserved across calls." (see [[ 
> https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#integer-calling-convention
>  | psABI Integer Calling Convention ]]) This effectively means that with this 
> combination, `f0-f31` are treated exactly the same as `t0-t6`, and so should 
> be able to be restored when unwinding. It is not necessarily the case that 
> with a soft float ABI, `f0-f31` are not used at all. This is similar to ARM's 
> `soft` vs `softfp` calling conventions.
> 
> The expectation is that if you are compiling your programs with a specific 
> `-march`, then you should be compiling your runtime libraries with the same 
> `-march`. Eventually there should be enough details in the ELF file to allow 
> you to ensure both `-march` and `-mabi` match when linking programs, but 
> support for this is not widespread.
A soft-float *ABI* doesn't mean that FPRs aren't used at all, it means that 
floating-point arguments aren't passed in the floating-point registers. From a 
quick Google search I got the impression that `__mips_hard_float` was used for 
a mips softfloat target (i.e. without hardware floating-point support, not for 
a soft-float ABI), so that's probably not a comparable example.


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[PATCH] D68391: [RISCV] Improve sysroot computation if no GCC install detected

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

This is indeed an issue that would be nice to fix, I've often been annoyed by 
clang just defaulting to the root when some misconfiguration occurs. I have to 
wonder though, this patch only changes the clang RISC-V toolchain driver, but 
the problem isn't specific to RISC-V. Couldn't this tweak be generalized and 
made to apply to multiple/all target drivers?


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[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

The priority for this patch is to address the issues reported by @apazos but 
after that please check the clang-format output. There are some cases in this 
patch where it might make sense to use a different formatting than clang-format 
indicates, but the remaining should be addressed.

@apazos Have you considered tweaking the patch code to not do a tail call, just 
to check if that's what's causing the remaining failures? I'm not sure if 
that's too hard, but it could eventually be easier than drilling into the 
failing cases.




Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:27
+// registers.
+static int getLibCallID(const MachineFunction ,
+const std::vector ) {

The return value isn't used as just an opaque index, it also reflects the frame 
size and is used for that purpose. The function comment should probably reflect 
that.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:34
+
+  unsigned MaxReg = 0;
+  for (auto  : CSI)

Use `Register` and `RISCV::NoRegister`. (You'll have to use `MaxReg.id()` 
instead in the call to `max`).



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:36
+  for (auto  : CSI)
+if (CS.getFrameIdx() < 0)
+  MaxReg = std::max(MaxReg, CS.getReg());

Might be worth adding a small comment explaining how this serves as a filters 
for the registers we are interested in. Or point to a later relevant comment?



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:39
+
+  if (MaxReg == 0)
+return -1;

Ditto `NoRegister`.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:66
+const std::vector ) {
+  static const char *const spillLibCalls[] = {
+"__riscv_save_0",

Check LLVM naming convention capitalization. Ditto other vars here.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:93
+  const std::vector ) {
+  static const char *const restoreLibCalls[] = {
+"__riscv_restore_0",

Check LLVM naming convention capitalization. Ditto other vars here.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:190
 
+static std::vector
+getNonLibcallCSI(const std::vector ) {

This could probably use `SmallVector`.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:706
+  for (auto  : reverse(NonLibcallCSI)) {
+unsigned Reg = CS.getReg();
+const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);

Ditto `Register`.



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:95
+// by save/restore libcalls.
+static const std::map FixedCSRFIMap = {
+  {/*ra*/  RISCV::X1,   -1},

Use `IndexedMap` instead?



Comment at: llvm/test/CodeGen/RISCV/saverestore.ll:348
+
+; Check that functions with varargs do not use save/restore code
+

Maybe for these tests just put a -NOT check that __riscv_save_ isn't called?


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[PATCH] D67185: [RISCV] Add support for -ffixed-xX flags

[Luís Marques via Phabricator via cfe-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

Overall LGTM. Caveats:

- Address the issues in the inline comments;
- Shouldn't the TLS lowering also complain when `-ffixed-x4` is used?
- Is there a way to ensure we don't forget to check any such reserved reg uses? 
I'm not quite confident we haven't overlooked anything.
- (Remember to check for the `-ffixed-xX` flags when implementing the 
callee-saved regs via libcalls (D62686 ), etc.)

Apologies for the delayed review.




Comment at: clang/include/clang/Driver/Options.td:2224
   HelpText<"Don't workaround Cortex-A53 erratum 835769 (AArch64 only)">;
-foreach i = {1-7,9-15,18,20-28} in
-  def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group,
-HelpText<"Reserve the "#i#" register (AArch64 only)">;
+foreach i = {1-31} in
+  def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group,

Given the expansion of the flags here, the AArch64 driver should probably 
detect and reject the flags `-ffixed-x[8,16-17,19,29-31]`, to preserve the old 
behavior where passing those flags  would be an error and to ensure that 
erroneous flags are not silently accepted.



Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2412
+  }))
+F.getContext().diagnose(DiagnosticInfoUnsupported{F, "Argument register"
+  " required, but has been reserved."});

clang-format indicates another formatting style here.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:53
 : RISCVGenSubtargetInfo(TT, CPU, FS),
+  UserReservedRegister(RISCV::NUM_TARGET_REGS),
   FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),

This includes more than the x0 - x31 registers. If the intent is to only allow 
reserving the GPRs then this should be tightened.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:98
+  bool isRegisterReservedByUser(size_t i) const {
+return UserReservedRegister[i];
+  }

Consider adding a bounds checking assert.


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[PATCH] D66591: [RISCV] Correct Logic around ilp32e macros

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luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D66003: [RISCV] Make -march=rv{32, 64}gc the default in RISC-V Linux

[Luís Marques via Phabricator via cfe-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux

[Luís Marques via Phabricator via cfe-commits]

luismarques added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:386
+  else
+return Triple.getArch() == llvm::Triple::riscv32 ? "ilp32" : "lp64";
 }

luismarques wrote:
> When I compile a bare metal GNU toolchain (using 
> , reports GCC 8.3.0) I seem to 
> get lp64d by default. Should we not match that behaviour?
> 
> ```
> 
> $ cat test.c
> float foo() { return 42.0; }
> $ riscv64-unknown-elf-gcc -O2 -S test.c
> $ cat test.s
> (...)
> foo:
> lui a5,%hi(.LC0)
> flw fa0,%lo(.LC0)(a5)
> (...)
> ```
To clarify, that's a toolchain configured with `--enable-multilib`.


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[PATCH] D65634: [RISCV] Default to ilp32d/lp64d in RISC-V Linux

[Luís Marques via Phabricator via cfe-commits]

luismarques added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:386
+  else
+return Triple.getArch() == llvm::Triple::riscv32 ? "ilp32" : "lp64";
 }

When I compile a bare metal GNU toolchain (using 
, reports GCC 8.3.0) I seem to 
get lp64d by default. Should we not match that behaviour?

```

$ cat test.c
float foo() { return 42.0; }
$ riscv64-unknown-elf-gcc -O2 -S test.c
$ cat test.s
(...)
foo:
lui a5,%hi(.LC0)
flw fa0,%lo(.LC0)(a5)
(...)
```


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[PATCH] D66002: [RISCV] Move architecture parsing code into its own function

[Luís Marques via Phabricator via cfe-commits]

luismarques added a comment.

LGTM.


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