Re: [coreboot] OpenBMC & KGPE-D16

[taii...@gmx.com]

On 02/22/2018 04:36 PM, Timothy Pearson wrote:


Actually, for OpenBMC work, hotplugging is often the only way to go.
Just be very careful to align the pins correctly the first time; you
don't have a second chance if you misalign the pins and fry the module...
I stand corrected, but I am nervous about doing this myself - is it 
possible to use a tester clip?


Have you found a source for ASMB4 or ASMB5 modules? Many people I know 
who bought their boards on ebay didn't get one and the D8 unfortunately 
doesn't come with them either. I am going to contact ASUS and see if 
they have a stash.


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Re: [coreboot] [SeaBIOS] Mysterious "is VARVERIFY32INIT but used from" problem while trying to improve SeaBIOS

[Kevin O'Connor]

On Sun, Feb 25, 2018 at 08:51:56PM +0300, Mike Banon wrote:
> >
> >  Please see the developer documentation:
> >
> 
> I am afraid this documentation does not answer why this build problem
> does not happen when I apply this patch to the standalone cloned seabios
> while it does happens when I apply it to the seabios built by a coreboot

The default seabios configuration is to build for qemu and not
coreboot.  So, by default it would not include that code and would not
raise a compile time error.  If you configured seabios to build for
coreboot and it didn't raise a compile time error then that seems like
a build defect.

-Kevin

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Re: [coreboot] Atom c3000 Harcuvar and Intel ME

[Szafranski, MariuszX]

Hi,

In case of Harcuvar CRB we have 16M SPI flash: first 8M for ME (which is 
outside of CBFS) and last 8M for coreboot.
We need to specify two things in coreboot config:

-  ROM chip size – 16M – physical size of SPI flash (needed for correct 
flash offset calculations inside coreboot code)

-  Size of CBFS filesystem in ROM – 8M (0x80) or less
16M coreboot.rom file should be built with above config.
You need to manually inject 8M ME blob at offset 0 into ‘coreboot.rom’ file.
Or just flash last 8M from coreboot.rom into last 8M of SPI flash if ME blob is 
already there.

Mariusz

From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Sumo
Sent: Monday, February 26, 2018 9:15 PM
To: coreboot@coreboot.org
Subject: [coreboot] Atom c3000 Harcuvar and Intel ME

Hi,

In the coreboot build menu there is no option regarding the Intel ME 
integration.
The 'coreboot.rom' file is the full SPI flash image or this file is suitable to
replace the BIOS region of the SPI flash (0x0080--0x00ff)?
(i.e. in the SPI flash we already have a region for Intel ME firmware)

Thanks,
Sumo
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Re: [coreboot] Atom c3000 Harcuvar and Intel ME

[Julien Viard de Galbert]

> Le 27 févr. 2018 à 13:42, Sumo  a écrit :
> 
> > When configuring CB with menuconfig you have to select your platform
> > and type in the path to your ME-binary-blob.
> 
> For the Harcuvar CRB there is no such configuration.
> 
> This conf. is available to other mainboards (e.g. Intel "Little Plains" 
> mainboard:
> menu "Chipset"->"Intel Firmware"->"Add Intel descriptor.bin file"->"Add Intel
> ME/TXE firmware"->"Path to management engine firmware").
> 
> Maybe for the Harcuvar CRB the Intel ME FW is installed in the second
> SPI flash, therefore there is no need to add the ME blob in the coreboot
> build? I´m not sure about this, some board maintainer can confirm
> this?
No it’s in the same flash. Basically your first idea is what I am doing:
> replace the BIOS region of the SPI flash (0x0080–0x00ff)
Or use intel fitc tool to build the final SPI image.

> 
> Do we have any documentation regarding the coreboot port for Harcuvar?
Do you have access to intel support ? If yes there should be a document, but
I’m not even sure it has been updated when the support was upstreamed.

Hope this helps,

Julien VdG

> 
> Thanks,
> Sumo
> 
> 2018-02-26 19:42 GMT-03:00 Philipp Stanner  >:
> Am Montag, den 26.02.2018, 17:14 -0300 schrieb Sumo:
> > Hi,
> >
> > In the coreboot build menu there is no option regarding the Intel ME
> > integration.
> > The 'coreboot.rom' file is the full SPI flash image or this file is
> > suitable to
> > replace the BIOS region of the SPI flash (0x0080--0x00ff)?
> > (i.e. in the SPI flash we already have a region for Intel ME
> > firmware)
> 
> I'm not sure what the question is. 
> 
> When configuring CB with menuconfig you have to select your platform
> and type in the path to your ME-binary-blob. The later has to be
> provided by you; meaning you have to extract the BIOS from the flash,
> extract the ME-binary using coreboot/utils, clean it with ME-cleaner
> (optional) and then build coreboot with your blob.
> 
> The toolchain takes care automatically about the correct placement of
> the ME in the right address-ranges.
> 
> I hope this was helpful.
> 
> > Thanks,
> > Sumo
> 
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Re: [coreboot] Atom c3000 Harcuvar and Intel ME

[Sumo]

 > When configuring CB with menuconfig you have to select your platform
> and type in the path to your ME-binary-blob.

For the Harcuvar CRB there is no such configuration.

This conf. is available to other mainboards (e.g. Intel "Little Plains"
mainboard:
menu "Chipset"->"Intel Firmware"->"Add Intel descriptor.bin file"->"Add
Intel
ME/TXE firmware"->"Path to management engine firmware").

Maybe for the Harcuvar CRB the Intel ME FW is installed in the second
SPI flash, therefore there is no need to add the ME blob in the coreboot
build? I´m not sure about this, some board maintainer can confirm
this?

Do we have any documentation regarding the coreboot port for Harcuvar?

Thanks,
Sumo

2018-02-26 19:42 GMT-03:00 Philipp Stanner :

> Am Montag, den 26.02.2018, 17:14 -0300 schrieb Sumo:
> > Hi,
> >
> > In the coreboot build menu there is no option regarding the Intel ME
> > integration.
> > The 'coreboot.rom' file is the full SPI flash image or this file is
> > suitable to
> > replace the BIOS region of the SPI flash (0x0080--0x00ff)?
> > (i.e. in the SPI flash we already have a region for Intel ME
> > firmware)
>
> I'm not sure what the question is.
>
> When configuring CB with menuconfig you have to select your platform
> and type in the path to your ME-binary-blob. The later has to be
> provided by you; meaning you have to extract the BIOS from the flash,
> extract the ME-binary using coreboot/utils, clean it with ME-cleaner
> (optional) and then build coreboot with your blob.
>
> The toolchain takes care automatically about the correct placement of
> the ME in the right address-ranges.
>
> I hope this was helpful.
>
> > Thanks,
> > Sumo
>
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