[edk2-devel] [edk2-platforms][PATCH V2 2/2] Platform/Sgi: Extend SMBIOS support for RD-V2 platform
The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB
of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level
cache. Extend the SMBIOS support for RD-V2 platform with this
configuration.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c| 5
-
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 7
+--
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 18
++
3 files changed, 27 insertions(+), 3 deletions(-)
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index b7e2238fb39c..fe3c88672d7e 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -33,7 +33,8 @@
"RdV1Mc\0"\
"RdN2\0" \
"RdN2Cfg1\0" \
- "RdN2Cfg2\0"
+ "RdN2Cfg2\0" \
+ "RdV2\0"
typedef enum {
ManufacturerName = 1,
@@ -71,6 +72,8 @@ STATIC GUID mSmbiosUid[] = {
{0xa4941d3d, 0xfac3, 0x4ace, {0x9a, 0x7e, 0xce, 0x26, 0x76, 0x64, 0x5e,
0xda}},
/* Rd-N2-Cfg2*/
{0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1,
0x60}},
+ /* Rd-V2 */
+ {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43,
0x45}},
};
/* System information */
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index b59172cf1cb9..0f403e41a3c7 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -27,7 +27,7 @@
#define SOCKET_TYPE_BASE3
#define SOCKET_TYPE_NUM 1
#define PROCESSOR_VERSION_BASE (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM)
-#define PROCESSOR_VERSION_NUM 10
+#define PROCESSOR_VERSION_NUM 11
#define SERIAL_NUMBER_BASE (PROCESSOR_VERSION_BASE +
PROCESSOR_VERSION_NUM)
#define TYPE4_STRINGS \
"0x000\0" /* Part Number */ \
@@ -43,6 +43,7 @@
"Neoverse-N2\0" \
"Neoverse-N2\0" \
"Neoverse-N2\0" \
+ "Neoverse-V2\0" \
"000-0\0" /* Serial number */ \
"783-3\0" \
"786-1\0" \
@@ -52,7 +53,8 @@
"78A-2\0" \
"7B7-1\0" \
"7B6-1\0" \
- "7B7-1\0"
+ "7B7-1\0" \
+ "7F2-1\0"
typedef enum {
PartNumber = 1,
@@ -178,6 +180,7 @@ InstallType4ProcessorInformation (
break;
case RdN2:
case RdN2Cfg1:
+ case RdV2:
mArmRdSmbiosType4.Base.CoreCount = CoreCount;
mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index b71ce721e2e8..d65ae9520679 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -334,6 +334,24 @@ InstallType7CacheInformation (
mArmRdSmbiosType7[4].Base.InstalledSize2 = 8192; // 8MB SLC
mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
break;
+ case RdV2:
+/* L1 instruction cache */
+mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64;// 64KB
+mArmRdSmbiosType7[0].Base.InstalledSize2 = 64; // 64KB
+mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
+/* L1 data cache */
+mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64;// 64KB
+mArmRdSmbiosType7[1].Base.InstalledSize2 = 64; // 64KB
+mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
+/* L2 cache */
+mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 2048; // 2MB
+mArmRdSmbiosType7[2].Base.InstalledSize2 = 2048; // 2MB
+mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
+/* System level cache */
+mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 32768
[edk2-devel] [edk2-platforms][PATCH V2 1/2] Platform/Sgi: Define RD-V2 platform id values
Add the RD-V2 platform identification values including the part
number and configuration number. This information will be used in
populating the SMBIOS tables.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 5 +
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 6 ++
2 files changed, 11 insertions(+)
diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index e83853664c4c..ea197b9f50bc 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -47,6 +47,10 @@
#define RD_N2_PART_NUM0x7B7
#define RD_N2_CONF_ID 0x1
+// RD-V2 Platform Identification values
+#define RD_V2_PART_NUM0x7F2
+#define RD_V2_CONF_ID 0x1
+
#define SGI_CONFIG_MASK 0x0F
#define SGI_CONFIG_SHIFT 0x1C
#define SGI_PART_NUM_MASK 0xFFF
@@ -85,6 +89,7 @@ typedef enum {
RdN2,
RdN2Cfg1,
RdN2Cfg2,
+ RdV2,
} ARM_RD_PRODUCT_ID;
// Arm ProductId look-up table
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index fa006320025b..0562f40d4604 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
@@ -79,6 +79,12 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = {
RD_N2_CONF_ID,
1
},
+ {
+RdV2,
+RD_V2_PART_NUM,
+RD_V2_CONF_ID,
+0
+ },
};
EFI_BOOT_MODE
--
2.34.1
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[edk2-devel] [edk2-platforms][PATCH V2 0/2] Add SMBIOS support for RD-V2 platform
Changes since V1: - Rebase the patches on top of latest master branch SMBIOS provides basic hardware and firmware configuration information through table-driven data structure. This patch series adds SMBIOS support for Arm's RD-V2 platforms. The first patch in this series defines platform-id values for the RD-V2 platform. The second patch add CPU information and cache attributes for RD-V2 platform. Link to branch with the patches in this series - https://git.gitlab.arm.com/infra-solutions/reference-design/platsw/edk2-platforms/-/tree/topics/rdv2-smbios-v2-upstream Pranav Madhu (2): Platform/Sgi: Define RD-V2 platform id values Platform/Sgi: Extend SMBIOS support for RD-V2 platform Platform/ARM/SgiPkg/Include/SgiPlatform.h | 5 + Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c| 5 - Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 7 +-- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 18 ++ Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 6 ++ 5 files changed, 38 insertions(+), 3 deletions(-) -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112522): https://edk2.groups.io/g/devel/message/112522 Mute This Topic: https://groups.io/mt/103168056/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH v1 1/1] Platform/Sgi: update fastchannel address for RD-N2 variants
For RD-N2 and variant platforms, the shared SRAM memory carveouts have
changed due to updates in the platform firmware. Correspondingly,
update the fastchannel address to align with the rest of the platform
firmware components.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 41
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 22 +--
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl | 34
3 files changed, 52 insertions(+), 45 deletions(-)
Link to branch for this patch -
https://gitlab.arm.com/infra-solutions/reference-design/platsw/edk2-platforms/-/tree/topics/rdn2-fastchannel-update-v1
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
index 0f63ca42d505..bac90f828d3f 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
@@ -1,10 +1,17 @@
/** @file
* Differentiated System Description Table Fields (DSDT)
*
-* Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
+* This file describes the peripheral devices, system hardware features and the
+* information about supported power events.
+*
+* Copyright (c) 2020 - 2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
+* @par Specification Reference:
+* - ACPI 6.4, Chapter 5, Section 5.2.11.1, Differentiated System Description
+* Table (DSDT)
+*
**/
#include "SgiPlatform.h"
@@ -124,7 +131,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_STA, 0xF)
Name (_CPC, Package()
- CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 160, 160, 115, 115, 5)
+ CPPC_PACKAGE_INIT (0x06000800, 0x06000804, 20, 160, 160, 115, 115, 5)
)
Name (_PSD, Package () {
@@ -148,7 +155,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_STA, 0xF)
Name (_CPC, Package()
- CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 160, 160, 115, 115, 5)
+ CPPC_PACKAGE_INIT (0x06000818, 0x0600081C, 20, 160, 160, 115, 115, 5)
)
Name (_PSD, Package () {
@@ -172,7 +179,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_STA, 0xF)
Name (_CPC, Package()
- CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 160, 160, 115, 115, 5)
+ CPPC_PACKAGE_INIT (0x06000830, 0x06000834, 20, 160, 160, 115, 115, 5)
)
Name (_PSD, Package () {
@@ -196,7 +203,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_STA, 0xF)
Name (_CPC, Package()
- CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 160, 160, 115, 115, 5)
+ CPPC_PACKAGE_INIT (0x06000848, 0x0600084C, 20, 160, 160, 115, 115, 5)
)
Name (_PSD, Package () {
@@ -220,7 +227,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_STA, 0xF)
Name (_CPC, Package()
- CPPC_PACKAGE_INIT (0x06000560, 0x06000564, 20, 160, 160, 115, 115, 5)
+ CPPC_PACKAGE_INIT (0x06000860, 0x06000864, 20, 160, 160, 115, 115, 5)
)
Name (_PSD, Package () {
@@ -244,7 +251,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_STA, 0xF)
Name (_CPC, Package()
- CPPC_PACKAGE_INIT (0x06000578, 0x0600057C, 20, 160, 160, 115, 115, 5)
+ CPPC_PACKAGE_INIT (0x06000878, 0x0600087C, 20, 160, 160, 115, 115, 5)
)
Name (_PSD, Package () {
@@ -268,7 +275,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_STA, 0xF)
Name (_CPC, Package()
- CPPC_PACKAGE_INIT (0x06000590, 0x06000594, 20, 160, 160, 115, 115, 5)
+ CPPC_PACKAGE_INIT (0x06000890, 0x06000894, 20, 160, 160, 115, 115, 5)
)
Name (_PSD, Package () {
@@ -292,7 +299,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_STA, 0xF)
Name (_CPC, Package()
- CPPC_PACKAGE_INIT (0x060005A8, 0x060005AC, 20, 160, 160, 115, 115, 5)
+ CPPC_PACKAGE_INIT (0x060008A8, 0x060008AC, 20, 160, 160, 115, 115, 5)
)
Name (_PSD, Package () {
@@ -316,7 +323,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_STA, 0xF)
Name (_CPC, Package()
- CPPC_PACKAGE_INIT (0x060005C0, 0x060005C4, 20, 160, 160, 115, 115, 5)
+ CPPC_PACKAGE_INIT (0x060008C0, 0x060008C4, 20, 160,
[edk2-devel] [edk2-platforms][PATCH v1 2/2] Platform/Sgi: Extend SMBIOS support for RD-V2 platform
The Neoverse RD-V2 FVP platform includes 16 CPUs and each CPU has 64KB
of L1 instruction/data cache, 2MB of L2 cache and 32MB of system level
cache. Extend the SMBIOS support for RD-V2 platform with this
configuration.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c| 5
-
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 7
+--
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 18
++
3 files changed, 27 insertions(+), 3 deletions(-)
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index b7e2238fb39c..fe3c88672d7e 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -33,7 +33,8 @@
"RdV1Mc\0"\
"RdN2\0" \
"RdN2Cfg1\0" \
- "RdN2Cfg2\0"
+ "RdN2Cfg2\0" \
+ "RdV2\0"
typedef enum {
ManufacturerName = 1,
@@ -71,6 +72,8 @@ STATIC GUID mSmbiosUid[] = {
{0xa4941d3d, 0xfac3, 0x4ace, {0x9a, 0x7e, 0xce, 0x26, 0x76, 0x64, 0x5e,
0xda}},
/* Rd-N2-Cfg2*/
{0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1,
0x60}},
+ /* Rd-V2 */
+ {0x3b1180a3, 0x0744, 0x4194, {0xae, 0x2e, 0xed, 0xa5, 0xbc, 0x2e, 0x43,
0x45}},
};
/* System information */
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index b59172cf1cb9..0f403e41a3c7 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -27,7 +27,7 @@
#define SOCKET_TYPE_BASE3
#define SOCKET_TYPE_NUM 1
#define PROCESSOR_VERSION_BASE (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM)
-#define PROCESSOR_VERSION_NUM 10
+#define PROCESSOR_VERSION_NUM 11
#define SERIAL_NUMBER_BASE (PROCESSOR_VERSION_BASE +
PROCESSOR_VERSION_NUM)
#define TYPE4_STRINGS \
"0x000\0" /* Part Number */ \
@@ -43,6 +43,7 @@
"Neoverse-N2\0" \
"Neoverse-N2\0" \
"Neoverse-N2\0" \
+ "Neoverse-V2\0" \
"000-0\0" /* Serial number */ \
"783-3\0" \
"786-1\0" \
@@ -52,7 +53,8 @@
"78A-2\0" \
"7B7-1\0" \
"7B6-1\0" \
- "7B7-1\0"
+ "7B7-1\0" \
+ "7F2-1\0"
typedef enum {
PartNumber = 1,
@@ -178,6 +180,7 @@ InstallType4ProcessorInformation (
break;
case RdN2:
case RdN2Cfg1:
+ case RdV2:
mArmRdSmbiosType4.Base.CoreCount = CoreCount;
mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index b71ce721e2e8..d65ae9520679 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -334,6 +334,24 @@ InstallType7CacheInformation (
mArmRdSmbiosType7[4].Base.InstalledSize2 = 8192; // 8MB SLC
mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
break;
+ case RdV2:
+/* L1 instruction cache */
+mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64;// 64KB
+mArmRdSmbiosType7[0].Base.InstalledSize2 = 64; // 64KB
+mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
+/* L1 data cache */
+mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64;// 64KB
+mArmRdSmbiosType7[1].Base.InstalledSize2 = 64; // 64KB
+mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
+/* L2 cache */
+mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 2048; // 2MB
+mArmRdSmbiosType7[2].Base.InstalledSize2 = 2048; // 2MB
+mArmRdSmbiosType7[2].Base.Associativity = CacheAssociativity8Way;
+/* System level cache */
+mArmRdSmbiosType7[4].Base.MaximumCacheSize2 = 32768
[edk2-devel] [edk2-platforms][PATCH v1 1/2] Platform/Sgi: Define RD-V2 platform id values
Add the RD-V2 platform identification values including the part
number and configuration number. This information will be used in
populating the SMBIOS tables.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 5 +
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 6 ++
2 files changed, 11 insertions(+)
diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index e83853664c4c..ea197b9f50bc 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -47,6 +47,10 @@
#define RD_N2_PART_NUM0x7B7
#define RD_N2_CONF_ID 0x1
+// RD-V2 Platform Identification values
+#define RD_V2_PART_NUM0x7F2
+#define RD_V2_CONF_ID 0x1
+
#define SGI_CONFIG_MASK 0x0F
#define SGI_CONFIG_SHIFT 0x1C
#define SGI_PART_NUM_MASK 0xFFF
@@ -85,6 +89,7 @@ typedef enum {
RdN2,
RdN2Cfg1,
RdN2Cfg2,
+ RdV2,
} ARM_RD_PRODUCT_ID;
// Arm ProductId look-up table
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index fa006320025b..0562f40d4604 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
@@ -79,6 +79,12 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = {
RD_N2_CONF_ID,
1
},
+ {
+RdV2,
+RD_V2_PART_NUM,
+RD_V2_CONF_ID,
+0
+ },
};
EFI_BOOT_MODE
--
2.34.1
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[edk2-devel] [edk2-platforms][PATCH v1 0/2] Add SMBIOS support for RD-V2 platform
SMBIOS provides basic hardware and firmware configuration information through table-driven data structure. This patch series adds SMBIOS support for Arm's RD-V2 platforms. The first patch in this series defines platform-id values for the RD-V2 platform. The second patch add CPU information and cache attributes for RD-V2 platform. Link to branch with the patches in this series - https://gitlab.arm.com/infra-solutions/reference-design/platsw/edk2-platforms/-/tree/topics/rdv2-smbios-v1 Pranav Madhu (2): Platform/Sgi: Define RD-V2 platform id values Platform/Sgi: Extend SMBIOS support for RD-V2 platform Platform/ARM/SgiPkg/Include/SgiPlatform.h | 5 + Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c| 5 - Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 7 +-- Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 18 ++ Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 6 ++ 5 files changed, 38 insertions(+), 3 deletions(-) -- 2.34.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109482): https://edk2.groups.io/g/devel/message/109482 Mute This Topic: https://groups.io/mt/101871394/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2][PATCH V4 1/1] ArmPkg: Handle warm reboot request correctly
The warm reboot requests from OSPM are mapped to cold reboot. To handle
the warm reboot separately from a cold reboot, update
ArmSmcPsciResetSystemLib and to invoke the PSCI call with parameters
for warm reboot.
Signed-off-by: Pranav Madhu
---
ArmPkg/Include/IndustryStandard/ArmStdSmc.h| 2 ++
ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c | 19
+--
2 files changed, 19 insertions(+), 2 deletions(-)
Changes since V1:
- Addressed comments from Ard.
Changes since V2:
- Remove 32 bit warm reboot PSCI support.
- Update ResetWarm() to check whether platform support warm reset.
- Addressed comments from Sami
Changes since V3:
- Rebased on top of latest upstream master branch.
Link to github branch for this patch -
https://github.com/Pranav-Madhu/edk2/tree/topics/warm_reboot
diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
index 655edc21b205..78ce77cd734d 100644
--- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
@@ -93,6 +93,8 @@
#define ARM_SMC_ID_PSCI_MIGRATE_AARCH320x8405
#define ARM_SMC_ID_PSCI_SYSTEM_OFF 0x8408
#define ARM_SMC_ID_PSCI_SYSTEM_RESET 0x8409
+#define ARM_SMC_ID_PSCI_FEATURES 0x840A
+#define ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64 0xC412
/* The current PSCI version is: 0.2 */
#define ARM_SMC_PSCI_VERSION_MAJOR 0
diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c
b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c
index af6738459e43..b710cd066e8b 100644
--- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c
+++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c
@@ -3,6 +3,7 @@
Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.
Copyright (c) 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -47,8 +48,22 @@ ResetWarm (
VOID
)
{
- // Map a warm reset into a cold reset
- ResetCold ();
+ UINTN Arg1 = ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64;
+ UINTN ret;
+
+ // Is SYSTEM_RESET2 supported?
+ ret = ArmCallSmc0 (ARM_SMC_ID_PSCI_FEATURES, , NULL, NULL);
+ if (ret == ARM_SMC_PSCI_RET_SUCCESS) {
+// Send PSCI SYSTEM_RESET2 command
+ArmCallSmc0 (Arg1, NULL, NULL, NULL);
+ } else {
+// Map a warm reset into a cold reset
+DEBUG ((
+ DEBUG_INFO,
+ "Warm reboot not supported by platform, issuing cold reboot\n"
+ ));
+ResetCold ();
+ }
}
/**
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V2 7/7] Platform/Sgi: Fix ACPI Low Power Idle states for RD-N2-Cfg1
RD-N2-Cfg1 platform supports only the platform co-ordinated LPI. So fix
the LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method. As
the cpus are directly connected to the interconnect on this platform,
remove the cluster _LPI control method as well.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 54 ++--
1 file changed, 4 insertions(+), 50 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
index b6decc77f480..2e9e588806c6 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
@@ -68,38 +68,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Return (Arg3)
}
-Name (CLPI, Package () { /* LPI for Cluster, support 1 LPI state */
- 0, // Version
- 0, // Level Index
- 1, // Count
- Package () {// Power Gating state for Cluster
-2500, // Min residency (uS)
-1150, // Wake latency (uS)
-1,// Flags
-1,// Arch Context Flags
-100, // Residency Counter Frequency
-0,// No Parent State
-0x0020, // Integer Entry method
-ResourceTemplate () { // Null Residency Counter
- Register (SystemMemory, 0, 0, 0, 0)
-},
-ResourceTemplate () { // Null Usage Counter
- Register (SystemMemory, 0, 0, 0, 0)
-},
-"LPI2-Cluster"
- },
-})
-
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -122,8 +100,8 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
-1,// Parent node can be in any shallower state
+0,// Residency Counter Frequency
+0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
32, // Bit Width
@@ -145,9 +123,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL00) { // Cluster 0
Name (_HID, "ACPI0010")
Name (_UID, 0)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP00) { // Neoverse N2 core 0
Name (_HID, "ACPI0007")
@@ -172,9 +147,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL01) { // Cluster 1
Name (_HID, "ACPI0010")
Name (_UID, 1)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP01) { // Neoverse N2 core 1
Name (_HID, "ACPI0007")
@@ -199,9 +171,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL02) { // Cluster 2
Name (_HID, "ACPI0010")
Name (_UID, 2)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP02) { // Neoverse N2 core 2
Name (_HID, "ACPI0007")
@@ -226,9 +195,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL03) { // Cluster 3
Name (_HID, "ACPI0010")
Name (_UID, 3)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP03) { // Neoverse N2 core 3
Name (_HID, "ACPI0007")
@@ -253,9 +219,6 @@ DefinitionBlock ("DsdtTable.a
[edk2-devel] [edk2-platforms][PATCH V2 6/7] Platform/Sgi: Fix ACPI Low Power Idle states for RD-N2
RD-N2 platform supports only the platform co-ordinated LPI. So fix the
LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method. As
the cpus are directly connected to the interconnect on this platform,
remove the cluster _LPI control method as well.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 78 +---
1 file changed, 4 insertions(+), 74 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
index ccd98f829652..0f63ca42d505 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
@@ -62,38 +62,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Return (Arg3)
}
-Name (CLPI, Package () { /* LPI for Cluster, support 1 LPI state */
- 0, // Version
- 0, // Level Index
- 1, // Count
- Package () {// Power Gating state for Cluster
-2500, // Min residency (uS)
-1150, // Wake latency (uS)
-1,// Flags
-1,// Arch Context Flags
-100, // Residency Counter Frequency
-0,// No Parent State
-0x0020, // Integer Entry method
-ResourceTemplate () { // Null Residency Counter
- Register (SystemMemory, 0, 0, 0, 0)
-},
-ResourceTemplate () { // Null Usage Counter
- Register (SystemMemory, 0, 0, 0, 0)
-},
-"LPI2-Cluster"
- },
-})
-
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -116,8 +94,8 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
-1,// Parent node can be in any shallower state
+0,// Residency Counter Frequency
+0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
32, // Bit Width
@@ -139,9 +117,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL00) { // Cluster 0
Name (_HID, "ACPI0010")
Name (_UID, 0)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP00) { // Neoverse N2 core 0
Name (_HID, "ACPI0007")
@@ -166,9 +141,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL01) { // Cluster 1
Name (_HID, "ACPI0010")
Name (_UID, 1)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP01) { // Neoverse N2 core 1
Name (_HID, "ACPI0007")
@@ -193,9 +165,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL02) { // Cluster 2
Name (_HID, "ACPI0010")
Name (_UID, 2)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP02) { // Neoverse N2 core 2
Name (_HID, "ACPI0007")
@@ -220,9 +189,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL03) { // Cluster 3
Name (_HID, "ACPI0010")
Name (_UID, 3)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP03) { // Neoverse N2 core 3
Name (_HID, "ACPI0007")
@@ -247,9 +213,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT&
[edk2-devel] [edk2-platforms][PATCH V2 5/7] Platform/Sgi: Fix ACPI Low Power Idle states for RD-V1-MC
RD-V1-MC platform supports only the platform co-ordinated LPI. So fix
the LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
index e084d82de7c0..152a3076fedd 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
@@ -64,14 +64,14 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -94,8 +94,8 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
-1,// Parent node can be in any shallower state
+0,// Residency Counter Frequency
+0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
32, // Bit Width
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V2 4/7] Platform/Sgi: Fix ACPI Low Power Idle states for RD-V1
RD-V1 platform supports only the platform co-ordinated LPI. So fix the
LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
index db9c19780e16..3c9c878dd880 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
@@ -64,14 +64,14 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -94,8 +94,8 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
-1,// Parent node can be in any shallower state
+0,// Residency Counter Frequency
+0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
32, // Bit Width
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V2 3/7] Platform/Sgi: Fix ACPI Low Power Idle states for RD-N1-Edge-X2
RD-N1-Edge-X2 platform supports only the platform co-ordinated LPI. So
fix the LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
index 9cb2b175418c..28e255c6de6e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
@@ -60,7 +60,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
1150, // Wake latency (uS)
1,// Flags
1,// Arch Context Flags
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No Parent State
0x0020, // Integer Entry method
ResourceTemplate () { // Null Residency Counter
@@ -75,14 +75,14 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -105,7 +105,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
1,// Parent node can be in any shallower state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V2 2/7] Platform/Sgi: Fix ACPI Low Power Idle states for RD-N1-Edge
RD-N1-Edge platform supports only the platform co-ordinated LPI. So fix
the LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
index bd8efa544a59..7b4bbd36d8c0 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
@@ -58,7 +58,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
1150, // Wake latency (uS)
1,// Flags
1,// Arch Context Flags
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No Parent State
0x0020, // Integer Entry method
ResourceTemplate () { // Null Residency Counter
@@ -73,14 +73,14 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -103,7 +103,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
1,// Parent node can be in any shallower state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V2 1/7] Platform/Sgi: Fix ACPI Low Power Idle states for SGI575
SGI-575 platform supports only the platform co-ordinated LPI. So fix the
LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
index 80075ee1238b..f4e84e806a65 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
@@ -57,7 +57,7 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI", EFI_ACPI_ARM_OEM
1150, // Wake latency (uS)
1,// Flags
1,// Arch Context Flags
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No Parent State
0x0020, // Integer Entry method
ResourceTemplate () { // Null Residency Counter
@@ -72,14 +72,14 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI", EFI_ACPI_ARM_OEM
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -102,7 +102,7 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI", EFI_ACPI_ARM_OEM
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
1,// Parent node can be in any shallower state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V2 0/7] Fix ACPI Low Power Idle states for RD platforms
Changes since V1: - Rebased on top of latest master branch. The DSDT ACPI table used for Neoverse reference design platforms include the _LPI control method for the kernel to enter idle states. This patch series fixes bugs in the existing _LPI control method due to which certain high level OS failed to boot on the supported Neoverse reference design platforms. For each platform, the fixes include - clearing level ID value as the platform supports only platform co-ordinated _LPI and removing residency counter frequency as the platform does not implement residency counter. In addition to this, the RD-N2 and RD-N2-Cfg1 platforms are direct connect platforms and so the _LPI control method for cluster is removed. Link to github branch with the patches in this series - https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/lpi_fix_for_rd_platforms Reviewed-by: Pierre Gondois Reviewed-by: Thomas Abraham Pranav Madhu (7): Platform/Sgi: Fix ACPI Low Power Idle states for SGI575 Platform/Sgi: Fix ACPI Low Power Idle states for RD-N1-Edge Platform/Sgi: Fix ACPI Low Power Idle states for RD-N1-Edge-X2 Platform/Sgi: Fix ACPI Low Power Idle states for RD-V1 Platform/Sgi: Fix ACPI Low Power Idle states for RD-V1-MC Platform/Sgi: Fix ACPI Low Power Idle states for RD-N2 Platform/Sgi: Fix ACPI Low Power Idle states for RD-N2-Cfg1 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 8 +- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 8 +- Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 78 +--- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 54 +- Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 8 +- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 8 +- Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 8 +- 7 files changed, 28 insertions(+), 144 deletions(-) -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90813): https://edk2.groups.io/g/devel/message/90813 Mute This Topic: https://groups.io/mt/92050002/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH V1 0/5] Platform/Sgi: Add initial support for RD-N2-Cfg2 platform
RD-N2-Cfg2 platform is the multichip variant of the RD-N2 platform. The
platform is based on 4xMP1 Neoverse N2 CPUs per chip, CMN-700
interconnect 6x6 mesh, multiple AXI expansion ports for I/O Coherent
PCIe, Ethernet, offload and Arm Cortex-M7 for System Control Processor
(SCP) and Manageability Control Processor (MCP).
The first patch in this series defines the addressable bit per chip. The
second patch add the product ID unique for this platform. The third
patch adds ACPI tables, the fourth patch add Edk2 build system files.
The last patch in this series adds SMBIOS support.
This patch series should be applied on top of the patch series:
https://edk2.groups.io/g/devel/message/90765
Link to github branch with the patches in this series -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rdn2cfg2-initial-support
Pranav Madhu (1):
Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg2
Vijayenthiran Subramaniam (4):
Platform/Sgi: Add a new PCD for defining addressable bits per chip
Platform/Sgi: Add ProductId lookup values for RD-N2-Cfg2 Platform
Platform/Sgi: Add ACPI tables for RD-N2-Cfg2 platform
Platform/Sgi: Add support for RD-N2-Cfg2 Platform
Platform/ARM/SgiPkg/SgiPlatform.dec
| 5 +-
Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
| 5 +-
Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
| 5 +-
Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.dsc
| 58 +++
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
| 3 +-
Platform/ARM/SgiPkg/AcpiTables/{RdV1McAcpiTables.inf =>
RdN2Cfg2AcpiTables.inf} | 48 +-
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
| 3 +-
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
| 3 +-
Platform/ARM/SgiPkg/Include/SgiPlatform.h
| 10 +-
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
| 7 +-
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
| 15 +-
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
| 3 +-
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
| 8 +-
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl
| 532
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Madt.aslc
| 145 ++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Pptt.aslc
| 172 +++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Srat.aslc
| 117 +
Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.fdf.inc
| 10 +
18 files changed, 1102 insertions(+), 47 deletions(-)
create mode 100644 Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.dsc
copy Platform/ARM/SgiPkg/AcpiTables/{RdV1McAcpiTables.inf =>
RdN2Cfg2AcpiTables.inf} (71%)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Madt.aslc
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Pptt.aslc
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Srat.aslc
create mode 100644 Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.fdf.inc
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V1 5/5] Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg2
Extend the SMBIOS support for RD-N2-Cfg2 platform which is a quad-chip
variant of the RD-N2 platform. Most the SMBIOS information is shared
with the RD-N2 platform except for the number of the CPUs supported on
the RD-N2-Cfg2 platform.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c| 7
+--
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 15
---
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 3
++-
3 files changed, 19 insertions(+), 6 deletions(-)
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index 17361f63359b..b7e2238fb39c 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -5,7 +5,7 @@
Reference Design platforms. Type 1 table defines attributes of the
overall system such as manufacturer, product name, UUID etc.
- Copyright (c) 2021, ARM Limited. All rights reserved.
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@@ -32,7 +32,8 @@
"RdV1\0" \
"RdV1Mc\0"\
"RdN2\0" \
- "RdN2Cfg1\0"
+ "RdN2Cfg1\0" \
+ "RdN2Cfg2\0"
typedef enum {
ManufacturerName = 1,
@@ -68,6 +69,8 @@ STATIC GUID mSmbiosUid[] = {
{0xf2cded73, 0x37f9, 0x4ec9, {0xd9, 0xf9, 0x89, 0x9b, 0x74, 0x91, 0x20,
0x49}},
/* Rd-N2-Cfg1*/
{0xa4941d3d, 0xfac3, 0x4ace, {0x9a, 0x7e, 0xce, 0x26, 0x76, 0x64, 0x5e,
0xda}},
+ /* Rd-N2-Cfg2*/
+ {0xd2946d07, 0x8057, 0x4c26, {0xbf, 0x53, 0x78, 0xa6, 0x5b, 0xe1, 0xc1,
0x60}},
};
/* System information */
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index b554ee6dea58..b59172cf1cb9 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -6,7 +6,7 @@
family, processor id, maximum operating frequency, and other information
related to the processor.
- Copyright (c) 2021, ARM Limited. All rights reserved.
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@@ -27,7 +27,7 @@
#define SOCKET_TYPE_BASE3
#define SOCKET_TYPE_NUM 1
#define PROCESSOR_VERSION_BASE (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM)
-#define PROCESSOR_VERSION_NUM 9
+#define PROCESSOR_VERSION_NUM 10
#define SERIAL_NUMBER_BASE (PROCESSOR_VERSION_BASE +
PROCESSOR_VERSION_NUM)
#define TYPE4_STRINGS \
"0x000\0" /* Part Number */ \
@@ -42,6 +42,7 @@
"Neoverse-V1\0" \
"Neoverse-N2\0" \
"Neoverse-N2\0" \
+ "Neoverse-N2\0" \
"000-0\0" /* Serial number */ \
"783-3\0" \
"786-1\0" \
@@ -50,7 +51,8 @@
"78A-1\0" \
"78A-2\0" \
"7B7-1\0" \
- "7B6-1\0"
+ "7B6-1\0" \
+ "7B7-1\0"
typedef enum {
PartNumber = 1,
@@ -188,6 +190,13 @@ InstallType4ProcessorInformation (
mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount * FixedPcdGet32
(PcdChipCount);
mArmRdSmbiosType4.Base.ThreadCount = CoreCount * FixedPcdGet32
(PcdChipCount);
break;
+ case RdN2Cfg2:
+mArmRdSmbiosType4.Base.CoreCount = CoreCount * FixedPcdGet32
(PcdChipCount);
+mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount * FixedPcdGet32
(PcdChipCount);
+mArmRdSmbiosType4.Base.ThreadCount = CoreCount * FixedPcdGet32
(PcdChipCount);
+mArmRdSmbiosType4.Base.MaxSpeed = 3200; // Frequency in MHz
+mArmRdSmbiosType4.Base.CurrentSpeed = 3200; // Frequency in MHz
+break;
case RdE1Edge:
mArmRdSmbiosType4.Base.CoreCount = CoreCount /
NEOVERSE_E1_THREADS_PER_CORE;
mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount /
NEOVERSE_E1_THREADS_PER_CORE;
diff --git
a/Platform/ARM/SgiPkg/Drivers/Smbios
[edk2-devel] [edk2-platforms][PATCH V1 4/5] Platform/Sgi: Add support for RD-N2-Cfg2 Platform
From: Vijayenthiran Subramaniam The RD-N2-Cfg2 platform is a quad-chip variant of the RD-N2 platform. Each chip has reduced core count of four Neoverse N2 CPUs when compared to the single-chip RD-N2 platform. Enable support for the RD-N2-Cfg2 platform. Signed-off-by: Vijayenthiran Subramaniam Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.dsc | 58 Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.fdf.inc | 10 2 files changed, 68 insertions(+) diff --git a/Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.dsc b/Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.dsc new file mode 100644 index ..0a7991e77b78 --- /dev/null +++ b/Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.dsc @@ -0,0 +1,58 @@ +# +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +# +# Defines Section - statements that will be processed to create a Makefile. +# + +[Defines] + PLATFORM_NAME = RdN2Cfg2 + PLATFORM_GUID = fd272907-b48e-4148-b6e5-fe762f20653d + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES= AARCH64 + BUILD_TARGETS = NOOPT|DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/ARM/SgiPkg/SgiPlatform.fdf + BOARD_DXE_FV_COMPONENTS= Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.fdf.inc + BUILD_NUMBER = 1 + +# include common definitions from SgiPlatform.dsc +!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +!include Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc + +# include common/basic libraries from MdePkg. +!include MdePkg/MdeLibs.dsc.inc + + +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# + + +[PcdsFixedAtBuild.common] + # GIC Base Addresses + gArmTokenSpaceGuid.PcdGicDistributorBase|0x3000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x301C + gArmSgiTokenSpaceGuid.PcdGicSize|0x20 + + # ARM Cores and Clusters + gArmPlatformTokenSpaceGuid.PcdCoreCount|1 + gArmPlatformTokenSpaceGuid.PcdClusterCount|4 + + # Number of chips in the multi-chip package + gArmSgiTokenSpaceGuid.PcdChipCount|4 + + +# +# Components Section - list of all EDK II Modules needed by this Platform +# + + +[Components.common] + Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf diff --git a/Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.fdf.inc b/Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.fdf.inc new file mode 100644 index ..89df6d905811 --- /dev/null +++ b/Platform/ARM/SgiPkg/RdN2Cfg2/RdN2Cfg2.fdf.inc @@ -0,0 +1,10 @@ +# +# Copyright (c) 2022, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +# Per-platform additional content of the DXE phase firmware volume + + # ACPI support + INF RuleOverride=ACPITABLE Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90779): https://edk2.groups.io/g/devel/message/90779 Mute This Topic: https://groups.io/mt/92015425/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH V1 3/5] Platform/Sgi: Add ACPI tables for RD-N2-Cfg2 platform
From: Vijayenthiran Subramaniam
Add MADT, DSDT and SRAT ACPI tables that are specific for RD-N2-Cfg2
platform. The rest of the ACPI tables are reused from the shared ACPI
tables in SgiPkg.
Signed-off-by: Vijayenthiran Subramaniam
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf | 71 +++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl | 532
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Madt.aslc | 145 ++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Pptt.aslc | 172 +++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Srat.aslc | 117 +
5 files changed, 1037 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf
new file mode 100644
index ..2354f2dc65eb
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2AcpiTables.inf
@@ -0,0 +1,71 @@
+## @file
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION= 0x0001001A
+ BASE_NAME = RdN2Cfg2AcpiTables
+ FILE_GUID = c712719a-0aaf-438c-9cdd-35ab4d60207d #
gArmSgiAcpiTablesGuid
+ MODULE_TYPE= USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dbg2.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ RdN2Cfg2/Dsdt.asl
+ RdN2Cfg2/Madt.aslc
+ RdN2Cfg2/Pptt.aslc
+ RdN2Cfg2/Srat.aslc
+ Spcr.aslc
+ SsdtRos.asl
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdClusterCount
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+ gArmSgiTokenSpaceGuid.PcdChipCount
+ gArmSgiTokenSpaceGuid.PcdDramBlock2Base
+ gArmSgiTokenSpaceGuid.PcdDramBlock2Size
+ gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
+ gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip
+ gArmSgiTokenSpaceGuid.PcdOscLpiEnable
+ gArmSgiTokenSpaceGuid.PcdOscCppcEnable
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+ gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+ gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv
+ gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl
new file mode 100644
index ..94d65fbbda2c
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg2/Dsdt.asl
@@ -0,0 +1,532 @@
+/** @file
+ Differentiated System Description Table (DSDT) for RD-N2-Cfg2 platform
+
+ This file describes the peripheral devices, system hardware features and the
+ information about supported power events.
+
+ Copyright (c) 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.11.1, Differentiated System Description
+Table (DSDT)
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+
+ Scope (_SB) {
+
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+ CreateDWordField (Arg3, 0x00, STS0)
+ CreateDWordField (Arg3, 0x04, CAP0)
+
+ /* Platform-wide Capabilities */
+ If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+
+ If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+
+ If (And (CAP0, OSC_CAP_PLAT_COORDINATED_
[edk2-devel] [edk2-platforms][PATCH V1 2/5] Platform/Sgi: Add ProductId lookup values for RD-N2-Cfg2 Platform
From: Vijayenthiran Subramaniam
The RD-N2-Cfg2 platform is a quad-chip variant of the RD-N2 platform
but with reduced core count, that is, each instance of the RD-N2 chip
has four cores. This platform shares the same product and config ID
as the RD-N2 platform.
As a preparatory step towards adding support for RD-N2-Cfg2 Platfrom,
add the Product ID lookup values for GetProductID API.
Signed-off-by: Vijayenthiran Subramaniam
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 3 ++-
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 8 +++-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index 04390d6dcc20..e83853664c4c 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -83,7 +83,8 @@ typedef enum {
RdV1,
RdV1Mc,
RdN2,
- RdN2Cfg1
+ RdN2Cfg1,
+ RdN2Cfg2,
} ARM_RD_PRODUCT_ID;
// Arm ProductId look-up table
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index a982e3d403fa..fa006320025b 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018-2021, ARM Limited. All rights reserved.
+* Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -73,6 +73,12 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = {
RD_N2_CFG1_CONF_ID,
0
},
+ {
+RdN2Cfg2,
+RD_N2_PART_NUM,
+RD_N2_CONF_ID,
+1
+ },
};
EFI_BOOT_MODE
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V1 1/5] Platform/Sgi: Add a new PCD for defining addressable bits per chip
From: Vijayenthiran Subramaniam
Add a new PCD to define the maximum number of address bits used for
addresses within a chip. The value of this PCD can be used to derive the
maximum addressable memory region for each chip and to calculate the
address space offset of a remote chip on multi-chip platform.
In preparation of adding a multi-chip variant of the RD-N2 platform,
use this new PCD to allow maximum address space of 64TB per chip for all
RD-N2 platform variants.
Signed-off-by: Vijayenthiran Subramaniam
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 5 -
Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc| 5 -
Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 5 -
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 3 ++-
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 3 ++-
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 3 ++-
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 ---
7 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index 8cd818a9bf64..b9be5c9060b6 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2020, ARM Limited. All rights reserved.
+# Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -90,5 +90,8 @@
gArmSgiTokenSpaceGuid.PcdOscLpiEnable|0|UINT32|0x0025
gArmSgiTokenSpaceGuid.PcdOscCppcEnable|0|UINT32|0x0026
+ # Address bus width
+ gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|0x0|UINT64|0x0027
+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b,
0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
index 5d4b6ae726f6..0c577c42 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020 - 2022, ARM Limited. All rights reserved.
+# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -45,6 +45,9 @@
gArmTokenSpaceGuid.PcdPciMmio64Size|0x30
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x6000
+ # Address bus width - 4TB address space
+ gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|42
+
# Timer & Watchdog interrupts
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv|92
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv|91
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
index 1e9cd0982f5c..78ee48e354a8 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020 - 2022, ARM Limited. All rights reserved.
+# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -45,6 +45,9 @@
gArmTokenSpaceGuid.PcdPciMmio64Size|0x40
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x101000
+ # Address bus width - 64TB address space
+ gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip|46
+
# Timer & Watchdog interrupts
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv|109
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv|108
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index 1999bc1553e9..c96d0e40d2cd 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020-2021, ARM Ltd. All rights reserved.
+# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -66,6 +66,7 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip
gArmSgiTokenSpaceGuid.PcdOscLpiEnable
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
index deaca3719ae4..61a2f3a2452b 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
+# Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -66,6 +66,7 @@
gArmSgiTokenSpaceGuid.PcdGpioController0I
[edk2-devel] [edk2-platforms][PATCH V4 7/9] Platform/Sgi: Update ACPI version to v6.4 for RD-V1-MC platform
Update the RD-V1-MC platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 64
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc | 165 ++--
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 84 +-
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc | 82 +-
4 files changed, 210 insertions(+), 185 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
index c2dad0e137d5..b8485cd98ea4 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
@@ -1,17 +1,25 @@
/** @file
-* Heterogeneous Memory Attribute Table (HMAT)
-*
-* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ The (HMAT) describes the memory attributes, such as memory side cache
+ attributes and bandwidth and latency details, related to Memory Proximity
+ Domains. The software is expected to use this information as a hint for
+ optimization, or when the system has heterogeneous memory. The attributes of
+ the memory connected to the two chips on this platform are listed in this
+ table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute Table
**/
-#include
#include
#include
-#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
#define INITATOR_PROXIMITY_DOMAIN_CNT 4
@@ -29,14 +37,14 @@ typedef struct InitiatorTargetProximityMatrix {
} INITIATOR_TARGET_PROXIMITY_MATRIX;
typedef struct {
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
INITIATOR_TARGET_PROXIMITY_MATRIX
Matrix;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache2;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache3;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache2;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache3;
} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
#pragma pack ()
@@ -45,9 +53,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
),
{
EFI_ACPI_RESERVED_BYTE,
@@ -59,19 +67,19 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Memory Proximity Domain
{
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x0, 0x0),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x1, 0x1),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x2, 0x2),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x3, 0x3),
},
// Latency Info
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_I
[edk2-devel] [edk2-platforms][PATCH V4 2/9] Platform/Sgi: Update ACPI version to v6.4 for SGI575 platform
Update the SGI575 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc | 105 +++-
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 87
2 files changed, 101 insertions(+), 91 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
index f04b77929d71..d3d7d946655f 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the SGI-575
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORES (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,75 +27,76 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTUREGicInterfaces[CORES];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTUREGicInterfaces[CORES];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0, // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-2
+ 0, 2, GET_MPID(0
[edk2-devel] [edk2-platforms][PATCH V4 4/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge-X2 platform
Update the RD-N1-Edge-X2 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 52 ---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 151 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 96 +++--
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc | 74 +-
4 files changed, 200 insertions(+), 173 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
index 704708f94baf..4a55c33396b6 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
@@ -1,17 +1,25 @@
/** @file
-* Heterogeneous Memory Attribute Table (HMAT)
-*
-* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ The (HMAT) describes the memory attributes, such as memory side cache
+ attributes and bandwidth and latency details, related to Memory Proximity
+ Domains. The software is expected to use this information as a hint for
+ optimization, or when the system has heterogeneous memory. The attributes of
+ the memory connected to the two chips on this platform are listed in this
+ table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute Table
**/
-#include
#include
#include
-#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
#define INITATOR_PROXIMITY_DOMAIN_CNT 2
@@ -29,12 +37,12 @@ typedef struct InitiatorTargetProximityMatrix {
} INITIATOR_TARGET_PROXIMITY_MATRIX;
typedef struct {
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
INITIATOR_TARGET_PROXIMITY_MATRIX
Matrix;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
#pragma pack ()
@@ -43,9 +51,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
),
{
EFI_ACPI_RESERVED_BYTE,
@@ -57,15 +65,15 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Memory Proximity Domain
{
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x0, 0x0),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x1, 0x1),
},
// Latency Info
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
-0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+0, 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
{
{0, 1},
{0, 1},
@@ -82,7 +90,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
},
// Memory Side Cache
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x0,
SIZE_8MB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
@@ -94,7 +102,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat
[edk2-devel] [edk2-platforms][PATCH V4 9/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N2-Cfg1 platform
Update the RD-N2-Cfg1 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 76 ++---
2 files changed, 96 insertions(+), 92 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
index c6bb29a25c61..65926027eadf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
@@ -1,23 +1,22 @@
/** @file
-* Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
-*
-* This file lists all the processors available on the platform that the OSPM
-* can enumerate and boot. It also lists all the interrupt controllers available
-* in the system.
-*
-* Copyright (c) 2021, Arm Ltd. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Table
+ Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N2-Cfg1
+ platform is included in this table.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
#include
#include
#include
-#include
-
#include "SgiAcpiHeader.h"
#include "SgiPlatform.h"
@@ -28,69 +27,70 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts[3];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts[3];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
- 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
- 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
- 0, 5,
[edk2-devel] [edk2-platforms][PATCH V4 8/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N2 platform
Update the RD-N2 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 163 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 80 +-
2 files changed, 127 insertions(+), 116 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
index dbb23683113a..cdf8b3f2e953 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N2
platform
+ is included in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,112 +27,113 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts[6];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts[6];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_A
[edk2-devel] [edk2-platforms][PATCH V4 6/9] Platform/Sgi: Update ACPI version to v6.4 for RD-V1 platform
Update the RD-V1 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 ++--
Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 80 +-
2 files changed, 125 insertions(+), 114 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
index c4551e92c0f2..374b0e2bddbf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-V1
platform
+ is included in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,110 +27,111 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts[4];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts[4];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( /
[edk2-devel] [edk2-platforms][PATCH V4 5/9] Platform/Sgi: Update ACPI version to v6.4 for RD-E1-Edge platform
Update the RD-E1-Edge platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 ++--
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 109 -
2 files changed, 184 insertions(+), 172 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
index cb70394bfe91..0b2bba575bf5 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-E1-Edge
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,173 +27,174 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-0 Thread-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1
- 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1
+ 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0
- 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 T
[edk2-devel] [edk2-platforms][PATCH V4 3/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge platform
Update the RD-N1-Edge platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 +++-
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 91 +
2 files changed, 104 insertions(+), 92 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
index 05eb78c5616a..df2576e1d9b7 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N1-Edge
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,75 +27,76 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+
[edk2-devel] [edk2-platforms][PATCH V4 1/9] Platform/Sgi: Update ACPI version to v6.4
Update the common ACPI tables used by all the Neoverse Reference Design
platforms to ACPI version v6.4. Significant changes introduced are
update API/macro definitions to incorporate with the extra fields
introduced in ACPI 6.4, such as SPE overflow interrupt number field to
GICC structure of MADT table and adding cache ID field to the cache
structure of PPTT table.
Signed-off-by: Pranav Madhu
Reviewed-by: Pierre Gondois
Reviewed-by: Thomas Abraham
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 252 +++-
Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc| 30 ++-
Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc| 38 +--
Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc| 69 +++---
Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc| 26 +-
Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc| 29 ++-
6 files changed, 252 insertions(+), 192 deletions(-)
diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index e9b6923cb035..033d398fdb63 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018-2021, ARM Limited. All rights reserved.
+* Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -41,136 +41,170 @@
#define OSC_CAP_PLAT_COORDINATED_LPI (1U << 7)
#define OSC_CAP_OS_INITIATED_LPI (1U << 8)
+// Cache type identifier used to calculate unique cache ID for PPTT
+typedef enum {
+ L1DataCache = 1,
+ L1InstructionCache,
+ L2Cache,
+ L3Cache,
+} RD_PPTT_CACHE_TYPE;
+
#pragma pack(1)
// PPTT processor core structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Core;
UINT32 ResourceOffset[2];
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L2Cache;
} RD_PPTT_CORE;
// PPTT processor cluster structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster;
UINT32 ResourceOffset;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L3Cache;
RD_PPTT_CORE Core[CORE_COUNT];
} RD_PPTT_CLUSTER;
// PPTT processor cluster structure without cache
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster;
RD_PPTT_CORE Core[CORE_COUNT];
} RD_PPTT_MINIMAL_CLUSTER;
// PPTT processor package structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package;
RD_PPTT_MINIMAL_CLUSTERCluster[CLUSTER_COUNT];
} RD_PPTT_PACKAGE;
#pragma pack ()
//
// PPTT processor structure flags for different SoC components as defined in
-// ACPI 6.3 specification
+// ACPI 6.4 specification
//
// Processor structure flags for SoC package
#define PPTT_PROCESSOR_PACKAGE_FLAGS
\
{
\
-EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
\
-EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
\
-EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
\
+EFI_ACPI_6_4_PPTT_PACKAGE_PHYSICAL,
\
+EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID,
\
+EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD,
\
+EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF,
\
+EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL
\
}
// Processor structure flags for cluster
#define PPTT_PROCESSOR_CLUSTER_FLAGS
\
{
\
-EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
\
-EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
\
-EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
\
+EFI_ACPI_6_4_PPTT_PACKAGE_
[edk2-devel] [edk2-platforms][PATCH V4 0/9] Upadate the ACPI tables for RD platforms
Changes since V3: - Addressed comments from Pierre Gondois - Rebased on top of latest master branch Changes since V2: - Rebased on top of latest master branch - Update PPTT table with unique cache ID across the system for different levels of cache. Changes since V1: - Rebased on top of latest master branch. - Rebased on top of patch to remove SLC cache entries from PPTT (link for the same in edk2.groups.io is provided below) Arm infrastructure reference design platforms uses ACPI tables to provide the hardware information to the operating system. Currently the ACPI tables are aligned with ACPI v6.2 and v6.3 specification. This patch series update the tables to ACPI v6.4 specificaion. Features like MPAM relies on cache ID field of PPTT tables to distinguish between different physical caches, which is introduced in PPTT table in ACPI v6.4. Also ServerReady (SBBR compliaance) strictly recomments all the tables in the system should allign with same version of ACPI. Hence upgrade all ACPI tables mentioned in ACPI specification to v6.4. The first patch in this series update the generic tables which are common for all platfoms. The subsequent patches in this series update platform specific ACPI tables to v6.4 for the respective platform. This patch series also update the headers in the .aslc files to match the coding style as per edk2 coding guidelines. Link to github branch with the patches in this series - https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/acpi64_for_rd_platforms Reviewed-by: Pierre Gondois Reviewed-by: Thomas Abraham Pranav Madhu (9): Platform/Sgi: Update ACPI version to v6.4 Platform/Sgi: Update ACPI version to v6.4 for SGI575 platform Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge platform Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge-X2 platform Platform/Sgi: Update ACPI version to v6.4 for RD-E1-Edge platform Platform/Sgi: Update ACPI version to v6.4 for RD-V1 platform Platform/Sgi: Update ACPI version to v6.4 for RD-V1-MC platform Platform/Sgi: Update ACPI version to v6.4 for RD-N2 platform Platform/Sgi: Update ACPI version to v6.4 for RD-N2-Cfg1 platform Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 252 +++- Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc| 30 ++- Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc| 38 +-- Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc| 69 +++--- Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc| 26 +- Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 +-- Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 109 + Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 91 +++ Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 52 ++-- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 151 ++-- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 96 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc | 74 +++--- Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 163 +++-- Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 80 --- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 - Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 76 +++--- Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 ++-- Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 80 --- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 64 ++--- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc | 165 +++-- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 84 +++ Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc | 82 --- Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc | 105 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 87 +++ Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc| 29 ++- 26 files changed, 1399 insertions(+), 1227 deletions(-) -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90765): https://edk2.groups.io/g/devel/message/90765 Mute This Topic: https://groups.io/mt/92015130/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH V1 0/7] Fix ACPI Low Power Idle states for RD platforms
Hi Pierre,
Thanks for reviewing this patch series. Please find my reply inline.
Regards,
Pranav
> -Original Message-
> From: Pierre Gondois
> Sent: Tuesday, June 21, 2022 2:15 PM
> To: devel@edk2.groups.io; Pranav Madhu ;
> Thomas Abraham
> Cc: Sami Mujawar ; Ard Biesheuvel
> ; nd
> Subject: Re: [edk2-devel] [edk2-platforms][PATCH V1 0/7] Fix ACPI Low
> Power Idle states for RD platforms
>
> Hello Pranav,
> Would it be possible to extend this change to the Juno aswell as the platform
> has a Null Residency Counter and doesn't support OS Initiated LPI ?
It can be changed for Juno as well, but I do not have access to any Juno boards
and this patch series is focusing on RD platforms. The Juno board update can be
posted as a separate patch.
>
> Another remark is that for RdV1MC, RdN2, RdV1 and RdN2Cfg1 platforms,
> CPUs don't need to be encapsulated anymore in cluster objects
> Cf:
> Device (CL00) { // Cluster 0
>Name (_HID, "ACPI0010")
>Name (_UID, 0)
>...
> }
> since Clusters don't have any additional information. But keeping them is
> correct aswell.
These platforms have a minimal cluster logic but does not support low power
states. But the cluster encapsulation represents the platform topology
accurately. So it would be better to keep the cluster encapsulation.
>
> Regards,
> Pierre
>
> On 6/20/22 18:53, Pranav Madhu via groups.io wrote:
> > Hi All,
> >
> > Could you please let me know if any updates required for this series of
> patch?
> >
> > Regards,
> > Pranav
> >
> > *From:* Thomas Abraham
> > *Sent:* Sunday, June 12, 2022 2:16 AM
> > *To:* Pranav Madhu ; devel@edk2.groups.io
> > *Subject:* Re: [edk2-devel] [edk2-platforms][PATCH V1 0/7] Fix ACPI
> > Low Power Idle states for RD platforms
> >
> > On Thu, Jun 9, 2022 at 11:20 AM, Pranav Madhu wrote:
> >
> > The DSDT ACPI table used for Neoverse reference design platforms
> include
> > the _LPI control method for the kernel to enter idle states. This patch
> > series fixes bugs in the existing _LPI control method due to which
> > certain high level OS failed to boot on the supported Neoverse reference
> > design platforms. For each platform, the fixes include - clearing level
> > ID value as the platform supports only platform co-ordinated _LPI and
> > removing residency counter frequency as the platform does not
> implement
> > residency counter.
> >
> > In addition to this, the RD-N2 and RD-N2-Cfg1 platforms are direct
> > connect platforms and so the _LPI control method for cluster is removed.
> >
> > Link to github branch with the patches in this series -
> > https://github.com/Pranav-Madhu/edk2-
> platforms/tree/topics/lpi_fix_for_rd= <https://github.com/Pranav-
> Madhu/edk2-platforms/tree/topics/lpi_fix_for_rd=>
> > _platforms
> >
> > Pranav Madhu (7):
> > Platform/Sgi: Fix ACPI Low Power Idle states for SGI575
> > Platform/Sgi: Fix ACPI Low Power Idle states for RD-N1-Edge
> > Platform/Sgi: Fix ACPI Low Power Idle states for RD-N1-Edge-X2
> > Platform/Sgi: Fix ACPI Low Power Idle states for RD-V1
> > Platform/Sgi: Fix ACPI Low Power Idle states for RD-V1-MC
> > Platform/Sgi: Fix ACPI Low Power Idle states for RD-N2
> > Platform/Sgi: Fix ACPI Low Power Idle states for RD-N2-Cfg1
> >
> > Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 8 +-
> > Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 8 +-
> > Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 78 +---=
> >
> > Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 54 +-
> > Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 8 +-
> > Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 8 +-
> > Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 8 +-
> > 7 files changed, 28 insertions(+), 144 deletions(-)
> >
> >
> > For this series -
> > Reviewed-by: Thomas Abraham > <mailto:thomas.abra...@arm.com>>
> >
> >
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Re: [edk2-devel] [edk2-platforms][PATCH V2 0/9] Upadate the ACPI tables for RD platforms
Hi Pierre, Thanks for reviewing the patch series. IORT table has separate specification document and not included as a part of ACPI 6.4. That was the reason for excluding IORT from this series. If required, it will be updated in a separate patch. I've posted V3 of this patch, no major changes, I request you to have a look at that: https://edk2.groups.io/g/devel/message/90399. Regards, Pranav > On 6/22/22 10:57, Pranav Madhu via groups.io wrote:> > Hello Pranav, > > The definitions for the IORT table are still at 6_0, (IORT revision=0): > MdePkg/Include/IndustryStandard/IoRemappingTable.h > and the definitions are used at: > Platform/ARM/SgiPkg/AcpiTables/Iort.aslc > > The IORT spec is now at the version E.d (revision=5). > Does the IORT need to be updated aswell ? > > Regards, > Pierre > > On 6/20/22 18:52, Pranav Madhu via groups.io wrote: > > Hi All, > > > > Could you please let me know if any updates are required for this series of > patch? > > > > Regards, > > Pranav > > > >> -Original Message- > >> From: Thomas Abraham > >> Sent: Tuesday, April 19, 2022 1:40 AM > >> To: devel@edk2.groups.io; Pranav Madhu > >> Cc: Ard Biesheuvel ; Sami Mujawar > >> > >> Subject: Re: [edk2-devel] [edk2-platforms][PATCH V2 0/9] Upadate the > >> ACPI tables for RD platforms > >> > >> > >> On 4/18/22 12:54, Pranav Madhu via groups.io wrote: > >>> Changes since V1: > >>> - Rebased on top of latest master branch. > >>> - Rebased on top of patch to remove SLC cache entries from PPTT (link > >>> for the same in edk2.groups.io is provided below) > >>> > >>> Arm infrastructure reference design platforms uses ACPI tables to > >>> provide the hardware information to the operating system. Currently > >>> the ACPI tables are aligned with ACPI v6.2 and v6.3 specification. > >>> This patch series update the tables to ACPI v6.4 specificaion. > >>> > >>> The first patch in this series update the generic tables which are > >>> common for all platfoms. The subsequent patches in this series > >>> update platform specific ACPI tables to v6.4 for the respective platform. > >>> > >>> This patch series also update the headers in the .aslc files to > >>> match the coding style as per edk2 coding guidelines. > >>> > >>> This patch series should be applied on top of the patch series > >>> https://edk2.groups.io/g/devel/message/88996 > >>> > >>> Link to github branch with the patches in this series - > >>> https://github.com/Pranav-Madhu/edk2- > >> platforms/tree/topics/acpi64_for_ > >>> rd_platforms > >>> > >>> > >>> Pranav Madhu (9): > >>> Platform/Sgi: Update ACPI version to v6.4 > >>> Platform/Sgi: Update ACPI version to v6.4 for SGI-575 platform > >>> Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge platform > >>> Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge-X2 platform > >>> Platform/Sgi: Update ACPI version to v6.4 for Rd-E1-Edge platform > >>> Platform/Sgi: Update ACPI version to v6.4 for Rd-V1 platform > >>> Platform/Sgi: Update ACPI version to v6.4 for Rd-V1-MC platform > >>> Platform/Sgi: Update ACPI version to v6.4 for Rd-N2 platform > >>> Platform/Sgi: Update ACPI version to v6.4 for Rd-N2-Cfg1 > >>> platform > >> > >> For this series - > >> Reviewed-by: Thomas Abraham > > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, > please notify the sender immediately and do not disclose the contents to any > other person, use it for any purpose, or store or copy the information in any > medium. Thank you. > > > > > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90669): https://edk2.groups.io/g/devel/message/90669 Mute This Topic: https://groups.io/mt/90537675/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH V1 0/7] Fix ACPI Low Power Idle states for RD platforms
Hi All, Could you please let me know if any updates required for this series of patch? Regards, Pranav From: Thomas Abraham Sent: Sunday, June 12, 2022 2:16 AM To: Pranav Madhu ; devel@edk2.groups.io Subject: Re: [edk2-devel] [edk2-platforms][PATCH V1 0/7] Fix ACPI Low Power Idle states for RD platforms On Thu, Jun 9, 2022 at 11:20 AM, Pranav Madhu wrote: The DSDT ACPI table used for Neoverse reference design platforms include the _LPI control method for the kernel to enter idle states. This patch series fixes bugs in the existing _LPI control method due to which certain high level OS failed to boot on the supported Neoverse reference design platforms. For each platform, the fixes include - clearing level ID value as the platform supports only platform co-ordinated _LPI and removing residency counter frequency as the platform does not implement residency counter. In addition to this, the RD-N2 and RD-N2-Cfg1 platforms are direct connect platforms and so the _LPI control method for cluster is removed. Link to github branch with the patches in this series - https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/lpi_fix_for_rd= _platforms Pranav Madhu (7): Platform/Sgi: Fix ACPI Low Power Idle states for SGI575 Platform/Sgi: Fix ACPI Low Power Idle states for RD-N1-Edge Platform/Sgi: Fix ACPI Low Power Idle states for RD-N1-Edge-X2 Platform/Sgi: Fix ACPI Low Power Idle states for RD-V1 Platform/Sgi: Fix ACPI Low Power Idle states for RD-V1-MC Platform/Sgi: Fix ACPI Low Power Idle states for RD-N2 Platform/Sgi: Fix ACPI Low Power Idle states for RD-N2-Cfg1 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 8 +- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 8 +- Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 78 +---= Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 54 +- Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 8 +- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 8 +- Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 8 +- 7 files changed, 28 insertions(+), 144 deletions(-) For this series - Reviewed-by: Thomas Abraham mailto:thomas.abra...@arm.com>> -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90633): https://edk2.groups.io/g/devel/message/90633 Mute This Topic: https://groups.io/mt/91652410/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH V2 0/9] Upadate the ACPI tables for RD platforms
Hi All, Could you please let me know if any updates are required for this series of patch? Regards, Pranav > -Original Message- > From: Thomas Abraham > Sent: Tuesday, April 19, 2022 1:40 AM > To: devel@edk2.groups.io; Pranav Madhu > Cc: Ard Biesheuvel ; Sami Mujawar > > Subject: Re: [edk2-devel] [edk2-platforms][PATCH V2 0/9] Upadate the ACPI > tables for RD platforms > > > On 4/18/22 12:54, Pranav Madhu via groups.io wrote: > > Changes since V1: > > - Rebased on top of latest master branch. > > - Rebased on top of patch to remove SLC cache entries from PPTT (link > >for the same in edk2.groups.io is provided below) > > > > Arm infrastructure reference design platforms uses ACPI tables to > > provide the hardware information to the operating system. Currently > > the ACPI tables are aligned with ACPI v6.2 and v6.3 specification. > > This patch series update the tables to ACPI v6.4 specificaion. > > > > The first patch in this series update the generic tables which are > > common for all platfoms. The subsequent patches in this series update > > platform specific ACPI tables to v6.4 for the respective platform. > > > > This patch series also update the headers in the .aslc files to match > > the coding style as per edk2 coding guidelines. > > > > This patch series should be applied on top of the patch series > > https://edk2.groups.io/g/devel/message/88996 > > > > Link to github branch with the patches in this series - > > https://github.com/Pranav-Madhu/edk2- > platforms/tree/topics/acpi64_for_ > > rd_platforms > > > > > > Pranav Madhu (9): > >Platform/Sgi: Update ACPI version to v6.4 > >Platform/Sgi: Update ACPI version to v6.4 for SGI-575 platform > >Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge platform > >Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge-X2 platform > >Platform/Sgi: Update ACPI version to v6.4 for Rd-E1-Edge platform > >Platform/Sgi: Update ACPI version to v6.4 for Rd-V1 platform > >Platform/Sgi: Update ACPI version to v6.4 for Rd-V1-MC platform > >Platform/Sgi: Update ACPI version to v6.4 for Rd-N2 platform > >Platform/Sgi: Update ACPI version to v6.4 for Rd-N2-Cfg1 platform > > For this series - > Reviewed-by: Thomas Abraham IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90632): https://edk2.groups.io/g/devel/message/90632 Mute This Topic: https://groups.io/mt/90537675/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH V1 7/7] Platform/Sgi: Fix ACPI Low Power Idle states for RD-N2-Cfg1
RD-N2-Cfg1 platform supports only the platform co-ordinated LPI. So fix
the LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method. As
the cpus are directly connected to the interconnect on this platform,
remove the cluster _LPI control method as well.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 54 ++--
1 file changed, 4 insertions(+), 50 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
index b6decc77f480..2e9e588806c6 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
@@ -68,38 +68,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Return (Arg3)
}
-Name (CLPI, Package () { /* LPI for Cluster, support 1 LPI state */
- 0, // Version
- 0, // Level Index
- 1, // Count
- Package () {// Power Gating state for Cluster
-2500, // Min residency (uS)
-1150, // Wake latency (uS)
-1,// Flags
-1,// Arch Context Flags
-100, // Residency Counter Frequency
-0,// No Parent State
-0x0020, // Integer Entry method
-ResourceTemplate () { // Null Residency Counter
- Register (SystemMemory, 0, 0, 0, 0)
-},
-ResourceTemplate () { // Null Usage Counter
- Register (SystemMemory, 0, 0, 0, 0)
-},
-"LPI2-Cluster"
- },
-})
-
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -122,8 +100,8 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
-1,// Parent node can be in any shallower state
+0,// Residency Counter Frequency
+0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
32, // Bit Width
@@ -145,9 +123,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL00) { // Cluster 0
Name (_HID, "ACPI0010")
Name (_UID, 0)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP00) { // Neoverse N2 core 0
Name (_HID, "ACPI0007")
@@ -172,9 +147,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL01) { // Cluster 1
Name (_HID, "ACPI0010")
Name (_UID, 1)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP01) { // Neoverse N2 core 1
Name (_HID, "ACPI0007")
@@ -199,9 +171,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL02) { // Cluster 2
Name (_HID, "ACPI0010")
Name (_UID, 2)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP02) { // Neoverse N2 core 2
Name (_HID, "ACPI0007")
@@ -226,9 +195,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL03) { // Cluster 3
Name (_HID, "ACPI0010")
Name (_UID, 3)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP03) { // Neoverse N2 core 3
Name (_HID, "ACPI0007")
@@ -253,9 +219,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
[edk2-devel] [edk2-platforms][PATCH V1 6/7] Platform/Sgi: Fix ACPI Low Power Idle states for RD-N2
RD-N2 platform supports only the platform co-ordinated LPI. So fix the
LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method. As
the cpus are directly connected to the interconnect on this platform,
remove the cluster _LPI control method as well.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 78 +---
1 file changed, 4 insertions(+), 74 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
index ccd98f829652..0f63ca42d505 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
@@ -62,38 +62,16 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Return (Arg3)
}
-Name (CLPI, Package () { /* LPI for Cluster, support 1 LPI state */
- 0, // Version
- 0, // Level Index
- 1, // Count
- Package () {// Power Gating state for Cluster
-2500, // Min residency (uS)
-1150, // Wake latency (uS)
-1,// Flags
-1,// Arch Context Flags
-100, // Residency Counter Frequency
-0,// No Parent State
-0x0020, // Integer Entry method
-ResourceTemplate () { // Null Residency Counter
- Register (SystemMemory, 0, 0, 0, 0)
-},
-ResourceTemplate () { // Null Usage Counter
- Register (SystemMemory, 0, 0, 0, 0)
-},
-"LPI2-Cluster"
- },
-})
-
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -116,8 +94,8 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
-1,// Parent node can be in any shallower state
+0,// Residency Counter Frequency
+0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
32, // Bit Width
@@ -139,9 +117,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL00) { // Cluster 0
Name (_HID, "ACPI0010")
Name (_UID, 0)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP00) { // Neoverse N2 core 0
Name (_HID, "ACPI0007")
@@ -166,9 +141,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL01) { // Cluster 1
Name (_HID, "ACPI0010")
Name (_UID, 1)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP01) { // Neoverse N2 core 1
Name (_HID, "ACPI0007")
@@ -193,9 +165,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL02) { // Cluster 2
Name (_HID, "ACPI0010")
Name (_UID, 2)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP02) { // Neoverse N2 core 2
Name (_HID, "ACPI0007")
@@ -220,9 +189,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Device (CL03) { // Cluster 3
Name (_HID, "ACPI0010")
Name (_UID, 3)
- Method (_LPI, 0, NotSerialized) {
-Return (\_SB.CLPI)
- }
Device (CP03) { // Neoverse N2 core 3
Name (_HID, "ACPI0007")
@@ -247,9 +213,6 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Devic
[edk2-devel] [edk2-platforms][PATCH V1 5/7] Platform/Sgi: Fix ACPI Low Power Idle states for RD-V1-MC
RD-V1-MC platform supports only the platform co-ordinated LPI. So fix
the LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
index e084d82de7c0..152a3076fedd 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl
@@ -64,14 +64,14 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -94,8 +94,8 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
-1,// Parent node can be in any shallower state
+0,// Residency Counter Frequency
+0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
32, // Bit Width
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V1 3/7] Platform/Sgi: Fix ACPI Low Power Idle states for RD-N1-Edge-X2
RD-N1-Edge-X2 platform supports only the platform co-ordinated LPI. So
fix the LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
index 9cb2b175418c..28e255c6de6e 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl
@@ -60,7 +60,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
1150, // Wake latency (uS)
1,// Flags
1,// Arch Context Flags
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No Parent State
0x0020, // Integer Entry method
ResourceTemplate () { // Null Residency Counter
@@ -75,14 +75,14 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -105,7 +105,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
1,// Parent node can be in any shallower state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V1 4/7] Platform/Sgi: Fix ACPI Low Power Idle states for RD-V1
RD-V1 platform supports only the platform co-ordinated LPI. So fix the
LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
index db9c19780e16..3c9c878dd880 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl
@@ -64,14 +64,14 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -94,8 +94,8 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
-1,// Parent node can be in any shallower state
+0,// Residency Counter Frequency
+0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
32, // Bit Width
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V1 2/7] Platform/Sgi: Fix ACPI Low Power Idle states for RD-N1-Edge
RD-N1-Edge platform supports only the platform co-ordinated LPI. So fix
the LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
index bd8efa544a59..7b4bbd36d8c0 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl
@@ -58,7 +58,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
1150, // Wake latency (uS)
1,// Flags
1,// Arch Context Flags
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No Parent State
0x0020, // Integer Entry method
ResourceTemplate () { // Null Residency Counter
@@ -73,14 +73,14 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -103,7 +103,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
1,// Parent node can be in any shallower state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V1 0/7] Fix ACPI Low Power Idle states for RD platforms
The DSDT ACPI table used for Neoverse reference design platforms include the _LPI control method for the kernel to enter idle states. This patch series fixes bugs in the existing _LPI control method due to which certain high level OS failed to boot on the supported Neoverse reference design platforms. For each platform, the fixes include - clearing level ID value as the platform supports only platform co-ordinated _LPI and removing residency counter frequency as the platform does not implement residency counter. In addition to this, the RD-N2 and RD-N2-Cfg1 platforms are direct connect platforms and so the _LPI control method for cluster is removed. Link to github branch with the patches in this series - https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/lpi_fix_for_rd_platforms Pranav Madhu (7): Platform/Sgi: Fix ACPI Low Power Idle states for SGI575 Platform/Sgi: Fix ACPI Low Power Idle states for RD-N1-Edge Platform/Sgi: Fix ACPI Low Power Idle states for RD-N1-Edge-X2 Platform/Sgi: Fix ACPI Low Power Idle states for RD-V1 Platform/Sgi: Fix ACPI Low Power Idle states for RD-V1-MC Platform/Sgi: Fix ACPI Low Power Idle states for RD-N2 Platform/Sgi: Fix ACPI Low Power Idle states for RD-N2-Cfg1 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 8 +- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 8 +- Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 78 +--- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 54 +- Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 8 +- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 8 +- Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 8 +- 7 files changed, 28 insertions(+), 144 deletions(-) -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90411): https://edk2.groups.io/g/devel/message/90411 Mute This Topic: https://groups.io/mt/91652410/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH V1 1/7] Platform/Sgi: Fix ACPI Low Power Idle states for SGI575
SGI-575 platform supports only the platform co-ordinated LPI. So fix the
LPI Level ID value accordingly.
Additionally, as this platform does not support residency counter, clear
the residency counter frequency from _LPI object's control method.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
index a292d20d8afb..a6187995be56 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl
@@ -57,7 +57,7 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI", EFI_ACPI_ARM_OEM
1150, // Wake latency (uS)
1,// Flags
1,// Arch Context Flags
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No Parent State
0x0020, // Integer Entry method
ResourceTemplate () { // Null Residency Counter
@@ -72,14 +72,14 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI", EFI_ACPI_ARM_OEM
Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
0, // Version
- 1, // Level Index
+ 0, // Level Index
2, // Count
Package () {// WFI for CPU
1,// Min residency (uS)
1,// Wake latency (uS)
1,// Flags
0,// Arch Context lost Flags (no loss)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
0,// No parent state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
@@ -102,7 +102,7 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI", EFI_ACPI_ARM_OEM
350, // Wake latency (uS)
1,// Flags
1,// Arch Context lost Flags (Core context lost)
-100, // Residency Counter Frequency
+0,// Residency Counter Frequency
1,// Parent node can be in any shallower state
ResourceTemplate () { // Register Entry method
Register (FFixedHW,
--
2.25.1
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[edk2-devel] [edk2-platforms][PATCH V3 8/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N2 platform
Update the RD-N2 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 163 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 86 ++-
2 files changed, 133 insertions(+), 116 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
index dbb23683113a..cdf8b3f2e953 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N2
platform
+ is included in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,112 +27,113 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts[6];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts[6];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N
[edk2-devel] [edk2-platforms][PATCH V3 9/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N2-Cfg1 platform
Update the RD-N2-Cfg1 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 82 +++---
2 files changed, 102 insertions(+), 92 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
index c6bb29a25c61..65926027eadf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
@@ -1,23 +1,22 @@
/** @file
-* Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
-*
-* This file lists all the processors available on the platform that the OSPM
-* can enumerate and boot. It also lists all the interrupt controllers available
-* in the system.
-*
-* Copyright (c) 2021, Arm Ltd. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Table
+ Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N2-Cfg1
+ platform is included in this table.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
#include
#include
#include
-#include
-
#include "SgiAcpiHeader.h"
#include "SgiPlatform.h"
@@ -28,69 +27,70 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts[3];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts[3];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
- 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
- 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
- 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
-
[edk2-devel] [edk2-platforms][PATCH V3 7/9] Platform/Sgi: Update ACPI version to v6.4 for RD-V1-MC platform
Update the RD-V1-MC platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 64
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc | 165 ++--
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 92 ++-
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc | 82 +-
4 files changed, 218 insertions(+), 185 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
index c2dad0e137d5..b8485cd98ea4 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
@@ -1,17 +1,25 @@
/** @file
-* Heterogeneous Memory Attribute Table (HMAT)
-*
-* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ The (HMAT) describes the memory attributes, such as memory side cache
+ attributes and bandwidth and latency details, related to Memory Proximity
+ Domains. The software is expected to use this information as a hint for
+ optimization, or when the system has heterogeneous memory. The attributes of
+ the memory connected to the two chips on this platform are listed in this
+ table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute Table
**/
-#include
#include
#include
-#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
#define INITATOR_PROXIMITY_DOMAIN_CNT 4
@@ -29,14 +37,14 @@ typedef struct InitiatorTargetProximityMatrix {
} INITIATOR_TARGET_PROXIMITY_MATRIX;
typedef struct {
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
INITIATOR_TARGET_PROXIMITY_MATRIX
Matrix;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache2;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache3;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache2;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache3;
} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
#pragma pack ()
@@ -45,9 +53,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
),
{
EFI_ACPI_RESERVED_BYTE,
@@ -59,19 +67,19 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Memory Proximity Domain
{
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x0, 0x0),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x1, 0x1),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x2, 0x2),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x3, 0x3),
},
// Latency Info
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
-0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXI
[edk2-devel] [edk2-platforms][PATCH V3 6/9] Platform/Sgi: Update ACPI version to v6.4 for RD-V1 platform
Update the RD-V1 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 ++--
Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 86 ++-
2 files changed, 131 insertions(+), 114 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
index c4551e92c0f2..374b0e2bddbf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-V1
platform
+ is included in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,110 +27,111 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts[4];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts[4];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6
[edk2-devel] [edk2-platforms][PATCH V3 5/9] Platform/Sgi: Update ACPI version to v6.4 for RD-E1-Edge platform
Update the RD-E1-Edge platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 ++--
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 127 +-
2 files changed, 202 insertions(+), 172 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
index cb70394bfe91..0b2bba575bf5 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-E1-Edge
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,173 +27,174 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-0 Thread-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1
- 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1
+ 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0
- 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-0
+ 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6
[edk2-devel] [edk2-platforms][PATCH V3 4/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge-X2 platform
Update the RD-N1-Edge-X2 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 52 ---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 151 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 115 +--
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc | 74 +-
4 files changed, 219 insertions(+), 173 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
index 704708f94baf..4a55c33396b6 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
@@ -1,17 +1,25 @@
/** @file
-* Heterogeneous Memory Attribute Table (HMAT)
-*
-* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ The (HMAT) describes the memory attributes, such as memory side cache
+ attributes and bandwidth and latency details, related to Memory Proximity
+ Domains. The software is expected to use this information as a hint for
+ optimization, or when the system has heterogeneous memory. The attributes of
+ the memory connected to the two chips on this platform are listed in this
+ table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute Table
**/
-#include
#include
#include
-#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
#define INITATOR_PROXIMITY_DOMAIN_CNT 2
@@ -29,12 +37,12 @@ typedef struct InitiatorTargetProximityMatrix {
} INITIATOR_TARGET_PROXIMITY_MATRIX;
typedef struct {
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
INITIATOR_TARGET_PROXIMITY_MATRIX
Matrix;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
#pragma pack ()
@@ -43,9 +51,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
),
{
EFI_ACPI_RESERVED_BYTE,
@@ -57,15 +65,15 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Memory Proximity Domain
{
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x0, 0x0),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x1, 0x1),
},
// Latency Info
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
-0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+0, 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
{
{0, 1},
{0, 1},
@@ -82,7 +90,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
},
// Memory Side Cache
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x0,
SIZE_8MB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
@@ -94,7 +102,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
),
0),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_
[edk2-devel] [edk2-platforms][PATCH V3 2/9] Platform/Sgi: Update ACPI version to v6.4 for SGI575 platform
Update the SGI575 platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc | 105 +++-
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 104 +++
2 files changed, 118 insertions(+), 91 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
index f04b77929d71..d3d7d946655f 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the SGI-575
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORES (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,75 +27,76 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTUREGicInterfaces[CORES];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTUREGicInterfaces[CORES];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0, // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-2
+ 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
[edk2-devel] [edk2-platforms][PATCH V3 3/9] Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge platform
Update the RD-N1-Edge platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 ++-
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 108
2 files changed, 121 insertions(+), 92 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
index 05eb78c5616a..df2576e1d9b7 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N1-Edge
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,75 +27,76 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neover
[edk2-devel] [edk2-platforms][PATCH V3 1/9] Platform/Sgi: Update ACPI version to v6.4
Update the common ACPI tables used by all the Neoverse Reference Design
platforms to ACPI version v6.4. Significant changes introduced are
update API/macro definitions to incorporate with the extra fields
introduced in ACPI 6.4, such as SPE overflow interrupt number field to
GICC structure of MADT table and adding cache ID field to the cache
structure of PPTT table.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 227 ++--
Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc| 30 +--
Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc| 38 ++--
Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc| 69 +++---
Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc| 26 +--
Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc| 29 ++-
6 files changed, 227 insertions(+), 192 deletions(-)
diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index e9b6923cb035..8393897cd4e8 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018-2021, ARM Limited. All rights reserved.
+* Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -41,134 +41,143 @@
#define OSC_CAP_PLAT_COORDINATED_LPI (1U << 7)
#define OSC_CAP_OS_INITIATED_LPI (1U << 8)
+// Cache type identifier used to calculate unique cache ID for PPTT
+typedef enum {
+ L1DataCache,
+ L1InstructionCache,
+ L2Cache,
+ L3Cache,
+} RD_PPTT_CACHE;
+
#pragma pack(1)
// PPTT processor core structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Core;
UINT32 ResourceOffset[2];
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L2Cache;
} RD_PPTT_CORE;
// PPTT processor cluster structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster;
UINT32 ResourceOffset;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L3Cache;
RD_PPTT_CORE Core[CORE_COUNT];
} RD_PPTT_CLUSTER;
// PPTT processor cluster structure without cache
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster;
RD_PPTT_CORE Core[CORE_COUNT];
} RD_PPTT_MINIMAL_CLUSTER;
// PPTT processor package structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package;
RD_PPTT_MINIMAL_CLUSTERCluster[CLUSTER_COUNT];
} RD_PPTT_PACKAGE;
#pragma pack ()
//
// PPTT processor structure flags for different SoC components as defined in
-// ACPI 6.3 specification
+// ACPI 6.4 specification
//
// Processor structure flags for SoC package
#define PPTT_PROCESSOR_PACKAGE_FLAGS
\
{
\
-EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
\
-EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
\
-EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
\
+EFI_ACPI_6_4_PPTT_PACKAGE_PHYSICAL,
\
+EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID,
\
+EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD,
\
+EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF,
\
+EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL
\
}
// Processor structure flags for cluster
#define PPTT_PROCESSOR_CLUSTER_FLAGS
\
{
\
-EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
\
-EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
\
-EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
\
+EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL,
\
+EFI_ACPI_6_4_PPTT_PROCES
[edk2-devel] [edk2-platforms][PATCH V3 0/9] Upadate the ACPI tables for RD platforms
Changes since V2: - Rebased on top of latest master branch - Update PPTT table with unique cache ID across the system for different levels of cache. Changes since V1: - Rebased on top of latest master branch. - Rebased on top of patch to remove SLC cache entries from PPTT (link for the same in edk2.groups.io is provided below) Arm infrastructure reference design platforms uses ACPI tables to provide the hardware information to the operating system. Currently the ACPI tables are aligned with ACPI v6.2 and v6.3 specification. This patch series update the tables to ACPI v6.4 specificaion. Features like MPAM relies on cache ID field of PPTT tables to distinguish between different physical caches, which is introduced in PPTT table in ACPI v6.4. Also ServerReady (SBBR compliaance) strictly recomments all the tables in the system should allign with same version of ACPI. Hence upgrade all ACPI tables mentioned in ACPI specification to v6.4. The first patch in this series update the generic tables which are common for all platfoms. The subsequent patches in this series update platform specific ACPI tables to v6.4 for the respective platform. This patch series also update the headers in the .aslc files to match the coding style as per edk2 coding guidelines. Link to github branch with the patches in this series - https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/acpi64_for_rd_platforms Pranav Madhu (9): Platform/Sgi: Update ACPI version to v6.4 Platform/Sgi: Update ACPI version to v6.4 for SGI575 platform Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge platform Platform/Sgi: Update ACPI version to v6.4 for RD-N1-Edge-X2 platform Platform/Sgi: Update ACPI version to v6.4 for RD-E1-Edge platform Platform/Sgi: Update ACPI version to v6.4 for RD-V1 platform Platform/Sgi: Update ACPI version to v6.4 for RD-V1-MC platform Platform/Sgi: Update ACPI version to v6.4 for RD-N2 platform Platform/Sgi: Update ACPI version to v6.4 for RD-N2-Cfg1 platform Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 227 +- Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc| 30 ++- Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc| 38 +-- Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc| 69 +++--- Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc| 26 ++- Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 ++-- Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 127 +- Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 + Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 108 + Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 52 +++-- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 151 ++-- Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 115 + Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc | 74 +++--- Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 163 ++--- Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 86 --- Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 - Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 82 --- Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 +++-- Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 86 --- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 64 ++--- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc | 165 ++--- Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 92 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc | 82 --- Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc | 105 + Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 104 + Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc| 29 ++- 26 files changed, 1471 insertions(+), 1227 deletions(-) -- 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#90399): https://edk2.groups.io/g/devel/message/90399 Mute This Topic: https://groups.io/mt/91650531/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
Re: [edk2-devel] [edk2-platforms][PATCH V2 0/9] Upadate the ACPI tables for RD platforms
Hi Ard, Thanks for your time in reviewing this patch series. Please find my response inline. > -Original Message- > From: Ard Biesheuvel > Sent: Wednesday, April 20, 2022 1:11 PM > To: Pranav Madhu > Cc: edk2-devel-groups-io ; Ard Biesheuvel > ; Sami Mujawar > Subject: Re: [edk2-platforms][PATCH V2 0/9] Upadate the ACPI tables for RD > platforms > > On Mon, 18 Apr 2022 at 13:54, Pranav Madhu > wrote: > > > > Changes since V1: > > - Rebased on top of latest master branch. > > - Rebased on top of patch to remove SLC cache entries from PPTT (link > > for the same in edk2.groups.io is provided below) > > > > Arm infrastructure reference design platforms uses ACPI tables to > > provide the hardware information to the operating system. Currently > > the ACPI tables are aligned with ACPI v6.2 and v6.3 specification. > > This patch series update the tables to ACPI v6.4 specificaion. > > > > Why is this necessary? By doing this, you will lose the ability to boot an OS > that > implements ACPI 6.2 but not ACPI 6.4, and so this should only be done if you > are > actually relying on a feature that was not available in ACPI 6.2. Otherwise, > this > is just pointless busywork. > As per SystemReady SBBR specification, all the ACPI tables should adhere to a specific ACPI revision. At present the FADT, GTDT, MADT... tables are as per ACPI specification 6.2 and PPTT, HMAT... tables are as per specification 6.3. To achieve compliance, we need to either downgrade some tables to 6.2 or else upgrade the rest of the tables to 6.3. As a solution for this, upgrade all tables to 6.4 as this is the most recent. The effort required to bring all tables to ACPI 6.3 and 6.4 are almost same. Also, with ACPI 6.4 we successfully validated WinPE and other Linux distributions. > > > The first patch in this series update the generic tables which are > > common for all platfoms. The subsequent patches in this series update > > platform specific ACPI tables to v6.4 for the respective platform. > > > > This patch series also update the headers in the .aslc files to match > > the coding style as per edk2 coding guidelines. > > > > This patch series should be applied on top of the patch series > > https://edk2.groups.io/g/devel/message/88996 > > > > Link to github branch with the patches in this series - > > https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/acpi64_for_ > > rd_platforms > > > > > > Pranav Madhu (9): > > Platform/Sgi: Update ACPI version to v6.4 > > Platform/Sgi: Update ACPI version to v6.4 for SGI-575 platform > > Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge platform > > Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge-X2 platform > > Platform/Sgi: Update ACPI version to v6.4 for Rd-E1-Edge platform > > Platform/Sgi: Update ACPI version to v6.4 for Rd-V1 platform > > Platform/Sgi: Update ACPI version to v6.4 for Rd-V1-MC platform > > Platform/Sgi: Update ACPI version to v6.4 for Rd-N2 platform > > Platform/Sgi: Update ACPI version to v6.4 for Rd-N2-Cfg1 platform > > > > Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 219 > > Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc | 30 ++- > > Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc | 38 +-- > > Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc | 69 ++--- > > Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc | 26 +- > > .../ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 > > +- .../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | > > 106 .../ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 > > .../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 88 --- > > .../SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc| 52 ++-- > > .../SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc| 151 ++- > > .../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc| 92 +++ > > .../SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc| 74 +++--- > > Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 163 ++-- > > Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 77 +++--- > > .../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 > > .../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 73 +++--- > > Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 +-- > > Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 77 +++--- > > .../ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc| 64 +++-- > > .../ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc| 165 ++-- > > .../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc| 81 +++--- > > .../ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc| 82
Re: [edk2-devel] [edk2-platforms][PATCH V1 1/1] Platform/Sgi: Remove SLC entry from PPTT table
Hi Ard, Please find my response inline. > -Original Message- > From: Ard Biesheuvel > Sent: Wednesday, April 20, 2022 1:05 PM > To: Pranav Madhu > Cc: edk2-devel-groups-io ; Ard Biesheuvel > ; Sami Mujawar > Subject: Re: [edk2-platforms][PATCH V1 1/1] Platform/Sgi: Remove SLC entry > from PPTT table > > On Mon, 18 Apr 2022 at 10:14, Pranav Madhu > wrote: > > > > Remove system level cache (SLC) entry from ACPI PPTT table. SLC on the > > Neoverse reference design platforms is the memory side cache and so it > > is removed from PPTT table. > > > > Could you elaborate? Why does the former justify/imply the latter? The SLC cache in Neoverse reference design is not a processor resource, instead it is an interconnect resource. As PPTT is used to describe the processor topology and processor resources, it is better to remove the SLC cache from PPTT and the best place for SLC is HMAT/SRAT tables. > > > Signed-off-by: Pranav Madhu > > --- > > Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 4 +--- > > Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 24 > > +++- > > Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 20 +++- > > Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 23 +++--- > - > > Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 21 - > > Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 21 - > > Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 21 - > > Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 23 > > ------- > > 8 files changed, 26 insertions(+), 131 deletions(-) > > > > Link to github branch for this patch - > > https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/remove_slc_ > > from_pptt > > <...> Regards, Pranav -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89121): https://edk2.groups.io/g/devel/message/89121 Mute This Topic: https://groups.io/mt/90535814/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH V2 7/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-V1-MC platform
Update the Rd-V1 multichip platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 64
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc | 165 ++--
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 81 +-
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc | 82 +-
4 files changed, 207 insertions(+), 185 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
index c2dad0e137d5..b8485cd98ea4 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
@@ -1,17 +1,25 @@
/** @file
-* Heterogeneous Memory Attribute Table (HMAT)
-*
-* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ The (HMAT) describes the memory attributes, such as memory side cache
+ attributes and bandwidth and latency details, related to Memory Proximity
+ Domains. The software is expected to use this information as a hint for
+ optimization, or when the system has heterogeneous memory. The attributes of
+ the memory connected to the two chips on this platform are listed in this
+ table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute Table
**/
-#include
#include
#include
-#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
#define INITATOR_PROXIMITY_DOMAIN_CNT 4
@@ -29,14 +37,14 @@ typedef struct InitiatorTargetProximityMatrix {
} INITIATOR_TARGET_PROXIMITY_MATRIX;
typedef struct {
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
INITIATOR_TARGET_PROXIMITY_MATRIX
Matrix;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache2;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache3;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache2;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache3;
} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
#pragma pack ()
@@ -45,9 +53,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
),
{
EFI_ACPI_RESERVED_BYTE,
@@ -59,19 +67,19 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Memory Proximity Domain
{
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x0, 0x0),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x1, 0x1),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x2, 0x2),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x3, 0x3),
},
// Latency Info
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
-0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+0, 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
[edk2-devel] [edk2-platforms][PATCH V2 9/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N2-Cfg1 platform
Update the Rd-N2-Cfg1 platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 73 ++---
2 files changed, 93 insertions(+), 92 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
index c6bb29a25c61..65926027eadf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
@@ -1,23 +1,22 @@
/** @file
-* Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
-*
-* This file lists all the processors available on the platform that the OSPM
-* can enumerate and boot. It also lists all the interrupt controllers available
-* in the system.
-*
-* Copyright (c) 2021, Arm Ltd. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Table
+ Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N2-Cfg1
+ platform is included in this table.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
#include
#include
#include
-#include
-
#include "SgiAcpiHeader.h"
#include "SgiPlatform.h"
@@ -28,69 +27,70 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts[3];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts[3];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
- 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
- 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
- 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6
- 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
-
[edk2-devel] [edk2-platforms][PATCH V2 8/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N2 platform
Update the Rd-N2 platform specific ACPI tables to ACPI version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 163 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 77 -
2 files changed, 124 insertions(+), 116 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
index dbb23683113a..cdf8b3f2e953 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N2
platform
+ is included in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,112 +27,113 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts[6];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts[6];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */
[edk2-devel] [edk2-platforms][PATCH V2 6/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-V1 platform
Update the Rd-V1 platform specific ACPI tables to ACPI version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 ++--
Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 77 +-
2 files changed, 122 insertions(+), 114 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
index c4551e92c0f2..374b0e2bddbf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-V1
platform
+ is included in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,110 +27,111 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts[4];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts[4];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_I
[edk2-devel] [edk2-platforms][PATCH V2 4/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge-X2 platform
Update the Rd-N1-Edge multichip platform specific ACPI tables to ACPI
version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 52 ---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 151 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 92 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc | 74 +-
4 files changed, 196 insertions(+), 173 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
index 704708f94baf..4a55c33396b6 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
@@ -1,17 +1,25 @@
/** @file
-* Heterogeneous Memory Attribute Table (HMAT)
-*
-* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ The (HMAT) describes the memory attributes, such as memory side cache
+ attributes and bandwidth and latency details, related to Memory Proximity
+ Domains. The software is expected to use this information as a hint for
+ optimization, or when the system has heterogeneous memory. The attributes of
+ the memory connected to the two chips on this platform are listed in this
+ table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute Table
**/
-#include
#include
#include
-#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
#define INITATOR_PROXIMITY_DOMAIN_CNT 2
@@ -29,12 +37,12 @@ typedef struct InitiatorTargetProximityMatrix {
} INITIATOR_TARGET_PROXIMITY_MATRIX;
typedef struct {
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
INITIATOR_TARGET_PROXIMITY_MATRIX
Matrix;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
#pragma pack ()
@@ -43,9 +51,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
),
{
EFI_ACPI_RESERVED_BYTE,
@@ -57,15 +65,15 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Memory Proximity Domain
{
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x0, 0x0),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x1, 0x1),
},
// Latency Info
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
-0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+0, 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
{
{0, 1},
{0, 1},
@@ -82,7 +90,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
},
// Memory Side Cache
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x0,
SIZE_8MB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
@@ -94,7 +102,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
),
0),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x1,
SIZE_8MB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
diff --git a
[edk2-devel] [edk2-platforms][PATCH V2 5/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-E1-Edge platform
Update the Rd-E1-Edge platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 ++--
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 106 -
2 files changed, 181 insertions(+), 172 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
index cb70394bfe91..0b2bba575bf5 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-E1-Edge
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,173 +27,174 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-0 Thread-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1
- 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1
+ 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0
- 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-0
+ 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // C
[edk2-devel] [edk2-platforms][PATCH V2 3/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge platform
Update the Rd-N1-Edge platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 +++-
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 88
2 files changed, 101 insertions(+), 92 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
index 05eb78c5616a..df2576e1d9b7 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N1-Edge
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,75 +27,76 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-2
+ 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01000
[edk2-devel] [edk2-platforms][PATCH V2 2/9] Platform/Sgi: Update ACPI version to v6.4 for SGI-575 platform
Update the SGI-575 platform specific ACPI tables to ACPI version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc | 105 +++-
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 86
2 files changed, 100 insertions(+), 91 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
index f04b77929d71..d3d7d946655f 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the SGI-575
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORES (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,75 +27,76 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTUREGicInterfaces[CORES];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTUREGicInterfaces[CORES];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0, // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-2
+ 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-3
- 0, 3, GET_MPID(0
[edk2-devel] [edk2-platforms][PATCH V2 1/9] Platform/Sgi: Update ACPI version to v6.4
Update the common ACPI tables used by all the Neoverse Reference Design
platforms to ACPI version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 219 ++--
Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc| 30 +--
Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc| 38 ++--
Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc| 69 +++---
Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc| 26 +--
Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc| 29 ++-
6 files changed, 219 insertions(+), 192 deletions(-)
diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index e9b6923cb035..72ece6cd153f 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018-2021, ARM Limited. All rights reserved.
+* Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -44,131 +44,132 @@
#pragma pack(1)
// PPTT processor core structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Core;
UINT32 ResourceOffset[2];
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L2Cache;
} RD_PPTT_CORE;
// PPTT processor cluster structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster;
UINT32 ResourceOffset;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L3Cache;
RD_PPTT_CORE Core[CORE_COUNT];
} RD_PPTT_CLUSTER;
// PPTT processor cluster structure without cache
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster;
RD_PPTT_CORE Core[CORE_COUNT];
} RD_PPTT_MINIMAL_CLUSTER;
// PPTT processor package structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package;
RD_PPTT_MINIMAL_CLUSTERCluster[CLUSTER_COUNT];
} RD_PPTT_PACKAGE;
#pragma pack ()
//
// PPTT processor structure flags for different SoC components as defined in
-// ACPI 6.3 specification
+// ACPI 6.4 specification
//
// Processor structure flags for SoC package
#define PPTT_PROCESSOR_PACKAGE_FLAGS
\
{
\
-EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
\
-EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
\
-EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
\
+EFI_ACPI_6_4_PPTT_PACKAGE_PHYSICAL,
\
+EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID,
\
+EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD,
\
+EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF,
\
+EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL
\
}
// Processor structure flags for cluster
#define PPTT_PROCESSOR_CLUSTER_FLAGS
\
{
\
-EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
\
-EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
\
-EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
\
+EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL,
\
+EFI_ACPI_6_4_PPTT_PROCESSOR_ID_VALID,
\
+EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD,
\
+EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF,
\
+EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL
\
}
// Processor structure flags for cluster with multi-thread core
#define PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS
[edk2-devel] [edk2-platforms][PATCH V2 0/9] Upadate the ACPI tables for RD platforms
Changes since V1: - Rebased on top of latest master branch. - Rebased on top of patch to remove SLC cache entries from PPTT (link for the same in edk2.groups.io is provided below) Arm infrastructure reference design platforms uses ACPI tables to provide the hardware information to the operating system. Currently the ACPI tables are aligned with ACPI v6.2 and v6.3 specification. This patch series update the tables to ACPI v6.4 specificaion. The first patch in this series update the generic tables which are common for all platfoms. The subsequent patches in this series update platform specific ACPI tables to v6.4 for the respective platform. This patch series also update the headers in the .aslc files to match the coding style as per edk2 coding guidelines. This patch series should be applied on top of the patch series https://edk2.groups.io/g/devel/message/88996 Link to github branch with the patches in this series - https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/acpi64_for_rd_platforms Pranav Madhu (9): Platform/Sgi: Update ACPI version to v6.4 Platform/Sgi: Update ACPI version to v6.4 for SGI-575 platform Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge platform Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge-X2 platform Platform/Sgi: Update ACPI version to v6.4 for Rd-E1-Edge platform Platform/Sgi: Update ACPI version to v6.4 for Rd-V1 platform Platform/Sgi: Update ACPI version to v6.4 for Rd-V1-MC platform Platform/Sgi: Update ACPI version to v6.4 for Rd-N2 platform Platform/Sgi: Update ACPI version to v6.4 for Rd-N2-Cfg1 platform Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 219 Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc | 30 ++- Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc | 38 +-- Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc | 69 ++--- Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc | 26 +- .../ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 +- .../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 106 .../ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 .../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 88 --- .../SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc| 52 ++-- .../SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc| 151 ++- .../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc| 92 +++ .../SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc| 74 +++--- Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 163 ++-- Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 77 +++--- .../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 .../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 73 +++--- Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 +-- Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 77 +++--- .../ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc| 64 +++-- .../ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc| 165 ++-- .../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc| 81 +++--- .../ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc| 82 +++--- .../ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc| 105 .../ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc| 86 +++--- Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc | 29 +- 26 files changed, 1343 insertions(+), 1227 deletions(-) -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88999): https://edk2.groups.io/g/devel/message/88999 Mute This Topic: https://groups.io/mt/90537675/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH V1 1/1] Platform/Sgi: Remove SLC entry from PPTT table
Remove system level cache (SLC) entry from ACPI PPTT table. SLC on the
Neoverse reference design platforms is the memory side cache and so it
is removed from PPTT table.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 4 +---
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 24 +++-
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 20 +++-
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 23 +++
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 21 -
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 21 -
Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 21 -
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 23 ---
8 files changed, 26 insertions(+), 131 deletions(-)
Link to github branch for this patch -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/remove_slc_from_pptt
diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index d75d54055436..e9b6923cb035 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -68,10 +68,8 @@ typedef struct {
// PPTT processor package structure
typedef struct {
EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
- UINT32 ResourceOffset;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
RD_PPTT_MINIMAL_CLUSTERCluster[CLUSTER_COUNT];
-} RD_PPTT_SLC_PACKAGE;
+} RD_PPTT_PACKAGE;
#pragma pack ()
//
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
index 3615a11d75b0..0ef9607c0732 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
@@ -8,7 +8,7 @@
* Each cluster includes a 2MB L3 cache. The platform also includes a system
* level cache of 8MB.
*
-* Copyright (c) 2021, ARM Limited. All rights reserved.
+* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -168,28 +168,12 @@
#define PPTT_PACKAGE_INIT(PackageId)
\
{
\
EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
\
- OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Slc),
\
+ OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Cluster[0]),
\
PPTT_PROCESSOR_PACKAGE_FLAGS,
\
0,
\
0,
\
- 1
\
+ 0
\
),
\
-
\
-/* Offsets of the private resources */
\
-OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
- Package.Slc),
\
-
\
-/* SLC parameters */
\
-EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
\
- PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
\
- 0, /* Next level of cache */
\
- SIZE_8MB, /* Size */
\
- 8192, /* Num of sets */
\
- 16, /* Associativity */
\
- PPTT_UNIFIED_CACHE_ATTR,/* Attributes */
\
- 64 /* Line size */
\
-),
\
-
\
{
\
PPTT_CLUSTER_INIT (PackageId, 0),
\
PPTT_CLUSTER_INIT (PackageId, 1),
\
@@ -219,8 +203,6 @@ typedef struct {
typedef struct {
EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
- UINT32 Offset;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
} RDE1EDGE_PPTT_PACKAGE;
diff --git a/Platform
[edk2-devel] [edk2-platforms][PATCH V1 1/1] Platform/Sgi: Replace EfiResetSystemLib with ResetSystemLib
Replace EfiResetSystemLib library with ResetSystemLib library. UEFI
ResetSystem() API is implemented in both these libraries, and the
implementation is also similar. The code for EfiResetSystemLib will be
removed from edk2. Update the platform build description files by
replacing EfiResetSystemLib with ResetSystemLib.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 4 ++--
Platform/ARM/SgiPkg/SgiPlatform.fdf | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
Link to github branch for this patch -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_resetlib
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
index 582efb0114c6..fd7fb11238d6 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -32,11 +32,11 @@
ArmPlatformSysConfigLib|Platform/ARM/VExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
ArmPlatformLib|Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
BasePathLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
-
EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
LcdHwLib|ArmPlatformPkg/Library/HdLcd/HdLcd.inf
LcdPlatformLib|Platform/ARM/SgiPkg/Library/HdLcdArmSgiLib/HdLcdArmSgiLib.inf
NorFlashPlatformLib|Platform/ARM/SgiPkg/Library/NorFlashLib/NorFlashLib.inf
HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+
ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf
TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
!if $(SECURE_BOOT_ENABLE) == TRUE
MmUnblockMemoryLib|MdePkg/Library/MmUnblockMemoryLib/MmUnblockMemoryLibNull.inf
@@ -258,10 +258,10 @@
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
!if $(SECURE_BOOT_ENABLE) == TRUE
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.fdf
b/Platform/ARM/SgiPkg/SgiPlatform.fdf
index 21eeb3706ba0..4018480b424c 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.fdf
+++ b/Platform/ARM/SgiPkg/SgiPlatform.fdf
@@ -87,10 +87,10 @@ READ_LOCK_STATUS = TRUE
INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
INF
MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
!if $(SECURE_BOOT_ENABLE) == TRUE
INF
SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
--
2.17.1
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[edk2-devel] [edk2][PATCH V3 1/1] ArmPkg: Handle warm reboot request correctly
The warm reboot requests were mapped to cold reboot as the power control
module was not capable of handling the warm reboot requests. That has
changed now and power control module supports warm reboot. Accordingly,
update ArmSmcPsciResetSystemLib and to invoke the PSCI call with
parameters for warm reboot.
Signed-off-by: Pranav Madhu
---
ArmPkg/Include/IndustryStandard/ArmStdSmc.h| 2 ++
ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c | 19
+--
2 files changed, 19 insertions(+), 2 deletions(-)
Changes since V1:
- Addressed comments from Ard.
Changes since V2:
- Remove 32 bit warm reboot PSCI support.
- Update ResetWarm() to check whether platform support warm reset.
- Addressed comments from Sami
Link to github branch for this patch -
https://github.com/Pranav-Madhu/edk2/tree/topics/warm_reboot
diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
index 655edc21b205..2025f5f10419 100644
--- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
@@ -93,6 +93,8 @@
#define ARM_SMC_ID_PSCI_MIGRATE_AARCH320x8405
#define ARM_SMC_ID_PSCI_SYSTEM_OFF 0x8408
#define ARM_SMC_ID_PSCI_SYSTEM_RESET 0x8409
+#define ARM_SMC_ID_PSCI_FEATURES 0x840A
+#define ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64 0xc412
/* The current PSCI version is: 0.2 */
#define ARM_SMC_PSCI_VERSION_MAJOR 0
diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c
b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c
index af6738459e43..4cc91a508d09 100644
--- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c
+++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c
@@ -3,6 +3,7 @@
Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.
Copyright (c) 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Arm Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -47,8 +48,22 @@ ResetWarm (
VOID
)
{
- // Map a warm reset into a cold reset
- ResetCold ();
+ UINTN Arg1 = ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64;
+ UINTN ret;
+
+ // Is SYSTEM_RESET2 supported?
+ ret = ArmCallSmc0 (ARM_SMC_ID_PSCI_FEATURES, , NULL, NULL);
+ if (ret == ARM_SMC_PSCI_RET_SUCCESS) {
+// Send PSCI SYSTEM_RESET2 command
+ArmCallSmc0 (ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64, NULL, NULL, NULL);
+ } else {
+// Map a warm reset into a cold reset
+DEBUG ((
+ DEBUG_INFO,
+ "Warm reboot not supported by platform, issuing cold reboot\n"
+ ));
+ResetCold ();
+ }
}
/**
--
2.17.1
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[edk2-devel] [edk2][PATCH V1 1/1] ArmPkg: Handle warm reboot request correctly
The warm reboot requests are mapped to cold reboot as the power control
module was not capable of handling the warm reboot requests in the
legacy implementation. The support for warm reboot support is added into
the power control module. To support warm reset, update
ArmPsciResetSystemLib, and there by invoke the PSCI call with parameters
for warm reboot.
Signed-off-by: Pranav Madhu
---
ArmPkg/Include/IndustryStandard/ArmStdSmc.h | 1 +
ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c | 7 +--
2 files changed, 6 insertions(+), 2 deletions(-)
Changes since V1:
- Addressed comments from Ard
Link to github branch for this patch -
https://github.com/Pranav-Madhu/edk2/tree/topics/warm_reboot
diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
index 655edc21b205..90123efcbd56 100644
--- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
@@ -93,6 +93,7 @@
#define ARM_SMC_ID_PSCI_MIGRATE_AARCH320x8405
#define ARM_SMC_ID_PSCI_SYSTEM_OFF 0x8408
#define ARM_SMC_ID_PSCI_SYSTEM_RESET 0x8409
+#define ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH32 0x8412
/* The current PSCI version is: 0.2 */
#define ARM_SMC_PSCI_VERSION_MAJOR 0
diff --git a/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
b/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
index 7bcd34849507..211941c57938 100644
--- a/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
+++ b/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
@@ -45,10 +45,13 @@ LibResetSystem (
ARM_SMC_ARGS ArmSmcArgs;
switch (ResetType) {
+case EfiResetWarm:
+ ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH32;
+ ArmSmcArgs.Arg1 = 0;
+ ArmSmcArgs.Arg2 = 0;
+ break;
case EfiResetPlatformSpecific:
// Map the platform specific reset as reboot
-case EfiResetWarm:
-// Map a warm reset into a cold reset
case EfiResetCold:
// Send a PSCI 0.2 SYSTEM_RESET command
ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
--
2.17.1
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Re: [edk2-devel] [edk2][PATCH V1 1/1] ArmPkg: Handle warm reboot request correctly
Hi Ard,
Thanks for your suggestions. Please find my reply inline.
Regards,
Pranav
> -Original Message-
> From: Ard Biesheuvel
> Sent: Thursday, March 10, 2022 8:56 PM
> To: Pranav Madhu
> Cc: edk2-devel-groups-io ; Ard Biesheuvel
> ; Sami Mujawar
> Subject: Re: [edk2][PATCH V1 1/1] ArmPkg: Handle warm reboot request
> correctly
>
> On Thu, 10 Mar 2022 at 14:10, Pranav Madhu
> wrote:
> >
> > The warm reboot requests are mapped to cold reboot as the power
> > control module was not capable of handling the warm reboot requests in
> > the legacy implementation. The support for warm reboot support is
> > added into the power control module. To support warm reset, update
> > ArmPsciResetSystemLib, and there by invoke the PSCI call with
> > parameters for warm reboot.
> >
> > Signed-off-by: Pranav Madhu
>
> What happens on 32-bit platforms with this change?
Will change this to PSCI_SYSTEM_RESET2_AARCH32, as this is compatible with
AARCH64 as well.
>
> What happens if the firmware does not implement
> ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64?
As per PSCI 1.1 specification, what I understood is before invoking
SYSTEM_RESET2, the OS should query the PSCI capabilities using PSCI_FEATURES
for SYSTEM_RESET2 support. The OS should invoke RESET2 only if PSCI_FEATURES
returns 0. If the OS is invoking this call without querying the features, PSCI
will return UNSUPPORTED.
>
> > ---
> > ArmPkg/Include/IndustryStandard/ArmStdSmc.h | 1 +
> > ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c | 7
> > +++++--
> > 2 files changed, 6 insertions(+), 2 deletions(-)
> >
> > Link to github branch for this patch -
> > https://github.com/Pranav-Madhu/edk2/tree/topics/warm_reboot
> >
> > diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
> > b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
> > index 655edc21b205..c9059dead6e9 100644
> > --- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
> > +++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
> > @@ -93,6 +93,7 @@
> > #define ARM_SMC_ID_PSCI_MIGRATE_AARCH320x8405
> > #define ARM_SMC_ID_PSCI_SYSTEM_OFF 0x8408
> > #define ARM_SMC_ID_PSCI_SYSTEM_RESET 0x8409
> > +#define ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64 0xc412
> >
> > /* The current PSCI version is: 0.2 */ #define
> > ARM_SMC_PSCI_VERSION_MAJOR 0 diff --git
> > a/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
> > b/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
> > index 7bcd34849507..27e048ba0f7a 100644
> > --- a/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
> > +++ b/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
> > @@ -45,10 +45,13 @@ LibResetSystem (
> >ARM_SMC_ARGS ArmSmcArgs;
> >
> >switch (ResetType) {
> > +case EfiResetWarm:
> > + ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64;
> > + ArmSmcArgs.Arg1 = 0;
> > + ArmSmcArgs.Arg2 = 0;
> > + break;
> > case EfiResetPlatformSpecific:
> > // Map the platform specific reset as reboot
> > -case EfiResetWarm:
> > -// Map a warm reset into a cold reset
> > case EfiResetCold:
> >// Send a PSCI 0.2 SYSTEM_RESET command
> >ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
> > --
> > 2.17.1
> >
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Re: [edk2-devel] [edk2][PATCH V1 1/1] ArmPkg: Handle warm reboot request correctly
Hi Sami,
Thanks for your comments. Please find my reply inline.
Regards,
Pranav
> -Original Message-
> From: Sami Mujawar
> Sent: Thursday, March 10, 2022 9:01 PM
> To: Pranav Madhu ; devel@edk2.groups.io
> Cc: Ard Biesheuvel ; nd
> Subject: Re: [edk2][PATCH V1 1/1] ArmPkg: Handle warm reboot request
> correctly
>
> Hi Pranav,
>
> Thank you for this patch.
>
> Please find my response inline marked [SAMI].
>
> Regards,
>
> Sami Mujawar
>
>
> On 10/03/2022 01:10 PM, Pranav Madhu wrote:
> > The warm reboot requests are mapped to cold reboot as the power
> > control module was not capable of handling the warm reboot requests in
> > the legacy implementation. The support for warm reboot support is
> > added into the power control module. To support warm reset, update
> > ArmPsciResetSystemLib, and there by invoke the PSCI call with
> > parameters for warm reboot.
> >
> > Signed-off-by: Pranav Madhu
> > ---
> > ArmPkg/Include/IndustryStandard/ArmStdSmc.h | 1 +
> > ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c | 7
> +--
> > 2 files changed, 6 insertions(+), 2 deletions(-)
> >
> > Link to github branch for this patch -
> > https://github.com/Pranav-Madhu/edk2/tree/topics/warm_reboot
> >
> > diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
> > b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
> > index 655edc21b205..c9059dead6e9 100644
> > --- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
> > +++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
> > @@ -93,6 +93,7 @@
> > #define ARM_SMC_ID_PSCI_MIGRATE_AARCH320x8405
> > #define ARM_SMC_ID_PSCI_SYSTEM_OFF 0x8408
> > #define ARM_SMC_ID_PSCI_SYSTEM_RESET 0x8409
> > +#define ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64 0xc412
> >
> > /* The current PSCI version is: 0.2 */
> > #define ARM_SMC_PSCI_VERSION_MAJOR 0 diff --git
> > a/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
> > b/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
> > index 7bcd34849507..27e048ba0f7a 100644
> > --- a/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
> > +++ b/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
> > @@ -45,10 +45,13 @@ LibResetSystem (
> > ARM_SMC_ARGS ArmSmcArgs;
> >
> > switch (ResetType) {
> > +case EfiResetWarm:
> > + ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64;
> > + ArmSmcArgs.Arg1 = 0;
> > + ArmSmcArgs.Arg2 = 0;
> > + break;
> [SAMI] SYSTEM_RESET2 is an optional feature and if not supported would
> return NOT_SUPPORTED. So, if a platform does not support SYSTEM_RESET2,
> should the code here fall back to SYSTEM_RESET?
> According to the PSCI specification, it is the responsibility of the OS to
> check
> that SYSTEM_RESET2 is supported before calling SYSTEM_RESET2 (I believe this
> is applicable for the case where UEFI is not used to boot the OS). However, if
> the runtime service ResetSystem() is invoked by the OS requesting a warm
> reset, is it not the firmware's responsibility to ensure that SYSTEM_RESET2 is
> supported? Any thoughts?
Right, from PSCI specification, what I understood is before invoking
SYSTEM_RESET2, the OS should query the PSCI capabilities using PSCI_FEATURES
for SYSTEM_RESET2. The OS should invoke RESET2 only if PSCI_FEATURES returns 0.
From spec, what I understood is it is not the responsibility of firmware. If OS
issue RESET2 without querying FEATURES, the only option for firmware is to
return NOT_SUPPORTED.
> [/SAMI]
> > case EfiResetPlatformSpecific:
> > // Map the platform specific reset as reboot
> > -case EfiResetWarm:
> > -// Map a warm reset into a cold reset
> > case EfiResetCold:
> > // Send a PSCI 0.2 SYSTEM_RESET command
> > ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
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[edk2-devel] [edk2][PATCH V1 1/1] ArmPkg: Handle warm reboot request correctly
The warm reboot requests are mapped to cold reboot as the power control
module was not capable of handling the warm reboot requests in the
legacy implementation. The support for warm reboot support is added into
the power control module. To support warm reset, update
ArmPsciResetSystemLib, and there by invoke the PSCI call with parameters
for warm reboot.
Signed-off-by: Pranav Madhu
---
ArmPkg/Include/IndustryStandard/ArmStdSmc.h | 1 +
ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c | 7 +--
2 files changed, 6 insertions(+), 2 deletions(-)
Link to github branch for this patch -
https://github.com/Pranav-Madhu/edk2/tree/topics/warm_reboot
diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
index 655edc21b205..c9059dead6e9 100644
--- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
+++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h
@@ -93,6 +93,7 @@
#define ARM_SMC_ID_PSCI_MIGRATE_AARCH320x8405
#define ARM_SMC_ID_PSCI_SYSTEM_OFF 0x8408
#define ARM_SMC_ID_PSCI_SYSTEM_RESET 0x8409
+#define ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64 0xc412
/* The current PSCI version is: 0.2 */
#define ARM_SMC_PSCI_VERSION_MAJOR 0
diff --git a/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
b/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
index 7bcd34849507..27e048ba0f7a 100644
--- a/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
+++ b/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c
@@ -45,10 +45,13 @@ LibResetSystem (
ARM_SMC_ARGS ArmSmcArgs;
switch (ResetType) {
+case EfiResetWarm:
+ ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET2_AARCH64;
+ ArmSmcArgs.Arg1 = 0;
+ ArmSmcArgs.Arg2 = 0;
+ break;
case EfiResetPlatformSpecific:
// Map the platform specific reset as reboot
-case EfiResetWarm:
-// Map a warm reset into a cold reset
case EfiResetCold:
// Send a PSCI 0.2 SYSTEM_RESET command
ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
--
2.17.1
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[edk2-devel] [edk2-platforms][PATCH V1 9/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N2-Cfg1 platform
Update the Rd-N2-Cfg1 platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 80 +++---
2 files changed, 97 insertions(+), 95 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
index c6bb29a25c61..65926027eadf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
@@ -1,23 +1,22 @@
/** @file
-* Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
-*
-* This file lists all the processors available on the platform that the OSPM
-* can enumerate and boot. It also lists all the interrupt controllers available
-* in the system.
-*
-* Copyright (c) 2021, Arm Ltd. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.12, Multiple APIC Description Table
+ Multiple APIC Description Table (MADT) for RD-N2-Cfg1 platform
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N2-Cfg1
+ platform is included in this table.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
#include
#include
#include
-#include
-
#include "SgiAcpiHeader.h"
#include "SgiPlatform.h"
@@ -28,69 +27,70 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts[3];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts[3];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
- 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
- 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
- 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
- 0, 0, 0, 25, 0, 0),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6
- 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
-
[edk2-devel] [edk2-platforms][PATCH V1 8/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N2 platform
Update the Rd-N2 platform specific ACPI tables to ACPI version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 163 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 84 +-
2 files changed, 128 insertions(+), 119 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
index dbb23683113a..cdf8b3f2e953 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N2
platform
+ is included in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,112 +27,113 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts[6];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts[6];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse N2 core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */
[edk2-devel] [edk2-platforms][PATCH V1 7/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-V1-MC platform
Update the Rd-V1 multichip platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 64
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc | 165 ++--
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 88 ++-
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc | 82 +-
4 files changed, 211 insertions(+), 188 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
index c2dad0e137d5..b8485cd98ea4 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
@@ -1,17 +1,25 @@
/** @file
-* Heterogeneous Memory Attribute Table (HMAT)
-*
-* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ The (HMAT) describes the memory attributes, such as memory side cache
+ attributes and bandwidth and latency details, related to Memory Proximity
+ Domains. The software is expected to use this information as a hint for
+ optimization, or when the system has heterogeneous memory. The attributes of
+ the memory connected to the two chips on this platform are listed in this
+ table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute Table
**/
-#include
#include
#include
-#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
#define INITATOR_PROXIMITY_DOMAIN_CNT 4
@@ -29,14 +37,14 @@ typedef struct InitiatorTargetProximityMatrix {
} INITIATOR_TARGET_PROXIMITY_MATRIX;
typedef struct {
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
INITIATOR_TARGET_PROXIMITY_MATRIX
Matrix;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache2;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache3;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache2;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache3;
} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
#pragma pack ()
@@ -45,9 +53,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
),
{
EFI_ACPI_RESERVED_BYTE,
@@ -59,19 +67,19 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Memory Proximity Domain
{
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x0, 0x0),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x1, 0x1),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x2, 0x2),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x3, 0x3),
},
// Latency Info
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
-0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+0, 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
[edk2-devel] [edk2-platforms][PATCH V1 6/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-V1 platform
Update the Rd-V1 platform specific ACPI tables to ACPI version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 ++--
Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 84 ++-
2 files changed, 126 insertions(+), 117 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
index c4551e92c0f2..374b0e2bddbf 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-V1
platform
+ is included in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,110 +27,111 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts[4];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts[4];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_I
[edk2-devel] [edk2-platforms][PATCH V1 5/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-E1-Edge platform
Update the Rd-E1-Edge platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 ++--
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 115 -
2 files changed, 186 insertions(+), 176 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
index cb70394bfe91..0b2bba575bf5 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-E1-Edge
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,173 +27,174 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-0 Thread-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-0 Thread-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-1
- 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-1
+ 0, 1, GET_MPID(0x0, 0x1), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Core-1 Thread-0
- 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Core-1 Thread-0
+ 0, 2, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // C
[edk2-devel] [edk2-platforms][PATCH V1 4/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge-X2 platform
Update the Rd-N1-Edge multichip platform specific ACPI tables to ACPI
version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 52 ---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc | 151 ++--
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 101 ++---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc | 74 +-
4 files changed, 201 insertions(+), 177 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
index 704708f94baf..4a55c33396b6 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
@@ -1,17 +1,25 @@
/** @file
-* Heterogeneous Memory Attribute Table (HMAT)
-*
-* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ The (HMAT) describes the memory attributes, such as memory side cache
+ attributes and bandwidth and latency details, related to Memory Proximity
+ Domains. The software is expected to use this information as a hint for
+ optimization, or when the system has heterogeneous memory. The attributes of
+ the memory connected to the two chips on this platform are listed in this
+ table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribute Table
**/
-#include
#include
#include
-#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
#define INITATOR_PROXIMITY_DOMAIN_CNT 2
@@ -29,12 +37,12 @@ typedef struct InitiatorTargetProximityMatrix {
} INITIATOR_TARGET_PROXIMITY_MATRIX;
typedef struct {
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER
Header;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES
Proximity[CHIP_CNT];
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO
LatencyInfo;
INITIATOR_TARGET_PROXIMITY_MATRIX
Matrix;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache0;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO
MemSideCache1;
} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
#pragma pack ()
@@ -43,9 +51,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
),
{
EFI_ACPI_RESERVED_BYTE,
@@ -57,15 +65,15 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
// Memory Proximity Domain
{
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x0, 0x0),
-EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
1, 0x1, 0x1),
},
// Latency Info
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
-0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+0, 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 100),
{
{0, 1},
{0, 1},
@@ -82,7 +90,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
},
// Memory Side Cache
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x0,
SIZE_8MB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
@@ -94,7 +102,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
),
0),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x1,
SIZE_8MB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
diff --git a
[edk2-devel] [edk2-platforms][PATCH V1 3/9] Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge platform
Update the Rd-N1-Edge platform specific ACPI tables to ACPI version
v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 +++-
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 97 +-
2 files changed, 106 insertions(+), 96 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
index 05eb78c5616a..df2576e1d9b7 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-N1-Edge
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,75 +27,76 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE
GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse-N1-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse-N1-2
+ 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01000
[edk2-devel] [edk2-platforms][PATCH V1 2/9] Platform/Sgi: Update ACPI version to v6.4 for SGI-575 platform
Update the SGI-575 platform specific ACPI tables to ACPI version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc | 105 +++-
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 86
2 files changed, 100 insertions(+), 91 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
index f04b77929d71..d3d7d946655f 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2018, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation on
+ systems with Generic interrupt controller (GIC). The information about the
GIC
+ CPU interface, redistributor, distributor and ITS blocks on the SGI-575
+ platform is included in this table.
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+- ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Table
**/
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include
#include
#include
-#include
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
#define CORES (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -21,75 +27,76 @@
#pragma pack (1)
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTUREGicInterfaces[CORES];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
- EFI_ACPI_6_2_GIC_ITS_STRUCTUREGicIts;
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTUREGicInterfaces[CORES];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTUREGicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_4_GIC_ITS_STRUCTUREGicIts;
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
#pragma pack ()
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0, // Flags
},
{
-// Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
+// Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr,
Flags,
// PmuIrq, GicBase, GicVBase,
// GicHBase, GsivId, GicRBase,
-// Efficiency)
+// Efficiency,
+// SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entry
-// (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+// (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-1
- 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-1
+ 0, 1, GET_MPID(0x0, 0x100), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-2
- 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c02, 0x2c01, 25, 0, 0, 0),
+EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // A75-2
+ 0, 2, GET_MPID(0x0, 0x200), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c02, 0x2c01, 25, 0 /* GicRBase */, 0 /* Efficiency */),
-EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // A75-3
- 0, 3, GET_MPID(0
[edk2-devel] [edk2-platforms][PATCH V1 1/9] Platform/Sgi: Update ACPI version to v6.4
Update the common ACPI tables used by all the Neoverse Reference Design
platforms to ACPI version v6.4.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 221 ++--
Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc| 30 +--
Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc| 38 ++--
Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc| 69 +++---
Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc| 26 +--
Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc| 29 ++-
6 files changed, 220 insertions(+), 193 deletions(-)
diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index d75d54055436..69af1df276a8 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018-2021, ARM Limited. All rights reserved.
+* Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -44,133 +44,134 @@
#pragma pack(1)
// PPTT processor core structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Core;
UINT32 ResourceOffset[2];
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L2Cache;
} RD_PPTT_CORE;
// PPTT processor cluster structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster;
UINT32 ResourceOffset;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE L3Cache;
RD_PPTT_CORE Core[CORE_COUNT];
} RD_PPTT_CLUSTER;
// PPTT processor cluster structure without cache
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Cluster;
RD_PPTT_CORE Core[CORE_COUNT];
} RD_PPTT_MINIMAL_CLUSTER;
// PPTT processor package structure
typedef struct {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR Package;
UINT32 ResourceOffset;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE Slc;
RD_PPTT_MINIMAL_CLUSTERCluster[CLUSTER_COUNT];
} RD_PPTT_SLC_PACKAGE;
#pragma pack ()
//
// PPTT processor structure flags for different SoC components as defined in
-// ACPI 6.3 specification
+// ACPI 6.4 specification
//
// Processor structure flags for SoC package
#define PPTT_PROCESSOR_PACKAGE_FLAGS
\
{
\
-EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
\
-EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
\
-EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
\
+EFI_ACPI_6_4_PPTT_PACKAGE_PHYSICAL,
\
+EFI_ACPI_6_4_PPTT_PROCESSOR_ID_INVALID,
\
+EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD,
\
+EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF,
\
+EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL
\
}
// Processor structure flags for cluster
#define PPTT_PROCESSOR_CLUSTER_FLAGS
\
{
\
-EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
\
-EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
\
-EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
\
-EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
\
+EFI_ACPI_6_4_PPTT_PACKAGE_NOT_PHYSICAL,
\
+EFI_ACPI_6_4_PPTT_PROCESSOR_ID_VALID,
\
+EFI_ACPI_6_4_PPTT_PROCESSOR_IS_NOT_THREAD,
\
+EFI_ACPI_6_4_PPTT_NODE_IS_NOT_LEAF,
\
+EFI_ACPI_6_4_PPTT_IMPLEMENTATION_IDENTICAL
\
}
// Processor structure flags for cluster with multi-thread core
#define PPTT_PROCESSOR_CLUSTER_THREADED_FLAGS
[edk2-devel] [edk2-platforms][PATCH V1 0/9] Upadate the ACPI tables for RD platforms
Arm infrastructure reference design platforms uses ACPI tables to provide the hardware information to the operating system. Currently the ACPI tables are aligned with ACPI v6.2 and v6.3 specification. This patch series update the tables to ACPI v6.4 specificaion. The first patch in this series update the generic tables which are common for all platfoms. The subsequent patches in this series update platform specific ACPI tables to v6.4 for the respective platform. This patch series also update the headers in the .aslc files to match the coding style as per edk2 coding guidelines. Link to github branch with the patches in this series - https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/acpi64_for_rd_platforms Pranav Madhu (9): Platform/Sgi: Update ACPI version to v6.4 Platform/Sgi: Update ACPI version to v6.4 for SGI-575 platform Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge platform Platform/Sgi: Update ACPI version to v6.4 for Rd-N1-Edge-X2 platform Platform/Sgi: Update ACPI version to v6.4 for Rd-E1-Edge platform Platform/Sgi: Update ACPI version to v6.4 for Rd-V1 platform Platform/Sgi: Update ACPI version to v6.4 for Rd-V1-MC platform Platform/Sgi: Update ACPI version to v6.4 for Rd-N2 platform Platform/Sgi: Update ACPI version to v6.4 for Rd-N2-Cfg1 platform Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 221 Platform/ARM/SgiPkg/AcpiTables/Dbg2.aslc | 30 ++- Platform/ARM/SgiPkg/AcpiTables/Fadt.aslc | 38 +-- Platform/ARM/SgiPkg/AcpiTables/Gtdt.aslc | 69 ++--- Platform/ARM/SgiPkg/AcpiTables/Mcfg.aslc | 26 +- .../ARM/SgiPkg/AcpiTables/RdE1Edge/Madt.aslc | 247 +- .../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 115 .../ARM/SgiPkg/AcpiTables/RdN1Edge/Madt.aslc | 105 .../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 97 +++ .../SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc| 52 ++-- .../SgiPkg/AcpiTables/RdN1EdgeX2/Madt.aslc| 151 ++- .../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc| 101 +++ .../SgiPkg/AcpiTables/RdN1EdgeX2/Srat.aslc| 74 +++--- Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 163 ++-- Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 84 +++--- .../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 112 .../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 80 +++--- Platform/ARM/SgiPkg/AcpiTables/RdV1/Madt.aslc | 159 +-- Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 84 +++--- .../ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc| 64 +++-- .../ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc| 165 ++-- .../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc| 88 --- .../ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc| 82 +++--- .../ARM/SgiPkg/AcpiTables/Sgi575/Madt.aslc| 105 .../ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc| 86 +++--- Platform/ARM/SgiPkg/AcpiTables/Spcr.aslc | 29 +- 26 files changed, 1375 insertions(+), 1252 deletions(-) -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#87406): https://edk2.groups.io/g/devel/message/87406 Mute This Topic: https://groups.io/mt/89684942/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH v2 5/5] Platform/Sgi: Cleanup build options for StandaloneMM context
From: Omkar Anand Kulkarni The Arm reference design platforms support only AArch64 mode for StandaloneMM execution context. So cleanup the existing build options specified for StandaloneMM. Signed-off-by: Omkar Anand Kulkarni Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc b/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc index 6839ec35da8a..2b461d5afbcb 100644 --- a/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc @@ -144,7 +144,5 @@ # ### [BuildOptions.AARCH64] - GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 -march=armv8-a+nofp - -[BuildOptions] - *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES + GCC:*_*_*_CC_FLAGS = -mstrict-align -march=armv8-a+nofp -D DISABLE_NEW_DEPRECATED_INTERFACES + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#76383): https://edk2.groups.io/g/devel/message/76383 Mute This Topic: https://groups.io/mt/83465460/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH v2 3/5] Platform/Sgi: define the macro ENABLE_GOP
From: Thomas Abraham Define and use the global macro ENABLE_GOP to enable the use of the Graphics Output Protocol (GOP). Enabling this macro allows GOP protocol to be used for display on the HDLCD controller of the platform. This macro is set to false by default for the all supported platforms. Signed-off-by: Thomas Abraham Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 5 + Platform/ARM/SgiPkg/SgiPlatform.fdf | 2 ++ 2 files changed, 7 insertions(+) diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc index e4aee7a09acf..2851cf180c0e 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc @@ -14,6 +14,9 @@ # Secure boot requires secure storage to be enabled as well. DEFINE SECURE_BOOT_ENABLE = FALSE + # To allow HDLCD display using the Graphics Output Protocol, set this to TRUE. + DEFINE ENABLE_GOP = FALSE + [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES @@ -234,7 +237,9 @@ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf ArmPkg/Drivers/TimerDxe/TimerDxe.inf ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf +!if $(ENABLE_GOP) == TRUE ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf +!endif ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf diff --git a/Platform/ARM/SgiPkg/SgiPlatform.fdf b/Platform/ARM/SgiPkg/SgiPlatform.fdf index d94e4633e36c..8227ae03330c 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.fdf +++ b/Platform/ARM/SgiPkg/SgiPlatform.fdf @@ -153,7 +153,9 @@ READ_LOCK_STATUS = TRUE INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf # Graphics Output Protocol +!if $(ENABLE_GOP) == TRUE INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf +!endif INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#76381): https://edk2.groups.io/g/devel/message/76381 Mute This Topic: https://groups.io/mt/83465458/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH v2 2/5] Platform/Sgi: Add GED support
Add ACPI Generic Event Device (GED) support for Arm's reference design
platforms. The SP804 dual-timer interrupt is used as the event source
for GED.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 5 ++
Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc| 5 ++
Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 5 ++
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/SsdtEvents.asl | 49
12 files changed, 88 insertions(+)
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index e0aabc566d88..ffbbb24f1c33 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -81,5 +81,10 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Size|0|UINT32|0x0020
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|0|UINT32|0x0021
+ # SP804 Dual Timer
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0|UINT32|0x0022
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0|UINT32|0x0023
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|0|UINT32|0x0024
+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b,
0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
index a567af8537ec..76707be73d7b 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
@@ -51,6 +51,11 @@
gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv|93
gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|94
+ # SP804 dual timer
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0x1C11
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0x0001
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|230
+
# SMMU
gArmSgiTokenSpaceGuid.PcdSmmuBase|0x4F00
gArmSgiTokenSpaceGuid.PcdSmmuSize|0x0100
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
index 5c137c0991e7..2d612f9b9674 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
@@ -51,6 +51,11 @@
gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv|110
gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|111
+ # SP804 dual timer
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0x0C11
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0x0001
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|486
+
# SMMU
gArmSgiTokenSpaceGuid.PcdSmmuBase|0x4000
gArmSgiTokenSpaceGuid.PcdSmmuSize|0x1000
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index 56b80f418398..8c34c2fa73e4 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -57,6 +57,9 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index fa6692bc86f6..8d46b001444c 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -57,6 +57,9 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index d0ee125fa1de..473c9eff0f55 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -66,6 +66,9 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
[edk2-devel] [edk2-platforms][PATCH v2 4/5] Platform/Sgi: update _OSC control method to control LPI and CPPC
Define and use the global macro LPI_EN and CPPC_EN to enable low power
idle and CPPC support for reference design platforms. Update platform
wide _OSC control method to enable/disable low power idle and CPPC
support based on pcd PcdOscLpiEnable and PcdOscCppcEnable. The pcds
are controlled by the global macros LPI_EN and CPPC_EN.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 4
Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 14 ++
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 2 ++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 2 ++
Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 2 ++
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 2 ++
Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 2 ++
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl| 8
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 8
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl| 15 +++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl| 15 +++
Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl| 15 +++
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 15 +++
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 8
17 files changed, 115 insertions(+)
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index ffbbb24f1c33..8cd818a9bf64 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -86,5 +86,9 @@
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0|UINT32|0x0023
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|0|UINT32|0x0024
+ # ACPI platform wide _OSC
+ gArmSgiTokenSpaceGuid.PcdOscLpiEnable|0|UINT32|0x0025
+ gArmSgiTokenSpaceGuid.PcdOscCppcEnable|0|UINT32|0x0026
+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b,
0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
index 2851cf180c0e..7e37732fb93c 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -17,6 +17,10 @@
# To allow HDLCD display using the Graphics Output Protocol, set this to
TRUE.
DEFINE ENABLE_GOP = FALSE
+ # To enable LPI and CPPC power management functionality, set this to TRUE.
+ DEFINE LPI_EN = FALSE
+ DEFINE CPPC_EN= FALSE
+
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
@@ -108,6 +112,16 @@
gArmSgiTokenSpaceGuid.PcdDramBlock2Base|0x808000
gArmSgiTokenSpaceGuid.PcdDramBlock2Size|0x18000
+!if $(LPI_EN) == TRUE
+ # Allow use of LPI in the response to _OSC method call
+ gArmSgiTokenSpaceGuid.PcdOscLpiEnable|1
+!endif
+
+!if $(CPPC_EN) == TRUE
+ # Allow use of CPPC in the response to _OSC method call
+ gArmSgiTokenSpaceGuid.PcdOscCppcEnable|1
+!endif
+
# NV Storage PCDs. Use base of 0x0800 for NOR0, 0xC000 for NOR 1
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x0140
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x0140
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index 8d46b001444c..ce89aa93ea7b 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -57,6 +57,7 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdOscLpiEnable
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index 473c9eff0f55..1999bc1553e9 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -66,6 +66,7 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdOscLpiEnable
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index c537db45e08f..25be2e276e85 100644
--- a/Platform/ARM/SgiPkg/AcpiTables
[edk2-devel] [edk2-platforms][PATCH v2 1/5] Platform/Sgi: Enable PrimeCell GPIO
The HW-Reduced ACPI model has specific requirements for GPIO
controllers. Arm's reference design Platforms has PrimeCell GPIO
(PL061) integrated in the RoS subsystem to provide GPIO support. Add
GPIO device entry and also add GPIO signalled ACPI event template for
reference.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 5 ++
Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc| 5 ++
Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 5 ++
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 5 ++
Platform/ARM/SgiPkg/AcpiTables/SsdtEvents.asl | 67
12 files changed, 115 insertions(+)
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index af08ed153eae..e0aabc566d88 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -76,5 +76,10 @@
gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT32|0x001D
gArmSgiTokenSpaceGuid.PcdSmmuSize|0|UINT32|0x001E
+ # GPIO Controller
+ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0|UINT32|0x001F
+ gArmSgiTokenSpaceGuid.PcdGpioController0Size|0|UINT32|0x0020
+ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|0|UINT32|0x0021
+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b,
0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
index d3d650323891..a567af8537ec 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
@@ -54,3 +54,8 @@
# SMMU
gArmSgiTokenSpaceGuid.PcdSmmuBase|0x4F00
gArmSgiTokenSpaceGuid.PcdSmmuSize|0x0100
+
+ # GPIO Controller
+ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x1C1D
+ gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x0001
+ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|136
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
index c593156e17be..5c137c0991e7 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
@@ -54,3 +54,8 @@
# SMMU
gArmSgiTokenSpaceGuid.PcdSmmuBase|0x4000
gArmSgiTokenSpaceGuid.PcdSmmuSize|0x1000
+
+ # GPIO controller
+ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D
+ gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x0001
+ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|392
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index 04ef2bfcaa26..56b80f418398 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -26,6 +26,7 @@
RdE1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
+ SsdtEvents.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -51,6 +52,9 @@
gArmTokenSpaceGuid.PcdPciBusMin
gArmTokenSpaceGuid.PcdPciBusMax
+ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress
+ gArmSgiTokenSpaceGuid.PcdGpioController0Size
+ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index eecb64186473..fa6692bc86f6 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -26,6 +26,7 @@
RdN1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
+ SsdtEvents.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -51,6 +52,9 @@
gArmTokenSpaceGuid.PcdPciBusMin
gArmTokenSpaceGuid.PcdPciBusMax
+ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress
+ gArmSgiTokenSpaceGuid.PcdGpioController0Size
+ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index 617519d9dd38..d0ee125fa1de 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -28,6 +28,7 @@
RdN1EdgeX2/Srat.aslc
Spcr.aslc
Ssdt.asl
+ SsdtEvents.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -60,6 +61,9
[edk2-devel] [edk2-platforms][PATCH v2 0/5] Platform/Sgi: Miscellaneous updates
Changes since V1: - Rebase the patches on top of latest master branch This patch series introduces few miscellaneous updates for Arm's Reference Design platforms. The first two patches add a template support for hardware reduced ACPI events. This allows helps the platform get better compliance coverage with SystemReady test suite. The third patch adds a build macro for enabling graphics output via the HDLCD. The fourth patch allow build time control for CPPC and LPI features on the platform. The fifth patch fixes StandaloneMM build options for the RD platforms. Link to github branch with the patches in this series - https://github.com/Pranav-Madhu/edk2-platforms/tree/topic/rd_misc Omkar Anand Kulkarni (1): Platform/Sgi: Cleanup build options for StandaloneMM context Pranav Madhu (3): Platform/Sgi: Enable PrimeCell GPIO Platform/Sgi: Add GED support Platform/Sgi: update _OSC control method to control LPI and CPPC Thomas Abraham (1): Platform/Sgi: define the macro ENABLE_GOP Platform/ARM/SgiPkg/SgiPlatform.dec | 14 +++ Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc | 10 ++ Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 10 ++ Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 19 +++ Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc | 6 +- Platform/ARM/SgiPkg/SgiPlatform.fdf | 2 + .../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 7 ++ .../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 8 ++ .../AcpiTables/RdN1EdgeX2AcpiTables.inf | 8 ++ .../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 9 ++ .../SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 9 ++ .../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 9 ++ .../SgiPkg/AcpiTables/RdV1McAcpiTables.inf| 9 ++ .../SgiPkg/AcpiTables/Sgi575AcpiTables.inf| 9 ++ Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 2 + .../ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 8 ++ .../ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 8 ++ Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 15 +++ .../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 15 +++ Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 15 +++ .../ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 15 +++ .../ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 8 ++ Platform/ARM/SgiPkg/AcpiTables/SsdtEvents.asl | 116 ++ 23 files changed, 327 insertions(+), 4 deletions(-) create mode 100644 Platform/ARM/SgiPkg/AcpiTables/SsdtEvents.asl -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#76378): https://edk2.groups.io/g/devel/message/76378 Mute This Topic: https://groups.io/mt/83465453/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH v1 5/5] Platform/Sgi: Cleanup build options for StandaloneMM context
From: Omkar Anand Kulkarni The Arm reference design platforms support only AArch64 mode for StandaloneMM execution context. So cleanup the existing build options specified for StandaloneMM. Signed-off-by: Omkar Anand Kulkarni Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc b/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc index 6839ec35da8a..2b461d5afbcb 100644 --- a/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc @@ -144,7 +144,5 @@ # ### [BuildOptions.AARCH64] - GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 -march=armv8-a+nofp - -[BuildOptions] - *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES + GCC:*_*_*_CC_FLAGS = -mstrict-align -march=armv8-a+nofp -D DISABLE_NEW_DEPRECATED_INTERFACES + GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000 -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#75855): https://edk2.groups.io/g/devel/message/75855 Mute This Topic: https://groups.io/mt/83169538/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH v1 3/5] Platform/Sgi: define the macro ENABLE_GOP
From: Thomas Abraham Define and use the global macro ENABLE_GOP to enable the use of the Graphics Output Protocol (GOP). Enabling this macro allows GOP protocol to be used for display on the HDLCD controller of the platform. This macro is set to false by default for the all supported platforms. Signed-off-by: Thomas Abraham Signed-off-by: Pranav Madhu --- Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 5 + Platform/ARM/SgiPkg/SgiPlatform.fdf | 2 ++ 2 files changed, 7 insertions(+) diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc index e4aee7a09acf..2851cf180c0e 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc +++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc @@ -14,6 +14,9 @@ # Secure boot requires secure storage to be enabled as well. DEFINE SECURE_BOOT_ENABLE = FALSE + # To allow HDLCD display using the Graphics Output Protocol, set this to TRUE. + DEFINE ENABLE_GOP = FALSE + [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES @@ -234,7 +237,9 @@ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf ArmPkg/Drivers/TimerDxe/TimerDxe.inf ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf +!if $(ENABLE_GOP) == TRUE ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf +!endif ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf diff --git a/Platform/ARM/SgiPkg/SgiPlatform.fdf b/Platform/ARM/SgiPkg/SgiPlatform.fdf index d94e4633e36c..8227ae03330c 100644 --- a/Platform/ARM/SgiPkg/SgiPlatform.fdf +++ b/Platform/ARM/SgiPkg/SgiPlatform.fdf @@ -153,7 +153,9 @@ READ_LOCK_STATUS = TRUE INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf # Graphics Output Protocol +!if $(ENABLE_GOP) == TRUE INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf +!endif INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#75853): https://edk2.groups.io/g/devel/message/75853 Mute This Topic: https://groups.io/mt/83169535/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH v1 4/5] Platform/Sgi: update _OSC control method to control LPI and CPPC
Define and use the global macro LPI_EN and CPPC_EN to enable low power
idle and CPPC support for reference design platforms. Update platform
wide _OSC control method to enable/disable low power idle and CPPC
support based on pcd PcdOscLpiEnable and PcdOscCppcEnable. The pcds
are controlled by the global macros LPI_EN and CPPC_EN.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 4
Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 14 ++
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 2 ++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 2 ++
Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 2 ++
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 2 ++
Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 2 ++
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl| 8
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 8
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl| 15 +++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl| 15 +++
Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl| 15 +++
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 15 +++
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 8
17 files changed, 115 insertions(+)
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index ffbbb24f1c33..8cd818a9bf64 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -86,5 +86,9 @@
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0|UINT32|0x0023
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|0|UINT32|0x0024
+ # ACPI platform wide _OSC
+ gArmSgiTokenSpaceGuid.PcdOscLpiEnable|0|UINT32|0x0025
+ gArmSgiTokenSpaceGuid.PcdOscCppcEnable|0|UINT32|0x0026
+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b,
0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
index 2851cf180c0e..7e37732fb93c 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -17,6 +17,10 @@
# To allow HDLCD display using the Graphics Output Protocol, set this to
TRUE.
DEFINE ENABLE_GOP = FALSE
+ # To enable LPI and CPPC power management functionality, set this to TRUE.
+ DEFINE LPI_EN = FALSE
+ DEFINE CPPC_EN= FALSE
+
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
@@ -108,6 +112,16 @@
gArmSgiTokenSpaceGuid.PcdDramBlock2Base|0x808000
gArmSgiTokenSpaceGuid.PcdDramBlock2Size|0x18000
+!if $(LPI_EN) == TRUE
+ # Allow use of LPI in the response to _OSC method call
+ gArmSgiTokenSpaceGuid.PcdOscLpiEnable|1
+!endif
+
+!if $(CPPC_EN) == TRUE
+ # Allow use of CPPC in the response to _OSC method call
+ gArmSgiTokenSpaceGuid.PcdOscCppcEnable|1
+!endif
+
# NV Storage PCDs. Use base of 0x0800 for NOR0, 0xC000 for NOR 1
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x0140
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x0140
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index 8d46b001444c..ce89aa93ea7b 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -57,6 +57,7 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdOscLpiEnable
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index 473c9eff0f55..1999bc1553e9 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -66,6 +66,7 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdOscLpiEnable
gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index c537db45e08f..25be2e276e85 100644
--- a/Platform/ARM/SgiPkg/AcpiTables
[edk2-devel] [edk2-platforms][PATCH v1 2/5] Platform/Sgi: Add GED support
Add ACPI Generic Event Device (GED) support for Arm's reference design
platforms. The SP804 dual-timer interrupt is used as the event source
for GED.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 5 ++
Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc| 5 ++
Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 5 ++
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 ++
Platform/ARM/SgiPkg/AcpiTables/SsdtEvents.asl | 49
12 files changed, 88 insertions(+)
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index e0aabc566d88..ffbbb24f1c33 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -81,5 +81,10 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Size|0|UINT32|0x0020
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|0|UINT32|0x0021
+ # SP804 Dual Timer
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0|UINT32|0x0022
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0|UINT32|0x0023
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|0|UINT32|0x0024
+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b,
0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
index a567af8537ec..76707be73d7b 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
@@ -51,6 +51,11 @@
gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv|93
gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|94
+ # SP804 dual timer
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0x1C11
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0x0001
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|230
+
# SMMU
gArmSgiTokenSpaceGuid.PcdSmmuBase|0x4F00
gArmSgiTokenSpaceGuid.PcdSmmuSize|0x0100
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
index 5c137c0991e7..2d612f9b9674 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
@@ -51,6 +51,11 @@
gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv|110
gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv|111
+ # SP804 dual timer
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress|0x0C11
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize|0x0001
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt|486
+
# SMMU
gArmSgiTokenSpaceGuid.PcdSmmuBase|0x4000
gArmSgiTokenSpaceGuid.PcdSmmuSize|0x1000
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index 56b80f418398..8c34c2fa73e4 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -57,6 +57,9 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index fa6692bc86f6..8d46b001444c 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -57,6 +57,9 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize
+ gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt
gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index d0ee125fa1de..473c9eff0f55 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -66,6 +66,9 @@
gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
[edk2-devel] [edk2-platforms][PATCH v1 0/5] Platform/Sgi: Miscellaneous updates
This patch series introduces few miscellaneous updates for Arm's Reference Design platforms. The first two patches add a template support for hardware reduced ACPI events. This allows helps the platform get better compliance coverage with SystemReady test suite. The third patch adds a build macro for enabling graphics output via the HDLCD. The fourth patch allow build time control for CPPC and LPI features on the platform. The fifth patch fixes StandaloneMM build options for the RD platforms. This patch series should be applied on top of the patch series https://edk2.groups.io/g/devel/message/75542 Link to github branch with the patches in this series - https://github.com/Pranav-Madhu/edk2-platforms/tree/topic/rd_misc Omkar Anand Kulkarni (1): Platform/Sgi: Cleanup build options for StandaloneMM context Pranav Madhu (3): Platform/Sgi: Enable PrimeCell GPIO Platform/Sgi: Add GED support Platform/Sgi: update _OSC control method to control LPI and CPPC Thomas Abraham (1): Platform/Sgi: define the macro ENABLE_GOP Platform/ARM/SgiPkg/SgiPlatform.dec | 14 +++ Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc | 10 ++ Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 10 ++ Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 19 +++ Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc | 6 +- Platform/ARM/SgiPkg/SgiPlatform.fdf | 2 + .../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 7 ++ .../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 8 ++ .../AcpiTables/RdN1EdgeX2AcpiTables.inf | 8 ++ .../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 9 ++ .../SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 9 ++ .../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 9 ++ .../SgiPkg/AcpiTables/RdV1McAcpiTables.inf| 9 ++ .../SgiPkg/AcpiTables/Sgi575AcpiTables.inf| 9 ++ Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 2 + .../ARM/SgiPkg/AcpiTables/RdN1Edge/Dsdt.asl | 8 ++ .../ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Dsdt.asl | 8 ++ Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 15 +++ .../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 15 +++ Platform/ARM/SgiPkg/AcpiTables/RdV1/Dsdt.asl | 15 +++ .../ARM/SgiPkg/AcpiTables/RdV1Mc/Dsdt.asl | 15 +++ .../ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 8 ++ Platform/ARM/SgiPkg/AcpiTables/SsdtEvents.asl | 116 ++ 23 files changed, 327 insertions(+), 4 deletions(-) create mode 100644 Platform/ARM/SgiPkg/AcpiTables/SsdtEvents.asl -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#75850): https://edk2.groups.io/g/devel/message/75850 Mute This Topic: https://groups.io/mt/83169531/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[edk2-devel] [edk2-platforms][PATCH v1 1/5] Platform/Sgi: Enable PrimeCell GPIO
The HW-Reduced ACPI model has specific requirements for GPIO
controllers. Arm's reference design Platforms has PrimeCell GPIO
(PL061) integrated in the RoS subsystem to provide GPIO support. Add
GPIO device entry and also add GPIO signalled ACPI event template for
reference.
Signed-off-by: Pranav Madhu
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 5 ++
Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc| 5 ++
Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc | 5 ++
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 4 ++
Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 5 ++
Platform/ARM/SgiPkg/AcpiTables/SsdtEvents.asl | 67
12 files changed, 115 insertions(+)
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec
b/Platform/ARM/SgiPkg/SgiPlatform.dec
index af08ed153eae..e0aabc566d88 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -76,5 +76,10 @@
gArmSgiTokenSpaceGuid.PcdSmmuBase|0|UINT32|0x001D
gArmSgiTokenSpaceGuid.PcdSmmuSize|0|UINT32|0x001E
+ # GPIO Controller
+ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0|UINT32|0x001F
+ gArmSgiTokenSpaceGuid.PcdGpioController0Size|0|UINT32|0x0020
+ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|0|UINT32|0x0021
+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b,
0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
index d3d650323891..a567af8537ec 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
@@ -54,3 +54,8 @@
# SMMU
gArmSgiTokenSpaceGuid.PcdSmmuBase|0x4F00
gArmSgiTokenSpaceGuid.PcdSmmuSize|0x0100
+
+ # GPIO Controller
+ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x1C1D
+ gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x0001
+ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|136
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
index c593156e17be..5c137c0991e7 100644
--- a/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap2.dsc.inc
@@ -54,3 +54,8 @@
# SMMU
gArmSgiTokenSpaceGuid.PcdSmmuBase|0x4000
gArmSgiTokenSpaceGuid.PcdSmmuSize|0x1000
+
+ # GPIO controller
+ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress|0x0C1D
+ gArmSgiTokenSpaceGuid.PcdGpioController0Size|0x0001
+ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt|392
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index 04ef2bfcaa26..56b80f418398 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -26,6 +26,7 @@
RdE1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
+ SsdtEvents.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -51,6 +52,9 @@
gArmTokenSpaceGuid.PcdPciBusMin
gArmTokenSpaceGuid.PcdPciBusMax
+ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress
+ gArmSgiTokenSpaceGuid.PcdGpioController0Size
+ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index eecb64186473..fa6692bc86f6 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -26,6 +26,7 @@
RdN1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
+ SsdtEvents.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -51,6 +52,9 @@
gArmTokenSpaceGuid.PcdPciBusMin
gArmTokenSpaceGuid.PcdPciBusMax
+ gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress
+ gArmSgiTokenSpaceGuid.PcdGpioController0Size
+ gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt
gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index 617519d9dd38..d0ee125fa1de 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -28,6 +28,7 @@
RdN1EdgeX2/Srat.aslc
Spcr.aslc
Ssdt.asl
+ SsdtEvents.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -60,6 +61,9
[edk2-devel] [edk2-platforms][PATCH V2 6/6] Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg1
Extend the SMBIOS support for RD-N2-Cfg1 platform. RD-N2-Cfg1 platform
is a derivative of the RD-N2 platform and so most of the table values
for RD-N2 platform is reused.
Signed-off-by: Pranav Madhu
Reviewed-by: Sami Mujawar
---
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c| 7
+--
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c | 7
+--
Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c | 18
++
3 files changed, 28 insertions(+), 4 deletions(-)
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
index 367587c07673..e8326cc6ef14 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
@@ -31,7 +31,8 @@
"RdE1Edge\0" \
"RdV1\0" \
"RdV1Mc\0"\
- "RdN2\0"
+ "RdN2\0" \
+ "RdN2Cfg1\0"
typedef enum {
ManufacturerName = 1,
@@ -64,7 +65,9 @@ STATIC GUID mSmbiosUid[] = {
/* Rd-V1Mc */
{0x1f3a0806, 0x18b5, 0x4eca, {0xad, 0xcd, 0xba, 0x9b, 0x07, 0xb1, 0x0a,
0xcf}},
/* Rd-N2 */
- {0xf2cded73, 0x37f9, 0x4ec9, {0xd9, 0xf9, 0x89, 0x9b, 0x74, 0x91, 0x20,
0x49}}
+ {0xf2cded73, 0x37f9, 0x4ec9, {0xd9, 0xf9, 0x89, 0x9b, 0x74, 0x91, 0x20,
0x49}},
+ /* Rd-N2-Cfg1*/
+ {0xa4941d3d, 0xfac3, 0x4ace, {0x9a, 0x7e, 0xce, 0x26, 0x76, 0x64, 0x5e,
0xda}},
};
/* System information */
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
index 9ecaea3603de..b554ee6dea58 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
@@ -27,7 +27,7 @@
#define SOCKET_TYPE_BASE3
#define SOCKET_TYPE_NUM 1
#define PROCESSOR_VERSION_BASE (SOCKET_TYPE_BASE + SOCKET_TYPE_NUM)
-#define PROCESSOR_VERSION_NUM 8
+#define PROCESSOR_VERSION_NUM 9
#define SERIAL_NUMBER_BASE (PROCESSOR_VERSION_BASE +
PROCESSOR_VERSION_NUM)
#define TYPE4_STRINGS \
"0x000\0" /* Part Number */ \
@@ -41,6 +41,7 @@
"Neoverse-V1\0" \
"Neoverse-V1\0" \
"Neoverse-N2\0" \
+ "Neoverse-N2\0" \
"000-0\0" /* Serial number */ \
"783-3\0" \
"786-1\0" \
@@ -48,7 +49,8 @@
"786-2\0" \
"78A-1\0" \
"78A-2\0" \
- "7B7-1\0"
+ "7B7-1\0" \
+ "7B6-1\0"
typedef enum {
PartNumber = 1,
@@ -173,6 +175,7 @@ InstallType4ProcessorInformation (
mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
break;
case RdN2:
+ case RdN2Cfg1:
mArmRdSmbiosType4.Base.CoreCount = CoreCount;
mArmRdSmbiosType4.Base.EnabledCoreCount = CoreCount;
mArmRdSmbiosType4.Base.ThreadCount = CoreCount;
diff --git
a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
index 6be62900bd71..aec7c1b585fc 100644
--- a/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
+++ b/Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c
@@ -315,6 +315,24 @@ InstallType7CacheInformation (
mArmRdSmbiosType7[4].Base.InstalledSize2 = 32768;// 32MB SLC
mArmRdSmbiosType7[4].Base.Associativity = CacheAssociativity16Way;
break;
+ case RdN2Cfg1:
+/* L1 instruction cache */
+mArmRdSmbiosType7[0].Base.MaximumCacheSize2 = 64;// 64KB
+mArmRdSmbiosType7[0].Base.InstalledSize2 = 64; // 64KB
+mArmRdSmbiosType7[0].Base.Associativity = CacheAssociativity4Way;
+/* L1 data cache */
+mArmRdSmbiosType7[1].Base.MaximumCacheSize2 = 64;// 64KB
+mArmRdSmbiosType7[1].Base.InstalledSize2 = 64; // 64KB
+mArmRdSmbiosType7[1].Base.Associativity = CacheAssociativity4Way;
+/* L2 cache */
+mArmRdSmbiosType7[2].Base.MaximumCacheSize2 = 1024; // 1MB
+mArmRdSmbiosType7[2].Base.InstalledSize2 = 1024; // 1MB
+mArmRdSmbiosType7
[edk2-devel] [edk2-platforms][PATCH V2 5/6] Platform/Sgi: Define RD-N2-Cfg1 platform id values
Add the RD-N2-Cfg1 platform identification values including the part
number and configuration number. This information will be used in
populating the SMBIOS tables.
Signed-off-by: Pranav Madhu
Reviewed-by: Sami Mujawar
---
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 ++-
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c | 8 +++-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index 4999c9870b49..dddb58832d73 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -39,6 +39,10 @@
#define RD_V1_CONF_ID 0x1
#define RD_V1_MC_CONF_ID 0x2
+// RD-N2-Cfg1 Platform Identification values
+#define RD_N2_CFG1_PART_NUM 0x7B6
+#define RD_N2_CFG1_CONF_ID0x1
+
// RD-N2 Platform Identification values
#define RD_N2_PART_NUM0x7B7
#define RD_N2_CONF_ID 0x1
@@ -77,7 +81,8 @@ typedef enum {
RdE1Edge,
RdV1,
RdV1Mc,
- RdN2
+ RdN2,
+ RdN2Cfg1
} ARM_RD_PRODUCT_ID;
// Arm ProductId look-up table
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
index f27c949dbc24..a982e3d403fa 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.c
@@ -66,7 +66,13 @@ STATIC CONST SGI_PRODUCT_ID_LOOKUP SgiProductIdLookup[] = {
RD_N2_PART_NUM,
RD_N2_CONF_ID,
0
- }
+ },
+ {
+RdN2Cfg1,
+RD_N2_CFG1_PART_NUM,
+RD_N2_CFG1_CONF_ID,
+0
+ },
};
EFI_BOOT_MODE
--
2.17.1
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[edk2-devel] [edk2-platforms][PATCH V2 4/6] Platform/Sgi: ACPI CPPC support for RD-N2-Cfg1
Enable ACPI CPPC mechanism for RD-N2-Cfg1 as defined by the ACPI
specification. The implementation uses AMU registers accessible as
Fixed-feature Hardware (FFixedHW) for monitoring the performance.
Non-secure SCMI fastchannels are used to communicate with SCP to set
the desired performance. RD-N2-Cfg1 platform does not support CPPC
revision 1 and below. So update the _OSC method to let OSPM know about
this fact.
Signed-off-by: Pranav Madhu
Reviewed-by: Sami Mujawar
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 78
1 file changed, 78 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
index 55f51cc26aff..411eff84334a 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
@@ -35,6 +35,12 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
}
+
+ If (And (CAP0, OSC_CAP_CPPC_SUPPORT)) {
+/* CPPC revision 1 and below not supported */
+And (CAP0, Not (OSC_CAP_CPPC_SUPPORT), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
} Else {
And (STS0, Not (OSC_STS_MASK), STS0)
Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
@@ -133,6 +139,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_UID, 0)
Name (_STA, 0xF)
+Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000500, 0x06000504, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+ Package ()
+PSD_INIT (0)
+})
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -151,6 +166,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_UID, 1)
Name (_STA, 0xF)
+Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000518, 0x0600051C, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+ Package ()
+PSD_INIT (1)
+})
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -169,6 +193,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_UID, 2)
Name (_STA, 0xF)
+Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000530, 0x06000534, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+ Package ()
+PSD_INIT (2)
+})
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -187,6 +220,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_UID, 3)
Name (_STA, 0xF)
+Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000548, 0x0600054C, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+ Package ()
+PSD_INIT (3)
+})
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -205,6 +247,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_UID, 4)
Name (_STA, 0xF)
+Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000560, 0x06000564, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+ Package ()
+PSD_INIT (4)
+})
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -223,6 +274,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_UID, 5)
Name (_STA, 0xF)
+Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000578, 0x0600057C, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+ Package ()
+PSD_INIT (5)
+})
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -241,6 +301,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
"ARMSGI",
Name (_UID, 6)
Name (_STA, 0xF)
+Name (_CPC, Package()
+ CPPC_PACKAGE_INIT (0x06000590, 0x06000594, 20, 160, 160, 115, 115, 5)
+)
+
+Name (_PSD, Package () {
+ Package ()
+PSD_INIT (6)
+})
+
Method (_LPI, 0, NotSerialized) {
Return (\_SB.PLPI)
}
@@ -259,6 +328,15 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD",
&quo
[edk2-devel] [edk2-platforms][PATCH V2 3/6] Platform/Sgi: Low Power Idle states for RD-N2-Cfg1
RD-N2-Cfg1 platform supports 2 LPI states, LPI1 (Standby WFI) and LPI3
(Power-down) and the cluster supports LPI2 (Power-down) state. The LPI
implementation also supports combined power state for core and cluster.
Signed-off-by: Pranav Madhu
Reviewed-by: Sami Mujawar
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 158
1 file changed, 158 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
index d68523bc43ed..55f51cc26aff 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
@@ -19,91 +19,249 @@
DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI",
EFI_ACPI_ARM_OEM_REVISION) {
Scope (_SB) {
+/* _OSC: Operating System Capabilities */
+Method (_OSC, 4, Serialized) {
+ CreateDWordField (Arg3, 0x00, STS0)
+ CreateDWordField (Arg3, 0x04, CAP0)
+
+ /* Platform-wide Capabilities */
+ If (LEqual (Arg0, ToUUID("0811b06e-4a27-44f9-8d60-3cbbc22e7b48"))) {
+/* OSC rev 1 supported, for other version, return failure */
+If (LEqual (Arg1, One)) {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+
+ If (And (CAP0, OSC_CAP_OS_INITIATED_LPI)) {
+/* OS initiated LPI not supported */
+And (CAP0, Not (OSC_CAP_OS_INITIATED_LPI), CAP0)
+Or (STS0, OSC_STS_CAPABILITY_MASKED, STS0)
+ }
+} Else {
+ And (STS0, Not (OSC_STS_MASK), STS0)
+ Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_REV), STS0)
+}
+ } Else {
+And (STS0, Not (OSC_STS_MASK), STS0)
+Or (STS0, Or (OSC_STS_FAILURE, OSC_STS_UNRECOGNIZED_UUID), STS0)
+ }
+
+ Return (Arg3)
+}
+
+Name (CLPI, Package () { /* LPI for Cluster, support 1 LPI state */
+ 0, // Version
+ 0, // Level Index
+ 1, // Count
+ Package () {// Power Gating state for Cluster
+2500, // Min residency (uS)
+1150, // Wake latency (uS)
+1,// Flags
+1,// Arch Context Flags
+100, // Residency Counter Frequency
+0,// No Parent State
+0x0020, // Integer Entry method
+ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI2-Cluster"
+ },
+})
+
+Name (PLPI, Package () { /* LPI for Processor, support 2 LPI states */
+ 0, // Version
+ 1, // Level Index
+ 2, // Count
+ Package () {// WFI for CPU
+1,// Min residency (uS)
+1,// Wake latency (uS)
+1,// Flags
+0,// Arch Context lost Flags (no loss)
+100, // Residency Counter Frequency
+0,// No parent state
+ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+32, // Bit Width
+0,// Bit Offset
+0x, // Address
+3,// Access Size
+ )
+},
+ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI1-Core"
+ },
+ Package () {// Power Gating state for CPU
+150, // Min residency (uS)
+350, // Wake latency (uS)
+1,// Flags
+1,// Arch Context lost Flags (Core context lost)
+100, // Residency Counter Frequency
+1,// Parent node can be in any shallower state
+ResourceTemplate () { // Register Entry method
+ Register (FFixedHW,
+32, // Bit Width
+0,// Bit Offset
+0x4002, // Address (PwrLvl:core, StateTyp:PwrDn)
+3,// Access Size
+ )
+},
+ResourceTemplate () { // Null Residency Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+},
+ResourceTemplate () { // Null Usage Counter
+ Register (SystemMemory, 0, 0, 0, 0)
+},
+"LPI3-Core"
+ },
+})
+
Device (CL00) { // Cluster 0
Name (_HID, "ACPI
[edk2-devel] [edk2-platforms][PATCH V2 2/6] Platform/Sgi: ACPI PPTT table for RD-N2-Cfg1 platform
The RD-N2-Cfg1 platform includes eight single-thread CPUS. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
cache. The platform also includes a system level cache of 8MB. Add PPTT
table for RD-N2-Cfg1 platform with this information.
Signed-off-by: Pranav Madhu
Reviewed-by: Sami Mujawar
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 166
2 files changed, 167 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
index f96353087b68..58468096de4f 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
@@ -22,6 +22,7 @@
Mcfg.aslc
RdN2Cfg1/Dsdt.asl
RdN2Cfg1/Madt.aslc
+ RdN2Cfg1/Pptt.aslc
Spcr.aslc
Ssdt.asl
SsdtRos.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
new file mode 100644
index ..5890544c0b92
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
@@ -0,0 +1,166 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N2-Cfg1 platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N2-Cfg1 platform in the form as defined by ACPI PPTT table. The RD-N2-Cfg1
+* platform includes eight single-thread CPUS. Each of the CPUs include 64KB
+* L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also
+* includes system level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include
+#include
+#include
+#include
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+/** Define helper macro for populating processor core information.
+
+ @param [in] PackageId Package instance number.
+ @param [in] ClusterId Cluster instance number.
+ @param [in] CpuId CPU instance number.
+**/
+#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId)
\
+ {
\
+/* Parameters for CPU Core */
\
+EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
\
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */
\
+ PPTT_PROCESSOR_CORE_FLAGS,/* Flag */
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+Package.Cluster[ClusterId]),/* Parent */
\
+ ((PackageId << 4) | ClusterId), /* ACPI Id */
\
+ 2 /* Num of private resource */
\
+),
\
+
\
+/* Offsets of the private resources */
\
+{
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+Package.Cluster[ClusterId].Core[CpuId].DCache),
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+Package.Cluster[ClusterId].Core[CpuId].ICache)
\
+},
\
+
\
+/* L1 data cache parameters */
\
+EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
\
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
\
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
\
+Package.Cluster[ClusterId].Core[CpuId].L2Cache),
\
+/* Next level of cache */
\
+ SIZE_64KB,/* Size */
\
+ 256, /* Num of sets */
\
+ 4,/* Associativity */
\
+ PPTT_DATA_CACHE_ATTR, /* Attributes */
\
+ 64/* Line size */
\
+),
\
+
\
+/* L1 in
