Re: Pi2 Mailbox IRQs was Re: Fwd: SMP support for Raspberry Pi 2
Joel and Rohini, I will have to take some time to catch up.. I apologize that I have not been able to keep up with the Raspberry Pi work lately, I have just been too busy with my work projects. ( which is usually a good thing :) Alan On 8/15/15, 5:37 PM, Joel Sherrill joel.sherr...@oarcorp.com wrote: Alan .. can you confirm what I am interpreting? On 08/15/2015 02:56 PM, Rohini Kulkarni wrote: On Sun, Aug 16, 2015 at 1:13 AM, Joel Sherrill joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com wrote: On 08/15/2015 02:35 PM, Rohini Kulkarni wrote: Hi I need some help with this. I am unable to figure out yet how to add an interrupt for the mailbox and determine interrupt number to be associated with it. If you can enable it and cause it, the fault handler will be one way to do it :) Can you tell from the documentation which pin(s) on the interrupt controller is associated with the mailbox? FWIW I don't even know what documentation to look at for the SoC to find this. If you point me to it, I will see what I can find. This https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/Q A7_rev3.4.pdf is the only official document which seems to be available. The Cortex A7 mpcore document didn't help here. Putitng this back on the devel list. Page 16 of that PDF (4.10) follows up on a previous section. There are sixteen mailboxes. Each core has four associated with it. In 4.10, there is a list of per-core interrupt sources. There are four addresses for core specific interrupt source registers. It looks like the interrupts are numerically next to the GPU interrupt. This much looks fairly straight-forward. Pick a mailbox to dedicate to interprocessor-interrupts. If you pick Bit 7 (mailbox 3), I would expect it to be one logical interrupt lower than the GPU interrupt source. Check the irq list for the BSP. This should be in a .h file. You will install one SMP IRQ handler. But based on the core number it is running on, you will have to do slightly different things to clear it (I think) since the interrupt registers are duplicated per core. Thanks. On Sat, Aug 15, 2015 at 10:52 PM, Rohini Kulkarni krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com wrote: On Wed, Aug 12, 2015 at 1:29 AM, Joel Sherrill joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com wrote: On 8/11/2015 2:06 PM, Rohini Kulkarni wrote: Hi, I would have to register the related mailbox interrupt and associate it with a handler that should be same as _SMP_Inter_processor_interrupt_handler(). Am I right? That sounds correct. From where can I get a reference of how to do this? I would look at the Xilinx code that registers interrupts. The API should be the same. Also the clock driver, etc. The actual handler and IRQ number will vary. How do I determine the interrupt number? I could fine the IPi handler being installed here in arm-a9mpcore-smp.c rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); On 11 Aug 2015 00:41, Joel Sherrill joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com wrote: The source for the CPU supplement is in doc/cpu_supplement in the RTEMS tree. I do not know when the latest online was built so reading it there is probably safest. To build it, you will likely have to install some texinfo and texlive tools. cd $r/doc ../bootstrap cd ../.. mkdir b-doc cd b-doc $r/doc/configure --enable-maintainer-mode \ --prefix=DIRECTORY make make install That should be similar to how it is built.
Re: Fwd: SMP support for Raspberry Pi 2
On Sat, Aug 15, 2015 at 1:22 PM, Rohini Kulkarni krohini1...@gmail.com wrote: On Wed, Aug 12, 2015 at 1:29 AM, Joel Sherrill joel.sherr...@oarcorp.com wrote: On 8/11/2015 2:06 PM, Rohini Kulkarni wrote: Hi, I would have to register the related mailbox interrupt and associate it with a handler that should be same as _SMP_Inter_processor_interrupt_handler(). Am I right? That sounds correct. From where can I get a reference of how to do this? I would look at the Xilinx code that registers interrupts. The API should be the same. Also the clock driver, etc. The actual handler and IRQ number will vary. How do I determine the interrupt number? I could fine the IPi handler being installed here in arm-a9mpcore-smp.c Interrupt numbers are usually part of a TRM. rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); On 11 Aug 2015 00:41, Joel Sherrill joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com wrote: The source for the CPU supplement is in doc/cpu_supplement in the RTEMS tree. I do not know when the latest online was built so reading it there is probably safest. To build it, you will likely have to install some texinfo and texlive tools. cd $r/doc ../bootstrap cd ../.. mkdir b-doc cd b-doc $r/doc/configure --enable-maintainer-mode \ --prefix=DIRECTORY make make install That should be similar to how it is built. --joel On 8/10/2015 1:35 PM, Rohini Kulkarni wrote: The documentation that Sebastian was referring to. On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. What is the CPU Architecture Supplement? You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. Thanks. On Wed, Jul 22, 2015 at 7:08 PM, Rohini Kulkarni krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com wrote: Ok. Qemu suggestion seems helpful for the cache configuration issue though. I am trying with Pi 1. Thanks. On 22 Jul 2015 18:59, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: Sorry, I cannot help you here since I never worked with a Raspberry Pi. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de
Pi2 Mailbox IRQs was Re: Fwd: SMP support for Raspberry Pi 2
Alan .. can you confirm what I am interpreting? On 08/15/2015 02:56 PM, Rohini Kulkarni wrote: On Sun, Aug 16, 2015 at 1:13 AM, Joel Sherrill joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com wrote: On 08/15/2015 02:35 PM, Rohini Kulkarni wrote: Hi I need some help with this. I am unable to figure out yet how to add an interrupt for the mailbox and determine interrupt number to be associated with it. If you can enable it and cause it, the fault handler will be one way to do it :) Can you tell from the documentation which pin(s) on the interrupt controller is associated with the mailbox? FWIW I don't even know what documentation to look at for the SoC to find this. If you point me to it, I will see what I can find. This https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf is the only official document which seems to be available. The Cortex A7 mpcore document didn't help here. Putitng this back on the devel list. Page 16 of that PDF (4.10) follows up on a previous section. There are sixteen mailboxes. Each core has four associated with it. In 4.10, there is a list of per-core interrupt sources. There are four addresses for core specific interrupt source registers. It looks like the interrupts are numerically next to the GPU interrupt. This much looks fairly straight-forward. Pick a mailbox to dedicate to interprocessor-interrupts. If you pick Bit 7 (mailbox 3), I would expect it to be one logical interrupt lower than the GPU interrupt source. Check the irq list for the BSP. This should be in a .h file. You will install one SMP IRQ handler. But based on the core number it is running on, you will have to do slightly different things to clear it (I think) since the interrupt registers are duplicated per core. Thanks. On Sat, Aug 15, 2015 at 10:52 PM, Rohini Kulkarni krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com wrote: On Wed, Aug 12, 2015 at 1:29 AM, Joel Sherrill joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com wrote: On 8/11/2015 2:06 PM, Rohini Kulkarni wrote: Hi, I would have to register the related mailbox interrupt and associate it with a handler that should be same as _SMP_Inter_processor_interrupt_handler(). Am I right? That sounds correct. From where can I get a reference of how to do this? I would look at the Xilinx code that registers interrupts. The API should be the same. Also the clock driver, etc. The actual handler and IRQ number will vary. How do I determine the interrupt number? I could fine the IPi handler being installed here in arm-a9mpcore-smp.c rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); On 11 Aug 2015 00:41, Joel Sherrill joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com wrote: The source for the CPU supplement is in doc/cpu_supplement in the RTEMS tree. I do not know when the latest online was built so reading it there is probably safest. To build it, you will likely have to install some texinfo and texlive tools. cd $r/doc ../bootstrap cd ../.. mkdir b-doc cd b-doc $r/doc/configure --enable-maintainer-mode \ --prefix=DIRECTORY make make install That should be similar to how it is built. --joel On 8/10/2015 1:35 PM, Rohini Kulkarni wrote: The documentation that Sebastian was referring to. On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de
Re: Fwd: SMP support for Raspberry Pi 2
On Wed, Aug 12, 2015 at 5:15 PM, Rohini Kulkarni krohini1...@gmail.com wrote: Hi, It would be great if somebody can help here. [1] How are the mailbox registers available for each core of Pi2 to be used. [2] Another thing is that I don't know which registers of Pi 1 are available for Pi2 as well. The ones in this link , are quite different from the ones for Pi 1. [3] Can the same mailbox interface as Pi1 be used? Are there any support boards/forums for the Pi2 that might have answers or knowledgeable folks who may be able to help? These questions are all related to how much compatibility exists between the Pi and Pi2 mailboxes. Gedare Thanks. On Wed, Aug 12, 2015 at 1:29 AM, Joel Sherrill joel.sherr...@oarcorp.com wrote: On 8/11/2015 2:06 PM, Rohini Kulkarni wrote: Hi, I would have to register the related mailbox interrupt and associate it with a handler that should be same as _SMP_Inter_processor_interrupt_handler(). Am I right? That sounds correct. From where can I get a reference of how to do this? I would look at the Xilinx code that registers interrupts. The API should be the same. Also the clock driver, etc. The actual handler and IRQ number will vary. On 11 Aug 2015 00:41, Joel Sherrill joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com wrote: The source for the CPU supplement is in doc/cpu_supplement in the RTEMS tree. I do not know when the latest online was built so reading it there is probably safest. To build it, you will likely have to install some texinfo and texlive tools. cd $r/doc ../bootstrap cd ../.. mkdir b-doc cd b-doc $r/doc/configure --enable-maintainer-mode \ --prefix=DIRECTORY make make install That should be similar to how it is built. --joel On 8/10/2015 1:35 PM, Rohini Kulkarni wrote: The documentation that Sebastian was referring to. On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. What is the CPU Architecture Supplement? You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. Thanks. On Wed, Jul 22, 2015 at 7:08 PM, Rohini Kulkarni krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com wrote: Ok. Qemu suggestion seems helpful for the cache configuration issue though. I am trying with Pi 1. Thanks. On 22 Jul 2015 18:59, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: Sorry, I cannot help you here since I never worked with a Raspberry Pi. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de
Re: Fwd: SMP support for Raspberry Pi 2
Hi, It would be great if somebody can help here. [1] How are the mailbox registers available for each core of Pi2 to be used. [2] Another thing is that I don't know which registers of Pi 1 are available for Pi2 as well. The ones in this link https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf , are quite different from the ones for Pi 1. [3] Can the same mailbox interface as Pi1 be used? Thanks. On Wed, Aug 12, 2015 at 1:29 AM, Joel Sherrill joel.sherr...@oarcorp.com wrote: On 8/11/2015 2:06 PM, Rohini Kulkarni wrote: Hi, I would have to register the related mailbox interrupt and associate it with a handler that should be same as _SMP_Inter_processor_interrupt_handler(). Am I right? That sounds correct. From where can I get a reference of how to do this? I would look at the Xilinx code that registers interrupts. The API should be the same. Also the clock driver, etc. The actual handler and IRQ number will vary. On 11 Aug 2015 00:41, Joel Sherrill joel.sherr...@oarcorp.com mailto: joel.sherr...@oarcorp.com wrote: The source for the CPU supplement is in doc/cpu_supplement in the RTEMS tree. I do not know when the latest online was built so reading it there is probably safest. To build it, you will likely have to install some texinfo and texlive tools. cd $r/doc ../bootstrap cd ../.. mkdir b-doc cd b-doc $r/doc/configure --enable-maintainer-mode \ --prefix=DIRECTORY make make install That should be similar to how it is built. --joel On 8/10/2015 1:35 PM, Rohini Kulkarni wrote: The documentation that Sebastian was referring to. On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de wrote: Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. What is the CPU Architecture Supplement? You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. Thanks. On Wed, Jul 22, 2015 at 7:08 PM, Rohini Kulkarni krohini1...@gmail.com mailto:krohini1...@gmail.com mailto: krohini1...@gmail.com mailto:krohini1...@gmail.com mailto: krohini1...@gmail.com mailto:krohini1...@gmail.com mailto: krohini1...@gmail.com mailto:krohini1...@gmail.com wrote: Ok. Qemu suggestion seems helpful for the cache configuration issue though. I am trying with Pi 1. Thanks. On 22 Jul 2015 18:59, Sebastian Huber sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de wrote: Sorry, I cannot help you here since I never worked with a Raspberry Pi. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto:
Re: Fwd: SMP support for Raspberry Pi 2
Hi, I would have to register the related mailbox interrupt and associate it with a handler that should be same as _SMP_Inter_processor_interrupt_handler(). Am I right? From where can I get a reference of how to do this? On 11 Aug 2015 00:41, Joel Sherrill joel.sherr...@oarcorp.com wrote: The source for the CPU supplement is in doc/cpu_supplement in the RTEMS tree. I do not know when the latest online was built so reading it there is probably safest. To build it, you will likely have to install some texinfo and texlive tools. cd $r/doc ../bootstrap cd ../.. mkdir b-doc cd b-doc $r/doc/configure --enable-maintainer-mode \ --prefix=DIRECTORY make make install That should be similar to how it is built. --joel On 8/10/2015 1:35 PM, Rohini Kulkarni wrote: The documentation that Sebastian was referring to. On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de wrote: Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. What is the CPU Architecture Supplement? You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. Thanks. On Wed, Jul 22, 2015 at 7:08 PM, Rohini Kulkarni krohini1...@gmail.com mailto:krohini1...@gmail.com mailto: krohini1...@gmail.com mailto:krohini1...@gmail.com wrote: Ok. Qemu suggestion seems helpful for the cache configuration issue though. I am trying with Pi 1. Thanks. On 22 Jul 2015 18:59, Sebastian Huber sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de wrote: Sorry, I cannot help you here since I never worked with a Raspberry Pi. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Rohini Kulkarni -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Rohini Kulkarni -- Joel Sherrill, Ph.D. Director of Research Development joel.sherr...@oarcorp.comOn-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available(256) 722-9985 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: Fwd: SMP support for Raspberry Pi 2
On 8/11/2015 2:06 PM, Rohini Kulkarni wrote: Hi, I would have to register the related mailbox interrupt and associate it with a handler that should be same as _SMP_Inter_processor_interrupt_handler(). Am I right? That sounds correct. From where can I get a reference of how to do this? I would look at the Xilinx code that registers interrupts. The API should be the same. Also the clock driver, etc. The actual handler and IRQ number will vary. On 11 Aug 2015 00:41, Joel Sherrill joel.sherr...@oarcorp.com mailto:joel.sherr...@oarcorp.com wrote: The source for the CPU supplement is in doc/cpu_supplement in the RTEMS tree. I do not know when the latest online was built so reading it there is probably safest. To build it, you will likely have to install some texinfo and texlive tools. cd $r/doc ../bootstrap cd ../.. mkdir b-doc cd b-doc $r/doc/configure --enable-maintainer-mode \ --prefix=DIRECTORY make make install That should be similar to how it is built. --joel On 8/10/2015 1:35 PM, Rohini Kulkarni wrote: The documentation that Sebastian was referring to. On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. What is the CPU Architecture Supplement? You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. Thanks. On Wed, Jul 22, 2015 at 7:08 PM, Rohini Kulkarni krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com mailto:krohini1...@gmail.com wrote: Ok. Qemu suggestion seems helpful for the cache configuration issue though. I am trying with Pi 1. Thanks. On 22 Jul 2015 18:59, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: Sorry, I cannot help you here since I never worked with a Raspberry Pi. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Rohini Kulkarni -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de
Re: SMP support for Raspberry Pi 2
There is no documentation or information from forums I can find to get a lead. I suppose i will go ahead with mailboxes. Each core has 4 mailboxes, usage being left to us. One of the mailboxes can be used here. On Sun, Aug 9, 2015 at 2:28 AM, Joel Sherrill joel.sherr...@oarcorp.com wrote: On August 8, 2015 3:17:01 PM CDT, Rohini Kulkarni krohini1...@gmail.com wrote: Can mailboxes be useful here? Nothing else that is coming to my mind They may be and I am seeing references to ARM's own mpcore which uses the GIC. This appears to be SOC specific but ARM has recommendations which may be followed by the SOC manufacturer On Sun, Aug 9, 2015 at 1:44 AM, Rohini Kulkarni krohini1...@gmail.com wrote: Hi, I am stuck at how to set up IPI for Pi 2. This is a document I have referred to get an idea of interrupts. Would be great to get some help on how to proceed. On Fri, Jul 31, 2015 at 7:33 PM, Joel Sherrill joel.sherr...@oarcorp.com wrote: On 7/31/2015 8:11 AM, Rohini Kulkarni wrote: Hi, How is the number of processors to be used for an application specified? The used count minimum of that supported in hardware and that configured. How to specify the latter? https://docs.rtems.org/doc-current/share/rtems/html/c_user/Configuring-a-System-SMP-Specific-Configuration-Parameters.html#Configuring-a-System-SMP-Specific-Configuration-Parameters and see the smptests. Many of which do specify the maximum. Thanks. On 29 Jul 2015 15:29, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: On 29/07/15 11:52, Rohini Kulkarni wrote: On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. I could locate the function in arm-a9mpcore-smp.c. but it would be helpful if I can know where this being called from, a deeper call hierarchy, so that I can ascertain this is a problem. I can see a Send_messgae function call this. But don't know where the send message is being called from. You can run one of the SMP tests on the realview_pbx_a9_qemu_smp BSP on Qemu and set a break point to _CPU_SMP_Send_interrupt() if you want to know how it is used. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Joel Sherrill, Ph.D. Director of Research Development joel.sherr...@oarcorp.comOn-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available(256) 722-9985 -- Rohini Kulkarni -- Rohini Kulkarni --joel -- Rohini Kulkarni ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
Can mailboxes be useful here? Nothing else that is coming to my mind On Sun, Aug 9, 2015 at 1:44 AM, Rohini Kulkarni krohini1...@gmail.com wrote: Hi, I am stuck at how to set up IPI for Pi 2. This https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf is a document I have referred to get an idea of interrupts. Would be great to get some help on how to proceed. On Fri, Jul 31, 2015 at 7:33 PM, Joel Sherrill joel.sherr...@oarcorp.com wrote: On 7/31/2015 8:11 AM, Rohini Kulkarni wrote: Hi, How is the number of processors to be used for an application specified? The used count minimum of that supported in hardware and that configured. How to specify the latter? https://docs.rtems.org/doc-current/share/rtems/html/c_user/Configuring-a-System-SMP-Specific-Configuration-Parameters.html#Configuring-a-System-SMP-Specific-Configuration-Parameters and see the smptests. Many of which do specify the maximum. Thanks. On 29 Jul 2015 15:29, Sebastian Huber sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de wrote: On 29/07/15 11:52, Rohini Kulkarni wrote: On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de wrote: Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. I could locate the function in arm-a9mpcore-smp.c. but it would be helpful if I can know where this being called from, a deeper call hierarchy, so that I can ascertain this is a problem. I can see a Send_messgae function call this. But don't know where the send message is being called from. You can run one of the SMP tests on the realview_pbx_a9_qemu_smp BSP on Qemu and set a break point to _CPU_SMP_Send_interrupt() if you want to know how it is used. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Joel Sherrill, Ph.D. Director of Research Development joel.sherr...@oarcorp.comOn-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available(256) 722-9985 -- Rohini Kulkarni -- Rohini Kulkarni ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
On August 8, 2015 3:17:01 PM CDT, Rohini Kulkarni krohini1...@gmail.com wrote: Can mailboxes be useful here? Nothing else that is coming to my mind They may be and I am seeing references to ARM's own mpcore which uses the GIC. This appears to be SOC specific but ARM has recommendations which may be followed by the SOC manufacturer On Sun, Aug 9, 2015 at 1:44 AM, Rohini Kulkarni krohini1...@gmail.com wrote: Hi, I am stuck at how to set up IPI for Pi 2. This is a document I have referred to get an idea of interrupts. Would be great to get some help on how to proceed. On Fri, Jul 31, 2015 at 7:33 PM, Joel Sherrill joel.sherr...@oarcorp.com wrote: On 7/31/2015 8:11 AM, Rohini Kulkarni wrote: Hi, How is the number of processors to be used for an application specified? The used count minimum of that supported in hardware and that configured. How to specify the latter? https://docs.rtems.org/doc-current/share/rtems/html/c_user/Configuring-a-System-SMP-Specific-Configuration-Parameters.html#Configuring-a-System-SMP-Specific-Configuration-Parameters and see the smptests. Many of which do specify the maximum. Thanks. On 29 Jul 2015 15:29, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: On 29/07/15 11:52, Rohini Kulkarni wrote: On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. I could locate the function in arm-a9mpcore-smp.c. but it would be helpful if I can know where this being called from, a deeper call hierarchy, so that I can ascertain this is a problem. I can see a Send_messgae function call this. But don't know where the send message is being called from. You can run one of the SMP tests on the realview_pbx_a9_qemu_smp BSP on Qemu and set a break point to _CPU_SMP_Send_interrupt() if you want to know how it is used. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Joel Sherrill, Ph.D. Director of Research Development joel.sherr...@oarcorp.comOn-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available(256) 722-9985 -- Rohini Kulkarni -- Rohini Kulkarni --joel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
On 7/31/2015 8:11 AM, Rohini Kulkarni wrote: Hi, How is the number of processors to be used for an application specified? The used count minimum of that supported in hardware and that configured. How to specify the latter? https://docs.rtems.org/doc-current/share/rtems/html/c_user/Configuring-a-System-SMP-Specific-Configuration-Parameters.html#Configuring-a-System-SMP-Specific-Configuration-Parameters and see the smptests. Many of which do specify the maximum. Thanks. On 29 Jul 2015 15:29, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: On 29/07/15 11:52, Rohini Kulkarni wrote: On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. I could locate the function in arm-a9mpcore-smp.c. but it would be helpful if I can know where this being called from, a deeper call hierarchy, so that I can ascertain this is a problem. I can see a Send_messgae function call this. But don't know where the send message is being called from. You can run one of the SMP tests on the realview_pbx_a9_qemu_smp BSP on Qemu and set a break point to _CPU_SMP_Send_interrupt() if you want to know how it is used. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Joel Sherrill, Ph.D. Director of Research Development joel.sherr...@oarcorp.comOn-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available(256) 722-9985 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
Hi, How is the number of processors to be used for an application specified? The used count minimum of that supported in hardware and that configured. How to specify the latter? Thanks. On 29 Jul 2015 15:29, Sebastian Huber sebastian.hu...@embedded-brains.de wrote: On 29/07/15 11:52, Rohini Kulkarni wrote: On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber sebastian.hu...@embedded-brains.de mailto: sebastian.hu...@embedded-brains.de wrote: Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. I could locate the function in arm-a9mpcore-smp.c. but it would be helpful if I can know where this being called from, a deeper call hierarchy, so that I can ascertain this is a problem. I can see a Send_messgae function call this. But don't know where the send message is being called from. You can run one of the SMP tests on the realview_pbx_a9_qemu_smp BSP on Qemu and set a break point to _CPU_SMP_Send_interrupt() if you want to know how it is used. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
On Tue, Jul 28, 2015 at 12:24 PM, Sebastian Huber sebastian.hu...@embedded-brains.de wrote: Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. I could locate the function in arm-a9mpcore-smp.c. but it would be helpful if I can know where this being called from, a deeper call hierarchy, so that I can ascertain this is a problem. I can see a Send_messgae function call this. But don't know where the send message is being called from. Thanks. On Wed, Jul 22, 2015 at 7:08 PM, Rohini Kulkarni krohini1...@gmail.com mailto:krohini1...@gmail.com wrote: Ok. Qemu suggestion seems helpful for the cache configuration issue though. I am trying with Pi 1. Thanks. On 22 Jul 2015 18:59, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: Sorry, I cannot help you here since I never worked with a Raspberry Pi. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Rohini Kulkarni -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Rohini Kulkarni ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
Hello Rohini, please use the devel list. On 28/07/15 07:41, Rohini Kulkarni wrote: Hi, I wish to understand where the interprocessor interrupts are used during the boot process. During final initialization of SMP I can see rtems_interrupt_handler_install( ARM_GIC_IRQ_SGI_0, IPI, RTEMS_INTERRUPT_UNIQUE, bsp_inter_processor_interrupt, NULL ); Raspberry Pi 2 does not have the generic interrupt controller. Interrupt routing will have to be handled differently. So I wish to understand how/ where it is used. I suppose this might be the problem. Sorry, that the documentation is so scattered. I think we should move everything into the CPU Architecture Supplement. It would be nice if you can help to improve the documentation since you have a different view point. You must install the IPI during the system initialization. It is raised via the _CPU_SMP_Send_interrupt() function, for an example see arm-a9mpcore-smp.c. Thanks. On Wed, Jul 22, 2015 at 7:08 PM, Rohini Kulkarni krohini1...@gmail.com mailto:krohini1...@gmail.com wrote: Ok. Qemu suggestion seems helpful for the cache configuration issue though. I am trying with Pi 1. Thanks. On 22 Jul 2015 18:59, Sebastian Huber sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de wrote: Sorry, I cannot help you here since I never worked with a Raspberry Pi. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de mailto:sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Rohini Kulkarni -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
On 19/07/15 09:52, Rohini Kulkarni wrote: Do I have to just run the smp tests executables bare metal? You should run the SMP tests like all the other tests. RTEMS kernel image runs fine, but the smp01 executable that I tried produces no output at all. In case for example ticker.exe runs, and smp01.exe produces no output, then something is wrong with the SMP startup. You can debug this problem on Qemu. Without a debugger it will be very hard. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
Did you change configure, or configure.ac? After you change configure.ac or Makefile.am files, you need to run sb-bootstrap again. On Sun, Jul 12, 2015 at 7:05 AM, Rohini Kulkarni krohini1...@gmail.com wrote: Hi, I don't have #define RTEMS_SMP 1 in cpuopts.h. Have made changes only to libbsp/arm/raspberrypi/configure . On Sun, Jul 12, 2015 at 1:50 AM, Sebastian Huber sebastian.hu...@embedded-brains.de wrote: In the build tree, there are exactly two identical cpuopts.h files. In this file you must find a: /* if SMP is enabled */ #define RTEMS_SMP 1 -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.huber at embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Rohini Kulkarni ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
Hi, I don't have #define RTEMS_SMP 1 in cpuopts.h. Have made changes only to libbsp/arm/raspberrypi/configure . On Sun, Jul 12, 2015 at 1:50 AM, Sebastian Huber sebastian.hu...@embedded-brains.de wrote: In the build tree, there are exactly two identical cpuopts.h files. In this file you must find a: /* if SMP is enabled */ #define RTEMS_SMP 1 -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.huber at embedded-brains.de http://lists.rtems.org/mailman/listinfo/devel PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. -- Rohini Kulkarni ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
Hi, I am building with the --enable-smp option. But RTEMS_SMP is not getting defined. I have referred to the configure files of other BSPs which includes the script for --enable-smp option and changed the configure script for raspberry pi. What can be the reason, I am unable to understand what I am missing. Thanks. On 3 Jul 2015 22:43, Joel Sherrill joel.sherr...@oarcorp.com wrote: On July 3, 2015 11:53:07 AM CDT, Rohini Kulkarni krohini1...@gmail.com wrote: Any help that I can with this? On 1 Jul 2015 16:59, Rohini Kulkarni krohini1...@gmail.com wrote: Hi all, I wish to know where the maximum number of processors for a variant are configured. I took a look at some configure scripts. I could see the processor count defined for xilinx-zynq in its configuration file as ZYNQ_CPUS=2. This looks to be BSP specific and could originate in configure.ac or a .h file. It is likely that each BSP has an underlying hardware limit. rtems_configuration_get_maximum_processors() called in gets this configured number. But I don't know from where. This is set initially based on the confdefs.h parameter CONFIGURE_SMP_MAXIMUM_PROCESSORS or something close to that (on phone). Ultimately the maximum CPUs for an application is the lower of those available or RTEMS is configured for. Also where is RTEMS_SMP defined for a bsp? A side-effect of building with --enable-smp. Thanks. -- Rohini Kulkarni --joel ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
In the build tree, there are exactly two identical cpuopts.h files. In this file you must find a: /* if SMP is enabled */ #define RTEMS_SMP 1-- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.huber at embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
On 08/07/15 14:54, Rohini Kulkarni wrote: This piece of code gets the configured number of CPUs. I suppose this number is not specified and will have to be specified by me somewhere in the configurations. But I am unable to find out where. For examples, please have a look at testsuite/smptests. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
On 7/8/2015 9:51 AM, Hesham ALMatary wrote: Hi Rohini, On Wed, Jul 8, 2015 at 1:54 PM, Rohini Kulkarni krohini1...@gmail.com wrote: Hi, I found this piece of code in confdefs.h #if defined(RTEMS_SMP) /* * If configured for SMP, then we need to know the maximum CPU cores. */ #if !defined(CONFIGURE_SMP_APPLICATION) #if !defined(CONFIGURE_SMP_MAXIMUM_PROCESSORS) #define CONFIGURE_SMP_MAXIMUM_PROCESSORS 1 #endif #else #if !defined(CONFIGURE_SMP_MAXIMUM_PROCESSORS) #error CONFIGURE_SMP_MAXIMUM_PROCESSORS not specified for SMP Application #endif #endif #endif This piece of code gets the configured number of CPUs. I suppose this number is not specified and will have to be specified by me somewhere in the configurations. But I am unable to find out where. Every BSP that supports SMP should define the number of cores/processors in its linkcmds file. For example have a look at Realview linkcmds file here [1] The pc386 treats the configured value as the maximum to be supported. It does not hard code the number on the hardware but probes at run-time. See libbsp/i386/shared/smp. The key is that the BSP can set a hard limit or determine the available set at run-time. There are two factors: + number RTEMS is configured for + number present in hardware - BSP can probe - can be hard-coded An RTEMS SMP application configured for 2 CPUs on a quad-core system will simply ignore the other two. [1] https://github.com/RTEMS/rtems/blob/master/c/src/lib/libbsp/arm/realview-pbx-a9/startup/linkcmds.realview_pbx_a9_qemu_smp#L1 Thanks! On Sat, Jul 4, 2015 at 4:07 PM, Rohini Kulkarni krohini1...@gmail.com wrote: On Fri, Jul 3, 2015 at 10:43 PM, Joel Sherrill joel.sherr...@oarcorp.com wrote: On July 3, 2015 11:53:07 AM CDT, Rohini Kulkarni krohini1...@gmail.com wrote: Any help that I can with this? On 1 Jul 2015 16:59, Rohini Kulkarni krohini1...@gmail.com wrote: Hi all, I wish to know where the maximum number of processors for a variant are configured. I took a look at some configure scripts. I could see the processor count defined for xilinx-zynq in its configuration file as ZYNQ_CPUS=2. This looks to be BSP specific and could originate in configure.ac or a .h file. I found this under ~/libbsp/arm/xilinx-zynq/configure # Check whether --enable-smp was given. if test $rtems_cv_HAS_SMP = yes; then : ZYNQ_CPUS=2 fi It is likely that each BSP has an underlying hardware limit. Yes rtems_configuration_get_maximum_processors() called in gets this configured number. But I don't know from where. This is set initially based on the confdefs.h parameter CONFIGURE_SMP_MAXIMUM_PROCESSORS or something close to that (on phone). Ya, I found this piece of code in confdefs.h #if defined(RTEMS_SMP) /* * If configured for SMP, then we need to know the maximum CPU cores. */ #if !defined(CONFIGURE_SMP_APPLICATION) #if !defined(CONFIGURE_SMP_MAXIMUM_PROCESSORS) #define CONFIGURE_SMP_MAXIMUM_PROCESSORS 1 #endif #else #if !defined(CONFIGURE_SMP_MAXIMUM_PROCESSORS) #error CONFIGURE_SMP_MAXIMUM_PROCESSORS not specified for SMP Application #endif #endif #endif This piece of code gets the configured number of CPUs. I suppose this number is not specified and will have to be specified by me somewhere in the configurations. But I am unable to find out where. Ultimately the maximum CPUs for an application is the lower of those available or RTEMS is configured for. Yes. Also where is RTEMS_SMP defined for a bsp? A side-effect of building with --enable-smp. Oh,alright. Thanks. -- Rohini Kulkarni --joel -- Rohini Kulkarni -- Rohini Kulkarni ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel -- Joel Sherrill, Ph.D. Director of Research Development joel.sherr...@oarcorp.comOn-Line Applications Research Ask me about RTEMS: a free RTOS Huntsville AL 35805 Support Available(256) 722-9985 ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
On Wed, Jul 8, 2015 at 6:25 PM, Sebastian Huber sebastian.hu...@embedded-brains.de wrote: On 08/07/15 14:54, Rohini Kulkarni wrote: This piece of code gets the configured number of CPUs. I suppose this number is not specified and will have to be specified by me somewhere in the configurations. But I am unable to find out where. For examples, please have a look at testsuite/smptests. Umm,I don't see how the smptests will help figure out where to configure the number of processors. Don't they just use the number already configured for the variant. -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.hu...@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel -- Rohini Kulkarni ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
Re: SMP support for Raspberry Pi 2
Hi Rohini, On Wed, Jul 8, 2015 at 1:54 PM, Rohini Kulkarni krohini1...@gmail.com wrote: Hi, I found this piece of code in confdefs.h #if defined(RTEMS_SMP) /* * If configured for SMP, then we need to know the maximum CPU cores. */ #if !defined(CONFIGURE_SMP_APPLICATION) #if !defined(CONFIGURE_SMP_MAXIMUM_PROCESSORS) #define CONFIGURE_SMP_MAXIMUM_PROCESSORS 1 #endif #else #if !defined(CONFIGURE_SMP_MAXIMUM_PROCESSORS) #error CONFIGURE_SMP_MAXIMUM_PROCESSORS not specified for SMP Application #endif #endif #endif This piece of code gets the configured number of CPUs. I suppose this number is not specified and will have to be specified by me somewhere in the configurations. But I am unable to find out where. Every BSP that supports SMP should define the number of cores/processors in its linkcmds file. For example have a look at Realview linkcmds file here [1] [1] https://github.com/RTEMS/rtems/blob/master/c/src/lib/libbsp/arm/realview-pbx-a9/startup/linkcmds.realview_pbx_a9_qemu_smp#L1 Thanks! On Sat, Jul 4, 2015 at 4:07 PM, Rohini Kulkarni krohini1...@gmail.com wrote: On Fri, Jul 3, 2015 at 10:43 PM, Joel Sherrill joel.sherr...@oarcorp.com wrote: On July 3, 2015 11:53:07 AM CDT, Rohini Kulkarni krohini1...@gmail.com wrote: Any help that I can with this? On 1 Jul 2015 16:59, Rohini Kulkarni krohini1...@gmail.com wrote: Hi all, I wish to know where the maximum number of processors for a variant are configured. I took a look at some configure scripts. I could see the processor count defined for xilinx-zynq in its configuration file as ZYNQ_CPUS=2. This looks to be BSP specific and could originate in configure.ac or a .h file. I found this under ~/libbsp/arm/xilinx-zynq/configure # Check whether --enable-smp was given. if test $rtems_cv_HAS_SMP = yes; then : ZYNQ_CPUS=2 fi It is likely that each BSP has an underlying hardware limit. Yes rtems_configuration_get_maximum_processors() called in gets this configured number. But I don't know from where. This is set initially based on the confdefs.h parameter CONFIGURE_SMP_MAXIMUM_PROCESSORS or something close to that (on phone). Ya, I found this piece of code in confdefs.h #if defined(RTEMS_SMP) /* * If configured for SMP, then we need to know the maximum CPU cores. */ #if !defined(CONFIGURE_SMP_APPLICATION) #if !defined(CONFIGURE_SMP_MAXIMUM_PROCESSORS) #define CONFIGURE_SMP_MAXIMUM_PROCESSORS 1 #endif #else #if !defined(CONFIGURE_SMP_MAXIMUM_PROCESSORS) #error CONFIGURE_SMP_MAXIMUM_PROCESSORS not specified for SMP Application #endif #endif #endif This piece of code gets the configured number of CPUs. I suppose this number is not specified and will have to be specified by me somewhere in the configurations. But I am unable to find out where. Ultimately the maximum CPUs for an application is the lower of those available or RTEMS is configured for. Yes. Also where is RTEMS_SMP defined for a bsp? A side-effect of building with --enable-smp. Oh,alright. Thanks. -- Rohini Kulkarni --joel -- Rohini Kulkarni -- Rohini Kulkarni ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel -- Hesham ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
