[edk2] [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Clean up build scripts

[Wei, David]

Reviewed-by: David Wei  mailto:david@intel.com>>


Thanks,
David  Wei

Intel SSG/STO/UEFI BIOS

From: Steele, Kelly
Sent: Friday, September 21, 2018 1:58 AM
To: edk2-devel@lists.01.org
Cc: Wei, David mailto:david@intel.com>>; Guo, Mang 
mailto:mang@intel.com>>
Subject: [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Clean up build 
scripts

>From 62aef5b6fdb4e85878bafed4ab9c41631689b69d Mon Sep 17 00:00:00 2001
From: Kelly Steele mailto:kelly.ste...@intel.com>>
Date: Thu, 20 Sep 2018 10:47:06 -0700
Subject: [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Clean up build
scripts

Went thru the build scripts and cleaned them up. There was a couple of
"magic" numbers being used in BuildBxtBios.bat that are derived from
defines.dsc. I switched from "magic" numbers to parsing defines.dsc to
use what is set there.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Kelly Steele 
mailto:kelly.ste...@intel.com>>
---
BuildBIOS.bat|  12 +-
Platform/BroxtonPlatformPkg/BuildBxtBios.bat | 232 -
Platform/BroxtonPlatformPkg/BuildIFWI.bat| 497 ++-
3 files changed, 410 insertions(+), 331 deletions(-)

diff --git a/BuildBIOS.bat b/BuildBIOS.bat
index d8275aca14..500c2244c9 100644
--- a/BuildBIOS.bat
+++ b/BuildBIOS.bat
@@ -34,13 +34,14 @@ echo  Call Build Script of Broxton 

 if not exist Platform\%PlatformName%PlatformPkg\BuildIFWI.bat (
   echo Platform %PlatformName%PlatformPkg does not exist
-  echo. & echo Error - Unsupported Platform name: %1
+  echo. & echo Error - Unsupported Platform name: %1
   echo.
   goto Usage
)

-echo calling : Platform\%PlatformName%PlatformPkg\BuildIFWI.bat  %BuildFlags%  
/fspw MINN %BuildTarget%
-call Platform\%PlatformName%PlatformPkg\BuildIFWI.bat  %BuildFlags%  /fspw 
MINN %BuildTarget%
+echo calling : Platform\%PlatformName%PlatformPkg\BuildIFWI.bat  %BuildFlags%  
/fspw MINN %BuildTarget%
+call Platform\%PlatformName%PlatformPkg\BuildIFWI.bat  %BuildFlags%  /fspw 
MINN %BuildTarget%
+set ExitCode=%ErrorLevel%

 goto Exit

@@ -75,4 +76,7 @@ echo%thisscript% /vs13 /LH /B /x64 Broxton Debug
set exitCode=1

 :Exit
-exit /b %exitCode%
+(
+  EndLocal
+  exit /b %exitCode%
+)
diff --git a/Platform/BroxtonPlatformPkg/BuildBxtBios.bat 
b/Platform/BroxtonPlatformPkg/BuildBxtBios.bat
index 9858ceae58..2bc2556a8a 100644
--- a/Platform/BroxtonPlatformPkg/BuildBxtBios.bat
+++ b/Platform/BroxtonPlatformPkg/BuildBxtBios.bat
@@ -73,8 +73,9 @@ set FSP_BIN_PKG_NAME=BroxtonFspBinPkg
set STITCH_PATH=%WORKSPACE%\%PLATFORM_PATH%\Common\Tools\Stitch
set ResetVectorPath=%WORKSPACE%\%PLATFORM_RC_PACKAGE%\Cpu\ResetVector

-PATH=%PATH%;%WORKSPACE%\%PLATFORM_PATH%\Common\Tools\GenBiosId;%WORKSPACE%\%PLATFORM_PATH%\Common\Tools\nasm\Win32
-PATH=%PATH%;%WORKSPACE%\%PLATFORM_PATH%\Common\Tools\FCE;%WORKSPACE%\%PLATFORM_PATH%\Common\Tools\nasm\Win32
+PATH=%PATH%;%WORKSPACE%\%PLATFORM_PATH%\Common\Tools\FCE
+PATH=%PATH%;%WORKSPACE%\%PLATFORM_PATH%\Common\Tools\GenBiosId
+PATH=%PATH%;%WORKSPACE%\%PLATFORM_PATH%\Common\Tools\nasm\Win32

 ::**
:: Parse command line arguments
@@ -268,8 +269,8 @@ if "%Arch%"=="IA32" (
 echo DEFINE X64_CONFIG  = TRUE  >> 
%Build_Macros%
)

-echo DEFINE UP2_BOARD= %UP2_BOARD%   >> 
%Build_Macros%
-echo DEFINE MINNOW3_MODULE_BOARD = %MINNOW3_MODULE_BOARD%>> 
%Build_Macros%
+echo DEFINE UP2_BOARD   = %UP2_BOARD%   >> 
%Build_Macros%
+echo DEFINE MINNOW3_MODULE_BOARD= %MINNOW3_MODULE_BOARD%>> 
%Build_Macros%

 ::Stage of copy of BiosId.env in Conf/ with Platform_Type and Build_Target 
values removed

@@ -288,43 +289,63 @@ if /i "%~2" == "RELEASE" (
 echo BUILD_TYPE = D >> Conf\BiosId.env
)

-if %BoardId%==BG (
-  if %FabId%==B (
+if "%BoardId%" == "BG" (
+  if "%FabId%" == "A" (
+echo BOARD_REV = A >> Conf\BiosId.env
+  ) else if "%FabId%" == "B" (
 echo BOARD_REV = B >> Conf\BiosId.env
   ) else (
-echo BOARD_REV = A >> Conf\BiosId.env
+echo ERROR: Benson Glacier currently only supports Board Fab A & B^^^!
+goto BldFail
   )
)

-if %BoardId%==AG (
-  echo BOARD_REV = A >> Conf\BiosId.env
+if "%BoardId%" == "AG" (
+  if "%FabId%" == "A" (
+echo BOARD_REV = A >> Conf\BiosId.env
+  ) else (
+echo ERROR: Aurora Glacier currently only supports Board Fab A^^^!
+goto BldFail
+  )
)

-if %BoardId%==MN (
-  if %FabId%==B (
+if "%BoardId%" == "MN" (
+  if "%FabId%" == "A" (
+echo BOARD_REV = A >> Conf\BiosId.env
+  ) else if "%FabId%" == "B" (
 echo BOARD_REV = B >> Conf\BiosId.env
   ) else (
-echo BOARD_REV = A >> Conf\BiosId.env
+echo ERROR: Minnow Baord v3 currently only supports Board Fab A & B^^^!
+goto BldFail
   )
)

-if %BoardId%==MX (
-  if %FabId%==C (
+if "%BoardId%" == "MX" (
+  if "%FabId%" == "A" (
+

[edk2] [PATCH] UefiCpuPkg/MtrrLib: Revert "Skip MSR access when the pair is invalid"

[Ruiyu Ni]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1187

The patch reverts 9c8c4478cfcacaf5fd60b75ff78d26732d93a5b8
"UefiCpuPkg/MtrrLib: Skip Base MSR access when the pair is invalid".

Microsoft Windows will report an error in event manager if MTRR
usage is different across hibernate even when the difference is
in an non valid MTRR pair. This seems like a bug in Windows but
for compatibility and servicing reasons we think a change in UEFI
would wise.
A Windows change has already been submitted for the next iteration
(2019 time frame).

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Michael D Kinney 
Cc: Eric Dong 
Cc: Sean Brogan 
---
 UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 29 +
 1 file changed, 13 insertions(+), 16 deletions(-)

diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c 
b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
index dfce9a996b..086f7ad8f0 100644
--- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
+++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
@@ -449,13 +449,10 @@ MtrrGetVariableMtrrWorker (
 
   for (Index = 0; Index < VariableMtrrCount; Index++) {
 if (MtrrSetting == NULL) {
-  VariableSettings->Mtrr[Index].Mask = AsmReadMsr64 
(MSR_IA32_MTRR_PHYSMASK0 + (Index << 1));
-  //
-  // Skip to read the Base MSR when the Mask.V is not set.
-  //
-  if (((MSR_IA32_MTRR_PHYSMASK_REGISTER 
*)>Mtrr[Index].Mask)->Bits.V != 0) {
-VariableSettings->Mtrr[Index].Base = AsmReadMsr64 
(MSR_IA32_MTRR_PHYSBASE0 + (Index << 1));
-  }
+  VariableSettings->Mtrr[Index].Base =
+AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1));
+  VariableSettings->Mtrr[Index].Mask =
+AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1));
 } else {
   VariableSettings->Mtrr[Index].Base = 
MtrrSetting->Variables.Mtrr[Index].Base;
   VariableSettings->Mtrr[Index].Mask = 
MtrrSetting->Variables.Mtrr[Index].Mask;
@@ -2604,14 +2601,14 @@ MtrrSetVariableMtrrWorker (
   ASSERT (VariableMtrrCount <= ARRAY_SIZE (VariableSettings->Mtrr));
 
   for (Index = 0; Index < VariableMtrrCount; Index++) {
-//
-// Mask MSR is always updated since caller might need to invalidate the 
MSR pair.
-// Base MSR is skipped when Mask.V is not set.
-//
-AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), 
VariableSettings->Mtrr[Index].Mask);
-if (((MSR_IA32_MTRR_PHYSMASK_REGISTER 
*)>Mtrr[Index].Mask)->Bits.V != 0) {
-  AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), 
VariableSettings->Mtrr[Index].Base);
-}
+AsmWriteMsr64 (
+  MSR_IA32_MTRR_PHYSBASE0 + (Index << 1),
+  VariableSettings->Mtrr[Index].Base
+  );
+AsmWriteMsr64 (
+  MSR_IA32_MTRR_PHYSMASK0 + (Index << 1),
+  VariableSettings->Mtrr[Index].Mask
+  );
   }
 }
 
@@ -2868,7 +2865,7 @@ MtrrDebugPrintAllMtrrsWorker (
 }
 ContainVariableMtrr = FALSE;
 for (Index = 0; Index < VariableMtrrCount; Index++) {
-  if (((MSR_IA32_MTRR_PHYSMASK_REGISTER 
*)>Variables.Mtrr[Index].Mask)->Bits.V == 0) {
+  if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) {
 //
 // If mask is not valid, then do not display range
 //
-- 
2.16.1.windows.1

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Re: [edk2] [PATCH 3/3] MdeModulePkg/PciHostBridge: Add RESOURCE_VALID() to simplify code

[Ni, Ruiyu]

On 9/25/2018 11:13 AM, Zeng, Star wrote:

On 2018/9/25 10:47, Ni, Ruiyu wrote:

But then there will be a little inconsistent, for example OPERATION_TYPE 
is only used by PciRootBridgeIo.c.


Since coding style document doesn't define clear rule for this (I also 
don't like a coding style document with so many detailed restrictions. 
This removes the fun from coding.), I agree there is inconsistency.







I agree moving mIoMmuProtocol to PciHostBridge.h.
I am happy to do that in a separate patch in V2.


Thanks. If we will only move mIoMmuProtocol, it can be in a separated 
patch.



Star



Agree?



Thanks,
Star



With or without changes:

Reviewed-by: Laszlo Ersek 

Thanks
Laszlo











--
Thanks,
Ray
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[edk2] [PATCH] UefiCpuPkg SecCore:Add a GUID removed previously

[shenglei]

The Guid gPeiSecPerformancePpiGuid removed previously
is added into SecCore.inf.
https://bugzilla.tianocore.org/show_bug.cgi?id=1203

Cc: Eric Dong 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei 
---
 UefiCpuPkg/SecCore/SecCore.inf | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/UefiCpuPkg/SecCore/SecCore.inf b/UefiCpuPkg/SecCore/SecCore.inf
index b228610757..442f663911 100644
--- a/UefiCpuPkg/SecCore/SecCore.inf
+++ b/UefiCpuPkg/SecCore/SecCore.inf
@@ -70,6 +70,9 @@
   ## SOMETIMES_PRODUCES
   gEfiSecPlatformInformation2PpiGuid
   gEfiTemporaryRamDonePpiGuid  ## PRODUCES
+  ## NOTIFY
+  ## SOMETIMES_CONSUMES
+  gPeiSecPerformancePpiGuid
 
 [Guids]
   ## SOMETIMES_PRODUCES   ## HOB
-- 
2.18.0.windows.1

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Re: [edk2] [PATCH] NetworkPkg: fix read memory access overflow in HTTPBoot.

[Wu, Jiaxin]

Besides, I recommend to separate the patch for HttpDxe and HttpUtilitiesDxe.

Thanks,
Jiaxin

> -Original Message-
> From: Fu, Siyuan
> Sent: Tuesday, September 25, 2018 11:43 AM
> To: Li, Songpeng ; edk2-devel@lists.01.org
> Cc: Wu, Jiaxin 
> Subject: RE: [PATCH] NetworkPkg: fix read memory access overflow in
> HTTPBoot.
> 
> Hi, Songpeng
> 
> The change is ok with me while I have one comment for the original
> AllocateZeroPool() in these places. Since there will be always a CopyMem()
> to fill up data content to the new allocated buffer, there is no need to use
> AllocateZeroPool(), just AllocatePool() and adding null terminator should be
> enough. This will save the unnecessary ZeroMem() time cost for better
> performance. Thanks.
> 
> 
> BestRegards
> Fu Siyuan
> 
> 
> > -Original Message-
> > From: Li, Songpeng
> > Sent: Tuesday, September 25, 2018 11:29 AM
> > To: edk2-devel@lists.01.org
> > Cc: Fu, Siyuan ; Wu, Jiaxin 
> > Subject: [PATCH] NetworkPkg: fix read memory access overflow in
> HTTPBoot.
> >
> > The input param String of AsciiStrStr() requires a pointer to
> >  Null-terminated string, however in HttpTcpReceiveHeader() and
> >  HttpUtilitiesParse(), the Buffersize before AllocateZeroPool()
> >  is equal to the size of TCP header, after the CopyMem(), it
> >  might not end with Null-terminator. It might cause memory
> >  access overflow.
> >
> > Cc: Fu Siyuan 
> > Cc: Wu Jiaxin 
> > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1204
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Songpeng Li 
> > ---
> >  NetworkPkg/HttpDxe/HttpProto.c  | 4 ++--
> >  NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c | 4 +++-
> >  2 files changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/NetworkPkg/HttpDxe/HttpProto.c
> > b/NetworkPkg/HttpDxe/HttpProto.c
> > index 94f89f5665..c729f76eff 100644
> > --- a/NetworkPkg/HttpDxe/HttpProto.c
> > +++ b/NetworkPkg/HttpDxe/HttpProto.c
> > @@ -1917,7 +1917,7 @@ HttpTcpReceiveHeader (
> >// Append the response string.
> >//
> >*BufferSize = *SizeofHeaders + Fragment.Len;
> > -  Buffer  = AllocateZeroPool (*BufferSize);
> > +  Buffer  = AllocateZeroPool (*BufferSize + 1);
> >if (Buffer == NULL) {
> >  Status = EFI_OUT_OF_RESOURCES;
> >  return Status;
> > @@ -2016,7 +2016,7 @@ HttpTcpReceiveHeader (
> >// Append the response string.
> >//
> >*BufferSize = *SizeofHeaders + Fragment.Len;
> > -  Buffer  = AllocateZeroPool (*BufferSize);
> > +  Buffer  = AllocateZeroPool (*BufferSize + 1);
> >if (Buffer == NULL) {
> >  Status = EFI_OUT_OF_RESOURCES;
> >  return Status;
> > diff --git a/NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c
> > b/NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c
> > index a9a1c7c586..2292b52537 100644
> > --- a/NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c
> > +++ b/NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c
> > @@ -298,6 +298,7 @@ HttpUtilitiesParse (
> >CHAR8 *FieldName;
> >CHAR8 *FieldValue;
> >UINTN Index;
> > +  UINTN HttpBufferSize;
> >
> >Status  = EFI_SUCCESS;
> >TempHttpMessage = NULL;
> > @@ -311,7 +312,8 @@ HttpUtilitiesParse (
> >  return EFI_INVALID_PARAMETER;
> >}
> >
> > -  TempHttpMessage = AllocateZeroPool (HttpMessageSize);
> > +  HttpBufferSize = HttpMessageSize + 1;
> > +  TempHttpMessage = AllocateZeroPool (HttpBufferSize);
> >if (TempHttpMessage == NULL) {
> >  return EFI_OUT_OF_RESOURCES;
> >}
> > --
> > 2.18.0.windows.1

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Re: [edk2] [PATCH] NetworkPkg: fix read memory access overflow in HTTPBoot.

[Fu, Siyuan]

Hi, Songpeng

The change is ok with me while I have one comment for the original 
AllocateZeroPool() in these places. Since there will be always a CopyMem() to 
fill up data content to the new allocated buffer, there is no need to use 
AllocateZeroPool(), just AllocatePool() and adding null terminator should be 
enough. This will save the unnecessary ZeroMem() time cost for better 
performance. Thanks.


BestRegards
Fu Siyuan


> -Original Message-
> From: Li, Songpeng
> Sent: Tuesday, September 25, 2018 11:29 AM
> To: edk2-devel@lists.01.org
> Cc: Fu, Siyuan ; Wu, Jiaxin 
> Subject: [PATCH] NetworkPkg: fix read memory access overflow in HTTPBoot.
> 
> The input param String of AsciiStrStr() requires a pointer to
>  Null-terminated string, however in HttpTcpReceiveHeader() and
>  HttpUtilitiesParse(), the Buffersize before AllocateZeroPool()
>  is equal to the size of TCP header, after the CopyMem(), it
>  might not end with Null-terminator. It might cause memory
>  access overflow.
> 
> Cc: Fu Siyuan 
> Cc: Wu Jiaxin 
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1204
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Songpeng Li 
> ---
>  NetworkPkg/HttpDxe/HttpProto.c  | 4 ++--
>  NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c | 4 +++-
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/NetworkPkg/HttpDxe/HttpProto.c
> b/NetworkPkg/HttpDxe/HttpProto.c
> index 94f89f5665..c729f76eff 100644
> --- a/NetworkPkg/HttpDxe/HttpProto.c
> +++ b/NetworkPkg/HttpDxe/HttpProto.c
> @@ -1917,7 +1917,7 @@ HttpTcpReceiveHeader (
>// Append the response string.
>//
>*BufferSize = *SizeofHeaders + Fragment.Len;
> -  Buffer  = AllocateZeroPool (*BufferSize);
> +  Buffer  = AllocateZeroPool (*BufferSize + 1);
>if (Buffer == NULL) {
>  Status = EFI_OUT_OF_RESOURCES;
>  return Status;
> @@ -2016,7 +2016,7 @@ HttpTcpReceiveHeader (
>// Append the response string.
>//
>*BufferSize = *SizeofHeaders + Fragment.Len;
> -  Buffer  = AllocateZeroPool (*BufferSize);
> +  Buffer  = AllocateZeroPool (*BufferSize + 1);
>if (Buffer == NULL) {
>  Status = EFI_OUT_OF_RESOURCES;
>  return Status;
> diff --git a/NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c
> b/NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c
> index a9a1c7c586..2292b52537 100644
> --- a/NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c
> +++ b/NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c
> @@ -298,6 +298,7 @@ HttpUtilitiesParse (
>CHAR8 *FieldName;
>CHAR8 *FieldValue;
>UINTN Index;
> +  UINTN HttpBufferSize;
> 
>Status  = EFI_SUCCESS;
>TempHttpMessage = NULL;
> @@ -311,7 +312,8 @@ HttpUtilitiesParse (
>  return EFI_INVALID_PARAMETER;
>}
> 
> -  TempHttpMessage = AllocateZeroPool (HttpMessageSize);
> +  HttpBufferSize = HttpMessageSize + 1;
> +  TempHttpMessage = AllocateZeroPool (HttpBufferSize);
>if (TempHttpMessage == NULL) {
>  return EFI_OUT_OF_RESOURCES;
>}
> --
> 2.18.0.windows.1

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[edk2] [Patch 4/6] NetworkPkg/TcpDxe: Add the clarification compared to Tcp4Dxe in MdeModulePkg.

[Jiaxin Wu]

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205

This patch is to add the driver usage/difference clarification
compared to Tcp4Dxe in MdeModulePkg.

Cc: Ye Ting 
Cc: Fu Siyuan 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wu Jiaxin 
---
 NetworkPkg/TcpDxe/TcpDxe.inf | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/NetworkPkg/TcpDxe/TcpDxe.inf b/NetworkPkg/TcpDxe/TcpDxe.inf
index eb693a147f..56cfd16b98 100644
--- a/NetworkPkg/TcpDxe/TcpDxe.inf
+++ b/NetworkPkg/TcpDxe/TcpDxe.inf
@@ -1,12 +1,17 @@
 ## @file
 #  TCPv4 I/O and TCPv6 I/O services.
 #
 #  This module provides EFI TCPv4 Protocol and EFI TCPv6 Protocol to send and 
receive data stream.
-#  It might provide TCPv4 Protocol or TCPv6 Protocol or both of them that 
depends on
-#  which network stack has been loaded in system.
+#  It might provide TCPv4 Protocol or TCPv6 Protocol or both of them that 
depends on which network 
+#  stack has been loaded in system. This driver supports both IPv4 and IPv6 
network stack.
 #
+#  Notes: 
+#  1) This driver can't co-work with the Tcp4Dxe driver in MdeModulePkg. 
+#  2) This driver includes more bugs fix and supports more features (e.g. 
IPv6, TCP Cancel 
+# function) than the Tcp4Dxe driver in MdeModulePkg. So, we recommand to 
use this driver 
+# even both of them can be used.
 #
 #  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
-- 
2.17.1.windows.2

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[edk2] [Patch 5/6] NetworkPkg/IScsiDxe: Add the clarification compared to IScsiDxe in MdeModulePkg.

[Jiaxin Wu]

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205

This patch is to add the driver usage/difference clarification
compared to IScsiDxe in MdeModulePkg.

Cc: Ye Ting 
Cc: Fu Siyuan 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wu Jiaxin 
---
 NetworkPkg/IScsiDxe/IScsiDxe.inf | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/NetworkPkg/IScsiDxe/IScsiDxe.inf b/NetworkPkg/IScsiDxe/IScsiDxe.inf
index 61a0693a07..007418fd9c 100644
--- a/NetworkPkg/IScsiDxe/IScsiDxe.inf
+++ b/NetworkPkg/IScsiDxe/IScsiDxe.inf
@@ -1,10 +1,20 @@
 ## @file
 #  Client-side iSCSI service.
 #
 #  The iSCSI driver provides iSCSI service in the preboot environment and 
supports
-#  booting over iSCSI.
+#  booting over iSCSI. This driver supports both IPv4 and IPv6 network stack.
+#
+#  Notes: 
+#  1) This driver can't co-work with the IScsiDxe driver in MdeModulePkg. 
+#  2) This driver includes more bugs fix and supports more features (e.g. 
IPv6, Dns 
+# support for target URL configuration, iSCSI keyword support) than the 
IscsiDxe 
+# driver in MdeModulePkg. So, we recommand to use this driver even both of 
them 
+# can be used.
+#  3) This driver depends on the OpenSSL building. To use this driver, please 
follow 
+# the instructions found in the file "Patch-HOWTO.txt" located in 
+# CryptoPkg\Library\OpensslLib to enable the OpenSSL building first.
 #
 # Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
 # This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD 
License
 # which accompanies this distribution.  The full text of the license may be 
found at
-- 
2.17.1.windows.2

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[edk2] [Patch 6/6] NetworkPkg/UefiPxeBcDxe: Add the clarification compared to UefiPxeBcDxe in MdeModulePkg.

[Jiaxin Wu]

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205

This patch is to add the driver usage/difference clarification
compared to UefiPxeBcDxe in MdeModulePkg.

Cc: Ye Ting 
Cc: Fu Siyuan 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wu Jiaxin 
---
 NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf 
b/NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
index e2a0eb44b1..f2ec34df93 100644
--- a/NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+++ b/NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
@@ -1,12 +1,17 @@
 ## @file
 #  Access PXE-compatible devices for network access and network booting.
 #
 #  This driver provides PXE Base Code Protocol which is used to accessing
-#  PXE-compatible device for network access or booting. It could work together
-#  with an IPv4 stack, an IPv6 stack or both.
+#  PXE-compatible device for network access or booting. This driver supports 
+#  both IPv4 and IPv6 network stack.
 #
+#  Notes: 
+#  1) This driver can't co-work with the UefiPxeBcDxe driver in MdeModulePkg. 
+#  2) This driver includes more bugs fix and supports more features (e.g. 
IPv6, 
+# MTFTP windowsize) than the UefiPxeBcDxe driver in MdeModulePkg. So, we 
+# recommand to use this driver even both of them can be used.
 #
 #  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
-- 
2.17.1.windows.2

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[edk2] [Patch 3/6] MdeModulePkg/UefiPxeBcDxe: Add the clarification compared to UefiPxeBcDxe in NetworkPkg.

[Jiaxin Wu]

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205

This patch is to add the driver usage/difference clarification
compared to UefiPxeBcDxe in NetworkPkg.

Cc: Ye Ting 
Cc: Fu Siyuan 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wu Jiaxin 
---
 .../Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf   | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf 
b/MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
index b5b9e80710..0fef0058bd 100644
--- a/MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+++ b/MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
@@ -2,11 +2,20 @@
 #  This module produces EFI Preboot Execution Environment (PXE) Base Code 
Protocol.
 #
 #  This module produces EFI PXE Base Code Protocol upon EFI MMP Protocl and 
IPv4
 #  network stack, used to control PXE-compatible devices. It produces EFI Load 
File
 #  Protocol to provide one clean way to otain control from the boot manager if 
the
-#  boot patch is from the remote device.
+#  boot patch is from the remote device. This driver only supports IPv4 
network stack.
+#
+#  Notes: 
+#  1) This driver can't co-work with the UefiPxeBcDxe driver in NetworkPkg. 
+#  2) This driver might have some issues that have been fixed in the 
UefiPxeBcDxe 
+# driver in NetworkPkg. 
+#  3) This driver supports less feature than the UefiPxeBcDxe driver in 
NetworkPkg 
+# (e.g. IPv6, MTFTP windowsize).
+#  4) UefiPxeBcDxe driver in NetworkPkg is recommanded to use instead of this 
one even 
+# both of them can be used.
 #
 #  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
 #  which accompanies this distribution. The full text of the license may be 
found at
-- 
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[edk2] [Patch 1/6] MdeModulePkg/Tcp4Dxe: Add the clarification compared to TcpDxe in NetworkPkg.

[Jiaxin Wu]

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205

This patch is to add the driver usage/difference clarification
compared to TcpDxe in NetworkPkg.

Cc: Ye Ting 
Cc: Fu Siyuan 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wu Jiaxin 
---
 MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf 
b/MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
index b54321caaa..0561eb7421 100644
--- a/MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+++ b/MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
@@ -1,10 +1,20 @@
 ## @file
 #  This module produces EFI TCPv4 Protocol and EFI TCPv4 Service Binding 
Protocol.
 #
 #  This module produces EFI TCPv4(Transmission Control Protocol version 4) 
Protocol
-#  upon EFI IPv4 Protocol, to provide basic TCPv4 I/O services.
+#  upon EFI IPv4 Protocol, to provide basic TCPv4 I/O services. This driver 
only 
+#  supports IPv4 network stack.
+#
+#  Notes: 
+#  1) This driver can't co-work with the TcpDxe driver in NetworkPkg. 
+#  2) This driver might have some issues that have been fixed in the TcpDxe 
driver 
+# in NetworkPkg. 
+#  3) This driver supports less feature than the TcpDxe driver in NetworkPkg 
(e.g. IPv6, 
+# TCP Cancel function). 
+#  4) TcpDxe driver in NetworkPkg is recommanded to use instead of this one 
even both 
+# of them can be used.
 #
 #  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
 #  which accompanies this distribution. The full text of the license may be 
found at
-- 
2.17.1.windows.2

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[edk2] [Patch 2/6] MdeModulePkg/IScsiDxe: Add the clarification compared to IScsiDxe in NetworkPkg.

[Jiaxin Wu]

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205

This patch is to add the driver usage/difference clarification
compared to IScsiDxe in NetworkPkg.

Cc: Ye Ting 
Cc: Fu Siyuan 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wu Jiaxin 
---
 MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf 
b/MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
index c3b8c7d15a..cd6a2ef843 100644
--- a/MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+++ b/MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
@@ -2,11 +2,21 @@
 #  This module produces EFI iSCSI Initiator Name Protocol.
 #
 #  This module produces EFI iSCSI Initiator Name Protocol upon EFI TCPv4 
Protocol
 #  and EFI DHCPv4 Protocol, to provide the capability to do the transport for 
SCSI
 #  data over TCP/IP. It installs EFI HII Configuration Access Protocol to 
provide
-#  one way to configurate the iSCSI setting.
+#  one way to configurate the iSCSI setting. This driver only supports IPv4 
network 
+#  stack.
+#
+#  Notes: 
+#  1) This driver can't co-work with the IScsiDxe driver in NetworkPkg. 
+#  2) This driver might have some issues that have been fixed in the IScsiDxe 
driver 
+# in NetworkPkg.
+#  3) This driver supports less feature than the IScsiDxe driver in NetworkPkg 
+# (e.g. IPv6, Dns support for target URL configuration, iSCSI keyword 
support).
+#  4) IScsiDxe driver in NetworkPkg is recommanded to use instead of this one 
even 
+# both of them can be used.
 #
 #  Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD 
License
 #  which accompanies this distribution.  The full text of the license may be 
found at
-- 
2.17.1.windows.2

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[edk2] [Patch 0/6] Add the clarification for TCP/ISCSI/PXE drivers.

[Jiaxin Wu]

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1205

The series patches describe the difference against the overlapped network 
drivers between NetworkPkg and MdeModulePkg (ISCSI/TCP/PXE drivers - 
Tcp4Dxe VS TcpDxe, IScsiDxe VS IScsiDxe,  UefiPxeBcDxe VS UefiPxeBcDxe).

Cc: Ye Ting 
Cc: Fu Siyuan 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wu Jiaxin 

Jiaxin Wu (6):
  MdeModulePkg/Tcp4Dxe: Add the clarification compared to TcpDxe in
NetworkPkg.
  MdeModulePkg/IScsiDxe: Add the clarification compared to IScsiDxe in
NetworkPkg.
  MdeModulePkg/UefiPxeBcDxe: Add the clarification compared to
UefiPxeBcDxe in NetworkPkg.
  NetworkPkg/TcpDxe: Add the clarification compared to Tcp4Dxe in
MdeModulePkg.
  NetworkPkg/IScsiDxe: Add the clarification compared to IScsiDxe in
MdeModulePkg.
  NetworkPkg/UefiPxeBcDxe: Add the clarification compared to
UefiPxeBcDxe in MdeModulePkg.

 MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf | 12 +++-
 MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf   | 12 +++-
 .../Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf  | 11 ++-
 NetworkPkg/IScsiDxe/IScsiDxe.inf | 12 +++-
 NetworkPkg/TcpDxe/TcpDxe.inf |  9 +++--
 NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf |  9 +++--
 6 files changed, 57 insertions(+), 8 deletions(-)

-- 
2.17.1.windows.2

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[edk2] [PATCH] NetworkPkg: fix read memory access overflow in HTTPBoot.

[Songpeng Li]

The input param String of AsciiStrStr() requires a pointer to
 Null-terminated string, however in HttpTcpReceiveHeader() and
 HttpUtilitiesParse(), the Buffersize before AllocateZeroPool()
 is equal to the size of TCP header, after the CopyMem(), it
 might not end with Null-terminator. It might cause memory
 access overflow.

Cc: Fu Siyuan 
Cc: Wu Jiaxin 
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1204
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Songpeng Li 
---
 NetworkPkg/HttpDxe/HttpProto.c  | 4 ++--
 NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c | 4 +++-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/NetworkPkg/HttpDxe/HttpProto.c b/NetworkPkg/HttpDxe/HttpProto.c
index 94f89f5665..c729f76eff 100644
--- a/NetworkPkg/HttpDxe/HttpProto.c
+++ b/NetworkPkg/HttpDxe/HttpProto.c
@@ -1917,7 +1917,7 @@ HttpTcpReceiveHeader (
   // Append the response string.
   //
   *BufferSize = *SizeofHeaders + Fragment.Len;
-  Buffer  = AllocateZeroPool (*BufferSize);
+  Buffer  = AllocateZeroPool (*BufferSize + 1);
   if (Buffer == NULL) {
 Status = EFI_OUT_OF_RESOURCES;
 return Status;
@@ -2016,7 +2016,7 @@ HttpTcpReceiveHeader (
   // Append the response string.
   //
   *BufferSize = *SizeofHeaders + Fragment.Len;
-  Buffer  = AllocateZeroPool (*BufferSize);
+  Buffer  = AllocateZeroPool (*BufferSize + 1);
   if (Buffer == NULL) {
 Status = EFI_OUT_OF_RESOURCES;
 return Status;
diff --git a/NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c 
b/NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c
index a9a1c7c586..2292b52537 100644
--- a/NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c
+++ b/NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesProtocol.c
@@ -298,6 +298,7 @@ HttpUtilitiesParse (
   CHAR8 *FieldName;
   CHAR8 *FieldValue;
   UINTN Index;
+  UINTN HttpBufferSize;
 
   Status  = EFI_SUCCESS;
   TempHttpMessage = NULL;
@@ -311,7 +312,8 @@ HttpUtilitiesParse (
 return EFI_INVALID_PARAMETER;
   }
 
-  TempHttpMessage = AllocateZeroPool (HttpMessageSize);
+  HttpBufferSize = HttpMessageSize + 1;
+  TempHttpMessage = AllocateZeroPool (HttpBufferSize);
   if (TempHttpMessage == NULL) {
 return EFI_OUT_OF_RESOURCES;
   }
-- 
2.18.0.windows.1

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Re: [edk2] [PATCH v2 2/2] MdeModulePkg/DxeIpl: support more NX related PCDs

[Wang, Jian J]

I'm fine with them too. So we have two minor changes:

1. Change EnableNonExec to IsEnableNonExecNeeded
2. Move IsExecuteDisableBitAvailable() to VirtualMemory.c

I think v3 is not necessary. I'll push the patch after enough test.

Regards,
Jian

> -Original Message-
> From: Laszlo Ersek [mailto:ler...@redhat.com]
> Sent: Friday, September 21, 2018 6:14 PM
> To: Zeng, Star ; Wang, Jian J ;
> edk2-devel@lists.01.org
> Cc: Ni, Ruiyu ; Yao, Jiewen 
> Subject: Re: [edk2] [PATCH v2 2/2] MdeModulePkg/DxeIpl: support more NX
> related PCDs
> 
> On 09/21/18 10:42, Zeng, Star wrote:
> > Another minor suggestion is to move IsExecuteDisableBitAvailable() to
> > VirtualMemory.c, then there will be no need to declare it in
> > VirtualMemeory.h.
> 
> I'm fine with both ideas (name change as you see fit, and code movement).
> 
> Thanks
> Laszlo
> 
> >
> >
> > Thanks,
> > Star
> > On 2018/9/21 14:00, Zeng, Star wrote:
> >> Jian and Laszlo,
> >>
> >> There is also a superficial comment at below.
> >>
> >> On 2018/9/20 14:02, Jian J Wang wrote:
>  v2 changes:
>      a. remove macros no longer needed
>      b. remove DEBUG and ASSERT in ToEnableExecuteDisableFeature()
>      c. change ToEnableExecuteDisableFeature to EnableNonExec
> >>>
> >>> BZ#1116: https://bugzilla.tianocore.org/show_bug.cgi?id=1116
> >>>
> >>> Currently IA32_EFER.NXE is only set against PcdSetNxForStack. This
> >>> confuses developers because following two other PCDs also need NXE
> >>> to be set, but actually not.
> >>>
> >>>  PcdDxeNxMemoryProtectionPolicy
> >>>  PcdImageProtectionPolicy
> >>>
> >>> This patch solves this issue by adding logic to enable IA32_EFER.NXE
> >>> if any of those PCDs have anything enabled.
> >>>
> >>> Cc: Star Zeng 
> >>> Cc: Laszlo Ersek 
> >>> Cc: Ard Biesheuvel 
> >>> Cc: Ruiyu Ni 
> >>> Cc: Jiewen Yao 
> >>> Contributed-under: TianoCore Contribution Agreement 1.1
> >>> Signed-off-by: Jian J Wang 
> >>> ---
> >>>   MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf  |  2 ++
> >>>   MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c  |  4 ++--
> >>>   MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 30
> >>> +++-
> >>>   MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h | 24
> >>> +++
> >>>   4 files changed, 57 insertions(+), 3 deletions(-)
> >>>
> >>> diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> >>> b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> >>> index fd82657404..068e700074 100644
> >>> --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> >>> +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> >>> @@ -117,6 +117,8 @@
> >>>   [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
> >>>     gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack   ##
> >>> SOMETIMES_CONSUMES
> >>> +  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy
> ##
> >>> SOMETIMES_CONSUMES
> >>> +  gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy   ##
> >>> SOMETIMES_CONSUMES
> >>>   [Depex]
> >>>     gEfiPeiLoadFilePpiGuid AND gEfiPeiMasterBootModePpiGuid
> >>> diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
> >>> b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
> >>> index d28baa3615..ccd30f964b 100644
> >>> --- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
> >>> +++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
> >>> @@ -245,7 +245,7 @@ ToBuildPageTable (
> >>>   return TRUE;
> >>>     }
> >>> -  if (PcdGetBool (PcdSetNxForStack) && IsExecuteDisableBitAvailable
> >>> ()) {
> >>> +  if (EnableNonExec ()) {
> >>>   return TRUE;
> >>>     }
> >>> @@ -436,7 +436,7 @@ HandOffToDxeCore (
> >>>   BuildPageTablesIa32Pae = ToBuildPageTable ();
> >>>   if (BuildPageTablesIa32Pae) {
> >>>     PageTables = Create4GPageTablesIa32Pae (BaseOfStack,
> >>> STACK_SIZE);
> >>> -  if (IsExecuteDisableBitAvailable ()) {
> >>> +  if (EnableNonExec ()) {
> >>>   EnableExecuteDisableBit();
> >>>     }
> >>>   }
> >>> diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> >>> b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> >>> index 496e219913..73b0f67c6b 100644
> >>> --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> >>> +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> >>> @@ -106,6 +106,31 @@ IsNullDetectionEnabled (
> >>>     return ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT0) !=
> >>> 0);
> >>>   }
> >>> +/**
> >>> +  Check if Execute Disable Bit (IA32_EFER.NXE) should be enabled or
> >>> not.
> >>> +
> >>> +  @retval TRUE    IA32_EFER.NXE should be enabled.
> >>> +  @retval FALSE   IA32_EFER.NXE should not be enabled.
> >>> +
> >>> +**/
> >>> +BOOLEAN
> >>> +EnableNonExec (
> >>> +  VOID
> >>> +  )
> >>> +{
> >>> +  if (!IsExecuteDisableBitAvailable ()) {
> >>> +    return FALSE;
> >>> +  }
> >>> +
> >>> +  //
> >>> +  // XD flag (BIT63) in page table entry is only valid if
> >>> IA32_EFER.NXE is set.
> >>> +  // Features controlled by Following PCDs need this feature to be
> >>> enabled.

Re: [edk2] [PATCH 3/3] MdeModulePkg/PciHostBridge: Add RESOURCE_VALID() to simplify code

[Zeng, Star]

On 2018/9/25 10:47, Ni, Ruiyu wrote:

On 9/25/2018 10:35 AM, Zeng, Star wrote:

On 2018/9/21 19:12, Laszlo Ersek wrote:

On 09/21/18 09:25, Ruiyu Ni wrote:

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Star Zeng 
---
  .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 26 
++

  1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c

index f6234b5d11..916709e276 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -21,6 +21,8 @@ extern EDKII_IOMMU_PROTOCOL    *mIoMmuProtocol;
  #define NO_MAPPING  (VOID *) (UINTN) -1
+#define RESOURCE_VALID(R) ((R).Base <= (R).Limit)
+
  //
  // Lookup table for increment values based on transfer widths
  //
@@ -122,25 +124,25 @@ CreateRootBridge (
    //
    // Make sure Mem and MemAbove4G apertures are valid
    //
-  if (Bridge->Mem.Base <= Bridge->Mem.Limit) {
+  if (RESOURCE_VALID (Bridge->Mem)) {
  ASSERT (Bridge->Mem.Limit < SIZE_4GB);
  if (Bridge->Mem.Limit >= SIZE_4GB) {
    return NULL;
  }
    }
-  if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {
+  if (RESOURCE_VALID (Bridge->MemAbove4G)) {
  ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
  if (Bridge->MemAbove4G.Base < SIZE_4GB) {
    return NULL;
  }
    }
-  if (Bridge->PMem.Base <= Bridge->PMem.Limit) {
+  if (RESOURCE_VALID (Bridge->PMem)) {
  ASSERT (Bridge->PMem.Limit < SIZE_4GB);
  if (Bridge->PMem.Limit >= SIZE_4GB) {
    return NULL;
  }
    }
-  if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {
+  if (RESOURCE_VALID (Bridge->PMemAbove4G)) {
  ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
  if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
    return NULL;
@@ -157,11 +159,9 @@ CreateRootBridge (
    // support separate windows for Non-prefetchable and 
Prefetchable

    // memory.
    //
-  ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);
-  ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
-  if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||
-  (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
-  ) {
+  ASSERT (!RESOURCE_VALID (Bridge->PMem));
+  ASSERT (!RESOURCE_VALID (Bridge->PMemAbove4G));
+  if (RESOURCE_VALID (Bridge->PMem) || RESOURCE_VALID 
(Bridge->PMemAbove4G)) {

  return NULL;
    }
  }
@@ -171,11 +171,9 @@ CreateRootBridge (
    // If this bit is not set, then the PCI Root Bridge does not 
support

    // 64 bit memory windows.
    //
-  ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);
-  ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
-  if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||
-  (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
-  ) {
+  ASSERT (!RESOURCE_VALID (Bridge->MemAbove4G));
+  ASSERT (!RESOURCE_VALID (Bridge->PMemAbove4G));
+  if (RESOURCE_VALID (Bridge->MemAbove4G) || RESOURCE_VALID 
(Bridge->PMemAbove4G)) {

  return NULL;
    }
  }



Two superficial comments:

- edk2 prefers long parameter names, so I suggest replacing "R" in the
macro definition with "Resource"

- taking the parameter as a pointer is frequently considered more 
flexible.


#define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)

if (RESOURCE_VALID (>Mem)) {


Up to you -- if you like these, feel free to update the patch before
pushing it (from my side anyway; you do need MdeModulePkg maintainer
review as well).


I have no strong preference here. Let Ray to make the choice.
I have another very small comment.
Is it better to add "#define RESOURCE_VALID(R) ((R).Base <= 
(R).Limit)" in PciRootBridge.h?

Also move "#define NO_MAPPING  (VOID *) (UINTN) -1" into PciRootBridge.h?
And also move "extern EDKII_IOMMU_PROTOCOL    *mIoMmuProtocol;" 
into PciHostBridge.h?


The NO_MAPPING, RESOURCE_VALID macros are only used in this C file.
I prefer to put them in PciRootBridge.h only when another C file needs 
to reference these macros.


But then there will be a little inconsistent, for example OPERATION_TYPE 
is only used by PciRootBridgeIo.c.





I agree moving mIoMmuProtocol to PciHostBridge.h.
I am happy to do that in a separate patch in V2.


Thanks. If we will only move mIoMmuProtocol, it can be in a separated patch.


Star



Agree?



Thanks,
Star



With or without changes:

Reviewed-by: Laszlo Ersek 

Thanks
Laszlo








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Re: [edk2] [PATCH 1/3] MdeModulePkg/PciHostBridge: Enhance boundary check in Io/Mem.Read/Write

[Zeng, Star]

On 2018/9/25 10:43, Ni, Ruiyu wrote:

On 9/25/2018 10:14 AM, Zeng, Star wrote:

Two very small comments are added below.

On 2018/9/21 15:25, Ruiyu Ni wrote:

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Star Zeng 
---
  .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 26 
+-

  1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c

index f8a1239ceb..0b6b56f846 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -321,6 +321,7 @@ RootBridgeIoCheckParameter (
    UINT64   Base;
    UINT64   Limit;
    UINT32   Size;
+  UINT64   Length;
    //
    // Check to see if Buffer is NULL
@@ -337,7 +338,7 @@ RootBridgeIoCheckParameter (
    }
    //
-  // For FIFO type, the target address won't increase during the 
access,
+  // For FIFO type, the device address won't increase during the 
access,

    // so treat Count as 1
    //
    if (Width >= EfiPciWidthFifoUint8 && Width <= 
EfiPciWidthFifoUint64) {

@@ -347,6 +348,13 @@ RootBridgeIoCheckParameter (
    Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
    Size  = 1 << Width;
+  //
+  // Make sure (Count * Size) doesn't exceed MAX_UINT64
+  //
+  if (Count > DivU64x32 (MAX_UINT64, Size)) {
+    return EFI_INVALID_PARAMETER;
+  }
+


Mark as "Code Block 1".


    //
    // Check to see if Address is aligned
    //
@@ -354,6 +362,14 @@ RootBridgeIoCheckParameter (
  return EFI_UNSUPPORTED;
    }
+  //
+  // Make sure (Address + Count * Size) doesn't exceed MAX_UINT64
+  //
+  Length = MultU64x32 (Count, Size);
+  if (Address > MAX_UINT64 - Length) {
+    return EFI_INVALID_PARAMETER;
+  }
+


Is there some reason this code block is not put together with the 
"Code Block 1"? Both are checking integer overflow.


This code block is to check whether the Address is valid.
I group the code by the parameter. If you check the original code, you 
will see the checks performed on parameters: Buffer, Width, Count, Address.


Got it about the checking sequence.
But even this code block is moved to before "Check to see if Address is 
aligned" and after "Make sure (Count * Size) doesn't exceed MAX_UINT64", 
the checking sequence is kept. Only difference is first checking 
unsupported or first checking invalid for Address parameter.


Anyway, I have no strong opinion for that. You can decide. :)






How about also enhancing the function description a little to add one 
line for describing the overflow invalid parameter cases?


   @retval EFI_INVALID_PARAMETER  XXX.


Sure, I will send V2 with the updated function description.


Thanks. You may consider just updating the below EFI_UNSUPPORTED to 
EFI_INVALID_PARAMETER.


  @retval EFI_UNSUPPORTEDThe address range specified by 
Address, Width,

 and Count is not valid for this PI system.



Star





or just updating the line below?

   @retval EFI_UNSUPPORTED    The address range specified by 
Address, Width,
  and Count is not valid for this PI 
system.



Thanks,
Star


    RootBridge = ROOT_BRIDGE_FROM_THIS (This);
    //
@@ -372,7 +388,7 @@ RootBridgeIoCheckParameter (
  //
  // Allow Legacy IO access
  //
-    if (Address + MultU64x32 (Count, Size) <= 0x1000) {
+    if (Address + Length <= 0x1000) {
    if ((RootBridge->Attributes & (
 EFI_PCI_ATTRIBUTE_ISA_IO | 
EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |
 EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | 
EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |

@@ -386,7 +402,7 @@ RootBridgeIoCheckParameter (
  //
  // Allow Legacy MMIO access
  //
-    if ((Address >= 0xA) && (Address + MultU64x32 (Count, Size)) 
<= 0xC) {

+    if ((Address >= 0xA) && (Address + Length) <= 0xC) {
    if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) 
!= 0) {

  return EFI_SUCCESS;
    }
@@ -395,7 +411,7 @@ RootBridgeIoCheckParameter (
  // By comparing the Address against Limit we know which range 
to be used

  // for checking
  //
-    if (Address + MultU64x32 (Count, Size) <= RootBridge->Mem.Limit 
+ 1) {

+    if (Address + Length <= RootBridge->Mem.Limit + 1) {
    Base = RootBridge->Mem.Base;
    Limit = RootBridge->Mem.Limit;
  } else {
@@ -427,7 +443,7 @@ RootBridgeIoCheckParameter (
    return EFI_INVALID_PARAMETER;
    }
-  if (Address + MultU64x32 (Count, Size) > Limit + 1) {
+  if (Address + Length > Limit + 1) {
  return EFI_INVALID_PARAMETER;
    }








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Re: [edk2] [PATCH 3/3] MdeModulePkg/PciHostBridge: Add RESOURCE_VALID() to simplify code

[Ni, Ruiyu]

On 9/25/2018 10:35 AM, Zeng, Star wrote:

On 2018/9/21 19:12, Laszlo Ersek wrote:

On 09/21/18 09:25, Ruiyu Ni wrote:

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Star Zeng 
---
  .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 26 
++

  1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c

index f6234b5d11..916709e276 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -21,6 +21,8 @@ extern EDKII_IOMMU_PROTOCOL    *mIoMmuProtocol;
  #define NO_MAPPING  (VOID *) (UINTN) -1
+#define RESOURCE_VALID(R) ((R).Base <= (R).Limit)
+
  //
  // Lookup table for increment values based on transfer widths
  //
@@ -122,25 +124,25 @@ CreateRootBridge (
    //
    // Make sure Mem and MemAbove4G apertures are valid
    //
-  if (Bridge->Mem.Base <= Bridge->Mem.Limit) {
+  if (RESOURCE_VALID (Bridge->Mem)) {
  ASSERT (Bridge->Mem.Limit < SIZE_4GB);
  if (Bridge->Mem.Limit >= SIZE_4GB) {
    return NULL;
  }
    }
-  if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {
+  if (RESOURCE_VALID (Bridge->MemAbove4G)) {
  ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
  if (Bridge->MemAbove4G.Base < SIZE_4GB) {
    return NULL;
  }
    }
-  if (Bridge->PMem.Base <= Bridge->PMem.Limit) {
+  if (RESOURCE_VALID (Bridge->PMem)) {
  ASSERT (Bridge->PMem.Limit < SIZE_4GB);
  if (Bridge->PMem.Limit >= SIZE_4GB) {
    return NULL;
  }
    }
-  if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {
+  if (RESOURCE_VALID (Bridge->PMemAbove4G)) {
  ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
  if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
    return NULL;
@@ -157,11 +159,9 @@ CreateRootBridge (
    // support separate windows for Non-prefetchable and 
Prefetchable

    // memory.
    //
-  ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);
-  ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
-  if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||
-  (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
-  ) {
+  ASSERT (!RESOURCE_VALID (Bridge->PMem));
+  ASSERT (!RESOURCE_VALID (Bridge->PMemAbove4G));
+  if (RESOURCE_VALID (Bridge->PMem) || RESOURCE_VALID 
(Bridge->PMemAbove4G)) {

  return NULL;
    }
  }
@@ -171,11 +171,9 @@ CreateRootBridge (
    // If this bit is not set, then the PCI Root Bridge does not 
support

    // 64 bit memory windows.
    //
-  ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);
-  ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
-  if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||
-  (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
-  ) {
+  ASSERT (!RESOURCE_VALID (Bridge->MemAbove4G));
+  ASSERT (!RESOURCE_VALID (Bridge->PMemAbove4G));
+  if (RESOURCE_VALID (Bridge->MemAbove4G) || RESOURCE_VALID 
(Bridge->PMemAbove4G)) {

  return NULL;
    }
  }



Two superficial comments:

- edk2 prefers long parameter names, so I suggest replacing "R" in the
macro definition with "Resource"

- taking the parameter as a pointer is frequently considered more 
flexible.


#define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)

if (RESOURCE_VALID (>Mem)) {


Up to you -- if you like these, feel free to update the patch before
pushing it (from my side anyway; you do need MdeModulePkg maintainer
review as well).


I have no strong preference here. Let Ray to make the choice.
I have another very small comment.
Is it better to add "#define RESOURCE_VALID(R) ((R).Base <= (R).Limit)" 
in PciRootBridge.h?

Also move "#define NO_MAPPING  (VOID *) (UINTN) -1" into PciRootBridge.h?
And also move "extern EDKII_IOMMU_PROTOCOL    *mIoMmuProtocol;" into 
PciHostBridge.h?


The NO_MAPPING, RESOURCE_VALID macros are only used in this C file.
I prefer to put them in PciRootBridge.h only when another C file needs 
to reference these macros.


I agree moving mIoMmuProtocol to PciHostBridge.h.
I am happy to do that in a separate patch in V2.

Agree?



Thanks,
Star



With or without changes:

Reviewed-by: Laszlo Ersek 

Thanks
Laszlo






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Re: [edk2] [PATCH 1/3] MdeModulePkg/PciHostBridge: Enhance boundary check in Io/Mem.Read/Write

[Ni, Ruiyu]

On 9/25/2018 10:14 AM, Zeng, Star wrote:

Two very small comments are added below.

On 2018/9/21 15:25, Ruiyu Ni wrote:

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Star Zeng 
---
  .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 26 
+-

  1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c

index f8a1239ceb..0b6b56f846 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -321,6 +321,7 @@ RootBridgeIoCheckParameter (
    UINT64   Base;
    UINT64   Limit;
    UINT32   Size;
+  UINT64   Length;
    //
    // Check to see if Buffer is NULL
@@ -337,7 +338,7 @@ RootBridgeIoCheckParameter (
    }
    //
-  // For FIFO type, the target address won't increase during the access,
+  // For FIFO type, the device address won't increase during the access,
    // so treat Count as 1
    //
    if (Width >= EfiPciWidthFifoUint8 && Width <= 
EfiPciWidthFifoUint64) {

@@ -347,6 +348,13 @@ RootBridgeIoCheckParameter (
    Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
    Size  = 1 << Width;
+  //
+  // Make sure (Count * Size) doesn't exceed MAX_UINT64
+  //
+  if (Count > DivU64x32 (MAX_UINT64, Size)) {
+    return EFI_INVALID_PARAMETER;
+  }
+


Mark as "Code Block 1".


    //
    // Check to see if Address is aligned
    //
@@ -354,6 +362,14 @@ RootBridgeIoCheckParameter (
  return EFI_UNSUPPORTED;
    }
+  //
+  // Make sure (Address + Count * Size) doesn't exceed MAX_UINT64
+  //
+  Length = MultU64x32 (Count, Size);
+  if (Address > MAX_UINT64 - Length) {
+    return EFI_INVALID_PARAMETER;
+  }
+


Is there some reason this code block is not put together with the "Code 
Block 1"? Both are checking integer overflow.


This code block is to check whether the Address is valid.
I group the code by the parameter. If you check the original code, you 
will see the checks performed on parameters: Buffer, Width, Count, Address.





How about also enhancing the function description a little to add one 
line for describing the overflow invalid parameter cases?


   @retval EFI_INVALID_PARAMETER  XXX.


Sure, I will send V2 with the updated function description.



or just updating the line below?

   @retval EFI_UNSUPPORTED    The address range specified by 
Address, Width,
  and Count is not valid for this PI 
system.



Thanks,
Star


    RootBridge = ROOT_BRIDGE_FROM_THIS (This);
    //
@@ -372,7 +388,7 @@ RootBridgeIoCheckParameter (
  //
  // Allow Legacy IO access
  //
-    if (Address + MultU64x32 (Count, Size) <= 0x1000) {
+    if (Address + Length <= 0x1000) {
    if ((RootBridge->Attributes & (
 EFI_PCI_ATTRIBUTE_ISA_IO | 
EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_ATTRIBUTE_VGA_IO |
 EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | 
EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |

@@ -386,7 +402,7 @@ RootBridgeIoCheckParameter (
  //
  // Allow Legacy MMIO access
  //
-    if ((Address >= 0xA) && (Address + MultU64x32 (Count, Size)) 
<= 0xC) {

+    if ((Address >= 0xA) && (Address + Length) <= 0xC) {
    if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) != 
0) {

  return EFI_SUCCESS;
    }
@@ -395,7 +411,7 @@ RootBridgeIoCheckParameter (
  // By comparing the Address against Limit we know which range to 
be used

  // for checking
  //
-    if (Address + MultU64x32 (Count, Size) <= RootBridge->Mem.Limit + 
1) {

+    if (Address + Length <= RootBridge->Mem.Limit + 1) {
    Base = RootBridge->Mem.Base;
    Limit = RootBridge->Mem.Limit;
  } else {
@@ -427,7 +443,7 @@ RootBridgeIoCheckParameter (
    return EFI_INVALID_PARAMETER;
    }
-  if (Address + MultU64x32 (Count, Size) > Limit + 1) {
+  if (Address + Length > Limit + 1) {
  return EFI_INVALID_PARAMETER;
    }






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Re: [edk2] [PATCH 3/3] MdeModulePkg/PciHostBridge: Add RESOURCE_VALID() to simplify code

[Zeng, Star]

On 2018/9/21 19:12, Laszlo Ersek wrote:

On 09/21/18 09:25, Ruiyu Ni wrote:

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Star Zeng 
---
  .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 26 ++
  1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index f6234b5d11..916709e276 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -21,6 +21,8 @@ extern EDKII_IOMMU_PROTOCOL*mIoMmuProtocol;
  
  #define NO_MAPPING  (VOID *) (UINTN) -1
  
+#define RESOURCE_VALID(R) ((R).Base <= (R).Limit)

+
  //
  // Lookup table for increment values based on transfer widths
  //
@@ -122,25 +124,25 @@ CreateRootBridge (
//
// Make sure Mem and MemAbove4G apertures are valid
//
-  if (Bridge->Mem.Base <= Bridge->Mem.Limit) {
+  if (RESOURCE_VALID (Bridge->Mem)) {
  ASSERT (Bridge->Mem.Limit < SIZE_4GB);
  if (Bridge->Mem.Limit >= SIZE_4GB) {
return NULL;
  }
}
-  if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {
+  if (RESOURCE_VALID (Bridge->MemAbove4G)) {
  ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
  if (Bridge->MemAbove4G.Base < SIZE_4GB) {
return NULL;
  }
}
-  if (Bridge->PMem.Base <= Bridge->PMem.Limit) {
+  if (RESOURCE_VALID (Bridge->PMem)) {
  ASSERT (Bridge->PMem.Limit < SIZE_4GB);
  if (Bridge->PMem.Limit >= SIZE_4GB) {
return NULL;
  }
}
-  if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {
+  if (RESOURCE_VALID (Bridge->PMemAbove4G)) {
  ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
  if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
return NULL;
@@ -157,11 +159,9 @@ CreateRootBridge (
// support separate windows for Non-prefetchable and Prefetchable
// memory.
//
-  ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);
-  ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
-  if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||
-  (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
-  ) {
+  ASSERT (!RESOURCE_VALID (Bridge->PMem));
+  ASSERT (!RESOURCE_VALID (Bridge->PMemAbove4G));
+  if (RESOURCE_VALID (Bridge->PMem) || RESOURCE_VALID 
(Bridge->PMemAbove4G)) {
  return NULL;
}
  }
@@ -171,11 +171,9 @@ CreateRootBridge (
// If this bit is not set, then the PCI Root Bridge does not support
// 64 bit memory windows.
//
-  ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);
-  ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
-  if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||
-  (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
-  ) {
+  ASSERT (!RESOURCE_VALID (Bridge->MemAbove4G));
+  ASSERT (!RESOURCE_VALID (Bridge->PMemAbove4G));
+  if (RESOURCE_VALID (Bridge->MemAbove4G) || RESOURCE_VALID 
(Bridge->PMemAbove4G)) {
  return NULL;
}
  }



Two superficial comments:

- edk2 prefers long parameter names, so I suggest replacing "R" in the
macro definition with "Resource"

- taking the parameter as a pointer is frequently considered more flexible.

#define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)

if (RESOURCE_VALID (>Mem)) {


Up to you -- if you like these, feel free to update the patch before
pushing it (from my side anyway; you do need MdeModulePkg maintainer
review as well).


I have no strong preference here. Let Ray to make the choice.
I have another very small comment.
Is it better to add "#define RESOURCE_VALID(R) ((R).Base <= (R).Limit)" 
in PciRootBridge.h?

Also move "#define NO_MAPPING  (VOID *) (UINTN) -1" into PciRootBridge.h?
And also move "extern EDKII_IOMMU_PROTOCOL*mIoMmuProtocol;" into 
PciHostBridge.h?


Thanks,
Star



With or without changes:

Reviewed-by: Laszlo Ersek 

Thanks
Laszlo



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Re: [edk2] [PATCH 2/3] MdeModulePkg/PciHostBridge: Fix a bug that prevents PMEM access

[Zeng, Star]

On 2018/9/21 15:25, Ruiyu Ni wrote:

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1196

RootBridgeIoCheckParameter() verifies that the requested MMIO access
can fit in any of the MEM/PMEM 32/64 ranges. But today's logic
somehow only checks the requested access against MEM 32/64 ranges.

It should also check the requested access against PMEM 32/64 ranges.

The patch fixes this issue.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Star Zeng 
Cc: Kirkendall, Garrett 


Reviewed-by: Star Zeng 

Thanks,
Star


---
  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 14 ++
  1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index 0b6b56f846..f6234b5d11 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -411,12 +411,18 @@ RootBridgeIoCheckParameter (
  // By comparing the Address against Limit we know which range to be used
  // for checking
  //
-if (Address + Length <= RootBridge->Mem.Limit + 1) {
-  Base = RootBridge->Mem.Base;
+if ((Address >= RootBridge->Mem.Base) && (Address + Length <= 
RootBridge->Mem.Limit + 1)) {
+  Base  = RootBridge->Mem.Base;
Limit = RootBridge->Mem.Limit;
-} else {
-  Base = RootBridge->MemAbove4G.Base;
+} else if ((Address >= RootBridge->PMem.Base) && (Address + Length <= 
RootBridge->PMem.Limit + 1)) {
+  Base  = RootBridge->PMem.Base;
+  Limit = RootBridge->PMem.Limit;
+} else if ((Address >= RootBridge->MemAbove4G.Base) && (Address + Length <= 
RootBridge->MemAbove4G.Limit + 1)) {
+  Base  = RootBridge->MemAbove4G.Base;
Limit = RootBridge->MemAbove4G.Limit;
+} else {
+  Base  = RootBridge->PMemAbove4G.Base;
+  Limit = RootBridge->PMemAbove4G.Limit;
  }
} else {
  PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) 



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Re: [edk2] [PATCH 1/3] MdeModulePkg/PciHostBridge: Enhance boundary check in Io/Mem.Read/Write

[Zeng, Star]

Two very small comments are added below.

On 2018/9/21 15:25, Ruiyu Ni wrote:

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Star Zeng 
---
  .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 26 +-
  1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index f8a1239ceb..0b6b56f846 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -321,6 +321,7 @@ RootBridgeIoCheckParameter (
UINT64   Base;
UINT64   Limit;
UINT32   Size;
+  UINT64   Length;
  
//

// Check to see if Buffer is NULL
@@ -337,7 +338,7 @@ RootBridgeIoCheckParameter (
}
  
//

-  // For FIFO type, the target address won't increase during the access,
+  // For FIFO type, the device address won't increase during the access,
// so treat Count as 1
//
if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
@@ -347,6 +348,13 @@ RootBridgeIoCheckParameter (
Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
Size  = 1 << Width;
  
+  //

+  // Make sure (Count * Size) doesn't exceed MAX_UINT64
+  //
+  if (Count > DivU64x32 (MAX_UINT64, Size)) {
+return EFI_INVALID_PARAMETER;
+  }
+


Mark as "Code Block 1".


//
// Check to see if Address is aligned
//
@@ -354,6 +362,14 @@ RootBridgeIoCheckParameter (
  return EFI_UNSUPPORTED;
}
  
+  //

+  // Make sure (Address + Count * Size) doesn't exceed MAX_UINT64
+  //
+  Length = MultU64x32 (Count, Size);
+  if (Address > MAX_UINT64 - Length) {
+return EFI_INVALID_PARAMETER;
+  }
+


Is there some reason this code block is not put together with the "Code 
Block 1"? Both are checking integer overflow.


How about also enhancing the function description a little to add one 
line for describing the overflow invalid parameter cases?


  @retval EFI_INVALID_PARAMETER  XXX.

or just updating the line below?

  @retval EFI_UNSUPPORTEDThe address range specified by 
Address, Width,

 and Count is not valid for this PI system.


Thanks,
Star


RootBridge = ROOT_BRIDGE_FROM_THIS (This);
  
//

@@ -372,7 +388,7 @@ RootBridgeIoCheckParameter (
  //
  // Allow Legacy IO access
  //
-if (Address + MultU64x32 (Count, Size) <= 0x1000) {
+if (Address + Length <= 0x1000) {
if ((RootBridge->Attributes & (
 EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | 
EFI_PCI_ATTRIBUTE_VGA_IO |
 EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | 
EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
@@ -386,7 +402,7 @@ RootBridgeIoCheckParameter (
  //
  // Allow Legacy MMIO access
  //
-if ((Address >= 0xA) && (Address + MultU64x32 (Count, Size)) <= 
0xC) {
+if ((Address >= 0xA) && (Address + Length) <= 0xC) {
if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) != 0) {
  return EFI_SUCCESS;
}
@@ -395,7 +411,7 @@ RootBridgeIoCheckParameter (
  // By comparing the Address against Limit we know which range to be used
  // for checking
  //
-if (Address + MultU64x32 (Count, Size) <= RootBridge->Mem.Limit + 1) {
+if (Address + Length <= RootBridge->Mem.Limit + 1) {
Base = RootBridge->Mem.Base;
Limit = RootBridge->Mem.Limit;
  } else {
@@ -427,7 +443,7 @@ RootBridgeIoCheckParameter (
return EFI_INVALID_PARAMETER;
}
  
-  if (Address + MultU64x32 (Count, Size) > Limit + 1) {

+  if (Address + Length > Limit + 1) {
  return EFI_INVALID_PARAMETER;
}
  



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Re: [edk2] [PATCH 3/3] MdeModulePkg/PciHostBridge: Add RESOURCE_VALID() to simplify code

[Ni, Ruiyu]

On 9/21/2018 7:12 PM, Laszlo Ersek wrote:

On 09/21/18 09:25, Ruiyu Ni wrote:

Two superficial comments:

- edk2 prefers long parameter names, so I suggest replacing "R" in the
macro definition with "Resource"

- taking the parameter as a pointer is frequently considered more flexible.

#define RESOURCE_VALID(Resource) ((Resource)->Base <= (Resource)->Limit)
...
if (RESOURCE_VALID (>Mem)) {
...

Up to you -- if you like these, feel free to update the patch before
pushing it (from my side anyway; you do need MdeModulePkg maintainer
review as well).


Good comments. I will update the patch then commit.



With or without changes:

Reviewed-by: Laszlo Ersek 

Thanks
Laszlo
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--
Thanks,
Ray
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Re: [edk2] [Patch v2 08/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition.

[Dong, Eric]

Hi Ruiyu & Laszlo,

Thanks for your comments. I will update V3 patches.

Thanks,
Eric

> -Original Message-
> From: Laszlo Ersek [mailto:ler...@redhat.com]
> Sent: Friday, September 21, 2018 5:42 PM
> To: Ni, Ruiyu ; Dong, Eric ; edk2-
> de...@lists.01.org
> Cc: Kinney, Michael D 
> Subject: Re: [Patch v2 08/14]
> UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure
> definition.
> 
> On 09/21/18 10:44, Ni, Ruiyu wrote:
> > On 9/21/2018 3:41 PM, Eric Dong wrote:
> >>   UINT32  User:1;
> >> -    UINT32  Reserved1:2;
> >> +    ///
> >> +    /// [Bit 4] PwrEvtEn.
> >> +    ///
> >> +    UINT32  PwrEvtEn:1;
> >> +    ///
> >> +    /// [Bit 5] FUPonPTW.
> >> +    ///
> >> +    UINT32  FUPonPTW:1;
> >>   ///
> >>   /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
> >>   ///
> >> @@ -4672,7 +4679,10 @@ typedef union {
> >>   /// [Bit 11] DisRETC.
> >>   ///
> >>   UINT32  DisRETC:1;
> >> -    UINT32  Reserved2:1;
> >> +    ///
> >> +    /// [Bit 12] PTWEn.
> >> +    ///
> >> +    UINT32  PTWEn:1;
> >>   ///
> >>   /// [Bit 13] BranchEn.
> >>   ///
> >> @@ -4681,17 +4691,17 @@ typedef union {
> >>   /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
> >>   ///
> >>   UINT32  MTCFreq:4;
> >> -    UINT32  Reserved3:1;
> >> +    UINT32  Reserved7:1;
> >
> > I prefer to not change this field name since the bit range for this
> > Reserved6 is not changed.
> >
> >>   ///
> >>   /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
> >>   ///
> >>   UINT32  CYCThresh:4;
> >> -    UINT32  Reserved4:1;
> >> +    UINT32  Reserved8:1;
> >
> > I prefer to not change this field name since the bit range for this
> > Reserved6 is not changed.
> >
> >>   ///
> >>   /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
> >>   ///
> >>   UINT32  PSBFreq:4;
> >> -    UINT32  Reserved5:4;
> >> +    UINT32  Reserved9:4;
> >
> > I prefer to not change this field name since the bit range for this
> > Reserved6 is not changed.
> >
> >>   ///
> >>   /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0]
> >> > 0).
> >>   ///
> >> @@ -4708,7 +4718,7 @@ typedef union {
> >>   /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0]
> >> > 3).
> >>   ///
> >>   UINT32  ADDR3_CFG:4;
> >> -    UINT32  Reserved6:16;
> >> +    UINT32  Reserved10:16;
> >
> > I prefer to not change this field name since the bit range for this
> > Reserved6 is not changed.
> >
> >>     } Bits;
> >
> >
> > Eric,
> > As comments above, I suggest we keep the original Reserved## name if
> > the bit range for that field doesn't change. We can only update the
> > Reserved## name if the bit range changes.
> >
> > In this way, we can maximally avoid build failure and also avoid
> > silent failure.
> >
> > In general, the Reserved## name is updated when the bit range changes.
> > The ## is updated to
> > 1 + MAX (all numbers used by Reserved## in this structure).
> >
> >
> > Laszlo,
> > What's your opinion?
> >
> 
> I agree with your suggestion.
> 
> Thanks
> Laszlo
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[edk2] [Patch v3 12/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and keep old one.

[Eric Dong]

Changes includes:
  1. Change MSR name:
1. MSR_SKYLAKE_SGXOWNER0 => MSR_SKYLAKE_SGXOWNEREPOCH0
2. MSR_SKYLAKE_SGXOWNER1 => MSR_SKYLAKE_SGXOWNEREPOCH1
  2. Keep old MSR definition(MSR_SKYLAKE_SGXOWNER0/1) for compatibility
1. Use below coding style to define old MSR
 #define MSR_SKYLAKE_SGXOWNER0  MSR_SKYLAKE_SGXOWNEREPOCH0

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 40 +++-
 1 file changed, 27 insertions(+), 13 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h 
b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 90cde86ccb..88f2c28eae 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -197,10 +197,12 @@ typedef union {
 
 
 /**
-  Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
-  an 128-bit external entropy value for key derivation of an enclave.
+  Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+  CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+  the package. Lower 64 bits of an 128-bit external entropy value for key
+  derivation of an enclave.
 
-  @param  ECX  MSR_SKYLAKE_SGXOWNER0 (0x0300)
+  @param  ECX  MSR_SKYLAKE_SGXOWNEREPOCH0 (0x0300)
   @param  EAX  Lower 32-bits of MSR value.
   @param  EDX  Upper 32-bits of MSR value.
 
@@ -208,18 +210,24 @@ typedef union {
   @code
   UINT64  Msr;
 
-  Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0);
+  Msr = 0;
+  AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr);
   @endcode
-  @note MSR_SKYLAKE_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.
+  @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.
 **/
-#define MSR_SKYLAKE_SGXOWNER00x0300
-
+#define MSR_SKYLAKE_SGXOWNEREPOCH00x0300
 
+//
+// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the 
SDM.
+//
+#define MSR_SKYLAKE_SGXOWNER0 
MSR_SKYLAKE_SGXOWNEREPOCH0
 /**
-  Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
-  an 128-bit external entropy value for key derivation of an enclave.
+  Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+  CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+  the package. Upper 64 bits of an 128-bit external entropy value for key
+  derivation of an enclave.
 
-  @param  ECX  MSR_SKYLAKE_SGXOWNER1 (0x0301)
+  @param  ECX  MSR_SKYLAKE_SGXOWNEREPOCH1 (0x0301)
   @param  EAX  Lower 32-bits of MSR value.
   @param  EDX  Upper 32-bits of MSR value.
 
@@ -227,11 +235,17 @@ typedef union {
   @code
   UINT64  Msr;
 
-  Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1);
+  Msr = 0;
+  AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr);
   @endcode
-  @note MSR_SKYLAKE_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.
+  @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.
 **/
-#define MSR_SKYLAKE_SGXOWNER10x0301
+#define MSR_SKYLAKE_SGXOWNEREPOCH10x0301
+
+//
+// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the 
SDM.
+//
+#define MSR_SKYLAKE_SGXOWNER1 MSR_SKYLAKE_SGXOWNEREPOCH1
 
 
 /**
-- 
2.15.0.windows.1

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[edk2] [Patch v3 14/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure definition.

[Eric Dong]

V3 changes include:
  1. Keep the ReservedX not change if bit info not changed for this field.

V2 changes include:
  1. Use X in ReservedX fields from totally new value if MSR structure 
definition changed.
 For example, if in current structure, the max reserved variable is 
Reserved2, in new
 definition, reserved variable is begin with Reserved3.

V1 Changes:
Changes includes:
  1. Update MSR structure definition, change some reserved fields to useful 
fields:
 1. MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
 2. MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
  2. For MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER structure, it expand the 
field range.
 Old definition like below:
   typedef union {
 ///
 /// Individual bit fields
 ///
 struct {
   ///
   /// [Bits 15:0] LVL_2 Base Address (R/W).
   ///
   UINT32  Lvl2Base:16;
   ///
   /// [Bits 18:16] C-state Range (R/W)  Specifies the encoding value 
of the
   /// maximum C-State code name to be included when IO read to MWAIT
   /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 
100b - C4
   /// is the max C-State to include 110b - C6 is the max C-State to 
include.
   ///
   UINT32  CStateRange:3;
   UINT32  Reserved1:13;
   UINT32  Reserved2:32;
 } Bits;
 ///
 /// All bit fields as a 32-bit value
 ///
 UINT32  Uint32;
 ///
 /// All bit fields as a 64-bit value
 ///
 UINT64  Uint64;
   } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;
This patch make below changes for this data structure, it expand 
"CStateRange" field width.
  old one:
UINT32  CStateRange:3;
UINT32  Reserved1:13;
  new one:
UINT32  CStateRange:7;
UINT32  Reserved1:9;

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 49 +++-
 1 file changed, 40 insertions(+), 9 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h 
b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index da74c2402c..1e22d98ad8 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -278,7 +278,25 @@ typedef union {
 /// [Bit 15] CFG Lock (R/WO).
 ///
 UINT32  CFGLock:1;
-UINT32  Reserved3:16;
+UINT32  Reserved5:10;
+///
+/// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor
+/// will conditionally demote C3/C6/C7 requests to C1 based on uncore
+/// auto-demote information.
+///
+UINT32  C1StateAutoDemotionEnable:1;
+UINT32  Reserved6:1;
+///
+/// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables
+/// Undemotion from Demoted C1.
+///
+UINT32  C1StateAutoUndemotionEnable:1;
+///
+/// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables
+/// Package C state demotion.
+///
+UINT32  PKGC_StateAutoDemotionEnable:1;
+UINT32  Reserved7:2;
 UINT32  Reserved4:32;
   } Bits;
   ///
@@ -325,13 +343,12 @@ typedef union {
 ///
 UINT32  Lvl2Base:16;
 ///
-/// [Bits 18:16] C-state Range (R/W)  Specifies the encoding value of the
-/// maximum C-State code name to be included when IO read to MWAIT
-/// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
-/// is the max C-State to include 110b - C6 is the max C-State to include.
+/// [Bits 22:16] C-State Range (R/W) The IO-port block size in which
+/// IO-redirection will be executed (0-127). Should be programmed based on
+/// the number of LVLx registers existing in the chipset.
 ///
-UINT32  CStateRange:3;
-UINT32  Reserved1:13;
+UINT32  CStateRange:7;
+UINT32  Reserved3:9;
 UINT32  Reserved2:32;
   } Bits;
   ///
@@ -477,8 +494,22 @@ typedef union {
   /// Individual bit fields
   ///
   struct {
-UINT32  Reserved1:32;
-UINT32  Reserved2:26;
+///
+/// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is
+/// set, that bank supports Enhanced MCA (Default all 0; does not support
+/// EMCA).
+///
+UINT32  BankSupport:32;
+UINT32  Reserved4:24;
+///
+/// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.
+///
+UINT32  TargetedSMI:1;
+///
+/// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature
+/// is supported.
+///
+UINT32  SMM_CPU_SVRSTR:1;
 ///
 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
 /// SMM code access restriction is supported and a host-space interface
-- 
2.15.0.windows.1

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[edk2] [Patch v3 09/14] UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR.

[Eric Dong]

Changes includes:
  1. Remove old MSR which not existed in 2018-05 version spec:
 1. MSR_CORE2_BBL_CR_CTL3

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 60 --
 1 file changed, 60 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h 
b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
index 22317fa1de..f01f7c5c97 100644
--- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
@@ -471,66 +471,6 @@ typedef union {
   UINT64  Uint64;
 } MSR_CORE2_FSB_FREQ_REGISTER;
 
-
-/**
-  Shared.
-
-  @param  ECX  MSR_CORE2_BBL_CR_CTL3 (0x011E)
-  @param  EAX  Lower 32-bits of MSR value.
-   Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
-  @param  EDX  Upper 32-bits of MSR value.
-   Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.
-
-  Example usage
-  @code
-  MSR_CORE2_BBL_CR_CTL3_REGISTER  Msr;
-
-  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);
-  AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);
-  @endcode
-  @note MSR_CORE2_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
-**/
-#define MSR_CORE2_BBL_CR_CTL30x011E
-
-/**
-  MSR information returned for MSR index #MSR_CORE2_BBL_CR_CTL3
-**/
-typedef union {
-  ///
-  /// Individual bit fields
-  ///
-  struct {
-///
-/// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
-/// Indicates if the L2 is hardware-disabled.
-///
-UINT32  L2HardwareEnabled:1;
-UINT32  Reserved1:7;
-///
-/// [Bit 8] L2 Enabled (R/W)  1 = L2 cache has been initialized 0 =
-/// Disabled (default) Until this bit is set the processor will not
-/// respond to the WBINVD instruction or the assertion of the FLUSH# input.
-///
-UINT32  L2Enabled:1;
-UINT32  Reserved2:14;
-///
-/// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.
-///
-UINT32  L2NotPresent:1;
-UINT32  Reserved3:8;
-UINT32  Reserved4:32;
-  } Bits;
-  ///
-  /// All bit fields as a 32-bit value
-  ///
-  UINT32  Uint32;
-  ///
-  /// All bit fields as a 64-bit value
-  ///
-  UINT64  Uint64;
-} MSR_CORE2_BBL_CR_CTL3_REGISTER;
-
-
 /**
   Shared.
 
-- 
2.15.0.windows.1

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[edk2] [Patch v3 10/14] UefiCpuPkg/Include/Register/Msr/P6Msr.h: Remove old MSR.

[Eric Dong]

Changes includes:
  1. Remove MSR which not existed in 2018-05 version spec: 
MSR_P6_ROB_CR_BKUPTMPDR6.

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/Msr/P6Msr.h | 48 -
 1 file changed, 48 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h 
b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
index d8af2db3da..9cef72b239 100644
--- a/UefiCpuPkg/Include/Register/Msr/P6Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
@@ -1153,54 +1153,6 @@ typedef union {
 **/
 #define MSR_P6_LASTINTTOIP   0x01DE
 
-
-/**
-
-
-  @param  ECX  MSR_P6_ROB_CR_BKUPTMPDR6 (0x01E0)
-  @param  EAX  Lower 32-bits of MSR value.
-   Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.
-  @param  EDX  Upper 32-bits of MSR value.
-   Described by the type MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER.
-
-  Example usage
-  @code
-  MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER  Msr;
-
-  Msr.Uint64 = AsmReadMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6);
-  AsmWriteMsr64 (MSR_P6_ROB_CR_BKUPTMPDR6, Msr.Uint64);
-  @endcode
-  @note MSR_P6_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.
-**/
-#define MSR_P6_ROB_CR_BKUPTMPDR6 0x01E0
-
-/**
-  MSR information returned for MSR index #MSR_P6_ROB_CR_BKUPTMPDR6
-**/
-typedef union {
-  ///
-  /// Individual bit fields
-  ///
-  struct {
-UINT32  Reserved1:2;
-///
-/// [Bit 2] Fast Strings Enable bit. Default is enabled.
-///
-UINT32  FastStrings:1;
-UINT32  Reserved2:29;
-UINT32  Reserved3:32;
-  } Bits;
-  ///
-  /// All bit fields as a 32-bit value
-  ///
-  UINT32  Uint32;
-  ///
-  /// All bit fields as a 64-bit value
-  ///
-  UINT64  Uint64;
-} MSR_P6_ROB_CR_BKUPTMPDR6_REGISTER;
-
-
 /**
 
 
-- 
2.15.0.windows.1

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[edk2] [Patch v3 11/14] UefiCpuPkg/Include/Register/Msr/CoreMsr.h: Remove old MSR.

[Eric Dong]

Changes includes:
  1. Remove old MSR which not existed in 2018-05 version spec:
 1. MSR_CORE_ROB_CR_BKUPTMPDR6

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 48 ---
 1 file changed, 48 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h 
b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
index bb2bdd2ca1..a4315d6e56 100644
--- a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
@@ -555,54 +555,6 @@ typedef union {
 **/
 #define MSR_CORE_LER_TO_LIP  0x01DE
 
-
-/**
-  Unique.
-
-  @param  ECX  MSR_CORE_ROB_CR_BKUPTMPDR6 (0x01E0)
-  @param  EAX  Lower 32-bits of MSR value.
-   Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
-  @param  EDX  Upper 32-bits of MSR value.
-   Described by the type MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER.
-
-  Example usage
-  @code
-  MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER  Msr;
-
-  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6);
-  AsmWriteMsr64 (MSR_CORE_ROB_CR_BKUPTMPDR6, Msr.Uint64);
-  @endcode
-  @note MSR_CORE_ROB_CR_BKUPTMPDR6 is defined as ROB_CR_BKUPTMPDR6 in SDM.
-**/
-#define MSR_CORE_ROB_CR_BKUPTMPDR6   0x01E0
-
-/**
-  MSR information returned for MSR index #MSR_CORE_ROB_CR_BKUPTMPDR6
-**/
-typedef union {
-  ///
-  /// Individual bit fields
-  ///
-  struct {
-UINT32  Reserved1:2;
-///
-/// [Bit 2] Fast Strings Enable bit. (Default, enabled).
-///
-UINT32  FastStrings:1;
-UINT32  Reserved2:29;
-UINT32  Reserved3:32;
-  } Bits;
-  ///
-  /// All bit fields as a 32-bit value
-  ///
-  UINT32  Uint32;
-  ///
-  /// All bit fields as a 64-bit value
-  ///
-  UINT64  Uint64;
-} MSR_CORE_ROB_CR_BKUPTMPDR6_REGISTER;
-
-
 /**
   Unique.
 
-- 
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[edk2] [Patch v3 13/14] UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: Add new MSR name and keep old one.

[Eric Dong]

Changes includes:
  1. Change MSR name:
1. MSR_GOLDMONT_SGXOWNER0 => MSR_GOLDMONT_SGXOWNEREPOCH0
2. MSR_GOLDMONT_SGXOWNER1 => MSR_GOLDMONT_SGXOWNEREPOCH1
  2. Keep old MSR definition (MSR_GOLDMONT_SGXOWNER0/1) for compatibility.
1. Define old MSR like below style:
   #define MSR_GOLDMONT_SGXOWNER0   MSR_GOLDMONT_SGXOWNEREPOCH0

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 34 +++
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h 
b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
index a9061133c9..383f31ee55 100644
--- a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
@@ -843,10 +843,12 @@ typedef union {
 
 
 /**
-  Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
-  an 128-bit external entropy value for key derivation of an enclave.
+  Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+  CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+  the package. Lower 64 bits of an 128-bit external entropy value for key
+  derivation of an enclave.
 
-  @param  ECX  MSR_GOLDMONT_SGXOWNER0 (0x0300)
+  @param  ECX  MSR_GOLDMONT_SGXOWNEREPOCH0 (0x0300)
   @param  EAX  Lower 32-bits of MSR value.
   @param  EDX  Upper 32-bits of MSR value.
 
@@ -854,18 +856,24 @@ typedef union {
   @code
   UINT64  Msr;
 
-  Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNER0);
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);
   @endcode
-  @note MSR_GOLDMONT_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM.
+  @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.
 **/
-#define MSR_GOLDMONT_SGXOWNER0   0x0300
+#define MSR_GOLDMONT_SGXOWNEREPOCH0   0x0300
+
+
+//
+// Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the 
SDM.
+//
+#define MSR_GOLDMONT_SGXOWNER0
MSR_GOLDMONT_SGXOWNEREPOCH0
 
 
 /**
   Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
   an 128-bit external entropy value for key derivation of an enclave.
 
-  @param  ECX  MSR_GOLDMONT_SGXOWNER1 (0x0301)
+  @param  ECX  MSR_GOLDMONT_SGXOWNEREPOCH1 (0x0301)
   @param  EAX  Lower 32-bits of MSR value.
   @param  EDX  Upper 32-bits of MSR value.
 
@@ -873,11 +881,17 @@ typedef union {
   @code
   UINT64  Msr;
 
-  Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNER1);
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);
   @endcode
-  @note MSR_GOLDMONT_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM.
+  @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.
 **/
-#define MSR_GOLDMONT_SGXOWNER1   0x0301
+#define MSR_GOLDMONT_SGXOWNEREPOCH1   0x0301
+
+
+//
+// Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the 
SDM.
+//
+#define MSR_GOLDMONT_SGXOWNER1
MSR_GOLDMONT_SGXOWNEREPOCH1
 
 
 /**
-- 
2.15.0.windows.1

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[edk2] [Patch v3 07/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR.

[Eric Dong]

Changes includes:
  1. Add new MSRs: MSR_IA32_L2_QOS_CFG/MSR_IA32_CSTAR.

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 64 ++
 1 file changed, 64 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h 
b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 5d2242aa80..b467ffaf26 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -5908,6 +5908,51 @@ typedef union {
   UINT64  Uint64;
 } MSR_IA32_L3_QOS_CFG_REGISTER;
 
+/**
+  L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).
+
+  @param  ECX  MSR_IA32_L2_QOS_CFG (0x0C82)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
+
+  Example usage
+  @code
+  MSR_IA32_L2_QOS_CFG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);
+  AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.
+**/
+#define MSR_IA32_L2_QOS_CFG  0x0C82
+
+/**
+  MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate
+/// in Code and Data Prioritization (CDP) mode.
+///
+UINT32  Enable:1;
+UINT32  Reserved1:31;
+UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_L2_QOS_CFG_REGISTER;
 
 /**
   Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
@@ -6380,6 +6425,25 @@ typedef union {
 **/
 #define MSR_IA32_LSTAR   0xC082
 
+/**
+  IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL
+  instruction is not recognized in compatibility mode. If
+  CPUID.8001:EDX.[29] = 1.
+
+  @param  ECX  MSR_IA32_CSTAR (0xC083)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_CSTAR);
+  AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);
+  @endcode
+  @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.
+**/
+#define MSR_IA32_CSTAR   0xC083
 
 /**
   System Call Flag Mask (R/W). If CPUID.8001:EDX.[29] = 1.
-- 
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[edk2] [Patch v3 03/14] UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR.

[Eric Dong]

Changes includes:
  1. Add new MSR: MSR_SILVERMONT_PLATFORM_INFO

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 48 +
 1 file changed, 48 insertions(+)

diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h 
b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
index 03bbd0af7c..c3d0f8c208 100644
--- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
@@ -375,6 +375,54 @@ typedef union {
 } MSR_SILVERMONT_FSB_FREQ_REGISTER;
 
 
+/**
+  Package. Platform Information: Contains power management and other model
+  specific features enumeration. See http://biosbits.org.
+
+  @param  ECX  MSR_SILVERMONT_PLATFORM_INFO (0x00CE)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
+
+  Example usage
+  @code
+  MSR_SILVERMONT_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SILVERMONT_PLATFORM_INFO 0x00CE
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:8;
+///
+/// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio
+/// of the maximum frequency that does not require turbo. Frequency =
+/// ratio * Scalable Bus Frequency.
+///
+UINT32  MaximumNon_TurboRatio:8;
+UINT32  Reserved2:16;
+UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_PLATFORM_INFO_REGISTER;
+
 /**
   Module. C-State Configuration Control (R/W)  Note: C-state values are
   processor specific C-state code names, unrelated to MWAIT extension C-state
-- 
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[edk2] [Patch v3 08/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition.

[Eric Dong]

V3 changes include:
  1. Keep ReservedX not change if bit info not changed for this field.

V2 changes include:
  1. Use X in ReservedX fields from totally new value if MSR structure 
definition changed.
 For example, if in current structure, the max reserved variable is 
Reserved2, in new
 definition, reserved variable is begin with Reserved3.

V1 Changes includes:
  1. Change fields which is reserved in old version: MSR_IA32_RTIT_CTL_REGISTER

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h 
b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index b467ffaf26..22d64e995b 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -4647,7 +4647,14 @@ typedef union {
 /// [Bit 3] User.
 ///
 UINT32  User:1;
-UINT32  Reserved1:2;
+///
+/// [Bit 4] PwrEvtEn.
+///
+UINT32  PwrEvtEn:1;
+///
+/// [Bit 5] FUPonPTW.
+///
+UINT32  FUPonPTW:1;
 ///
 /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
 ///
@@ -4672,7 +4679,10 @@ typedef union {
 /// [Bit 11] DisRETC.
 ///
 UINT32  DisRETC:1;
-UINT32  Reserved2:1;
+///
+/// [Bit 12] PTWEn.
+///
+UINT32  PTWEn:1;
 ///
 /// [Bit 13] BranchEn.
 ///
-- 
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[edk2] [Patch v3 01/14] UefiCpuPkg/Include/Register/Msr: Update reference spec info.

[Eric Dong]

Latest SDM has moved MSR related content from volume 3 chapter 35 to volume 4
chapter 2. Current MSR's comments need to be updated to reference the new
chapter info.

Changes includes:
  1. Update referenced chapter info from some MSRs.
  2. Update referenced SDM version info.

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/ArchitecturalMsr.h   |  44 ++---
 UefiCpuPkg/Include/Register/Msr/AtomMsr.h|  28 ++--
 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h   |   8 +-
 UefiCpuPkg/Include/Register/Msr/Core2Msr.h   |  42 ++---
 UefiCpuPkg/Include/Register/Msr/CoreMsr.h|  26 +--
 UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h|  54 +++---
 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h|   6 +-
 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h |  34 ++--
 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h   |   8 +-
 UefiCpuPkg/Include/Register/Msr/NehalemMsr.h |  52 +++---
 UefiCpuPkg/Include/Register/Msr/P6Msr.h  |  12 +-
 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h| 202 +++
 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h|  22 +--
 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h |  12 +-
 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h |  49 +++---
 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h  |  52 +++---
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h |  14 +-
 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h|   8 +-
 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h   |  28 ++--
 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h  |   6 +-
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h |  24 +--
 21 files changed, 359 insertions(+), 372 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h 
b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index 34fdf5be3a..5d2242aa80 100644
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -16,16 +16,8 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Specification Reference:
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
-  September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.1.
-
-  @par Specification Reference:
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
-  September 2016, Appendix A VMX Capability Reporting Facility, Section A.1.
-
-  @par Specification Reference:
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
-  September 2016, Appendix A VMX Capability Reporting Facility, Section A.6.
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
 
 **/
 
@@ -33,7 +25,7 @@
 #define __ARCHITECTURAL_MSR_H__
 
 /**
-  See Section 35.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
+  See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
 
   @param  ECX  MSR_IA32_P5_MC_ADDR (0x)
   @param  EAX  Lower 32-bits of MSR value.
@@ -52,7 +44,7 @@
 
 
 /**
-  See Section 35.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
+  See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
 
   @param  ECX  MSR_IA32_P5_MC_TYPE (0x0001)
   @param  EAX  Lower 32-bits of MSR value.
@@ -91,7 +83,7 @@
 
 
 /**
-  See Section 17.15, "Time-Stamp Counter.". Introduced at Display Family /
+  See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
   Display Model 05_01H.
 
   @param  ECX  MSR_IA32_TIME_STAMP_COUNTER (0x0010)
@@ -493,9 +485,8 @@ typedef union {
 UINT32  Valid:1;
 UINT32  Reserved1:1;
 ///
-/// [Bit 2] Determines whether executions of VMXOFF unblock SMIs under the
-/// default treatment of SMIs and SMM.  Executions of VMXOFF unblock SMIs
-/// unless bit 2 is 1 (the value of bit 0 is irrelevant).
+/// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
+/// IA32_VMX_MISC[28].
 ///
 UINT32  BlockSmi:1;
 UINT32  Reserved2:9;
@@ -1953,7 +1944,7 @@ typedef union {
 
 
 /**
-  SMRR Range Mask. (Writeable only in SMM)  Range Mask of SMM memory range. If
+  SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If
   IA32_MTRRCAP[SMRR] = 1.
 
   @param  ECX  MSR_IA32_SMRR_PHYSMASK (0x01F3)
@@ -4417,13 +4408,13 @@ typedef union {
   ///
   struct {
 ///
-/// [Bit 0] 

[edk2] [Patch v3 00/14] Update MSR definitions

[Eric Dong]

Current MSR definition are follow the SDM 2016-09 version. The latest SDM is 
2018-05. This patch serial update the MSR related definition to follow the 
latest SDM 2018-05 version. MSR related defintion are saved at 
UefiCpuPkg\Include\Register\.

V3 changes includes:
1. Only change Patch 8 and 14 which changed MSR data structures.
2. Keep ReservedX not change if bit info not changed for this field.

V2 changes include:
1. Only change Patch 8 and 14 which changed MSR data structures.
2. Use X in ReservedX fields from totally new value if MSR structure definition 
changed.
   For example, if in current structure, the max reserved variable is 
Reserved2, in new
   definition, reserved variable is begin with Reserved3.

V1 Changes include:
The changes for this serial includes:
1. Add new MSR definition and file.
2. Remove old MSR definition which not defined in new SDM.
3. Change MSR name to follow new SDM, keep old one for compatibility.
4. Change MSR data structure definition to follow new SDM.
5. Update comments to follow the new SDM, mainly related to chapter info.

Below changes are incompatible changes:
2. Remove old MSR definition which not defined in new SDM.
For this one, i search edk2 codebase, not found any code uses it. so no impact 
for edk2 codebase. Detail changes see patch 9 ~ 11.

4. Change MSR data structure definition to follow new SDM.
For this one, new data structure just change the original reserved bits to 
valid bits, should have no impact for the current code. Detail see patch 8 and 
patch 14

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 


Eric Dong (14):
  UefiCpuPkg/Include/Register/Msr: Update reference spec info.
  UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file
for goldmont plus microarchitecture.
  UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR.
  UefiCpuPkg/Include/Register/Msr/*.h: Add new MSR.
  UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR.
  UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs.
  UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR.
  UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure
definition.
  UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR.
  UefiCpuPkg/Include/Register/Msr/P6Msr.h: Remove old MSR.
  UefiCpuPkg/Include/Register/Msr/CoreMsr.h: Remove old MSR.
  UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and
keep old one.
  UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: Add new MSR name and
keep old one.
  UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure
definition.

 UefiCpuPkg/Include/Register/ArchitecturalMsr.h|  130 +-
 UefiCpuPkg/Include/Register/Msr.h |7 +-
 UefiCpuPkg/Include/Register/Msr/AtomMsr.h |   28 +-
 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h|   62 +-
 UefiCpuPkg/Include/Register/Msr/Core2Msr.h|  102 +-
 UefiCpuPkg/Include/Register/Msr/CoreMsr.h |   74 +-
 UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h |   88 +-
 UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h |  272 
 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h |   62 +-
 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h  |   34 +-
 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h|8 +-
 UefiCpuPkg/Include/Register/Msr/NehalemMsr.h  |   52 +-
 UefiCpuPkg/Include/Register/Msr/P6Msr.h   |   60 +-
 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h |  202 +--
 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h |   22 +-
 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h  |   12 +-
 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h  |   49 +-
 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h   |  100 +-
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h  | 1602 -
 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h |8 +-
 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h|   84 +-
 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h   |6 +-
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h  |  332 -
 23 files changed, 2816 insertions(+), 580 deletions(-)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h

-- 
2.15.0.windows.1

___
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel

[edk2] [Patch v3 02/14] UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file for goldmont plus microarchitecture.

[Eric Dong]

Changes includes:
  1. Add new MSR file which used for goldmont plus microarchitecture.

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/Msr.h |   7 +-
 UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h | 272 ++
 2 files changed, 276 insertions(+), 3 deletions(-)
 create mode 100644 UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h

diff --git a/UefiCpuPkg/Include/Register/Msr.h 
b/UefiCpuPkg/Include/Register/Msr.h
index 0ac8d5bdfd..abe0e136de 100644
--- a/UefiCpuPkg/Include/Register/Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.
+  Copyright (c) 2016 ~ 2018, Intel Corporation. All rights reserved.
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD 
License
   which accompanies this distribution.  The full text of the license may be 
found at
@@ -16,8 +16,8 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Specification Reference:
-  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
-  September 2016, Chapter 35 Model-Specific-Registers (MSR), Chapter 35.
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
 
 **/
 
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h 
b/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
new file mode 100644
index 00..d050464b7f
--- /dev/null
+++ b/UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
@@ -0,0 +1,272 @@
+/** @file
+  MSR Defintions for Intel Atom processors based on the Goldmont Plus 
microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2018, Intel Corporation. All rights reserved.
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __GOLDMONT_PLUS_MSR_H__
+#define __GOLDMONT_PLUS_MSR_H__
+
+#include 
+
+/**
+  Is Intel Atom processors based on the Goldmont plus microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (\
+DisplayModel == 0x7A\
+)   \
+   )
+
+/**
+  Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based
+  Sampling (PEBS).".
+
+  @param  ECX  MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x03F1)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
+
+  Example usage
+  @code
+  MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+**/
+#define MSR_GOLDMONT_PLUS_PEBS_ENABLE0x03F1
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0] Enable PEBS trigger and recording for the programmed event
+/// (precise or otherwise) on IA32_PMC0.
+///
+UINT32  Fix_Me_1:1;
+///
+/// [Bit 1] Enable PEBS trigger and recording for the programmed event
+/// (precise or otherwise) on IA32_PMC1.
+///
+UINT32  Fix_Me_2:1;
+///
+/// [Bit 2] Enable PEBS trigger and recording for the programmed event
+/// (precise or otherwise) on IA32_PMC2.
+///
+UINT32  Fix_Me_3:1;
+///
+/// [Bit 3] Enable PEBS trigger and recording for the programmed event
+/// (precise or otherwise) on IA32_PMC3.
+///
+UINT32  

[edk2] [Patch v3 06/14] UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs.

[Eric Dong]

Changes includes:
  1. Add new MSR definitions.
  2. Add support platform info.

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1548 +-
 1 file changed, 1547 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h 
b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 866fe30f05..90cde86ccb 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -39,7 +39,11 @@
   (DisplayFamily == 0x06 && \
(\
 DisplayModel == 0x4E || \
-DisplayModel == 0x5E\
+DisplayModel == 0x5E || \
+DisplayModel == 0x55 || \
+DisplayModel == 0x8E || \
+DisplayModel == 0x9E || \
+DisplayModel == 0x66\
 )   \
)
 
@@ -124,6 +128,74 @@ typedef union {
 #define MSR_SKYLAKE_LASTBRANCH_TOS   0x01C9
 
 
+/**
+  Core. Power Control Register See http://biosbits.org.
+
+  @param  ECX  MSR_SKYLAKE_POWER_CTL (0x01FC)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
+
+  Example usage
+  @code
+  MSR_SKYLAKE_POWER_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);
+  AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_POWER_CTL 0x01FC
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:1;
+///
+/// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU
+/// to switch to the Minimum Enhanced Intel SpeedStep Technology operating
+/// point when all execution cores enter MWAIT (C1).
+///
+UINT32  C1EEnable:1;
+UINT32  Reserved2:17;
+///
+/// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit
+/// disables the Race to Halt optimization and avoids this optimization
+/// limitation to execute below the most efficient frequency ratio.
+/// Default value is 0 for processors that support Race to Halt
+/// optimization. Default value is 1 for processors that do not support
+/// Race to Halt optimization.
+///
+UINT32  Fix_Me_1:1;
+///
+/// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit
+/// disables the P-States energy efficiency optimization. Default value is
+/// 0. Disable/enable the energy efficiency optimization in P-State legacy
+/// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the
+/// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP
+/// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS
+/// desired or OS maximize to the OS minimize performance setting.
+///
+UINT32  DisableEnergyEfficiencyOptimization:1;
+UINT32  Reserved3:11;
+UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_POWER_CTL_REGISTER;
+
+
 /**
   Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of
   an 128-bit external entropy value for key derivation of an enclave.
@@ -2254,4 +2326,1478 @@ typedef union {
   UINT64  Uint64;
 } MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;
 
+
+/**
+  Package. NPK Address Used by AET Messages (R/W).
+
+  @param  ECX  MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x0080)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type 
MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type 
MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
+
+  Example usage
+  @code
+  MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);
+  AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE   0x0080
+
+/**
+  MSR information returned for MSR index
+  #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock
+/// bit has to be set in order for the AET packets to be directed to NPK
+/// MMIO.
+///
+UINT32  Fix_Me_1:1;
+UINT32  Reserved:17;
+///
+/// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
+///
+UINT32  ACPIBAR_BASE_ADDRESS:14;
+///
+/// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address 

[edk2] [Patch v3 04/14] UefiCpuPkg/Include/Register/Msr/*.h: Add new MSR.

[Eric Dong]

Changes includes:
  1. Add new MSR: MSR_*_MSRUNCORE_RATIO_LIMIT

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 54 +
 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h  | 56 +-
 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 56 +-
 3 files changed, 164 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h 
b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
index 4e50f72008..a7a1967420 100644
--- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
@@ -285,6 +285,60 @@ typedef union {
 } MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
 
 
+/**
+  Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+  fields represent the widest possible range of uncore frequencies. Writing to
+  these fields allows software to control the minimum and the maximum
+  frequency that hardware will select.
+
+  @param  ECX  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x0620)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type 
MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type 
MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+  Example usage
+  @code
+  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+**/
+#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT  0x0620
+
+/**
+  MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+/// LLC/Ring.
+///
+UINT32  MAX_RATIO:7;
+UINT32  Reserved2:1;
+///
+/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+/// possible ratio of the LLC/Ring.
+///
+UINT32  MIN_RATIO:7;
+UINT32  Reserved3:17;
+UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
 /**
   Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
   Domains.".
diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h 
b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
index a75bdb2e13..985183b320 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
@@ -846,7 +846,61 @@ typedef union {
 
 
 /**
-  Package. Reserved (R/O)  Reads return 0.
+  Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+  fields represent the widest possible range of uncore frequencies. Writing to
+  these fields allows software to control the minimum and the maximum
+  frequency that hardware will select.
+
+  @param  ECX  MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x0620)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type 
MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type 
MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+  Example usage
+  @code
+  MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+**/
+#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT  0x0620
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+/// LLC/Ring.
+///
+UINT32  MAX_RATIO:7;
+UINT32  Reserved1:1;
+///
+/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+/// possible ratio of the LLC/Ring.
+///
+UINT32  MIN_RATIO:7;
+UINT32  Reserved2:17;
+UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+/**
+  Package. Reserved (R/O) Reads return 0.
 
   @param  ECX  MSR_HASWELL_E_PP0_ENERGY_STATUS (0x0639)
   @param  EAX  Lower 32-bits of MSR value.
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h 
b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
index cf013ea887..6dc4ee999e 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
@@ -754,7 +754,61 @@ typedef union {
 
 
 /**
-  

[edk2] [Patch v3 05/14] UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR.

[Eric Dong]

Changes includes:
  1. Add new MSR definition:
 1. MSR_XEON_PHI_PPIN_CTL
 2. MSR_XEON_PHI_PPIN
 3. MSR_XEON_PHI_MISC_FEATURE_ENABLES
 4. MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
  2. Add DisplayModule == 0x85 supports.

Cc: Michael D Kinney 
Cc: Ruiyu Ni 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong 
---
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 249 ++-
 1 file changed, 246 insertions(+), 3 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h 
b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index d7aa3ae850..da74c2402c 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -38,7 +38,8 @@
 #define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
   (DisplayFamily == 0x06 && \
(\
-DisplayModel == 0x57\
+DisplayModel == 0x57 || \
+DisplayModel == 0x85\
 )   \
)
 
@@ -85,9 +86,89 @@ typedef union {
   UINT64  Uint64;
 } MSR_XEON_PHI_SMI_COUNT_REGISTER;
 
+/**
+  Package. Protected Processor Inventory Number Enable Control (R/W).
+
+  @param  ECX  MSR_XEON_PHI_PPIN_CTL (0x004E)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_PHI_PPIN_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);
+  AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_PHI_PPIN_CTL0x004E
 
 /**
-  Package. See http://biosbits.org.
+  MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+///
+/// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to
+/// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if
+/// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an
+/// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a
+/// privileged inventory initialization agent to access MSR_PPIN. After
+/// reading MSR_PPIN, the privileged inventory initialization agent should
+/// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
+/// prevent unauthorized modification to MSR_PPIN_CTL.
+///
+UINT32  LockOut:1;
+///
+/// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
+/// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]
+/// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.
+/// Default is 0.
+///
+UINT32  Enable_PPIN:1;
+UINT32  Reserved1:30;
+UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_PPIN_CTL_REGISTER;
+
+
+/**
+  Package. Protected Processor Inventory Number (R/O). Protected Processor
+  Inventory Number (R/O) A unique value within a given CPUID
+  family/model/stepping signature that a privileged inventory initialization
+  agent can access to identify each physical processor, when access to
+  MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
+  MSR_PPIN_CTL[bits 1:0] = '10b'.
+
+  @param  ECX  MSR_XEON_PHI_PPIN (0x004F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  Example usage
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);
+  @endcode
+**/
+#define MSR_XEON_PHI_PPIN0x004F
+
+/**
+  Package. Platform Information Contains power management and other model
+  specific features enumeration. See http://biosbits.org.
 
   @param  ECX  MSR_XEON_PHI_PLATFORM_INFO (0x00CE)
   @param  EAX  Lower 32-bits of MSR value.
@@ -317,6 +398,56 @@ typedef union {
 } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;
 
 
+/**
+  Thread. MISC_FEATURE_ENABLES.
+
+  @param  ECX  MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x0140)
+  @param  EAX  Lower 32-bits of MSR value.
+   Described by the type 
MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+   Described by the type 
MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
+
+  Example usage
+  @code
+  MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);
+  AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_PHI_MISC_FEATURE_ENABLES0x0140
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+UINT32  Reserved1:1;
+///
+/// [Bit 1] User Mode MONITOR and 

Re: [edk2] [PATCH 2/3] MdeModulePkg/PciHostBridge: Fix a bug that prevents PMEM access

[Ni, Ruiyu]

On 9/21/2018 7:06 PM, Laszlo Ersek wrote:

On 09/21/18 09:25, Ruiyu Ni wrote:

The interesting thing about this patch is that, if any one of the first
three branches is taken, then the final checks will automatically pass.
That's because, on the first three branches, we select the base & the
limit *because* the access falls between them. Therefore, in the end,
when we check whether the access falls between base and end, they
miraculously happen to do so. :)


The code was written like this to maximally share the final check code:)



Reviewed-by: Laszlo Ersek 

Thanks
Laszlo
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--
Thanks,
Ray
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Re: [edk2] [PATCH] MdePkg: Add a inf path in MdePkg.dsc

[Gao, Liming]

Reviewed-by: Liming Gao 

>-Original Message-
>From: Zhang, Shenglei
>Sent: Friday, September 14, 2018 4:55 PM
>To: edk2-devel@lists.01.org
>Cc: Kinney, Michael D ; Gao, Liming
>
>Subject: [PATCH] MdePkg: Add a inf path in MdePkg.dsc
>
>DxeRuntimeDebugLibSerialPort.inf is missing in MdePkg.dsc.
>So add the path into it.
>https://bugzilla.tianocore.org/show_bug.cgi?id=1177
>
>Cc: Michael D Kinney 
>Cc: Liming Gao 
>Contributed-under: TianoCore Contribution Agreement 1.1
>Signed-off-by: shenglei 
>---
> MdePkg/MdePkg.dsc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
>index c7b93d4c8c..092a756c1f 100644
>--- a/MdePkg/MdePkg.dsc
>+++ b/MdePkg/MdePkg.dsc
>@@ -98,8 +98,8 @@
>   MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf
>   MdePkg/Library/DxeIoLibCpuIo2/DxeIoLibCpuIo2.inf
>   MdePkg/Library/DxeHstiLib/DxeHstiLib.inf
>-
>   MdePkg/Library/DxeRuntimePciExpressLib/DxeRuntimePciExpressLib.inf
>+
>MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialP
>ort.inf
>
>   MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
>
>MdePkg/Library/PeiDxePostCodeLibReportStatusCode/PeiDxePostCodeLibRe
>portStatusCode.inf
>--
>2.18.0.windows.1

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Re: [edk2] [PATCH v2] MdePkg UefiPciLibPciRootBridgeIo: Remove redundant dependency

[Gao, Liming]

Reviewed-by: Liming Gao 

>-Original Message-
>From: Zhang, Shenglei
>Sent: Tuesday, September 25, 2018 9:31 AM
>To: edk2-devel@lists.01.org
>Cc: Kinney, Michael D ; Gao, Liming
>
>Subject: [PATCH v2] MdePkg UefiPciLibPciRootBridgeIo: Remove redundant
>dependency
>
>PiDxe.h is not used PciSegmentLib.h.
>So  is deleted.
>https://bugzilla.tianocore.org/show_bug.cgi?id=1184
>
>v2:Update the bugzilla link.
>
>Cc: Michael D Kinney 
>Cc: Liming Gao 
>Contributed-under: TianoCore Contribution Agreement 1.1
>Signed-off-by: shenglei 
>---
> MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c | 2 --
> 1 file changed, 2 deletions(-)
>
>diff --git a/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
>b/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
>index 575d9c1f91..f89e3e2551 100644
>--- a/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
>+++ b/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
>@@ -13,8 +13,6 @@
>
> **/
>
>-#include 
>-
> #include 
>
> #include 
>--
>2.18.0.windows.1

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Re: [edk2] [PATCH v2 0/5] Support windowsize to benefit tftp/pxe download performance.

[Fu, Siyuan]

Reviewed-by: Fu Siyuan 

> -Original Message-
> From: Wu, Jiaxin
> Sent: Tuesday, September 25, 2018 9:12 AM
> To: edk2-devel@lists.01.org
> Cc: Ye, Ting ; Fu, Siyuan ; Carsey,
> Jaben ; Shao, Ming ; Laszlo
> Ersek ; Wu, Jiaxin 
> Subject: [PATCH v2 0/5] Support windowsize to benefit tftp/pxe download
> performance.
> 
> *v2: The first three patches(1/2/3) are the same with version 1, just
> update the last two
> patches (4/5):
> I)  windowsize.>
> This patch has been discarded since we rename and redefine the PCD in
> NetworkPkg instead
> of MdeModulePkg. The replacement is:
> [PATCH v2 4/5] NetworkPkg: Define one PCD for PXE to specify MTFTP
> windowsize.
> II) 
> Since the new PCD (PcdPxeTftpWindowSize) was renamed/defined in NetworkPkg
> instead of
> MdeModulePkg, we udpate the consuming PXE driver. The new version patch is:
> [PATCH v2 5/5] NetworkPkg/UefiPxeBcDxe: Use the specified MTFTP windowsize.
> 
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=886
> 
> The series patches are to support the TFTP windowsize option described in
> RFC 7440.
> TFTP shell command and UEFI PXE driver will use the feature to benefit the
> download
> performance.
> 
> Cc: Ye Ting 
> Cc: Fu Siyuan 
> Cc: Carsey Jaben 
> Cc: Shao Ming 
> Cc: Laszlo Ersek 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Wu Jiaxin 
> 
> Jiaxin Wu (5):
>   MdeModulePke/Mtftp4Dxe: Support windowsize in read request operation.
>   NetworkPkg/Mtftp6Dxe: Support windowsize in read request operation.
>   ShellPkg/TftpDynamicCommand: Add one option for tftp command to
> specify windowsize.
>   NetworkPkg: Define one PCD for PXE to specify MTFTP windowsize.
>   NetworkPkg/UefiPxeBcDxe: Use the specified MTFTP windowsize.
> 
>  .../Universal/Network/Mtftp4Dxe/Mtftp4Impl.c  |   5 +
>  .../Universal/Network/Mtftp4Dxe/Mtftp4Impl.h  |  10 ++
>  .../Network/Mtftp4Dxe/Mtftp4Option.c  |  25 +++-
>  .../Network/Mtftp4Dxe/Mtftp4Option.h  |   8 +-
>  .../Universal/Network/Mtftp4Dxe/Mtftp4Rrq.c   |  55 +--
>  .../Network/Mtftp4Dxe/Mtftp4Support.c |   8 +-
>  .../Network/Mtftp4Dxe/Mtftp4Support.h |  13 --
>  .../Universal/Network/Mtftp4Dxe/Mtftp4Wrq.c   |   2 +-
>  NetworkPkg/Mtftp6Dxe/Mtftp6Impl.h |  13 +-
>  NetworkPkg/Mtftp6Dxe/Mtftp6Option.c   |  22 ++-
>  NetworkPkg/Mtftp6Dxe/Mtftp6Option.h   |  14 +-
>  NetworkPkg/Mtftp6Dxe/Mtftp6Rrq.c  |  53 +--
>  NetworkPkg/Mtftp6Dxe/Mtftp6Support.c  |  10 ++
>  NetworkPkg/Mtftp6Dxe/Mtftp6Wrq.c  |   2 +-
>  NetworkPkg/NetworkPkg.dec |   6 +
>  NetworkPkg/NetworkPkg.uni |   6 +
>  NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c   |  10 +-
>  NetworkPkg/UefiPxeBcDxe/PxeBcMtftp.c  | 137 +-
>  NetworkPkg/UefiPxeBcDxe/PxeBcMtftp.h  |   6 +-
>  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf  |   3 +
>  .../DynamicCommand/TftpDynamicCommand/Tftp.c  |  65 +++--
>  .../TftpDynamicCommand/Tftp.uni   |   6 +-
>  22 files changed, 371 insertions(+), 108 deletions(-)
> 
> --
> 2.17.1.windows.2

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[edk2] [Patch] BaseTools: Fix the wrong reference _GetSkuIds() in AutoGen code

[Liming Gao]

DscBuildData has been updated to define SkuIds instead of _GetSkuIds().
The consumer code should refer to SkuIds.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao 
Cc: Yonghong Zhu 
Cc: Jaben Carsey 
---
 BaseTools/Source/Python/AutoGen/AutoGen.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/BaseTools/Source/Python/AutoGen/AutoGen.py 
b/BaseTools/Source/Python/AutoGen/AutoGen.py
index 5271b44..38f1260 100644
--- a/BaseTools/Source/Python/AutoGen/AutoGen.py
+++ b/BaseTools/Source/Python/AutoGen/AutoGen.py
@@ -1153,7 +1153,7 @@ class PlatformAutoGen(AutoGen):
 VpdRegionBase = FdRegion.Offset
 break
 
-VariableInfo = VariableMgr(self.DscBuildDataObj._GetDefaultStores(), 
self.DscBuildDataObj._GetSkuIds())
+VariableInfo = VariableMgr(self.DscBuildDataObj._GetDefaultStores(), 
self.DscBuildDataObj.SkuIds)
 VariableInfo.SetVpdRegionMaxSize(VpdRegionSize)
 VariableInfo.SetVpdRegionOffset(VpdRegionBase)
 Index = 0
-- 
2.10.0.windows.1

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[edk2] [PATCH v2] MdePkg UefiPciLibPciRootBridgeIo: Remove redundant dependency

[shenglei]

PiDxe.h is not used PciSegmentLib.h.
So  is deleted.
https://bugzilla.tianocore.org/show_bug.cgi?id=1184

v2:Update the bugzilla link.

Cc: Michael D Kinney 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei 
---
 MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c 
b/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
index 575d9c1f91..f89e3e2551 100644
--- a/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
+++ b/MdePkg/Library/UefiPciLibPciRootBridgeIo/PciLib.c
@@ -13,8 +13,6 @@
 
 **/
 
-#include 
-
 #include 
 
 #include 
-- 
2.18.0.windows.1

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Re: [edk2] [PATCH 1/3] IntelFrameworkModulePkg: Remove the missing PalLib in DSC file.

[Chen, Chen A]

Ok

-Original Message-
From: Gao, Liming 
Sent: Tuesday, September 25, 2018 9:16 AM
To: Chen, Chen A ; edk2-devel@lists.01.org
Cc: Kinney, Michael D 
Subject: RE: [PATCH 1/3] IntelFrameworkModulePkg: Remove the missing PalLib in 
DSC file.

Chen:
  Please update patch title and commit message to follow Star comments. 
 
 Reviewed-by: Liming Gao 

Thanks
Liming
>-Original Message-
>From: Chen, Chen A
>Sent: Friday, September 21, 2018 9:00 AM
>To: edk2-devel@lists.01.org
>Cc: Chen, Chen A ; Gao, Liming 
>; Kinney, Michael D 
>Subject: [PATCH 1/3] IntelFrameworkModulePkg: Remove the missing PalLib 
>in DSC file.
>
>The PalLib will remove in MdePkg, so remove this lib from DSC file.
>
>Cc: Liming Gao 
>Cc: Michael D Kinney 
>Contributed-under: TianoCore Contribution Agreement 1.1
>Signed-off-by: Chen A Chen 
>---
> IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc | 1 -
> 1 file changed, 1 deletion(-)
>
>diff --git a/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc
>b/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc
>index 84e1d890b5..894c5340a0 100644
>--- a/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc
>+++ b/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc
>@@ -75,7 +75,6 @@
>
>DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTable
>Lib.inf
>   UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
>   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
>-  PalLib|MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
>
> [LibraryClasses.common.PEIM]
>   HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
>--
>2.16.2.windows.1

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Re: [edk2] [PATCH 1/3] IntelFrameworkModulePkg: Remove the missing PalLib in DSC file.

[Gao, Liming]

Chen:
  Please update patch title and commit message to follow Star comments. 
 
 Reviewed-by: Liming Gao 

Thanks
Liming
>-Original Message-
>From: Chen, Chen A
>Sent: Friday, September 21, 2018 9:00 AM
>To: edk2-devel@lists.01.org
>Cc: Chen, Chen A ; Gao, Liming
>; Kinney, Michael D 
>Subject: [PATCH 1/3] IntelFrameworkModulePkg: Remove the missing PalLib
>in DSC file.
>
>The PalLib will remove in MdePkg, so remove this lib from DSC file.
>
>Cc: Liming Gao 
>Cc: Michael D Kinney 
>Contributed-under: TianoCore Contribution Agreement 1.1
>Signed-off-by: Chen A Chen 
>---
> IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc | 1 -
> 1 file changed, 1 deletion(-)
>
>diff --git a/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc
>b/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc
>index 84e1d890b5..894c5340a0 100644
>--- a/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc
>+++ b/IntelFrameworkModulePkg/IntelFrameworkModulePkg.dsc
>@@ -75,7 +75,6 @@
>
>DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTable
>Lib.inf
>   UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
>   PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
>-  PalLib|MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
>
> [LibraryClasses.common.PEIM]
>   HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
>--
>2.16.2.windows.1

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[edk2] [PATCH v2 5/5] NetworkPkg/UefiPxeBcDxe: Use the specified MTFTP windowsize.

[Jiaxin Wu]

*v2: Since the new PCD (PcdPxeTftpWindowSize) was renamed/defined in
NetworkPkg instead of MdeModulePkg, this new version is to update the
consuming PXE driver.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=886

This patch is to use the specified MTFTP windowsize to benefit the PXE
download performance.

Cc: Ye Ting 
Cc: Fu Siyuan 
Cc: Shao Ming 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wu Jiaxin 
---
 NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c  |  10 +-
 NetworkPkg/UefiPxeBcDxe/PxeBcMtftp.c | 137 +--
 NetworkPkg/UefiPxeBcDxe/PxeBcMtftp.h |   6 +-
 NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf |   3 +
 4 files changed, 121 insertions(+), 35 deletions(-)

diff --git a/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c 
b/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c
index 13396903f5..468b38d887 100644
--- a/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c
+++ b/NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c
@@ -847,11 +847,11 @@ EfiPxeBcMtftp (
   EFI_MTFTP4_CONFIG_DATA  Mtftp4Config;
   EFI_MTFTP6_CONFIG_DATA  Mtftp6Config;
   VOID*Config;
   EFI_STATUS  Status;
   EFI_PXE_BASE_CODE_IP_FILTER IpFilter;
-
+  UINTN   WindowSize;
 
   if ((This == NULL) ||
   (Filename == NULL) ||
   (BufferSize == NULL) ||
   (ServerIp == NULL) ||
@@ -871,10 +871,15 @@ EfiPxeBcMtftp (
   Config= NULL;
   Status= EFI_DEVICE_ERROR;
   Private   = PXEBC_PRIVATE_DATA_FROM_PXEBC (This);
   Mode  = Private->PxeBc.Mode;
 
+  //
+  // Get PcdPxeTftpWindowSize.
+  //
+  WindowSize = (UINTN) PcdGet64 (PcdPxeTftpWindowSize);
+
   if (Mode->UsingIpv6) {
 if (!NetIp6IsValidUnicast (>v6)) {
   return EFI_INVALID_PARAMETER;
 }
   } else {
@@ -928,10 +933,11 @@ EfiPxeBcMtftp (
 Status = PxeBcTftpGetFileSize (
Private,
Config,
Filename,
BlockSize,
+   (WindowSize > 1) ?  : NULL,
BufferSize
);
 
 break;
 
@@ -942,10 +948,11 @@ EfiPxeBcMtftp (
 Status = PxeBcTftpReadFile (
Private,
Config,
Filename,
BlockSize,
+   (WindowSize > 1) ?  : NULL,
BufferPtr,
BufferSize,
DontUseBuffer
);
 
@@ -974,10 +981,11 @@ EfiPxeBcMtftp (
 Status = PxeBcTftpReadDirectory (
Private,
Config,
Filename,
BlockSize,
+   (WindowSize > 1) ?  : NULL,
BufferPtr,
BufferSize,
DontUseBuffer
);
 
diff --git a/NetworkPkg/UefiPxeBcDxe/PxeBcMtftp.c 
b/NetworkPkg/UefiPxeBcDxe/PxeBcMtftp.c
index 270190d42e..9725fb40dd 100644
--- a/NetworkPkg/UefiPxeBcDxe/PxeBcMtftp.c
+++ b/NetworkPkg/UefiPxeBcDxe/PxeBcMtftp.c
@@ -17,11 +17,12 @@
 
 CHAR8 *mMtftpOptions[PXE_MTFTP_OPTION_MAXIMUM_INDEX] = {
   "blksize",
   "timeout",
   "tsize",
-  "multicast"
+  "multicast",
+  "windowsize"
 };
 
 
 /**
   This is a callback function when packets are received or transmitted in 
Mtftp driver.
@@ -120,28 +121,31 @@ EFI_STATUS
 PxeBcMtftp6GetFileSize (
   IN PXEBC_PRIVATE_DATA   *Private,
   IN EFI_MTFTP6_CONFIG_DATA   *Config,
   IN UINT8*Filename,
   IN UINTN*BlockSize,
+  IN UINTN*WindowSize,
   IN OUT UINT64   *BufferSize
   )
 {
   EFI_MTFTP6_PROTOCOL *Mtftp6;
-  EFI_MTFTP6_OPTION   ReqOpt[2];
+  EFI_MTFTP6_OPTION   ReqOpt[3];
   EFI_MTFTP6_PACKET   *Packet;
   EFI_MTFTP6_OPTION   *Option;
   UINT32  PktLen;
-  UINT8   OptBuf[128];
+  UINT8   OptBuf[PXE_MTFTP_OPTBUF_MAXNUM_INDEX];
+  UINTN   OptBufSize;
   UINT32  OptCnt;
   EFI_STATUS  Status;
 
   *BufferSize   = 0;
   Status= EFI_DEVICE_ERROR;
   Mtftp6= Private->Mtftp6;
   Packet= NULL;
   Option= NULL;
   PktLen= 0;
+  OptBufSize= PXE_MTFTP_OPTBUF_MAXNUM_INDEX;
   OptCnt= 1;
   Config->InitialServerPort = PXEBC_BS_DOWNLOAD_PORT;
 
   Status = Mtftp6->Configure (Mtftp6, Config);
   if (EFI_ERROR (Status)) {
@@ -150,17 +154,26 @@ PxeBcMtftp6GetFileSize (
 
   //
   // Build the required options for get info.
   //
   ReqOpt[0].OptionStr = (UINT8 *) mMtftpOptions[PXE_MTFTP_OPTION_TSIZE_INDEX];
-  PxeBcUintnToAscDec (0, OptBuf, PXE_MTFTP_OPTBUF_MAXNUM_INDEX);
+  PxeBcUintnToAscDec (0, OptBuf, OptBufSize);
   ReqOpt[0].ValueStr  = OptBuf;
 
   if (BlockSize != NULL) {
-ReqOpt[1].OptionStr 

[edk2] [PATCH v2 0/5] Support windowsize to benefit tftp/pxe download performance.

[Jiaxin Wu]

*v2: The first three patches(1/2/3) are the same with version 1, just update 
the last two
patches (4/5):
I) 
This patch has been discarded since we rename and redefine the PCD in 
NetworkPkg instead 
of MdeModulePkg. The replacement is: 
[PATCH v2 4/5] NetworkPkg: Define one PCD for PXE to specify MTFTP windowsize.
II) 
Since the new PCD (PcdPxeTftpWindowSize) was renamed/defined in NetworkPkg 
instead of 
MdeModulePkg, we udpate the consuming PXE driver. The new version patch is:
[PATCH v2 5/5] NetworkPkg/UefiPxeBcDxe: Use the specified MTFTP windowsize.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=886

The series patches are to support the TFTP windowsize option described in RFC 
7440.
TFTP shell command and UEFI PXE driver will use the feature to benefit the 
download 
performance.

Cc: Ye Ting 
Cc: Fu Siyuan 
Cc: Carsey Jaben 
Cc: Shao Ming 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wu Jiaxin 

Jiaxin Wu (5):
  MdeModulePke/Mtftp4Dxe: Support windowsize in read request operation.
  NetworkPkg/Mtftp6Dxe: Support windowsize in read request operation.
  ShellPkg/TftpDynamicCommand: Add one option for tftp command to
specify windowsize.
  NetworkPkg: Define one PCD for PXE to specify MTFTP windowsize.
  NetworkPkg/UefiPxeBcDxe: Use the specified MTFTP windowsize.

 .../Universal/Network/Mtftp4Dxe/Mtftp4Impl.c  |   5 +
 .../Universal/Network/Mtftp4Dxe/Mtftp4Impl.h  |  10 ++
 .../Network/Mtftp4Dxe/Mtftp4Option.c  |  25 +++-
 .../Network/Mtftp4Dxe/Mtftp4Option.h  |   8 +-
 .../Universal/Network/Mtftp4Dxe/Mtftp4Rrq.c   |  55 +--
 .../Network/Mtftp4Dxe/Mtftp4Support.c |   8 +-
 .../Network/Mtftp4Dxe/Mtftp4Support.h |  13 --
 .../Universal/Network/Mtftp4Dxe/Mtftp4Wrq.c   |   2 +-
 NetworkPkg/Mtftp6Dxe/Mtftp6Impl.h |  13 +-
 NetworkPkg/Mtftp6Dxe/Mtftp6Option.c   |  22 ++-
 NetworkPkg/Mtftp6Dxe/Mtftp6Option.h   |  14 +-
 NetworkPkg/Mtftp6Dxe/Mtftp6Rrq.c  |  53 +--
 NetworkPkg/Mtftp6Dxe/Mtftp6Support.c  |  10 ++
 NetworkPkg/Mtftp6Dxe/Mtftp6Wrq.c  |   2 +-
 NetworkPkg/NetworkPkg.dec |   6 +
 NetworkPkg/NetworkPkg.uni |   6 +
 NetworkPkg/UefiPxeBcDxe/PxeBcImpl.c   |  10 +-
 NetworkPkg/UefiPxeBcDxe/PxeBcMtftp.c  | 137 +-
 NetworkPkg/UefiPxeBcDxe/PxeBcMtftp.h  |   6 +-
 NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf  |   3 +
 .../DynamicCommand/TftpDynamicCommand/Tftp.c  |  65 +++--
 .../TftpDynamicCommand/Tftp.uni   |   6 +-
 22 files changed, 371 insertions(+), 108 deletions(-)

-- 
2.17.1.windows.2

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[edk2] [PATCH v2 4/5] NetworkPkg: Define one PCD for PXE to specify MTFTP windowsize.

[Jiaxin Wu]

*v2: Rename and redefine the PCD in NetworkPkg instead of MdeModulePkg.

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=886

This patch is to define one new PCD for PXE driver to specify MTFTP windowsize 
so as
to improve the PXE download performance. The default value is set to 4.

Cc: Ye Ting 
Cc: Fu Siyuan 
Cc: Shao Ming 
Cc: Laszlo Ersek 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wu Jiaxin 
---
 NetworkPkg/NetworkPkg.dec | 6 ++
 NetworkPkg/NetworkPkg.uni | 6 ++
 2 files changed, 12 insertions(+)

diff --git a/NetworkPkg/NetworkPkg.dec b/NetworkPkg/NetworkPkg.dec
index aae36226d5..aa721d8315 100644
--- a/NetworkPkg/NetworkPkg.dec
+++ b/NetworkPkg/NetworkPkg.dec
@@ -90,10 +90,16 @@
   # TRUE  - HTTP connections are allowed. Both the "https://; and "http://; 
URI schemes are permitted.
   # FALSE - HTTP connections are denied. Only the "https://; URI scheme is 
permitted.
   # @Prompt Indicates whether HTTP connections are permitted or not.
   gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|FALSE|BOOLEAN|0x0008
 
+  ## This setting is to specify the MTFTP windowsize used by UEFI PXE driver. 
+  # A value of 0 indicates the default value of windowsize(1). 
+  # A non-zero value will be used as windowsize.
+  # @Prompt PXE TFTP windowsize.
+  gEfiNetworkPkgTokenSpaceGuid.PcdPxeTftpWindowSize|0x4|UINT64|0x1008  
+
 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
   ## IPv6 DHCP Unique Identifier (DUID) Type configuration (From RFCs 3315 and 
6355).
   # 01 = DUID Based on Link-layer Address Plus Time [DUID-LLT]
   # 04 = UUID-Based DHCPv6 Unique Identifier (DUID-UUID)
   # 02 = DUID Assigned by Vendor Based on Enterprise Number [DUID-EN] (not 
supported)
diff --git a/NetworkPkg/NetworkPkg.uni b/NetworkPkg/NetworkPkg.uni
index 5604b1bf32..07585680e3 100644
--- a/NetworkPkg/NetworkPkg.uni
+++ b/NetworkPkg/NetworkPkg.uni
@@ -53,10 +53,16 @@
 
 #string STR_gEfiNetworkPkgTokenSpaceGuid_PcdAllowHttpConnections_HELP  
#language en-US "Indicates whether HTTP connections are permitted or not.\n"

"TRUE  - HTTP connections are allowed.\n"

"FALSE - HTTP connections are denied."
 
+#string STR_gEfiNetworkPkgTokenSpaceGuid_PcdPxeTftpWindowSize_PROMPT  
#language en-US "This setting is to specify the MTFTP windowsize used by UEFI 
PXE driver."
+
+#string STR_gEfiNetworkPkgTokenSpaceGuid_PcdPxeTftpWindowSize_HELP  #language 
en-US "Specify MTFTP windowsize used by UEFI PXE driver.\n"
+   
 "A value of 0 indicates the default value of windowsize(1).\n"
+   
 "A non-zero value will be used as windowsize." 
  
+
 #string STR_gEfiNetworkPkgTokenSpaceGuid_PcdIpsecCertificateEnabled_PROMPT  
#language en-US "Enable IPsec IKEv2 Certificate Authentication."
 
 #string STR_gEfiNetworkPkgTokenSpaceGuid_PcdIpsecCertificateEnabled_HELP  
#language en-US "Indicates if the IPsec IKEv2 Certificate Authentication 
feature is enabled or not.\n"

   "TRUE  - Certificate Authentication feature is enabled.\n"

   "FALSE - Does not support Certificate Authentication."
-- 
2.17.1.windows.2

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Re: [edk2] [PATCH V2] BaseTools: Latter full value should overwrite the former field value.

[Gao, Liming]

Reviewed-by: Liming Gao 

>-Original Message-
>From: Zhao, ZhiqiangX
>Sent: Wednesday, September 12, 2018 5:19 PM
>To: edk2-devel@lists.01.org
>Cc: Zhao, ZhiqiangX ; Gao, Liming
>; Zhu, Yonghong ; Feng,
>Bob C 
>Subject: [PATCH V2] BaseTools: Latter full value should overwrite the former
>field value.
>
>For structure Pcd, the latter full assign value in commandLine should
>override the former field assign value. For example in commandLine,
>build --pcd Token.pcd.field="haha" --pcd Token.pcd=H"{0x01,0x02}",
>the former field value "haha" will be ignored and overwrite by the latter
>full value "{0x01,0x02}".
>
>Contributed-under: TianoCore Contribution Agreement 1.1
>Signed-off-by: ZhiqiangX Zhao 
>Cc: Liming Gao 
>Cc: Yonghong Zhu 
>Cc: Bob Feng 
>---
> BaseTools/Source/Python/Workspace/DscBuildData.py | 17
>+
> BaseTools/Source/Python/build/BuildReport.py  | 20 -
>---
> 2 files changed, 33 insertions(+), 4 deletions(-)
>
>diff --git a/BaseTools/Source/Python/Workspace/DscBuildData.py
>b/BaseTools/Source/Python/Workspace/DscBuildData.py
>index 88ba415c5a..4e505c1e99 100644
>--- a/BaseTools/Source/Python/Workspace/DscBuildData.py
>+++ b/BaseTools/Source/Python/Workspace/DscBuildData.py
>@@ -1032,6 +1032,23 @@ class DscBuildData(PlatformBuildClassObject):
> PcdItem = BuildData.Pcds[key]
> if (TokenSpaceGuidCName, TokenCName) ==
>(PcdItem.TokenSpaceGuidCName, PcdItem.TokenCName) and FieldName
>=="":
> PcdItem.DefaultValue = pcdvalue
>+#In command line, the latter full assign value in commandLine should
>override the former field assign value.
>+#For example, --pcd Token.pcd.field="" --pcd Token.pcd=H"{}"
>+delete_assign = []
>+field_assign = {}
>+if GlobalData.BuildOptionPcd:
>+for pcdTuple in GlobalData.BuildOptionPcd:
>+TokenSpaceGuid, Token, Field = pcdTuple[0], pcdTuple[1],
>pcdTuple[2]
>+if Field:
>+if (TokenSpaceGuid, Token) not in field_assign:
>+field_assign[TokenSpaceGuid, Token] = []
>+field_assign[TokenSpaceGuid, Token].append(pcdTuple)
>+else:
>+if (TokenSpaceGuid, Token) in field_assign:
>+delete_assign.extend(field_assign[TokenSpaceGuid, 
>Token])
>+field_assign[TokenSpaceGuid, Token] = []
>+for item in delete_assign:
>+GlobalData.BuildOptionPcd.remove(item)
>
> @staticmethod
> def HandleFlexiblePcd(TokenSpaceGuidCName, TokenCName, PcdValue,
>PcdDatumType, GuidDict, FieldName=''):
>diff --git a/BaseTools/Source/Python/build/BuildReport.py
>b/BaseTools/Source/Python/build/BuildReport.py
>index a598d64244..3886a7a55e 100644
>--- a/BaseTools/Source/Python/build/BuildReport.py
>+++ b/BaseTools/Source/Python/build/BuildReport.py
>@@ -982,12 +982,16 @@ class PcdReport(object):
> PcdValue = DecDefaultValue
> if DscDefaultValue:
> PcdValue = DscDefaultValue
>-Pcd.DefaultValue = PcdValue
>+#The DefaultValue of StructurePcd already be the latest, no 
>need to
>update.
>+if not self.IsStructurePcd(Pcd.TokenCName,
>Pcd.TokenSpaceGuidCName):
>+Pcd.DefaultValue = PcdValue
> if ModulePcdSet is not None:
> if (Pcd.TokenCName, Pcd.TokenSpaceGuidCName, Type) not in
>ModulePcdSet:
> continue
> InfDefaultValue, PcdValue = ModulePcdSet[Pcd.TokenCName,
>Pcd.TokenSpaceGuidCName, Type]
>-Pcd.DefaultValue = PcdValue
>+#The DefaultValue of StructurePcd already be the latest, 
>no need
>to update.
>+if not self.IsStructurePcd(Pcd.TokenCName,
>Pcd.TokenSpaceGuidCName):
>+Pcd.DefaultValue = PcdValue
> if InfDefaultValue:
> try:
> InfDefaultValue = 
> ValueExpressionEx(InfDefaultValue,
>Pcd.DatumType, self._GuidDict)(True)
>@@ -1003,7 +1007,9 @@ class PcdReport(object):
> if pcd[2]:
> continue
> PcdValue = pcd[3]
>-Pcd.DefaultValue = PcdValue
>+#The DefaultValue of StructurePcd already be the 
>latest, no
>need to update.
>+if not self.IsStructurePcd(Pcd.TokenCName,
>Pcd.TokenSpaceGuidCName):
>+Pcd.DefaultValue = PcdValue
> BuildOptionMatch = True
> break
>
>@@ -1050,7 +1056,7 @@ class PcdReport(object):
> DscMatch = (DscDefaultValue.strip() == 
> PcdValue.strip())
>
> IsStructure = False
>-  

Re: [edk2] [PATCH] BaseTools: Correct the SkuOverwrite.

[Gao, Liming]

Zhiqiang:
  Please update patch title with more information to describe the correct 
behavior. 

>-Original Message-
>From: Zhao, ZhiqiangX
>Sent: Wednesday, September 12, 2018 11:25 AM
>To: edk2-devel@lists.01.org
>Cc: Zhao, ZhiqiangX ; Gao, Liming
>; Zhu, Yonghong ; Feng,
>Bob C 
>Subject: [PATCH] BaseTools: Correct the SkuOverwrite.
>
>StructurePcd, SkuA does not define any structure pcd overwrite,
>But SkuA inherit from DEFAULT sku, and DEFAULT sku define
>structure pcd overwrite, the pcd value of SkuA should same with
>DEFAULT sku.
>
>Contributed-under: TianoCore Contribution Agreement 1.1
>Signed-off-by: ZhiqiangX Zhao 
>Cc: Liming Gao 
>Cc: Yonghong Zhu 
>Cc: Bob Feng 
>---
> BaseTools/Source/Python/Workspace/DscBuildData.py | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
>diff --git a/BaseTools/Source/Python/Workspace/DscBuildData.py
>b/BaseTools/Source/Python/Workspace/DscBuildData.py
>index aaef404772..5321101def 100644
>--- a/BaseTools/Source/Python/Workspace/DscBuildData.py
>+++ b/BaseTools/Source/Python/Workspace/DscBuildData.py
>@@ -1838,12 +1838,15 @@ class DscBuildData(PlatformBuildClassObject):
> IsArray = IsFieldValueAnArray(FieldList[FieldName][0])
> if IsArray:
> try:
>-FieldList[FieldName][0] =
>ValueExpressionEx(FieldList[FieldName][0], TAB_VOID, self._GuidDict)(True)
>+FieldValue = 
>ValueExpressionEx(FieldList[FieldName][0],
>TAB_VOID, self._GuidDict)(True)
> except BadExpression:
> EdkLogger.error('Build', FORMAT_INVALID, "Invalid 
> value
>format for %s. From %s Line %d " %
> 
> (".".join((Pcd.TokenSpaceGuidCName,
>Pcd.TokenCName, FieldName)), FieldList[FieldName][1],
>FieldList[FieldName][2]))
> try:
>-Value, ValueSize = ParseFieldValue 
>(FieldList[FieldName][0])
>+if IsArray:
>+Value, ValueSize = ParseFieldValue (FieldValue)
>+else:
>+Value, ValueSize = ParseFieldValue 
>(FieldList[FieldName][0])
> except Exception:
> EdkLogger.error('Build', FORMAT_INVALID, "Invalid 
> value format
>for %s. From %s Line %d " % (".".join((Pcd.TokenSpaceGuidCName,
>Pcd.TokenCName, FieldName)), FieldList[FieldName][1],
>FieldList[FieldName][2]))
> if isinstance(Value, str):
>--
>2.14.1.windows.1

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Re: [edk2] [PATCH 2/3] MdeModulePkg: Remove the missing PalLib in DSC file.

[Chen, Chen A]

Good suggest for me.

-Original Message-
From: Zeng, Star 
Sent: Friday, September 21, 2018 11:48 AM
To: Chen, Chen A ; edk2-devel@lists.01.org
Cc: Dong, Eric ; Kinney, Michael D 
; Zeng, Star 
Subject: RE: [PATCH 2/3] MdeModulePkg: Remove the missing PalLib in DSC file.

As I remember, I raised comment about removing the PalLib in MdeModulePkg.dsc 
at https://lists.01.org/pipermail/edk2-devel/2018-June/026079.html.

I'd like suggest updating the title and commit message a little.

For title: How about "MdeModulePkg: Remove PalLib in dsc which was missed at 
de00522" ?

For commit message: How about like below?

The PalLib is IPF specific and will be removed from MdePkg.
So this patch removes PalLib in MdeModulePkg.dsc which was missed at 
de005223b77c473d45c9c8a11147f6968325f73e.

With them accepted, Reviewed-by: Star Zeng .


Thanks,
Star
-Original Message-
From: Chen, Chen A
Sent: Friday, September 21, 2018 9:00 AM
To: edk2-devel@lists.01.org
Cc: Chen, Chen A ; Zeng, Star ; 
Dong, Eric ; Kinney, Michael D 
Subject: [PATCH 2/3] MdeModulePkg: Remove the missing PalLib in DSC file.

The PalLib will remove in MdePkg, so remove this lib from DSC file.

Cc: Star Zeng 
Cc: Eric Dong 
Cc: Michael D Kinney 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chen A Chen 
---
 MdeModulePkg/MdeModulePkg.dsc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc 
index 8a81ea141f..3ff3b1213c 100644
--- a/MdeModulePkg/MdeModulePkg.dsc
+++ b/MdeModulePkg/MdeModulePkg.dsc
@@ -79,7 +79,6 @@
   SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
   PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-  PalLib|MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
   
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
   
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
   #
--
2.16.2.windows.1

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Re: [edk2] [PATCH v2] UefiCpuPkg PiSmmCpuDxeSmm: Update SmiEntry function run the same position

[Gao, Liming]

Laszlo:
  Thanks for your comments. I have corrected the patch and pushed it into edk2. 

Thanks
Liming
>-Original Message-
>From: Laszlo Ersek [mailto:ler...@redhat.com]
>Sent: Friday, September 21, 2018 6:49 PM
>To: Gao, Liming ; edk2-devel@lists.01.org
>Cc: Dong, Eric ; Yao, Jiewen 
>Subject: Re: [PATCH v2] UefiCpuPkg PiSmmCpuDxeSmm: Update SmiEntry
>function run the same position
>
>Hi Liming,
>
>On 09/21/18 02:56, Liming Gao wrote:
>> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1191
>>
>> Before commit e21e355e2ca7fefb15b4df7078f995d3fb9c2b89, jmp
>_SmiHandler
>> is commented. And below code, ASM_PFX(CpuSmmDebugEntry) is moved
>into rax,
>> then call it. But, this code doesn't work in XCODE5 tool chain. Because
>XCODE5
>> doesn't generated the absolute address in the EFI image. So, rax stores the
>> relative address. Once this logic is moved to another place, it will not 
>> work.
>> ;   jmp _SmiHandler ; instruction is not needed
>> ...
>> mov rax, ASM_PFX(CpuSmmDebugEntry)
>> callrax
>>
>> Commit e21e355e2ca7fefb15b4df7078f995d3fb9c2b89 is to support XCODE5.
>> One tricky way is selected to fix it. Although SmiEntry logic is copied to
>> another place and run, but here jmp _SmiHandler is enabled to jmp the
>original
>> code place, then call ASM_PFX(CpuSmmDebugEntry) with the relative
>address.
>> mov rax, strict qword 0 ;   mov rax, _SmiHandler
>> _SmiHandlerAbsAddr:
>> jmp rax
>> ...
>> callASM_PFX(CpuSmmDebugEntry)
>>
>> Now, BZ 1191 raises the issue that SmiHandler should run in the copied
>address,
>> can't run in the common address. So, jmp _SmiHandler is required to be
>removed,
>> the code is kept to run in copied address. And, the relative address is
>> requried to be fixed up to the absolute address. The necessary changes
>should
>> not affect the behavior of platforms that already consume
>PiSmmCpuDxeSmm.
>> OVMF SMM boot to shell with VS2017, GCC5 and XCODE5 tool chain has
>been verified.
>> ...
>> mov rax, strict qword 0 ;   callASM_PFX(CpuSmmDebugEntry)
>> CpuSmmDebugEntryAbsAddr:
>> callrax
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Liming Gao 
>> Cc: Laszlo Ersek 
>> Cc: Eric Dong 
>> Cc: Jiewen Yao 
>> ---
>>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 42
>++---
>>  1 file changed, 33 insertions(+), 9 deletions(-)
>>
>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
>b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
>> index 315d0f8..815f95b 100644
>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
>> @@ -173,9 +173,6 @@ SmiHandlerIdtrAbsAddr:
>>  mov gs, eax
>>  mov ax, [rbx + DSC_SS]
>>  mov ss, eax
>> -mov rax, strict qword 0 ;   mov rax, _SmiHandler
>> -_SmiHandlerAbsAddr:
>> -jmp rax
>>
>>  _SmiHandler:
>>  mov rbx, [rsp + 0x8] ; rcx <- CpuIndex
>> @@ -189,13 +186,19 @@ _SmiHandler:
>>  add rsp, -0x20
>>
>>  mov rcx, rbx
>> -callASM_PFX(CpuSmmDebugEntry)
>> +mov rax, strict qword 0 ;   call
>> ASM_PFX(CpuSmmDebugEntry)
>> +CpuSmmDebugEntryAbsAddr:
>> +callrax
>>
>>  mov rcx, rbx
>> -callASM_PFX(SmiRendezvous)
>> +mov rax, strict qword 0 ;   callASM_PFX(SmiRendezvous)
>> +SmiRendezvousAbsAddr:
>> +callrax
>>
>>  mov rcx, rbx
>> -callASM_PFX(CpuSmmDebugExit)
>> +mov rax, strict qword 0 ;   callASM_PFX(CpuSmmDebugExit)
>> +CpuSmmDebugExitAbsAddr:
>> +callrax
>>
>>  add rsp, 0x20
>>
>> @@ -206,7 +209,8 @@ _SmiHandler:
>>
>>  add rsp, 0x200
>>
>> -lea rax, [ASM_PFX(mXdSupported)]
>> +mov rax, strict qword 0 ;   lea rax, 
>> [ASM_PFX(mXdSupported)]
>> +mXdSupportedAbsAddr:
>>  mov al, [rax]
>>  cmp al, 0
>>  jz  .1
>> @@ -224,13 +228,33 @@ _SmiHandler:
>>
>>  ASM_PFX(gcSmiHandlerSize)DW  $ - _SmiEntryPoint
>>
>> +;
>> +; Retrieve the address and fill it into mov opcode.
>> +;
>> +; It is called in the driver entry point first.
>> +; It is used to fix up the real address in mov opcode.
>> +; Then, after the code logic is copied to the different location,
>
>The "git am" command complained that the line above added a whitespace
>error. Can you please strip the trailing space character when you push
>the patch?
>
>Reviewed-by: Laszlo Ersek 
>Tested-by: Laszlo Ersek 
>
>Thanks,
>Laszlo
>
>
>> +; the code can also run.
>> +;
>>  global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)
>>  ASM_PFX(PiSmmCpuSmiEntryFixupAddress):
>>  learax, [ASM_PFX(gSmiHandlerIdtr)]
>>  learcx, [SmiHandlerIdtrAbsAddr]
>>  movqword [rcx - 8], rax
>>
>> -learax, [_SmiHandler]
>> -learcx, [_SmiHandlerAbsAddr]
>> +learax, [ASM_PFX(CpuSmmDebugEntry)]
>> 

Re: [edk2] Stack issue after warm UEFI reset and MMU enabling on an Armv8 platform

[Vladimir Olovyannikov]

On Fri, Sep 21, 2018 at 5:14 PM Ard Biesheuvel
 wrote:
>
>
>
> On Fri 21 Sep 2018 at 16:57, Andrew Fish  wrote:
>>
>>
>>
>> > On Sep 21, 2018, at 4:24 PM, Vladimir Olovyannikov 
>> >  wrote:
>> >
>> > On Thu, Sep 20, 2018 at 2:52 PM Vladimir Olovyannikov
>> >  wrote:
>> >>
>> >> On Wed, Sep 19, 2018 at 5:21 PM Bill Paul  wrote:
>> >>>
>> >>> Of all the gin joints in all the towns in all the world, Vladimir
>> >>> Olovyannikov
>> >>> had to walk into mine at 16:58 on Wednesday 19 September 2018 and say:
>> >>>
>> > From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
>> > Sent: Wednesday, September 19, 2018 4:38 PM
>> > To: Vladimir Olovyannikov
>> > Cc: edk2-devel@lists.01.org
>> > Subject: Re: Stack issue after warm UEFI reset and MMU enabling on an
>> > Armv8 platform
>> >
>> >
>> > On 19 September 2018 at 15:55, Vladimir Olovyannikov
>> >
>> >  wrote:
>> >> Hi All,
>> >>
>> >> I need UEFI experts help on the problem with Armv8 board on warm UEFI
>> >> reset.
>> >> Cold reset works fine.
>> >>
>> >> Here is how I set up a warm reset:
>> >>
>> >> STATIC
>> >> EFI_STATUS
>> >> ShutdownUefiBootServices (
>> >>
>> >> VOID
>> >> )
>> >>
>> >> {
>> >>
>> >> EFI_STATUS  Status;
>> >> UINTN   MemoryMapSize;
>> >> EFI_MEMORY_DESCRIPTOR   *MemoryMap;
>> >> UINTN   MapKey;
>> >> UINTN   DescriptorSize;
>> >> UINT32  DescriptorVersion;
>> >> UINTN   Pages;
>> >>
>> >> MemoryMap = NULL;
>> >> MemoryMapSize = 0;
>> >> Pages = 0;
>> >>
>> >> do {
>> >>
>> >>   Status = gBS->GetMemoryMap (
>> >>
>> >>   ,
>> >>   MemoryMap,
>> >>   ,
>> >>   ,
>> >>   
>> >>   );
>> >>
>> >>   if (Status == EFI_BUFFER_TOO_SMALL) {
>> >>
>> >> Pages = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1;
>> >> MemoryMap = AllocatePages (Pages);
>> >>
>> >> //
>> >> // Get System MemoryMap
>> >> //
>> >> Status = gBS->GetMemoryMap (
>> >>
>> >> ,
>> >> MemoryMap,
>> >> ,
>> >> ,
>> >> 
>> >> );
>> >>
>> >>   }
>> >>
>> >>   // Don't do anything between the GetMemoryMap() and
>> >>   ExitBootServices() if (!EFI_ERROR(Status)) {
>> >>
>> >> Status = gBS->ExitBootServices (gImageHandle, MapKey);
>> >> if (EFI_ERROR(Status)) {
>> >>
>> >>   FreePages (MemoryMap, Pages);
>> >>   MemoryMap = NULL;
>> >>   MemoryMapSize = 0;
>> >>
>> >> }
>> >>
>> >>   }
>> >>
>> >> } while (EFI_ERROR(Status));
>> >>
>> >> return Status;
>> >>
>> >> }
>> >>
>> >> Then perform
>> >> ArmCleanDataCache ();
>> >> ArmInvalidateDataCache ();
>> >> ArmDisableInstructionCache ();
>> >> ArmInvalidateInstructionCache ();
>> >
>> > These don't do anything useful on ARM. You can only reliably perform
>> > cache
>> > maintenance by virtual address.
>> 
>>  So, should I just remove them altogether?
>> 
>> >> ArmDisableMmu ();
>> >
>> > ... so after this call returns, all bets are off with regards to
>> > whether
>> > what is popped from the stack is actually what we pushed when we
>> > entered
>> > the function.
>> 
>>  OK, thank you for explanation.
>>  But this call returns back into ResetLib implementation as it should,
>>  and
>>  then there is a direct jump to the start of FV.
>>  Am I doing anything wrong here?
>>  Then, up to the point of enabling of MMU the stack is OK. But right
>>  after
>>  enabling MMU it points at _ModuleEntryPoint end of function in
>>  DxeCoreEntryPoint.c
>>  Am I missing anything? Maybe some stack cleanup before jumping to the
>>  start
>>  of FV?
>> >>>
>> >>> When the MMU is enabled, does the mapping for the stack pages change? 
>> >>> That
>> >>> is,
>> >>> could the stack now be mapped to different physical page now?
>> >> Thanks for ideas Bill,
>> >> No, the mapping stays the same.
>> >> The issue is only with warm reset, and only on an A72 board.
>> >> There is another platform on A53 sharing the same code, which has no 
>> >> issues
>> >> with warm reset.
>> >> I cannot explain why.
>> >>>
>> >>> Instead of showing a stack trace, can you dump the stack pages and 
>> >>> compare
>> >>> the
>> >>> before and after contents?
>> >> I can clearly see that before and after contents are different.
>> >>>
>> >>> Assuming the same physical memory pages are still being used, then there
>> >>> could
>> >>> be a cache flushing 

Re: [edk2] Updating/adding video mode

[prabin ca]

Thanks Andrew,

For your reply. EDID overriding is the last solution for me. Any way thanks for 
pointing the EFI_EDID protocols.

> On 19-Sep-2018, at 11:01 PM, Andrew Fish  wrote:
> 
> Prabin,
> 
> There is not an easy answer to your question. 
> 1) What video resolution is available can be a function of what monitor is 
> plugged in to the graphics card. 
> 2) The monitor can publish an EDID that defines what resolutions the monitor 
> supports. EDID is a VESA standard. 
> 3) An EFI Platform can provide an EFI_EDID_OVERRIDE_PROTOCOL that can impact 
> the available video modes that get published. 
> 4) The GOP card will publish EDID information via the 
> EFI_EDID_DISCOVERED_PROTOCOL. 
> 
> As I mentioned the EDID data structure is defined by a VESA standard, but it 
> also has to be valid for what the monitor can support. Basically you can 
> override the EDID and tell the GOP card to does something the monitor can not 
> support. 
> 
> Some platforms use the ConSpliter and it produces a virtual GOP protocol that 
> will aggregate hardware GOPs. So for example if you system has an internal 
> panel and an external monitor installed you could end up with 2 HW GOP 
> protocols and a virtual GOP protocol that represents the ConSpliter. 
> 
> Thanks,
> 
> Andrew Fish 
> 
>> On Sep 15, 2018, at 10:37 PM, prabin ca  wrote:
>> 
>> Any points on this really helpful for me. 
>> 
>>> On 15-Sep-2018, at 6:46 AM, prabin ca  wrote:
>>> 
>>> Hi Team,
>>> I’m working with a platform having UHD (3840X2160as native resolution) 
>>> display screen. I have dump the video modes using EFI_GRAPHICS_PROTOCOL.
>>> 
>>> Following are the dump result 
>>> 
>>> Mode 0 : hRes = 3840 Vres=2160
>>> Mode 1 : hRes = 640  Vres = 480
>>> Mode 2 : hRes = 800 Vres = 600
>>> Mode 3 : hRes = 1024 Vres = 768
>>> Mode 4 : hRes = 1280 Vres = 1024
>>> Mode 5 : hRes = 1600 Vres = 1200
>>> Mode 6 : hRes = 1920 Vres = 1440 
>>> 
>>> In the supported video mode list, 1920X1080 is not there. Is there any way 
>>> to add support for this resolution. I have checked UEFI spec but didn’t 
>>> find any useful API/protocol 
>>> Any help really appreciate.
>> ___
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Re: [edk2] [PATCH v2 1/2] MdePkg/IndustryStandard: Add Global Plaform header file

[Kinney, Michael D]

Hi Ard,

The initial content is only from the TEE Client API Specification.
I noticed that there is an errata to that spec as well.  Does this
content follow the errata?

I also noticed that the specifications require the acceptance of
an additional license to view the contents.  Is there a version of
the content for this include file available that does not require
the acceptance of an additional license?

Thanks,

Mike

> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Monday, September 24, 2018 1:26 AM
> To: Sumit Garg 
> Cc: edk2-devel@lists.01.org; tee-...@lists.linaro.org;
> Leif Lindholm ; Daniel
> Thompson ; Matteo Carlini
> ; Achin Gupta
> ; Udit Kumar ;
> Kinney, Michael D ; Gao,
> Liming 
> Subject: Re: [edk2][PATCH v2 1/2]
> MdePkg/IndustryStandard: Add Global Plaform header file
> 
> On Sat, 22 Sep 2018 at 01:15, Ard Biesheuvel
>  wrote:
> >
> > On 27 August 2018 at 04:50, Sumit Garg
>  wrote:
> > > Add Global Plaform header file specific to TEE
> Client API Specification v1
> > >
>  >.
> > >
> > > Cc: Michael D Kinney 
> > > Cc: Liming Gao 
> > > Cc: Ard Biesheuvel 
> > > Cc: Leif Lindholm 
> > > Contributed-under: TianoCore Contribution Agreement
> 1.1
> > > Signed-off-by: Sumit Garg 
> >
> > Acked-by: Ard Biesheuvel 
> >
> > Mike,
> >
> > The header file is a bit light on content at
> introduction, but as
> > discussed online, we can add stuff as we go for other
> use cases.
> >
> 
> ... as discussed *offline*
> 
> >
> > > ---
> > >  MdePkg/Include/IndustryStandard/GlobalPlatform.h |
> 27 
> > >  1 file changed, 27 insertions(+)
> > >  create mode 100644
> MdePkg/Include/IndustryStandard/GlobalPlatform.h
> > >
> > > diff --git
> a/MdePkg/Include/IndustryStandard/GlobalPlatform.h
> b/MdePkg/Include/IndustryStandard/GlobalPlatform.h
> > > new file mode 100644
> > > index ..72c5af4ef588
> > > --- /dev/null
> > > +++
> b/MdePkg/Include/IndustryStandard/GlobalPlatform.h
> > > @@ -0,0 +1,27 @@
> > > +/** @file
> > > +  Standardized Global Platform header file.
> GlobalPlatform TEE Client API
> > > +  Specification v1.0:
>  >
> > > +
> > > +  Copyright (c) 2018, Linaro Ltd. All rights
> reserved.
> > > +
> > > +  This program and the accompanying materials
> > > +  are licensed and made available under the terms
> and conditions of the BSD License
> > > +  which accompanies this distribution.  The full
> text of the license may be found at
> > > +  http://opensource.org/licenses/bsd-license.php
> > > +
> > > +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE
> ON AN "AS IS" BASIS,
> > > +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
> KIND, EITHER EXPRESS OR IMPLIED.
> > > +
> > > +**/
> > > +
> > > +#ifndef _GLOBAL_PLATFORM_H_
> > > +#define _GLOBAL_PLATFORM_H_
> > > +
> > > +#define TEEC_ORIGIN_COMMS
> 0x0002
> > > +
> > > +#define TEEC_SUCCESS
> 0x
> > > +#define TEEC_ERROR_BAD_PARAMETERS
> 0x0006
> > > +#define TEEC_ERROR_OUT_OF_MEMORY
> 0x000C
> > > +#define TEEC_ERROR_COMMUNICATION
> 0x000E
> > > +
> > > +#endif
> > > --
> > > 2.7.4
> > >
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[edk2] [PATCH edk2-platforms 1/1] Platform/Comcast/RDKQemu: Incorporate ArmVirtQemu changes

[Moorthy B S]

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Moorthy B S 
Cc: Ard Biesheuvel 
---
 Platform/Comcast/RDKQemu/RDKQemu.dsc | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/Platform/Comcast/RDKQemu/RDKQemu.dsc 
b/Platform/Comcast/RDKQemu/RDKQemu.dsc
index 1301cefe..02ec53a85a28 100644
--- a/Platform/Comcast/RDKQemu/RDKQemu.dsc
+++ b/Platform/Comcast/RDKQemu/RDKQemu.dsc
@@ -57,6 +57,7 @@ [LibraryClasses.common]
   BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
   
PlatformBootManagerLib|ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
   
CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+  
FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
   QemuBootOrderLib|OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf
   FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
   
PciPcdProducerLib|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
@@ -355,10 +356,20 @@ [Components.common]
   MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
   MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
   MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
-  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
   MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+!if $(NETWORK_IP6_ENABLE) == TRUE
+  NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+  NetworkPkg/TcpDxe/TcpDxe.inf
+  NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+  NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+  NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+  NetworkPkg/IScsiDxe/IScsiDxe.inf
+!else
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
   MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
   MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!endif
 !if $(HTTP_BOOT_ENABLE) == TRUE
   NetworkPkg/DnsDxe/DnsDxe.inf
   NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
@@ -398,6 +409,7 @@ [Components.common]
   #
   # Video support
   #
+  OvmfPkg/QemuRamfbDxe/QemuRamfbDxe.inf
   OvmfPkg/VirtioGpuDxe/VirtioGpu.inf
   OvmfPkg/PlatformDxe/Platform.inf
 
-- 
2.17.0

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[edk2] [PATCH edk2-platforms 0/1] Incorporate ArmVirtQemu changes

[Moorthy B S]

Latest changes in ArmVirtQemu incorporated into RDKQemu
for maintenance

Cc: Ard Biesheuvel 

Moorthy B S (1):
  Platform/Comcast/RDKQemu: Incorporate ArmVirtQemu changes

 Platform/Comcast/RDKQemu/RDKQemu.dsc | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

-- 
2.17.0

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Re: [edk2] Minimum tianocore payload

[Oram, Isaac W]

Jorge,

A couple of other examples can be found in the MinPlatform work.

https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf
 
https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.fdf
 
Both include 
https://github.com/tianocore/edk2-platforms/blob/devel-MinPlatform/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreUefiBootInclude.fdf
 

FV.FvUefiBootUncompact has enough to boot to UEFI shell, with UART console.
We are looking to further reduce the contents, as the FvUefiBootUncompact 
contains SATA, USB, etc that aren't strictly necessary.

These three solutions are pretty similar, so cross referencing gets you a 
reasonable minimum list.  The main differences look to be around silicon policy 
configuration and boot media supported.

The other FV for OS boot and Security are not necessary initially, but should 
also be useful after you get minimum identified.  The OS boot FV adds minimal 
functionality for Linux/Windows style OS and the security FV adds secure boot 
functionality.

Regards,
Isaac


-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Kinney, 
Michael D
Sent: Monday, September 24, 2018 7:26 AM
To: Jorge Fernandez Monteagudo ; edk2-devel@lists.01.org; 
Kinney, Michael D 
Subject: Re: [edk2] Minimum tianocore payload

One example is Quark:

  https://github.com/tianocore/edk2/tree/master/QuarkPlatformPkg

It has both a minimum and a full example:

  https://github.com/tianocore/edk2/blob/master/QuarkPlatformPkg/QuarkMin.dsc
  https://github.com/tianocore/edk2/blob/master/QuarkPlatformPkg/QuarkMin.fdf

  https://github.com/tianocore/edk2/blob/master/QuarkPlatformPkg/Quark.dsc
  https://github.com/tianocore/edk2/blob/master/QuarkPlatformPkg/Quark.fdf

The min profiles uses a UART as a console and only supports booting from FLASH. 
 It does have a few additional features that could be removed related to menus 
and configuration, but at least a good example to study.

Mike

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-
> boun...@lists.01.org] On Behalf Of Jorge Fernandez Monteagudo
> Sent: Monday, September 24, 2018 3:41 AM
> To: edk2-devel@lists.01.org
> Subject: [edk2] Minimum tianocore payload
> 
> Hi all,
> 
> 
> Is there any example how to reduce the components needed in the 
> tianocore payload
> 
> to get a minimum payload? I'm thinking in a payload without console, 
> menu, no configurable
> 
> to be used in an embedded system...
> 
> 
> Thanks!
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Re: [edk2] [PATCH v2 0/3] remove most occurrences of ELILO on IPF PE/COFF header hack

[Ard Biesheuvel]

On Fri, 7 Sep 2018 at 07:42, Ard Biesheuvel  wrote:
>
> Now that Itanium support has been dropped from EDK2, we can remove most
> occurrences of the ELILO PE/COFF loader hack from the code base.
>
> Note that SecurityPkg appears to have four mostly identical implementations
> of the PE/COFF measuring routine, so this may be another area for cleanup
> later.
>
> Changes since v1:
> - fix copy/paste error in patch #3 which went unnoticed due to the fact that
>   SecurityPkg.dsc does not cover the module in question for AARCH64
> - drop EdkCompatibilityPkg patch, it is likely to go away soon anyway
> - add Reviewed-by tags
>
> Link: https://bugzilla.tianocore.org/show_bug.cgi?id=816
>
> Cc: Star Zeng 
> Cc: Jian J Wang 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> Cc: Chao Zhang 
> Cc: Jiewen Yao 
> Cc: Laszlo Ersek 
> Cc: Leif Lindholm 
>
> Ard Biesheuvel (3):
>   MdeModulePkg: remove PE/COFF header workaround for ELILO on IPF
>   MdePkg/BasePeCoffLib: remove PE/COFF header workaround for ELILO on
> IPF
>   SecurityPkg: remove PE/COFF header workaround for ELILO on IPF
>

Patches 1-2 pushed as 997731e796f5..60eb6c6d2e01 (#3 was merged
independently by Chao)

Thanks all

>  .../Core/Dxe/Mem/MemoryProfileRecord.c| 31 +-
>  MdeModulePkg/Core/Dxe/Misc/MemoryProtection.c | 17 +-
>  MdeModulePkg/Core/Dxe/Misc/PropertiesTable.c  | 17 +-
>  .../Core/PiSmmCore/MemoryAttributesTable.c| 17 +-
>  .../Core/PiSmmCore/SmramProfileRecord.c   | 31 +-
>  MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 61 +++
>  .../DxeImageVerificationLib.c | 47 +++---
>  .../DxeTpmMeasureBootLib.c| 27 ++--
>  SecurityPkg/Tcg/Tcg2Dxe/MeasureBootPeCoff.c   | 27 ++--
>  .../SecureBootConfigImpl.c| 25 ++--
>  10 files changed, 39 insertions(+), 261 deletions(-)
>
> --
> 2.17.1
>
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[edk2] [PATCH v1 5/7] BaseTools/GenFds: refactor FdfParser warnings

[Jaben Carsey]

make functions for common error messages
refactor to use these functions

Cc: Yonghong Zhu 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jaben Carsey 
---
 BaseTools/Source/Python/GenFds/FdfParser.py | 603 ++--
 1 file changed, 303 insertions(+), 300 deletions(-)

diff --git a/BaseTools/Source/Python/GenFds/FdfParser.py 
b/BaseTools/Source/Python/GenFds/FdfParser.py
index 6a2f87474f60..821b3edb7592 100644
--- a/BaseTools/Source/Python/GenFds/FdfParser.py
+++ b/BaseTools/Source/Python/GenFds/FdfParser.py
@@ -128,6 +128,24 @@ class Warning (Exception):
 def __str__(self):
 return self.Message
 
+# helper functions to facilitate consistency in warnings
+# each function is for a different common warning
+@staticmethod
+def Expected(Str, File, Line):
+return Warning("expected {}".format(Str), File, Line)
+@staticmethod
+def ExpectedEquals(File, Line):
+return Warning.Expected("'='", File, Line)
+@staticmethod
+def ExpectedCurlyOpen(File, Line):
+return Warning.Expected("'{'", File, Line)
+@staticmethod
+def ExpectedCurlyClose(File, Line):
+return Warning.Expected("'}'", File, Line)
+@staticmethod
+def ExpectedBracketClose(File, Line):
+return Warning.Expected("']'", File, Line)
+
 ## The Include file content class that used to record file data when parsing 
include file
 #
 # May raise Exception when opening file.
@@ -183,8 +201,6 @@ class IncludeFileProfile:
 
 return (self.FileName, Line - InsertedLines + 1)
 
-
-
 ## The FDF content class that used to record file data when parsing FDF
 #
 # May raise Exception when opening file.
@@ -562,10 +578,10 @@ class FdfParser:
 
 if self._Token == TAB_DEFINE:
 if not self._GetNextToken():
-raise Warning("expected Macro name", self.FileName, 
self.CurrentLineNumber)
+raise Warning.Expected("Macro name", self.FileName, 
self.CurrentLineNumber)
 Macro = self._Token
 if not self._IsToken(TAB_EQUAL_SPLIT):
-raise Warning("expected '='", self.FileName, 
self.CurrentLineNumber)
+raise Warning.ExpectedEquals(self.FileName, 
self.CurrentLineNumber)
 Value = self._GetExpression()
 MacroDict[Macro] = Value
 
@@ -574,7 +590,7 @@ class FdfParser:
 IncludeLine = self.CurrentLineNumber
 IncludeOffset = self.CurrentOffsetWithinLine - len(TAB_INCLUDE)
 if not self._GetNextToken():
-raise Warning("expected include file name", self.FileName, 
self.CurrentLineNumber)
+raise Warning.Expected("include file name", self.FileName, 
self.CurrentLineNumber)
 IncFileName = self._Token
 PreIndex = 0
 StartPos = IncFileName.find('$(', PreIndex)
@@ -730,10 +746,10 @@ class FdfParser:
 DefineLine = self.CurrentLineNumber - 1
 DefineOffset = self.CurrentOffsetWithinLine - 
len(TAB_DEFINE)
 if not self._GetNextToken():
-raise Warning("expected Macro name", self.FileName, 
self.CurrentLineNumber)
+raise Warning.Expected("Macro name", self.FileName, 
self.CurrentLineNumber)
 Macro = self._Token
 if not self._IsToken(TAB_EQUAL_SPLIT):
-raise Warning("expected '='", self.FileName, 
self.CurrentLineNumber)
+raise Warning.ExpectedEquals(self.FileName, 
self.CurrentLineNumber)
 
 Value = self._GetExpression()
 self._SetMacroValue(Macro, Value)
@@ -746,7 +762,7 @@ class FdfParser:
 PcdPair = self._GetNextPcdSettings()
 PcdName = "%s.%s" % (PcdPair[1], PcdPair[0])
 if not self._IsToken(TAB_EQUAL_SPLIT):
-raise Warning("expected '='", self.FileName, 
self.CurrentLineNumber)
+raise Warning.ExpectedEquals(self.FileName, 
self.CurrentLineNumber)
 
 Value = self._GetExpression()
 Value = self._EvaluateConditional(Value, 
self.CurrentLineNumber, 'eval', True)
@@ -1178,20 +1194,20 @@ class FdfParser:
 
 def _GetNextPcdSettings(self):
 if not self._GetNextWord():
-raise Warning("expected format of 
.", self.FileName, self.CurrentLineNumber)
+raise Warning.Expected("", self.FileName, 
self.CurrentLineNumber)
 pcdTokenSpaceCName = self._Token
 
 if not self._IsToken(TAB_SPLIT):
-raise Warning("expected format of 
.", self.FileName, self.CurrentLineNumber)
+raise Warning.Expected(".", self.FileName, self.CurrentLineNumber)
 
 if not self._GetNextWord():
-raise Warning("expected format of 
.", self.FileName, 

[edk2] [PATCH v1 2/7] BaseTools/GenFds: change objects to sets

[Jaben Carsey]

Change lists and tuples used solely for "in" testing to sets.
These operations are not order dependent.
fixed some line length for PEP8 compliance on some.

Cc: Liming Gao 
Cc: Yonghong Zhu 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jaben Carsey 
---
 BaseTools/Source/Python/GenFds/FdfParser.py | 222 +++-
 1 file changed, 123 insertions(+), 99 deletions(-)

diff --git a/BaseTools/Source/Python/GenFds/FdfParser.py 
b/BaseTools/Source/Python/GenFds/FdfParser.py
index 119992daf656..f99bb6215115 100644
--- a/BaseTools/Source/Python/GenFds/FdfParser.py
+++ b/BaseTools/Source/Python/GenFds/FdfParser.py
@@ -69,6 +69,7 @@ SEPARATORS = {TAB_EQUAL_SPLIT, TAB_VALUE_SPLIT, 
TAB_COMMA_SPLIT, '{', '}'}
 ALIGNMENTS = {"Auto", "8", "16", "32", "64", "128", "512", "1K", "4K", "32K", 
"64K", "128K",
 "256K", "512K", "1M", "2M", "4M", "8M", 
"16M"}
 ALIGNMENT_NOAUTO = ALIGNMENTS - {"Auto"}
+CR_LB_SET = {T_CHAR_CR, TAB_LINE_BREAK}
 
 RegionSizePattern = 
compile("\s*(?P(?:0x|0X)?[a-fA-F0-9]+)\s*\|\s*(?P(?:0x|0X)?[a-fA-F0-9]+)\s*")
 RegionSizeGuidPattern = 
compile("\s*(?P\w+\.\w+[\.\w\[\]]*)\s*\|\s*(?P\w+\.\w+[\.\w\[\]]*)\s*")
@@ -265,7 +266,7 @@ class FdfParser:
 #
 def _SkipWhiteSpace(self):
 while not self._EndOfFile():
-if self._CurrentChar() in (TAB_PRINTCHAR_NUL, T_CHAR_CR, 
TAB_LINE_BREAK, TAB_SPACE_SPLIT, T_CHAR_TAB):
+if self._CurrentChar() in {TAB_PRINTCHAR_NUL, T_CHAR_CR, 
TAB_LINE_BREAK, TAB_SPACE_SPLIT, T_CHAR_TAB}:
 self._SkippedChars += str(self._CurrentChar())
 self._GetOneChar()
 else:
@@ -405,14 +406,14 @@ class FdfParser:
 return
 
 Offset = StartPos[1]
-while self.Profile.FileLinesList[StartPos[0]][Offset] not in 
(T_CHAR_CR, TAB_LINE_BREAK):
+while self.Profile.FileLinesList[StartPos[0]][Offset] not in CR_LB_SET:
 self.Profile.FileLinesList[StartPos[0]][Offset] = Value
 Offset += 1
 
 Line = StartPos[0]
 while Line < EndPos[0]:
 Offset = 0
-while self.Profile.FileLinesList[Line][Offset] not in (T_CHAR_CR, 
TAB_LINE_BREAK):
+while self.Profile.FileLinesList[Line][Offset] not in CR_LB_SET:
 self.Profile.FileLinesList[Line][Offset] = Value
 Offset += 1
 Line += 1
@@ -706,7 +707,7 @@ class FdfParser:
 PreIndex = 0
 StartPos = CurLine.find('$(', PreIndex)
 EndPos = CurLine.find(')', StartPos+2)
-while StartPos != -1 and EndPos != -1 and self._Token not 
in [TAB_IF_DEF, TAB_IF_N_DEF, TAB_IF, TAB_ELSE_IF]:
+while StartPos != -1 and EndPos != -1 and self._Token not 
in {TAB_IF_DEF, TAB_IF_N_DEF, TAB_IF, TAB_ELSE_IF}:
 MacroName = CurLine[StartPos+2: EndPos]
 MacorValue = self._GetMacroValue(MacroName)
 if MacorValue is not None:
@@ -758,7 +759,7 @@ class FdfParser:
 self.Profile.PcdFileLineDict[PcdPair] = FileLineTuple
 
 self._WipeOffArea.append(((SetLine, SetOffset), 
(self.CurrentLineNumber - 1, self.CurrentOffsetWithinLine - 1)))
-elif self._Token in (TAB_IF_DEF, TAB_IF_N_DEF, TAB_IF):
+elif self._Token in {TAB_IF_DEF, TAB_IF_N_DEF, TAB_IF}:
 IfStartPos = (self.CurrentLineNumber - 1, 
self.CurrentOffsetWithinLine - len(self._Token))
 IfList.append([IfStartPos, None, None])
 
@@ -776,7 +777,7 @@ class FdfParser:
 IfList[-1] = [IfList[-1][0], ConditionSatisfied, 
BranchDetermined]
 if ConditionSatisfied:
 self._WipeOffArea.append((IfList[-1][0], 
(self.CurrentLineNumber - 1, self.CurrentOffsetWithinLine - 1)))
-elif self._Token in (TAB_ELSE_IF, '!else'):
+elif self._Token in {TAB_ELSE_IF, TAB_ELSE}:
 ElseStartPos = (self.CurrentLineNumber - 1, 
self.CurrentOffsetWithinLine - len(self._Token))
 if len(IfList) <= 0:
 raise Warning("Missing !if statement", self.FileName, 
self.CurrentLineNumber)
@@ -859,13 +860,12 @@ class FdfParser:
 
 MacroDict.update(GlobalData.gGlobalDefines)
 MacroDict.update(GlobalData.gCommandLineDefines)
-if GlobalData.BuildOptionPcd:
-for Item in GlobalData.BuildOptionPcd:
-if isinstance(Item, tuple):
-continue
-PcdName, TmpValue = Item.split(TAB_EQUAL_SPLIT)
-TmpValue = BuildOptionValue(TmpValue, {})
-MacroDict[PcdName.strip()] = TmpValue
+for Item in GlobalData.BuildOptionPcd:
+if isinstance(Item, tuple):
+continue
+PcdName, TmpValue = Item.split(TAB_EQUAL_SPLIT)
+TmpValue = BuildOptionValue(TmpValue, {})
+

[edk2] [PATCH v1 4/7] BaseTools/GenFds: remove MacroDict parameter

[Jaben Carsey]

The MacroDict parameter goes around in circles through 4 functions without use.
1. GetSectionData calls into GetLeafSection, otherwise doesn’t use MacroDict
2. GetLeafSection calls into GetFileStatement, otherwise doesn’t use MacroDict
3. GetFileStatement calls into GetFilePart, otherwise doesn’t use MacroDict
4. GetFilePart calls into GetSectionData, otherwise doesn’t use MacroDict
Go to 1 and repeat forever.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jaben Carsey 
---
 BaseTools/Source/Python/GenFds/FdfParser.py | 48 +++-
 1 file changed, 16 insertions(+), 32 deletions(-)

diff --git a/BaseTools/Source/Python/GenFds/FdfParser.py 
b/BaseTools/Source/Python/GenFds/FdfParser.py
index ff2efd8d7a57..6a2f87474f60 100644
--- a/BaseTools/Source/Python/GenFds/FdfParser.py
+++ b/BaseTools/Source/Python/GenFds/FdfParser.py
@@ -2112,12 +2112,12 @@ class FdfParser:
 if FvObj.FvNameString == 'TRUE' and not FvObj.FvNameGuid:
 raise Warning("FvNameString found but FvNameGuid was not found", 
self.FileName, self.CurrentLineNumber)
 
-self._GetAprioriSection(FvObj, FvObj.DefineVarDict.copy())
-self._GetAprioriSection(FvObj, FvObj.DefineVarDict.copy())
+self._GetAprioriSection(FvObj)
+self._GetAprioriSection(FvObj)
 
 while True:
 isInf = self._GetInfStatement(FvObj)
-isFile = self._GetFileStatement(FvObj, MacroDict = 
FvObj.DefineVarDict.copy())
+isFile = self._GetFileStatement(FvObj)
 if not isInf and not isFile:
 break
 
@@ -2352,11 +2352,10 @@ class FdfParser:
 #
 #   @param  selfThe object pointer
 #   @param  FvObj   for whom apriori is got
-#   @param  MacroDict   dictionary used to replace macro
 #   @retval TrueSuccessfully find apriori statement
 #   @retval False   Not able to find apriori statement
 #
-def _GetAprioriSection(self, FvObj, MacroDict = {}):
+def _GetAprioriSection(self, FvObj):
 if not self._IsKeyword("APRIORI"):
 return False
 
@@ -2371,7 +2370,6 @@ class FdfParser:
 AprSectionObj.AprioriType = AprType
 
 self._GetDefineStatements(AprSectionObj)
-MacroDict.update(AprSectionObj.DefineVarDict)
 
 while True:
 IsInf = self._GetInfStatement(AprSectionObj)
@@ -2525,11 +2523,10 @@ class FdfParser:
 #
 #   @param  selfThe object pointer
 #   @param  Obj for whom FILE statement is got
-#   @param  MacroDict   dictionary used to replace macro
 #   @retval TrueSuccessfully find FILE statement
 #   @retval False   Not able to find FILE statement
 #
-def _GetFileStatement(self, Obj, ForCapsule = False, MacroDict = {}):
+def _GetFileStatement(self, Obj, ForCapsule = False):
 if not self._IsKeyword("FILE"):
 return False
 
@@ -2560,7 +2557,7 @@ class FdfParser:
 
 FfsFileObj.NameGuid = self._Token
 
-self._GetFilePart(FfsFileObj, MacroDict.copy())
+self._GetFilePart(FfsFileObj)
 
 if ForCapsule:
 capsuleFfs = CapsuleFfs()
@@ -2607,9 +2604,8 @@ class FdfParser:
 #
 #   @param  selfThe object pointer
 #   @param  FfsFileObj   for whom component is got
-#   @param  MacroDict   dictionary used to replace macro
 #
-def _GetFilePart(self, FfsFileObj, MacroDict = {}):
+def _GetFilePart(self, FfsFileObj):
 self._GetFileOpts(FfsFileObj)
 
 if not self._IsToken("{"):
@@ -2644,11 +2640,11 @@ class FdfParser:
 
 elif self._Token in {TAB_DEFINE, "APRIORI", "SECTION"}:
 self._UndoToken()
-self._GetSectionData(FfsFileObj, MacroDict)
+self._GetSectionData(FfsFileObj)
 
 elif hasattr(FfsFileObj, 'FvFileType') and FfsFileObj.FvFileType == 
'RAW':
 self._UndoToken()
-self._GetRAWData(FfsFileObj, MacroDict)
+self._GetRAWData(FfsFileObj)
 
 else:
 FfsFileObj.CurrentLineNum = self.CurrentLineNumber
@@ -2665,9 +2661,8 @@ class FdfParser:
 #
 #   @param  self The object pointer
 #   @param  FfsFileObj   for whom section is got
-#   @param  MacroDictdictionary used to replace macro
 #
-def _GetRAWData(self, FfsFileObj, MacroDict = {}):
+def _GetRAWData(self, FfsFileObj):
 FfsFileObj.FileName = []
 FfsFileObj.SubAlignment = []
 while True:
@@ -2755,26 +2750,18 @@ class FdfParser:
 
 return False
 
-## _GetFilePart() method
+## _GetSectionData() method
 #
 #   Get section data for FILE statement
 #
 #   @param  selfThe object pointer
 #   @param  FfsFileObj   for whom section is got
-#   @param  MacroDict   dictionary used to replace macro
 #
-def _GetSectionData(self, FfsFileObj, MacroDict = {}):
-Dict = {}
-

[edk2] [PATCH v1 7/7] BaseTools/GenFds: create and use new variable in FdfParser

[Jaben Carsey]

replace lots of '}' and "}" with a shared new consistent variable.

Cc: Bob Feng 
Cc: Yonghong Zhu 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jaben Carsey 
---
 BaseTools/Source/Python/GenFds/FdfParser.py | 45 ++--
 1 file changed, 23 insertions(+), 22 deletions(-)

diff --git a/BaseTools/Source/Python/GenFds/FdfParser.py 
b/BaseTools/Source/Python/GenFds/FdfParser.py
index f6b79764b2a0..bd3e8f5b8fb7 100644
--- a/BaseTools/Source/Python/GenFds/FdfParser.py
+++ b/BaseTools/Source/Python/GenFds/FdfParser.py
@@ -64,8 +64,9 @@ T_CHAR_TAB = '\t'
 T_CHAR_DOUBLE_QUOTE = '\"'
 T_CHAR_SINGLE_QUOTE = '\''
 T_CHAR_STAR = '*'
+T_CHAR_BRACE_R = '}'
 
-SEPARATORS = {TAB_EQUAL_SPLIT, TAB_VALUE_SPLIT, TAB_COMMA_SPLIT, '{', '}'}
+SEPARATORS = {TAB_EQUAL_SPLIT, TAB_VALUE_SPLIT, TAB_COMMA_SPLIT, '{', 
T_CHAR_BRACE_R}
 ALIGNMENTS = {"Auto", "8", "16", "32", "64", "128", "512", "1K", "4K", "32K", 
"64K", "128K",
 "256K", "512K", "1M", "2M", "4M", "8M", 
"16M"}
 ALIGNMENT_NOAUTO = ALIGNMENTS - {"Auto"}
@@ -2020,7 +2021,7 @@ class FdfParser:
 DataString += self._Token
 DataString += TAB_COMMA_SPLIT
 
-if not self._IsToken("}"):
+if not self._IsToken(T_CHAR_BRACE_R):
 raise Warning.ExpectedCurlyClose(self.FileName, 
self.CurrentLineNumber)
 
 DataString = DataString.rstrip(TAB_COMMA_SPLIT)
@@ -2060,7 +2061,7 @@ class FdfParser:
 DataString += self._Token
 DataString += TAB_COMMA_SPLIT
 
-if not self._IsToken("}"):
+if not self._IsToken(T_CHAR_BRACE_R):
 raise Warning.ExpectedCurlyClose(self.FileName, 
self.CurrentLineNumber)
 
 DataString = DataString.rstrip(TAB_COMMA_SPLIT)
@@ -2328,10 +2329,10 @@ class FdfParser:
 DataString += self._Token
 DataString += TAB_COMMA_SPLIT
 
-if not self._IsToken("}"):
+if not self._IsToken(T_CHAR_BRACE_R):
 raise Warning.ExpectedCurlyClose(self.FileName, 
self.CurrentLineNumber)
 
-if not self._IsToken("}"):
+if not self._IsToken(T_CHAR_BRACE_R):
 raise Warning.ExpectedCurlyClose(self.FileName, 
self.CurrentLineNumber)
 
 DataString = DataString.rstrip(TAB_COMMA_SPLIT)
@@ -2346,7 +2347,7 @@ class FdfParser:
 
 FvObj.FvExtEntryData.append(self._Token)
 
-if not self._IsToken("}"):
+if not self._IsToken(T_CHAR_BRACE_R):
 raise Warning.ExpectedCurlyClose(self.FileName, 
self.CurrentLineNumber)
 
 return True
@@ -2382,7 +2383,7 @@ class FdfParser:
 if not IsInf and not IsFile:
 break
 
-if not self._IsToken("}"):
+if not self._IsToken(T_CHAR_BRACE_R):
 raise Warning.ExpectedCurlyClose(self.FileName, 
self.CurrentLineNumber)
 
 FvObj.AprioriSectionList.append(AprSectionObj)
@@ -2657,7 +2658,7 @@ class FdfParser:
 FfsFileObj.FileName = self._Token.replace('$(SPACE)', ' ')
 self._VerifyFile(FfsFileObj.FileName)
 
-if not self._IsToken("}"):
+if not self._IsToken(T_CHAR_BRACE_R):
 raise Warning.ExpectedCurlyClose(self.FileName, 
self.CurrentLineNumber)
 
 ## _GetRAWData() method
@@ -2682,7 +2683,7 @@ class FdfParser:
 raise Warning.Expected("Filename value", self.FileName, 
self.CurrentLineNumber)
 
 FileName = self._Token.replace('$(SPACE)', ' ')
-if FileName == '}':
+if FileName == T_CHAR_BRACE_R:
 self._UndoToken()
 raise Warning.Expected("Filename value", self.FileName, 
self.CurrentLineNumber)
 
@@ -2691,7 +2692,7 @@ class FdfParser:
 FfsFileObj.FileName.append(File.Path)
 FfsFileObj.SubAlignment.append(AlignValue)
 
-if self._IsToken("}"):
+if self._IsToken(T_CHAR_BRACE_R):
 self._UndoToken()
 break
 
@@ -2863,7 +2864,7 @@ class FdfParser:
 if not IsInf and not IsFile:
 break
 
-if not self._IsToken("}"):
+if not self._IsToken(T_CHAR_BRACE_R):
 raise Warning.ExpectedCurlyClose(self.FileName, 
self.CurrentLineNumber)
 
 FvImageSectionObj = FvImageSection()
@@ -2888,10 +2889,10 @@ class FdfParser:
 raise Warning.ExpectedEquals(self.FileName, 
self.CurrentLineNumber)
 if not self._IsToken("{"):
 raise Warning.ExpectedCurlyOpen(self.FileName, 
self.CurrentLineNumber)
-if not self._SkipToToken("}"):
+if not self._SkipToToken(T_CHAR_BRACE_R):
 raise Warning.Expected("Depex expression ending '}'", 
self.FileName, self.CurrentLineNumber)
 
-DepexSectionObj.Expression = 

[edk2] [PATCH v1 3/7] Basetools/GenFds: refactor class FV

[Jaben Carsey]

1) initialize UiFvName via __init__ parameter. No change to default behavior.
2) initialize 3 empty lists in __init__. Curently not guarenteed initialized.

Cc: Yonghong Zhu 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jaben Carsey 
---
 BaseTools/Source/Python/GenFds/FdfParser.py | 6 +-
 BaseTools/Source/Python/GenFds/Fv.py| 9 +
 2 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/BaseTools/Source/Python/GenFds/FdfParser.py 
b/BaseTools/Source/Python/GenFds/FdfParser.py
index f99bb6215115..ff2efd8d7a57 100644
--- a/BaseTools/Source/Python/GenFds/FdfParser.py
+++ b/BaseTools/Source/Python/GenFds/FdfParser.py
@@ -2089,8 +2089,7 @@ class FdfParser:
 if not self._IsToken(TAB_SECTION_END):
 raise Warning("expected ']'", self.FileName, 
self.CurrentLineNumber)
 
-FvObj = FV()
-FvObj.UiFvName = self.CurrentFvName
+FvObj = FV(Name=self.CurrentFvName)
 self.Profile.FvDict[self.CurrentFvName] = FvObj
 
 Status = self._GetCreateFile(FvObj)
@@ -2101,9 +2100,6 @@ class FdfParser:
 
 self._GetAddressStatements(FvObj)
 
-FvObj.FvExtEntryTypeValue = []
-FvObj.FvExtEntryType = []
-FvObj.FvExtEntryData = []
 while True:
 self._GetSetStatements(FvObj)
 
diff --git a/BaseTools/Source/Python/GenFds/Fv.py 
b/BaseTools/Source/Python/GenFds/Fv.py
index acb133573d72..cd19dff6c325 100644
--- a/BaseTools/Source/Python/GenFds/Fv.py
+++ b/BaseTools/Source/Python/GenFds/Fv.py
@@ -37,8 +37,8 @@ class FV (object):
 #
 #   @param  selfThe object pointer
 #
-def __init__(self):
-self.UiFvName = None
+def __init__(self, Name=None):
+self.UiFvName = Name
 self.CreateFileName = None
 self.BlockSizeList = []
 self.DefineVarDict = {}
@@ -61,7 +61,9 @@ class FV (object):
 self.FvForceRebase = None
 self.FvRegionInFD = None
 self.UsedSizeEnable = False
-
+self.FvExtEntryTypeValue = []
+self.FvExtEntryType = []
+self.FvExtEntryData = []
 ## AddToBuffer()
 #
 #   Generate Fv and add it to the Buffer
@@ -77,7 +79,6 @@ class FV (object):
 #   @retval string  Generated FV file path
 #
 def AddToBuffer (self, Buffer, BaseAddress=None, BlockSize= None, 
BlockNum=None, ErasePloarity='1', VtfDict=None, MacroDict = {}, Flag=False):
-
 if BaseAddress is None and self.UiFvName.upper() + 'fv' in 
GenFdsGlobalVariable.ImageBinDict:
 return GenFdsGlobalVariable.ImageBinDict[self.UiFvName.upper() + 
'fv']
 
-- 
2.16.2.windows.1

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[edk2] [PATCH v1 0/7] BaseTools/GenFds: cleanup GenFds

[Jaben Carsey]

Cleanup to many files for GenFds. No command line visible changes are included.
1) refactor imports to reduce namespace clutter.
2) refactor to use existing sharable objects (and create a few new)
3) eliminate shadowing of names
4) remove double underscored private methods for PEP8
5) eliminate unused code/parameters/variables
6) add standard warnings and use them for common code

Jaben Carsey (7):
  BaseTools/GenFds: cleanup GenFds
  BaseTools/GenFds: change objects to sets
  Basetools/GenFds: refactor class FV
  BaseTools/GenFds: remove MacroDict parameter
  BaseTools/GenFds: refactor FdfParser warnings
  BaseTools/GenFds: Remove duplicate function calls
  BaseTools/GenFds: create and use new variable in FdfParser

 BaseTools/Source/Python/CommonDataClass/FdfClass.py|   73 -
 BaseTools/Source/Python/Eot/Eot.py |   11 +-
 BaseTools/Source/Python/GenFds/AprioriSection.py   |   45 +-
 BaseTools/Source/Python/GenFds/Capsule.py  |   26 +-
 BaseTools/Source/Python/GenFds/CapsuleData.py  |1 -
 BaseTools/Source/Python/GenFds/CompressSection.py  |4 +-
 BaseTools/Source/Python/GenFds/DataSection.py  |4 +-
 BaseTools/Source/Python/GenFds/DepexSection.py |5 +-
 BaseTools/Source/Python/GenFds/EfiSection.py   |   16 +-
 BaseTools/Source/Python/GenFds/FdfParser.py| 3748 
++--
 BaseTools/Source/Python/GenFds/Ffs.py  |   82 +-
 BaseTools/Source/Python/GenFds/FfsFileStatement.py |   37 +-
 BaseTools/Source/Python/GenFds/FfsInfStatement.py  |   10 +-
 BaseTools/Source/Python/GenFds/Fv.py   |   54 +-
 BaseTools/Source/Python/GenFds/FvImageSection.py   |6 +-
 BaseTools/Source/Python/GenFds/GenFds.py   |  160 +-
 BaseTools/Source/Python/GenFds/GenFdsGlobalVariable.py |  208 +-
 BaseTools/Source/Python/GenFds/GuidSection.py  |4 +-
 BaseTools/Source/Python/GenFds/OptionRom.py|6 +-
 BaseTools/Source/Python/GenFds/Region.py   |   12 +-
 BaseTools/Source/Python/GenFds/UiSection.py|4 +-
 BaseTools/Source/Python/GenFds/VerSection.py   |   16 +-
 BaseTools/Source/Python/GenFds/Vtf.py  |   48 +-
 BaseTools/Source/Python/build/BuildReport.py   |5 +-
 24 files changed, 2196 insertions(+), 2389 deletions(-)

-- 
2.16.2.windows.1

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[edk2] [PATCH v1 6/7] BaseTools/GenFds: Remove duplicate function calls

[Jaben Carsey]

every call to GetAprioriSection() is duplicated on the line below.
remove one of the calls.

Cc: Bob Feng 
Cc: Yonghong Zhu 
Cc: Liming Gao 
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jaben Carsey 
---
 BaseTools/Source/Python/GenFds/FdfParser.py | 2 --
 1 file changed, 2 deletions(-)

diff --git a/BaseTools/Source/Python/GenFds/FdfParser.py 
b/BaseTools/Source/Python/GenFds/FdfParser.py
index 821b3edb7592..f6b79764b2a0 100644
--- a/BaseTools/Source/Python/GenFds/FdfParser.py
+++ b/BaseTools/Source/Python/GenFds/FdfParser.py
@@ -2121,7 +2121,6 @@ class FdfParser:
 raise Warning("FvNameString found but FvNameGuid was not found", 
self.FileName, self.CurrentLineNumber)
 
 self._GetAprioriSection(FvObj)
-self._GetAprioriSection(FvObj)
 
 while True:
 isInf = self._GetInfStatement(FvObj)
@@ -3780,7 +3779,6 @@ class FdfParser:
 self._GetFvAlignment(FvObj)
 self._GetFvAttributes(FvObj)
 self._GetAprioriSection(FvObj)
-self._GetAprioriSection(FvObj)
 
 while True:
 IsInf = self._GetInfStatement(FvObj)
-- 
2.16.2.windows.1

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Re: [edk2] Minimum tianocore payload

[Kinney, Michael D]

One example is Quark:

  https://github.com/tianocore/edk2/tree/master/QuarkPlatformPkg

It has both a minimum and a full example:

  https://github.com/tianocore/edk2/blob/master/QuarkPlatformPkg/QuarkMin.dsc
  https://github.com/tianocore/edk2/blob/master/QuarkPlatformPkg/QuarkMin.fdf

  https://github.com/tianocore/edk2/blob/master/QuarkPlatformPkg/Quark.dsc
  https://github.com/tianocore/edk2/blob/master/QuarkPlatformPkg/Quark.fdf

The min profiles uses a UART as a console and only supports booting from
FLASH.  It does have a few additional features that could be removed related
to menus and configuration, but at least a good example to study.

Mike

> -Original Message-
> From: edk2-devel [mailto:edk2-devel-
> boun...@lists.01.org] On Behalf Of Jorge Fernandez
> Monteagudo
> Sent: Monday, September 24, 2018 3:41 AM
> To: edk2-devel@lists.01.org
> Subject: [edk2] Minimum tianocore payload
> 
> Hi all,
> 
> 
> Is there any example how to reduce the components
> needed in the tianocore payload
> 
> to get a minimum payload? I'm thinking in a payload
> without console, menu, no configurable
> 
> to be used in an embedded system...
> 
> 
> Thanks!
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[edk2] [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Shift EEPROM PEI files

[Steele, Kelly]

>From 1ae6e8934e17e0a0d20d169551d852cf3e8a1227 Mon Sep 17 00:00:00 2001
From: Kelly Steele 
Date: Fri, 21 Sep 2018 11:14:02 -0700
Subject: [PATCH] [edk2-platforms/devel-IntelAtomProcessorE3900] Shift EEPROM
PEI files

Shifted the EEPROM PEI files into their own folders to help organize the
code better.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Kelly Steele 
---
.../EepromBinary/Docs/HowtoCreateTheEepromBinary.pdf   | Bin 307112 -> 0 bytes
.../Eeprom/EepromDataLib/EEPROM/{ => Pei}/HobDataPei.c |   0
.../Features/Eeprom/EepromDataLib/EepromDataLib.inf|   1 +
.../Features/Eeprom/EepromDataLib/EepromDataPeiLib.inf |   9 +
...promDataNullPeiLib.inf => EepromDataPeiNullLib.inf} |   2 +-
.../Eeprom/EepromDataLib/FV/{ => Pei}/GetImagePei.c|   0
.../Eeprom/EepromDataLib/Memory/{ => Pei}/HobDataPei.c |   0
.../EepromDataLib/{ => Pei}/MemoryAllocationPei.c  |   2 ++
.../PlatformDsc/PcdsFixedAtBuild.dsc   |  16 
9 files changed, 21 insertions(+), 9 deletions(-)
delete mode 100644 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromBinary/Docs/HowtoCreateTheEepromBinary.pdf
rename 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EEPROM/{ => 
Pei}/HobDataPei.c (100%)
rename 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/{EepromDataNullPeiLib.inf
 => EepromDataPeiNullLib.inf} (94%)
rename Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/FV/{ => 
Pei}/GetImagePei.c (100%)
rename 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/Memory/{ => 
Pei}/HobDataPei.c (100%)
rename Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/{ => 
Pei}/MemoryAllocationPei.c (95%)

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromBinary/Docs/HowtoCreateTheEepromBinary.pdf
 
b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromBinary/Docs/HowtoCreateTheEepromBinary.pdf
deleted file mode 100644
index 
84f6e594539fb8224493acd57ee41207cf0bee5e..

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EEPROM/HobDataPei.c
 
b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EEPROM/Pei/HobDataPei.c
similarity index 100%
rename from 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EEPROM/HobDataPei.c
rename to 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EEPROM/Pei/HobDataPei.c
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataLib.inf
 
b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataLib.inf
index 0ce2aaf9a6..a88d8fd1df 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataLib.inf
+++ 
b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataLib.inf
@@ -34,6 +34,7 @@
   DebugLib
   EepromPlatformLib
   HobLib
+  I2cLib
   MemoryAllocationLib
   PcdLib
   PrintLib
diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataPeiLib.inf
 
b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataPeiLib.inf
index de14765a7b..9d7462194d 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataPeiLib.inf
+++ 
b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataPeiLib.inf
@@ -34,6 +34,7 @@
   DebugLib
   EepromPlatformLib
   HobLib
+  I2cLib
   PcdLib
   PeiServicesLib
   PrintLib
@@ -57,16 +58,16 @@
   EepromDataLib.c
   EepromDataLib.h
   EepromDataLibConstructor.c
-  MemoryAllocationPei.c
   EEPROM/EepromDataEepromLib.c
   EEPROM/EepromDataEepromLib.h
-  EEPROM/HobDataPei.c
+  EEPROM/Pei/HobDataPei.c
   FV/EepromDataFvLib.c
   FV/EepromDataFvLib.h
-  FV/GetImagePei.c
+  FV/Pei/GetImagePei.c
   Memory/EepromDataMemoryLib.c
   Memory/EepromDataMemoryLib.h
-  Memory/HobDataPei.c
+  Memory/Pei/HobDataPei.c
   Null/EepromDataNullLib.c
   Null/EepromDataNullLib.h
+  Pei/MemoryAllocationPei.c

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataNullPeiLib.inf
 
b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataPeiNullLib.inf
similarity index 94%
rename from 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataNullPeiLib.inf
rename to 
Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataPeiNullLib.inf
index 456d75dbb0..48e2b8f5ea 100644
--- 
a/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataNullPeiLib.inf
+++ 
b/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/EepromDataPeiNullLib.inf
@@ -40,7 +40,7 @@
   EepromDataLib.c
   EepromDataLib.h
   EepromDataNullLibConstructor.c
-  MemoryAllocationPei.c
   Null/EepromDataNullLib.c
   Null/EepromDataNullLib.h
+  Pei/MemoryAllocationPei.c

diff --git 
a/Platform/BroxtonPlatformPkg/Common/Features/Eeprom/EepromDataLib/FV/GetImagePei.c
 

Re: [edk2] [PATCH 3/3] MdeModulePkg/PciHostBridge: Add RESOURCE_VALID() to simplify code

[Kirkendall, Garrett]

GARRETT KIRKENDALL
SMTS Firmware Engineer | CTE
7171 Southwest Parkway, Austin, TX 78735 USA 
AMD   facebook  |  amd.com

-Original Message-
From: edk2-devel  On Behalf Of Ruiyu Ni
Sent: Friday, September 21, 2018 2:26 AM
To: edk2-devel@lists.01.org
Cc: Star Zeng 
Subject: [edk2] [PATCH 3/3] MdeModulePkg/PciHostBridge: Add RESOURCE_VALID() to 
simplify code

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Star Zeng 
---
 .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 26 ++
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index f6234b5d11..916709e276 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -21,6 +21,8 @@ extern EDKII_IOMMU_PROTOCOL*mIoMmuProtocol;
 
 #define NO_MAPPING  (VOID *) (UINTN) -1
 
+#define RESOURCE_VALID(R) ((R).Base <= (R).Limit)
+
 //
 // Lookup table for increment values based on transfer widths  // @@ -122,25 
+124,25 @@ CreateRootBridge (
   //
   // Make sure Mem and MemAbove4G apertures are valid
   //
-  if (Bridge->Mem.Base <= Bridge->Mem.Limit) {
+  if (RESOURCE_VALID (Bridge->Mem)) {
 ASSERT (Bridge->Mem.Limit < SIZE_4GB);
 if (Bridge->Mem.Limit >= SIZE_4GB) {
   return NULL;
 }
   }
-  if (Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) {
+  if (RESOURCE_VALID (Bridge->MemAbove4G)) {
 ASSERT (Bridge->MemAbove4G.Base >= SIZE_4GB);
 if (Bridge->MemAbove4G.Base < SIZE_4GB) {
   return NULL;
 }
   }
-  if (Bridge->PMem.Base <= Bridge->PMem.Limit) {
+  if (RESOURCE_VALID (Bridge->PMem)) {
 ASSERT (Bridge->PMem.Limit < SIZE_4GB);
 if (Bridge->PMem.Limit >= SIZE_4GB) {
   return NULL;
 }
   }
-  if (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit) {
+  if (RESOURCE_VALID (Bridge->PMemAbove4G)) {
 ASSERT (Bridge->PMemAbove4G.Base >= SIZE_4GB);
 if (Bridge->PMemAbove4G.Base < SIZE_4GB) {
   return NULL;
@@ -157,11 +159,9 @@ CreateRootBridge (
   // support separate windows for Non-prefetchable and Prefetchable
   // memory.
   //
-  ASSERT (Bridge->PMem.Base > Bridge->PMem.Limit);
-  ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
-  if ((Bridge->PMem.Base <= Bridge->PMem.Limit) ||
-  (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
-  ) {
+  ASSERT (!RESOURCE_VALID (Bridge->PMem));
+  ASSERT (!RESOURCE_VALID (Bridge->PMemAbove4G));
+  if (RESOURCE_VALID (Bridge->PMem) || RESOURCE_VALID 
+ (Bridge->PMemAbove4G)) {
 return NULL;
   }
 }
@@ -171,11 +171,9 @@ CreateRootBridge (
   // If this bit is not set, then the PCI Root Bridge does not support
   // 64 bit memory windows.
   //
-  ASSERT (Bridge->MemAbove4G.Base > Bridge->MemAbove4G.Limit);
-  ASSERT (Bridge->PMemAbove4G.Base > Bridge->PMemAbove4G.Limit);
-  if ((Bridge->MemAbove4G.Base <= Bridge->MemAbove4G.Limit) ||
-  (Bridge->PMemAbove4G.Base <= Bridge->PMemAbove4G.Limit)
-  ) {
+  ASSERT (!RESOURCE_VALID (Bridge->MemAbove4G));
+  ASSERT (!RESOURCE_VALID (Bridge->PMemAbove4G));
+  if (RESOURCE_VALID (Bridge->MemAbove4G) || RESOURCE_VALID 
+ (Bridge->PMemAbove4G)) {
 return NULL;
   }
 }
--
2.16.1.windows.1

With Laszlo's comments
Reviewed-by: Garrett Kirkendall 
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Re: [edk2] [PATCH 2/3] MdeModulePkg/PciHostBridge: Fix a bug that prevents PMEM access

[Kirkendall, Garrett]

GARRETT KIRKENDALL
SMTS Firmware Engineer | CTE
7171 Southwest Parkway, Austin, TX 78735 USA 
AMD   facebook  |  amd.com

-Original Message-
From: Ruiyu Ni  
Sent: Friday, September 21, 2018 2:26 AM
To: edk2-devel@lists.01.org
Cc: Star Zeng ; Kirkendall; Kirkendall, Garrett 

Subject: [PATCH 2/3] MdeModulePkg/PciHostBridge: Fix a bug that prevents PMEM 
access

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1196

RootBridgeIoCheckParameter() verifies that the requested MMIO access can fit in 
any of the MEM/PMEM 32/64 ranges. But today's logic somehow only checks the 
requested access against MEM 32/64 ranges.

It should also check the requested access against PMEM 32/64 ranges.

The patch fixes this issue.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Star Zeng 
Cc: Kirkendall, Garrett 
---
 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index 0b6b56f846..f6234b5d11 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -411,12 +411,18 @@ RootBridgeIoCheckParameter (
 // By comparing the Address against Limit we know which range to be used
 // for checking
 //
-if (Address + Length <= RootBridge->Mem.Limit + 1) {
-  Base = RootBridge->Mem.Base;
+if ((Address >= RootBridge->Mem.Base) && (Address + Length <= 
RootBridge->Mem.Limit + 1)) {
+  Base  = RootBridge->Mem.Base;
   Limit = RootBridge->Mem.Limit;
-} else {
-  Base = RootBridge->MemAbove4G.Base;
+} else if ((Address >= RootBridge->PMem.Base) && (Address + Length <= 
RootBridge->PMem.Limit + 1)) {
+  Base  = RootBridge->PMem.Base;
+  Limit = RootBridge->PMem.Limit;
+} else if ((Address >= RootBridge->MemAbove4G.Base) && (Address + Length 
<= RootBridge->MemAbove4G.Limit + 1)) {
+  Base  = RootBridge->MemAbove4G.Base;
   Limit = RootBridge->MemAbove4G.Limit;
+} else {
+  Base  = RootBridge->PMemAbove4G.Base;
+  Limit = RootBridge->PMemAbove4G.Limit;
 }
   } else {
 PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) 
--
2.16.1.windows.1

Reviewed-by: Garrett Kirkendall 
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Re: [edk2] [PATCH 1/3] MdeModulePkg/PciHostBridge: Enhance boundary check in Io/Mem.Read/Write

[Kirkendall, Garrett]

GARRETT KIRKENDALL
SMTS Firmware Engineer | CTE
7171 Southwest Parkway, Austin, TX 78735 USA 
AMD   facebook  |  amd.com

-Original Message-
From: edk2-devel  On Behalf Of Ruiyu Ni
Sent: Friday, September 21, 2018 2:26 AM
To: edk2-devel@lists.01.org
Cc: Star Zeng 
Subject: [edk2] [PATCH 1/3] MdeModulePkg/PciHostBridge: Enhance boundary check 
in Io/Mem.Read/Write

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni 
Cc: Star Zeng 
---
 .../Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 26 +-
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c 
b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
index f8a1239ceb..0b6b56f846 100644
--- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -321,6 +321,7 @@ RootBridgeIoCheckParameter (
   UINT64   Base;
   UINT64   Limit;
   UINT32   Size;
+  UINT64   Length;
 
   //
   // Check to see if Buffer is NULL
@@ -337,7 +338,7 @@ RootBridgeIoCheckParameter (
   }
 
   //
-  // For FIFO type, the target address won't increase during the access,
+  // For FIFO type, the device address won't increase during the 
+ access,
   // so treat Count as 1
   //
   if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) { @@ 
-347,6 +348,13 @@ RootBridgeIoCheckParameter (
   Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
   Size  = 1 << Width;
 
+  //
+  // Make sure (Count * Size) doesn't exceed MAX_UINT64  //  if (Count 
+ > DivU64x32 (MAX_UINT64, Size)) {
+return EFI_INVALID_PARAMETER;
+  }
+
   //
   // Check to see if Address is aligned
   //
@@ -354,6 +362,14 @@ RootBridgeIoCheckParameter (
 return EFI_UNSUPPORTED;
   }
 
+  //
+  // Make sure (Address + Count * Size) doesn't exceed MAX_UINT64  //  
+ Length = MultU64x32 (Count, Size);  if (Address > MAX_UINT64 - Length) 
+ {
+return EFI_INVALID_PARAMETER;
+  }
+
   RootBridge = ROOT_BRIDGE_FROM_THIS (This);
 
   //
@@ -372,7 +388,7 @@ RootBridgeIoCheckParameter (
 //
 // Allow Legacy IO access
 //
-if (Address + MultU64x32 (Count, Size) <= 0x1000) {
+if (Address + Length <= 0x1000) {
   if ((RootBridge->Attributes & (
EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | 
EFI_PCI_ATTRIBUTE_VGA_IO |
EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | 
EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | @@ -386,7 +402,7 @@ 
RootBridgeIoCheckParameter (
 //
 // Allow Legacy MMIO access
 //
-if ((Address >= 0xA) && (Address + MultU64x32 (Count, Size)) <= 
0xC) {
+if ((Address >= 0xA) && (Address + Length) <= 0xC) {
   if ((RootBridge->Attributes & EFI_PCI_ATTRIBUTE_VGA_MEMORY) != 0) {
 return EFI_SUCCESS;
   }
@@ -395,7 +411,7 @@ RootBridgeIoCheckParameter (
 // By comparing the Address against Limit we know which range to be used
 // for checking
 //
-if (Address + MultU64x32 (Count, Size) <= RootBridge->Mem.Limit + 1) {
+if (Address + Length <= RootBridge->Mem.Limit + 1) {
   Base = RootBridge->Mem.Base;
   Limit = RootBridge->Mem.Limit;
 } else {
@@ -427,7 +443,7 @@ RootBridgeIoCheckParameter (
   return EFI_INVALID_PARAMETER;
   }
 
-  if (Address + MultU64x32 (Count, Size) > Limit + 1) {
+  if (Address + Length > Limit + 1) {
 return EFI_INVALID_PARAMETER;
   }
 
--
2.16.1.windows.1

Reviewed-by: Garrett Kirkendall 
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[edk2] Minimum tianocore payload

[Jorge Fernandez Monteagudo]

Hi all,


Is there any example how to reduce the components needed in the tianocore 
payload

to get a minimum payload? I'm thinking in a payload without console, menu, no 
configurable

to be used in an embedded system...


Thanks!
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[edk2] Tianocore and TPM2 pcr values

[Jorge Fernandez Monteagudo]

Hi all,


This is my first message in this list. I'm using tianocore as a payload for a 
Coreboot in order to

boot a custom board I'm working on it. Finally I've been able to enable the 
TPM2 support in

coreboot and in tianocore but I have some questions regarding the values I'm 
seeing in the PCRs.


I'm using Tianocore master branch as is selected by coreboot menuconfig and x64 
architecture.

Once the system is running I can read the PCRs and, if I'm not wrong, PCRs 0 to 
7 are handled

by the Tianocore/Coreboot. I've flashed a coreboot+tianocore in release mode 
and a coreboot+

tianocore in debug mode and the PCRs are the same. Is it ok? I thought that any 
change in the

coreboot.rom will made the PCR values to change...


pcr0: 3d458cfe55cc03ea1f443f1562beec8df51c75e14a9fcf9a7234a13f198e7969
pcr1: a3a3552caa68c6d9db64bf1ed4dca08080f99b59f1b26debc9abefa59ee8ca28
pcr2: 3d458cfe55cc03ea1f443f1562beec8df51c75e14a9fcf9a7234a13f198e7969
pcr3: 3d458cfe55cc03ea1f443f1562beec8df51c75e14a9fcf9a7234a13f198e7969
pcr4: 74a35102770e65ab94b35135a4bf54c411134ae8059e03df41060a33f573871f
pcr5: dfa65561584cb8604b1675c869f3341d0c99c642ce9d91353380361126235ad8
pcr6: 3d458cfe55cc03ea1f443f1562beec8df51c75e14a9fcf9a7234a13f198e7969
pcr7: b5710bf57d25623e4019027da116821fa99f5c81e9e38b87671cc574f9281439

Another test I've done is using the Tianocore stable branch as selected by 
coreboot
(STABLE_COMMIT_ID=315d9d08fd77db1024ccc5307823da8aaed85e2f) and I get the
same values from release and build coreboot.roms except that PCR1 has the same 
value
as PCR0, 2, 3 and 6, it seems it's not used in this version.

Is this the expected behavior?

Thanks!
Jorge
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Re: [edk2] [PATCH v2 1/2] MdePkg/IndustryStandard: Add Global Plaform header file

[Ard Biesheuvel]

On Sat, 22 Sep 2018 at 01:15, Ard Biesheuvel  wrote:
>
> On 27 August 2018 at 04:50, Sumit Garg  wrote:
> > Add Global Plaform header file specific to TEE Client API Specification v1
> > .
> >
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > Cc: Ard Biesheuvel 
> > Cc: Leif Lindholm 
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Sumit Garg 
>
> Acked-by: Ard Biesheuvel 
>
> Mike,
>
> The header file is a bit light on content at introduction, but as
> discussed online, we can add stuff as we go for other use cases.
>

... as discussed *offline*

>
> > ---
> >  MdePkg/Include/IndustryStandard/GlobalPlatform.h | 27 
> > 
> >  1 file changed, 27 insertions(+)
> >  create mode 100644 MdePkg/Include/IndustryStandard/GlobalPlatform.h
> >
> > diff --git a/MdePkg/Include/IndustryStandard/GlobalPlatform.h 
> > b/MdePkg/Include/IndustryStandard/GlobalPlatform.h
> > new file mode 100644
> > index ..72c5af4ef588
> > --- /dev/null
> > +++ b/MdePkg/Include/IndustryStandard/GlobalPlatform.h
> > @@ -0,0 +1,27 @@
> > +/** @file
> > +  Standardized Global Platform header file. GlobalPlatform TEE Client API
> > +  Specification v1.0: 
> > 
> > +
> > +  Copyright (c) 2018, Linaro Ltd. All rights reserved.
> > +
> > +  This program and the accompanying materials
> > +  are licensed and made available under the terms and conditions of the 
> > BSD License
> > +  which accompanies this distribution.  The full text of the license may 
> > be found at
> > +  http://opensource.org/licenses/bsd-license.php
> > +
> > +  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> > +  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
> > IMPLIED.
> > +
> > +**/
> > +
> > +#ifndef _GLOBAL_PLATFORM_H_
> > +#define _GLOBAL_PLATFORM_H_
> > +
> > +#define TEEC_ORIGIN_COMMS   0x0002
> > +
> > +#define TEEC_SUCCESS0x
> > +#define TEEC_ERROR_BAD_PARAMETERS   0x0006
> > +#define TEEC_ERROR_OUT_OF_MEMORY0x000C
> > +#define TEEC_ERROR_COMMUNICATION0x000E
> > +
> > +#endif
> > --
> > 2.7.4
> >
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