Re: grounding schemes EMI
Hi Dave, I've had this type of discussion at a previous telco company and the only explanation I ever received regarded ground potential differences between equipment through the mains (as we have discussed in a previous thread). And I always seemed to win by saying that if everything was chassis grounded, then that would be the path of least resistance anyway. At this other company, we shifted from isolated grounds to everything grounded to the chassis and I never saw any of the problems the designers said would happen. In fact, immunity robustness increased. I'll admit that this was with a limited number of products. And I'm sure others here may have different exeperiences. Regards, Doug McKean --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list
Re: grounding schemes EMI
Hi David (and the group), Take a look at the Technical Tidbits section of my site at http://emcesd.com where you will find some experimental evidence for your viewpoint. This month's article (at the bottom of the main page) presents some data and links to two other articles. Doug On Friday, Oct 11, 2002, at 12:53 US/Pacific, David Heald wrote: All, I'm trying to convince a few people here that completely separating the digital and chassis grounding on our product is not always the best way to go. Unfortunately, a lot of the people I'm dealing with are ex Bellcore engineers who worked a lot with isolated grounds and are convinced that isolated grounds are the only way to go. Now we're dealing with optical interfaces and speeds well in excess of 100MHz, so I really want to see the grounds tied together as much as possible. While I know that combining the digital and chassis grounds is for the most part better once you get above a few hundred MHz, putting together concrete arguments is proving to be a bit elusive. I luckily have some high level backing that will let me push my views, but I am one person up against a team of industry vets. If anyone has been in this boat before and won, could you share some of the tactics or arguments that you used? I know this issue has been discussed in the past, but a fresh discussion of the relative benefits of isolating the D and Cgnds would probably be beneficial to the group as well. See below for my views on the issue. Thanks Dave My views for telecom equipment with a backplane and plug in circuit packs (and a good tight chassis around it all): (Note that Analog grounds are outside of the scope of this statement - I'm focusing on Digital grounds and Chassis ground) The benefits of separating Dgnd and Cgnd have to do with defining your signal impedances and SI in general. When you place this system inside a Cgnd balloon, all should be well but maybe there is some extra noise due to RF being trapped within the balloon. However, if the Cgnd and Dgnd are tied together throughout the system, the effect should be similar to heat shrinking your conductive chassis Cgnd ballon onto your Dgnd. The single ended signal return currents should still follow their original paths and things should essentially remain unchanged. I could see some possibility (I'll avoid use of the word potential here :o) ) for RF currents on the circuit pack card grounds due to RF fields contained within the faraday cage, but I think these could be mitigated by clever bonding of the grounds on circuit packs. I think that isolating the faceplate from the Dgnd on the circuit packs but stitching the bottom edge (faceplate to backplane) Cgnd ESD guard band to Dgnd could alleviate stray currents on the cards and keep them relatively clean - all while still maintaining the bonding of the Cgnd and Dgnd on a system level. The idea (as my brain developed it) is to keep the stray currents at the periphery of the card by limiting the through connections on the circuit packs and forcing stray currents to flow near the edge of the card. The backplane should for the most part have Dgnd and Cgnd be one and the same. Does this raise any red flags for anyone? I'm expecting at least a few, but this is the best scheme that I can come up with right now. --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list ___ _Doug Smith \ / ) P.O. Box 1457 = Los Gatos, CA 95031-1457 _ / \ / \ _TEL/FAX: 408-356-4186/358-3799 / /\ \ ] / /\ \ Mobile: 408-858-4528 | q-( ) | o | Email: d...@dsmith.org \ _ /]\ _ / Web: http://www.dsmith.org --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list
Re: grounding schemes EMI
David, Telecom (Bellcore) usage is to keep signal, surge and power currents off chassis and safety grounds. This is understandable. It is due not only to audio sensitivity, but to the need to protect equipment from substantial peak (hundred of amps) surges at fairly high (thousands of volts) peak voltage. Practically speaking, if you isolate a ground, you must isolate all the signal and return conductors referenced to it as well. It requires good balance in signal and return conductors, and measures to sure that balance is not disturbed. This takes meticulous design, and some expense in manufacturing. I have seen this done with signals in the hundreds of MHz, but care had to be taken in layout, connector and cable selection and construction. Surge protector current must be routed away from signal return current. If the chassis of a device is connected to the surge return path, a surge on metallic conductors will be present on the chassis of the protected device. This may be of little consequence to the device, where all grounds and Vcc rise to the surge potential at once. But if it connects to another equipment whose chassis ground is different, a sizable potential can appear between signal conductors from the surged device and client equipment not sharing its ground. That is not a good thing! At sufficiently high frequencies there is no ground at all, really, only return paths of various shapes, lengths and impedance. We can then make the argument that - as long as we don't have to deal with surge currents -- our chassis and digital grounds be tied together. This simplifies shielding. But we still have to deal with surge somehow, and now, I suggest, we can say that the SURGE return should be isolated, not the digital ground. Higher frequency ESD transients are more problematic. Grounding circuit-pack faceplates only at the bottom is NOT helpful! Connecting them to the board ground is BAD. Before being laid off, I was slowly converting people to the idea that ESD currents need to be treated as UHF radio energy, and shields constructed accordingly; faceplates with 360 degree grounds to the chassis. In some cases, it is enough to provide paths to the chassis before such currents can flow onto the board, but induced fields are often troublesome. For sure, ESD must NOT be allowed into circuit pack Vcc and ground. An ESD trace or guard band is often used, but this can be unnecessary -- why parallel a metal panel with a trace? -- or insufficient; a guard band NOT connected to chassis, as when a card is being inserted, may actually couple an ESD event to places where it can do harm. Anyway, when it IS inserted, you can't reach it, so why have it? And a trace leading ESD to the backplane puts it exactly -- among all the nice clean signals -- where you do NOT want it! (I've also seen an encircling trace resonate and cause EMC problems.) My approach is very simple: Where will current go, and what will it do? If you use this approach, you will find others coming over to your point of view, especially when you are once in a while spectacularly right. Cortland --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list
Re: grounding schemes EMI
A good way to think about this, especially on a larger size board, is to imagine a transmission line resonator. Assume for the moment that the shielding enclosure and the board ground are tied together at one point. In this case, the board will go resonant when the length of the board ground measured from the tie point becomes 1/4 of a wavelenth. This is not that long of a distance at even a low order harmonics of 100 MHz. All kinds of nasty things happen with such a resonance, the worst being radiated/conducted emissions, though circuit operation of sensitive nodes can be affected as well. Don Borowski Schweitzer Engineering Labs Pullman, WA David Heald dhe...@tellium.com on 10/11/2002 12:53:27 PM Please respond to David Heald dhe...@tellium.com To: 'emc-p...@majordomo.ieee.org' emc-p...@majordomo.ieee.org cc:(bcc: Don Borowski/SEL) Subject: grounding schemes EMI All, I'm trying to convince a few people here that completely separating the digital and chassis grounding on our product is not always the best way to go. Unfortunately, a lot of the people I'm dealing with are ex Bellcore engineers who worked a lot with isolated grounds and are convinced that isolated grounds are the only way to go. Now we're dealing with optical interfaces and speeds well in excess of 100MHz, so I really want to see the grounds tied together as much as possible. While I know that combining the digital and chassis grounds is for the most part better once you get above a few hundred MHz, putting together concrete arguments is proving to be a bit elusive. I luckily have some high level backing that will let me push my views, but I am one person up against a team of industry vets. If anyone has been in this boat before and won, could you share some of the tactics or arguments that you used? I know this issue has been discussed in the past, but a fresh discussion of the relative benefits of isolating the D and Cgnds would probably be beneficial to the group as well. See below for my views on the issue. Thanks Dave My views for telecom equipment with a backplane and plug in circuit packs (and a good tight chassis around it all): (Note that Analog grounds are outside of the scope of this statement - I'm focusing on Digital grounds and Chassis ground) The benefits of separating Dgnd and Cgnd have to do with defining your signal impedances and SI in general. When you place this system inside a Cgnd balloon, all should be well but maybe there is some extra noise due to RF being trapped within the balloon. However, if the Cgnd and Dgnd are tied together throughout the system, the effect should be similar to heat shrinking your conductive chassis Cgnd ballon onto your Dgnd. The single ended signal return currents should still follow their original paths and things should essentially remain unchanged. I could see some possibility (I'll avoid use of the word potential here :o) ) for RF currents on the circuit pack card grounds due to RF fields contained within the faraday cage, but I think these could be mitigated by clever bonding of the grounds on circuit packs. I think that isolating the faceplate from the Dgnd on the circuit packs but stitching the bottom edge (faceplate to backplane) Cgnd ESD guard band to Dgnd could alleviate stray currents on the cards and keep them relatively clean - all while still maintaining the bonding of the Cgnd and Dgnd on a system level. The idea (as my brain developed it) is to keep the stray currents at the periphery of the card by limiting the through connections on the circuit packs and forcing stray currents to flow near the edge of the card. The backplane should for the most part have Dgnd and Cgnd be one and the same. Does this raise any red flags for anyone? I'm expecting at least a few, but this is the best scheme that I can come up with right now. --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list This e-mail may contain SEL confidential information. The opinions expressed are not necessarily those of SEL. Any unauthorized disclosure, distribution or other use is prohibited. If you received this e-mail in error, please notify the sender, permanently delete it, and destroy any printout. Thank you
grounding schemes EMI
All, I'm trying to convince a few people here that completely separating the digital and chassis grounding on our product is not always the best way to go. Unfortunately, a lot of the people I'm dealing with are ex Bellcore engineers who worked a lot with isolated grounds and are convinced that isolated grounds are the only way to go. Now we're dealing with optical interfaces and speeds well in excess of 100MHz, so I really want to see the grounds tied together as much as possible. While I know that combining the digital and chassis grounds is for the most part better once you get above a few hundred MHz, putting together concrete arguments is proving to be a bit elusive. I luckily have some high level backing that will let me push my views, but I am one person up against a team of industry vets. If anyone has been in this boat before and won, could you share some of the tactics or arguments that you used? I know this issue has been discussed in the past, but a fresh discussion of the relative benefits of isolating the D and Cgnds would probably be beneficial to the group as well. See below for my views on the issue. Thanks Dave My views for telecom equipment with a backplane and plug in circuit packs (and a good tight chassis around it all): (Note that Analog grounds are outside of the scope of this statement - I'm focusing on Digital grounds and Chassis ground) The benefits of separating Dgnd and Cgnd have to do with defining your signal impedances and SI in general. When you place this system inside a Cgnd balloon, all should be well but maybe there is some extra noise due to RF being trapped within the balloon. However, if the Cgnd and Dgnd are tied together throughout the system, the effect should be similar to heat shrinking your conductive chassis Cgnd ballon onto your Dgnd. The single ended signal return currents should still follow their original paths and things should essentially remain unchanged. I could see some possibility (I'll avoid use of the word potential here :o) ) for RF currents on the circuit pack card grounds due to RF fields contained within the faraday cage, but I think these could be mitigated by clever bonding of the grounds on circuit packs. I think that isolating the faceplate from the Dgnd on the circuit packs but stitching the bottom edge (faceplate to backplane) Cgnd ESD guard band to Dgnd could alleviate stray currents on the cards and keep them relatively clean - all while still maintaining the bonding of the Cgnd and Dgnd on a system level. The idea (as my brain developed it) is to keep the stray currents at the periphery of the card by limiting the through connections on the circuit packs and forcing stray currents to flow near the edge of the card. The backplane should for the most part have Dgnd and Cgnd be one and the same. Does this raise any red flags for anyone? I'm expecting at least a few, but this is the best scheme that I can come up with right now. --- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on browse and then emc-pstc mailing list
