[Freedreno] [PATCH] drm/msm/dpu: Fix memory leak in msm_mdss_parse_data_bus_icc_path
of_icc_get() alloc resources for path1, we should release it when not
need anymore. Early return when IS_ERR_OR_NULL(path0) may leak path1.
Add icc_put(path1) in the error path to fix this.
Fixes: b9364eed9232 ("drm/msm/dpu: Move min BW request and full BW disable back
to mdss")
Signed-off-by: Miaoqian Lin
---
drivers/gpu/drm/msm/msm_mdss.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index e13c5c12b775..a38fa9a9a3d6 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -49,8 +49,10 @@ static int msm_mdss_parse_data_bus_icc_path(struct device
*dev,
struct icc_path *path0 = of_icc_get(dev, "mdp0-mem");
struct icc_path *path1 = of_icc_get(dev, "mdp1-mem");
- if (IS_ERR_OR_NULL(path0))
+ if (IS_ERR_OR_NULL(path0)) {
+ icc_put(path1);
return PTR_ERR_OR_ZERO(path0);
+ }
msm_mdss->path[0] = path0;
msm_mdss->num_paths = 1;
--
2.25.1
[Freedreno] [PATCH] drm/msm/mdp5: Add check for kzalloc
As kzalloc may fail and return NULL pointer,
it should be better to check the return value
in order to avoid the NULL pointer dereference.
Fixes: 1cff7440a86e ("drm/msm: Convert to using
__drm_atomic_helper_crtc_reset() for reset.")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index e86421c69bd1..86036dd4e1e8 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -1139,7 +1139,10 @@ static void mdp5_crtc_reset(struct drm_crtc *crtc)
if (crtc->state)
mdp5_crtc_destroy_state(crtc, crtc->state);
- __drm_atomic_helper_crtc_reset(crtc, _cstate->base);
+ if (mdp5_cstate)
+ __drm_atomic_helper_crtc_reset(crtc, _cstate->base);
+ else
+ __drm_atomic_helper_crtc_reset(crtc, NULL);
}
static const struct drm_crtc_funcs mdp5_crtc_no_lm_cursor_funcs = {
--
2.25.1
[Freedreno] [PATCH] drm/msm/mdp5: Add check for kzalloc
As kzalloc may fail and return NULL pointer,
it should be better to check the return value
in order to avoid the NULL pointer dereference.
Fixes: 1cff7440a86e ("drm/msm: Convert to using
__drm_atomic_helper_crtc_reset() for reset.")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index e86421c69bd1..86036dd4e1e8 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -1139,7 +1139,10 @@ static void mdp5_crtc_reset(struct drm_crtc *crtc)
if (crtc->state)
mdp5_crtc_destroy_state(crtc, crtc->state);
- __drm_atomic_helper_crtc_reset(crtc, _cstate->base);
+ if (mdp5_cstate)
+ __drm_atomic_helper_crtc_reset(crtc, _cstate->base);
+ else
+ __drm_atomic_helper_crtc_reset(crtc, NULL);
}
static const struct drm_crtc_funcs mdp5_crtc_no_lm_cursor_funcs = {
--
2.25.1
Re: [Freedreno] [PATCH v9 4/5] drm/msm/dp: parser link-frequencies as property of dp_out endpoint
6 декабря 2022 г. 02:08:13 GMT+03:00, Kuogee Hsieh
пишет:
>Add capability to parser and retrieve max DP link supported rate from
>link-frequencies property of dp_out endpoint.
>
>Changes in v6:
>-- second patch after split parser patch into two patches
>
>Changes in v7:
>-- without checking cnt against DP_MAX_NUM_DP_LANES to retrieve link rate
>
>Changes in v9:
>-- separate parser link-frequencies out of data-lanes
>
>Signed-off-by: Kuogee Hsieh
>---
> drivers/gpu/drm/msm/dp/dp_parser.c | 20 ++--
> drivers/gpu/drm/msm/dp/dp_parser.h | 2 ++
> 2 files changed, 20 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c
>b/drivers/gpu/drm/msm/dp/dp_parser.c
>index b5f7e70..fdea843 100644
>--- a/drivers/gpu/drm/msm/dp/dp_parser.c
>+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
>@@ -94,15 +94,17 @@ static int dp_parser_ctrl_res(struct dp_parser *parser)
> static int dp_parser_misc(struct dp_parser *parser)
> {
> struct device_node *of_node = parser->pdev->dev.of_node;
>+ struct device_node *endpoint;
>+ u64 frequency;
> int cnt;
>
> /*
>* data-lanes is the property of dp_out endpoint
>*/
> cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1,
> DP_MAX_NUM_DP_LANES);
>- if (cnt > 0)
>+ if (cnt > 0) {
> parser->max_dp_lanes = cnt;
>- else {
>+ } else {
This belongs to the previous patch
> /*
>* legacy code, data-lanes is the property of mdss_dp node
>*/
>@@ -113,6 +115,20 @@ static int dp_parser_misc(struct dp_parser *parser)
> parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes
> */
> }
>
>+ cnt = 0;
>+ endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */
>+ if (endpoint)
>+ cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
>+ of_node_put(endpoint);
>+ if (cnt > 0) {
>+ of_property_read_u64_index(endpoint, "link-frequencies",
And this is use after free.
I still think than an additional function would make code simpler. You can
return an error code at any point. And then handle it in the calling code.
>+ cnt - 1, );
>+ frequency /= 10;/* from symbol rate to link rate */
>+ parser->max_dp_link_rate = (frequency / 1000); /* kbits */
>+ } else {
>+ parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 54 khz */
>+ }
>+
> return 0;
> }
>
>diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h
>b/drivers/gpu/drm/msm/dp/dp_parser.h
>index 866c1a8..3ddf639 100644
>--- a/drivers/gpu/drm/msm/dp/dp_parser.h
>+++ b/drivers/gpu/drm/msm/dp/dp_parser.h
>@@ -15,6 +15,7 @@
> #define DP_LABEL "MDSS DP DISPLAY"
> #define DP_MAX_PIXEL_CLK_KHZ 675000
> #define DP_MAX_NUM_DP_LANES 4
>+#define DP_LINK_RATE_HBR2 54
>
> enum dp_pm_type {
> DP_CORE_PM,
>@@ -119,6 +120,7 @@ struct dp_parser {
> struct dp_io io;
> struct dp_display_data disp_data;
> u32 max_dp_lanes;
>+ u32 max_dp_link_rate;
> struct drm_bridge *next_bridge;
>
> int (*parse)(struct dp_parser *parser);
[Freedreno] [PATCH v9 3/5] drm/msm/dp: parser data-lanes as property of dp_out endpoint
Add capability to parser data-lanes as property of dp_out endpoint.
Also retain the original capability to parser data-lanes as property
of mdss_dp node to handle legacy case.
Changes in v6:
-- first patch after split parser patch into two
Changes in v7:
-- check "data-lanes" from endpoint first
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_parser.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c
b/drivers/gpu/drm/msm/dp/dp_parser.c
index dd73221..b5f7e70 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.c
+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
@@ -94,16 +94,25 @@ static int dp_parser_ctrl_res(struct dp_parser *parser)
static int dp_parser_misc(struct dp_parser *parser)
{
struct device_node *of_node = parser->pdev->dev.of_node;
- int len;
-
- len = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
- if (len < 0) {
- DRM_WARN("Invalid property \"data-lanes\", default max DP lanes
= %d\n",
-DP_MAX_NUM_DP_LANES);
- len = DP_MAX_NUM_DP_LANES;
+ int cnt;
+
+ /*
+* data-lanes is the property of dp_out endpoint
+*/
+ cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1,
DP_MAX_NUM_DP_LANES);
+ if (cnt > 0)
+ parser->max_dp_lanes = cnt;
+ else {
+ /*
+* legacy code, data-lanes is the property of mdss_dp node
+*/
+ cnt = drm_of_get_data_lanes_count(of_node, 1,
DP_MAX_NUM_DP_LANES);
+ if (cnt > 0)
+ parser->max_dp_lanes = cnt;
+ else
+ parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes
*/
}
- parser->max_dp_lanes = len;
return 0;
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v9 5/5] drm/msm/dp: add support of max dp link rate
By default, HBR2 (5.4G) is the max link link be supported. This patch uses the
actual limit specified by DT and removes the artificial limitation to 5.4 Gbps.
Supporting HBR3 is a consequence of that.
Changes in v2:
-- add max link rate from dtsi
Changes in v3:
-- parser max_data_lanes and max_dp_link_rate from dp_out endpoint
Changes in v4:
-- delete unnecessary pr_err
Changes in v5:
-- split parser function into different patch
Changes in v9:
-- revised commit test
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_display.c | 4
drivers/gpu/drm/msm/dp/dp_panel.c | 7 ---
drivers/gpu/drm/msm/dp/dp_panel.h | 1 +
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index bfd0aef..edee550 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct
dp_display_private *dp)
struct edid *edid;
dp->panel->max_dp_lanes = dp->parser->max_dp_lanes;
+ dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate;
+
+ drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n",
+ dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate);
rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector);
if (rc)
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c
b/drivers/gpu/drm/msm/dp/dp_panel.c
index 5149ceb..933fa9c 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
+ /* Limit data lanes from data-lanes of endpoint properity of dtsi */
if (link_info->num_lanes > dp_panel->max_dp_lanes)
link_info->num_lanes = dp_panel->max_dp_lanes;
- /* Limit support upto HBR2 until HBR3 support is added */
- if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4)))
- link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4);
+ /* Limit link rate from link-frequencies of endpoint properity of dtsi
*/
+ if (link_info->rate > dp_panel->max_dp_link_rate)
+ link_info->rate = dp_panel->max_dp_link_rate;
drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor);
drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate);
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h
b/drivers/gpu/drm/msm/dp/dp_panel.h
index d861197a..f04d021 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.h
+++ b/drivers/gpu/drm/msm/dp/dp_panel.h
@@ -50,6 +50,7 @@ struct dp_panel {
u32 vic;
u32 max_dp_lanes;
+ u32 max_dp_link_rate;
u32 max_bw_code;
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v9 4/5] drm/msm/dp: parser link-frequencies as property of dp_out endpoint
Add capability to parser and retrieve max DP link supported rate from
link-frequencies property of dp_out endpoint.
Changes in v6:
-- second patch after split parser patch into two patches
Changes in v7:
-- without checking cnt against DP_MAX_NUM_DP_LANES to retrieve link rate
Changes in v9:
-- separate parser link-frequencies out of data-lanes
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_parser.c | 20 ++--
drivers/gpu/drm/msm/dp/dp_parser.h | 2 ++
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c
b/drivers/gpu/drm/msm/dp/dp_parser.c
index b5f7e70..fdea843 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.c
+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
@@ -94,15 +94,17 @@ static int dp_parser_ctrl_res(struct dp_parser *parser)
static int dp_parser_misc(struct dp_parser *parser)
{
struct device_node *of_node = parser->pdev->dev.of_node;
+ struct device_node *endpoint;
+ u64 frequency;
int cnt;
/*
* data-lanes is the property of dp_out endpoint
*/
cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1,
DP_MAX_NUM_DP_LANES);
- if (cnt > 0)
+ if (cnt > 0) {
parser->max_dp_lanes = cnt;
- else {
+ } else {
/*
* legacy code, data-lanes is the property of mdss_dp node
*/
@@ -113,6 +115,20 @@ static int dp_parser_misc(struct dp_parser *parser)
parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes
*/
}
+ cnt = 0;
+ endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */
+ if (endpoint)
+ cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
+ of_node_put(endpoint);
+ if (cnt > 0) {
+ of_property_read_u64_index(endpoint, "link-frequencies",
+ cnt - 1, );
+ frequency /= 10;/* from symbol rate to link rate */
+ parser->max_dp_link_rate = (frequency / 1000); /* kbits */
+ } else {
+ parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 54 khz */
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h
b/drivers/gpu/drm/msm/dp/dp_parser.h
index 866c1a8..3ddf639 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.h
+++ b/drivers/gpu/drm/msm/dp/dp_parser.h
@@ -15,6 +15,7 @@
#define DP_LABEL "MDSS DP DISPLAY"
#define DP_MAX_PIXEL_CLK_KHZ 675000
#define DP_MAX_NUM_DP_LANES4
+#define DP_LINK_RATE_HBR2 54
enum dp_pm_type {
DP_CORE_PM,
@@ -119,6 +120,7 @@ struct dp_parser {
struct dp_io io;
struct dp_display_data disp_data;
u32 max_dp_lanes;
+ u32 max_dp_link_rate;
struct drm_bridge *next_bridge;
int (*parse)(struct dp_parser *parser);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v9 2/5] dt-bindings: msm/dp: add data-lanes and link-frequencies property
Add both data-lanes and link-frequencies property into endpoint
Changes in v7:
-- split yaml out of dtsi patch
-- link-frequencies from link rate to symbol rate
-- deprecation of old data-lanes property
Changes in v8:
-- correct Bjorn mail address to kernel.org
Signed-off-by: Kuogee Hsieh `
---
Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 9 +
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index f2515af..38ce17d 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -81,6 +81,7 @@ properties:
data-lanes:
$ref: /schemas/types.yaml#/definitions/uint32-array
+deprecated: true
minItems: 1
maxItems: 4
items:
@@ -104,6 +105,11 @@ properties:
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output endpoint of the controller
+ data-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ link-frequencies:
+ $ref: /schemas/types.yaml#/definitions/uint64-array
required:
- compatible
@@ -193,6 +199,9 @@ examples:
reg = <1>;
endpoint {
remote-endpoint = <>;
+data-lanes = <1 2>;
+link-frequencies = /bits/ 64 <162000 27
+ 54 81>;
};
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v9 1/5] arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpoint
Move data-lanes property from mdss_dp node to dp_out endpoint. Also
add link-frequencies property into dp_out endpoint as well. The last
frequency specified at link-frequencies will be the max link rate
supported by DP.
Changes in v5:
-- revert changes at sc7180.dtsi and sc7280.dtsi
-- add _out to sc7180-trogdor.dtsi and sc7280-herobrine.dtsi
Changes in v6:
-- add data-lanes and link-frequencies to yaml
Changes in v7:
-- change 16000 to 162000
-- separate yaml to different patch
Changes in v8:
-- correct Bjorn mail address to kernel.org
Changes in v9:
-- use symbol rate (hz) for link-frequencies at dp_out at sc7180_trogdor.dtsi
Signed-off-by: Kuogee Hsieh
---
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 6 +-
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index eae22e6..93b0cde 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -814,7 +814,11 @@ hp_i2c: {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_hot_plug_det>;
- data-lanes = <0 1>;
+};
+
+_out {
+data-lanes = <0 1>;
+link-frequencies = /bits/ 64 <162000 27 54>;
};
_adc {
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index c11e371..3c7a9d8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -442,7 +442,11 @@ ap_i2c_tpm: {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_hot_plug_det>;
- data-lanes = <0 1>;
+};
+
+_out {
+ data-lanes = <0 1>;
+ link-frequencies = /bits/ 64 <162000 27 54
81>;
};
_mdp {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v9 0/5] Add data-lanes and link-frequencies to dp_out endpoint
Add DP both data-lanes and link-frequencies property to dp_out endpoint and support functions to DP driver. Kuogee Hsieh (5): arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpoint dt-bindings: msm/dp: add data-lanes and link-frequencies property drm/msm/dp: parser data-lanes as property of dp_out endpoint drm/msm/dp: parser link-frequencies as property of dp_out endpoint drm/msm/dp: add support of max dp link rate .../bindings/display/msm/dp-controller.yaml| 9 + arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 6 +++- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 +++- drivers/gpu/drm/msm/dp/dp_display.c| 4 +++ drivers/gpu/drm/msm/dp/dp_panel.c | 7 ++-- drivers/gpu/drm/msm/dp/dp_panel.h | 1 + drivers/gpu/drm/msm/dp/dp_parser.c | 39 ++ drivers/gpu/drm/msm/dp/dp_parser.h | 2 ++ 8 files changed, 62 insertions(+), 12 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [Freedreno] [PATCH v2 11/12] arm64: dts: qcom: sm6115: Add WCN node.
On Thu, Dec 01, 2022 at 11:38:16AM +0100, Krzysztof Kozlowski wrote: > On 30/11/2022 21:09, Adam Skladowski wrote: > > Add WCN node to allow using wifi module. > > > > A nit: Drop full stop from commit subject. > Done. Thanks for pointing it out :) Regards, Bjorn > Best regards, > Krzysztof >
Re: [Freedreno] [PATCH v4 08/13] drm/msm/dp: Implement hpd_notify()
On Tue, Dec 06, 2022 at 12:29:13AM +0300, Dmitry Baryshkov wrote:
>
>
> On 5 December 2022 20:44:28 GMT+03:00, Bjorn Andersson
> wrote:
> >From: Bjorn Andersson
> >
> >The DisplayPort controller's hot-plug mechanism is based on pinmuxing a
> >physical signal on a GPIO pin into the controller. This is not always
> >possible, either because there aren't dedicated GPIOs available or
> >because the hot-plug signal is a virtual notification, in cases such as
> >USB Type-C.
> >
> >For these cases, by implementing the hpd_notify() callback for the
> >DisplayPort controller's drm_bridge, a downstream drm_bridge
> >(next_bridge) can be used to track and signal the connection status
> >changes.
> >
> >This makes it possible to use downstream drm_bridges such as
> >display-connector or any virtual mechanism, as long as they are
> >implemented as a drm_bridge.
> >
> >Signed-off-by: Bjorn Andersson
> >[bjorn: Drop connector->fwnode assignment and dev from struct msm_dp]
> >Signed-off-by: Bjorn Andersson
>
> Reviewed-by: Dmitry Baryshkov
>
> Minor nit: if for the next revision you reorder the patches to have
> hpd_enable first, then missing conditions, then this patch, it will
> look more logical.
You're right, that will look better. I'll do so.
Thanks,
Bjorn
>
> >---
> >
> >Changes since v3:
> >- None
> >
> > drivers/gpu/drm/msm/dp/dp_display.c | 22 ++
> > drivers/gpu/drm/msm/dp/dp_drm.c | 1 +
> > drivers/gpu/drm/msm/dp/dp_drm.h | 2 ++
> > 3 files changed, 25 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
> >b/drivers/gpu/drm/msm/dp/dp_display.c
> >index 666b45c8ab80..17fcf8cd84cd 100644
> >--- a/drivers/gpu/drm/msm/dp/dp_display.c
> >+++ b/drivers/gpu/drm/msm/dp/dp_display.c
> >@@ -1772,3 +1772,25 @@ void dp_bridge_mode_set(struct drm_bridge *drm_bridge,
> > dp_display->dp_mode.h_active_low =
> > !!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC);
> > }
> >+
> >+void dp_bridge_hpd_notify(struct drm_bridge *bridge,
> >+ enum drm_connector_status status)
> >+{
> >+struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge);
> >+struct msm_dp *dp_display = dp_bridge->dp_display;
> >+struct dp_display_private *dp = container_of(dp_display, struct
> >dp_display_private, dp_display);
> >+
> >+/* Without next_bridge interrupts are handled by the DP core directly */
> >+if (!dp_display->next_bridge)
> >+return;
> >+
> >+if (!dp->core_initialized) {
> >+drm_dbg_dp(dp->drm_dev, "not initialized\n");
> >+return;
> >+}
> >+
> >+if (!dp_display->is_connected && status == connector_status_connected)
> >+dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0);
> >+else if (dp_display->is_connected && status ==
> >connector_status_disconnected)
> >+dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0);
> >+}
> >diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c
> >b/drivers/gpu/drm/msm/dp/dp_drm.c
> >index 6db82f9b03af..3898366ebd5e 100644
> >--- a/drivers/gpu/drm/msm/dp/dp_drm.c
> >+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
> >@@ -102,6 +102,7 @@ static const struct drm_bridge_funcs dp_bridge_ops = {
> > .get_modes= dp_bridge_get_modes,
> > .detect = dp_bridge_detect,
> > .atomic_check = dp_bridge_atomic_check,
> >+.hpd_notify = dp_bridge_hpd_notify,
> > };
> >
> > struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct
> > drm_device *dev,
> >diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h
> >b/drivers/gpu/drm/msm/dp/dp_drm.h
> >index 82035dbb0578..79e6b2cf2d25 100644
> >--- a/drivers/gpu/drm/msm/dp/dp_drm.h
> >+++ b/drivers/gpu/drm/msm/dp/dp_drm.h
> >@@ -32,5 +32,7 @@ enum drm_mode_status dp_bridge_mode_valid(struct
> >drm_bridge *bridge,
> > void dp_bridge_mode_set(struct drm_bridge *drm_bridge,
> > const struct drm_display_mode *mode,
> > const struct drm_display_mode *adjusted_mode);
> >+void dp_bridge_hpd_notify(struct drm_bridge *bridge,
> >+ enum drm_connector_status status);
> >
> > #endif /* _DP_DRM_H_ */
>
> --
> With best wishes
> Dmitry
Re: [Freedreno] [PATCH v8 2/5] dt-bindings: msm/dp: add data-lanes and link-frequencies property
On 5 December 2022 22:14:27 GMT+03:00, Kuogee Hsieh
wrote:
>Add both data-lanes and link-frequencies property into endpoint
>
>Changes in v7:
>-- split yaml out of dtsi patch
>-- link-frequencies from link rate to symbol rate
>-- deprecation of old data-lanes property
>
>Changes in v8:
>-- correct Bjorn mail address to kernel.org
>
>Signed-off-by: Kuogee Hsieh
>---
> .../bindings/display/msm/dp-controller.yaml| 22 --
> 1 file changed, 16 insertions(+), 6 deletions(-)
>
>diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
>b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
>index f2515af..13d2c3c 100644
>--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
>+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
>@@ -79,12 +79,6 @@ properties:
> aux-bus:
> $ref: /schemas/display/dp-aux-bus.yaml#
>
>- data-lanes:
>-$ref: /schemas/types.yaml#/definitions/uint32-array
>-minItems: 1
>-maxItems: 4
>-items:
>- maximum: 3
These properties can still be used, e.g. Bjorn is submitting patches with the
old property. I think this should be marked with deprecated: true instead of
removal.
>
> "#sound-dai-cells":
> const: 0
>@@ -105,6 +99,19 @@ properties:
> $ref: /schemas/graph.yaml#/properties/port
> description: Output endpoint of the controller
>
>+properties:
>+ endpoint:
>+$ref: /schemas/media/video-interfaces.yaml#
>+
>+ properties:
>+data-lanes:
>+ $ref: /schemas/types.yaml#/definitions/uint32-array
>+
>+link-frequencies:
>+ $ref: /schemas/types.yaml#/definitions/uint64-array
>+
>+ additionalProperties: false
>+
> required:
> - compatible
> - reg
>@@ -193,6 +200,9 @@ examples:
> reg = <1>;
> endpoint {
> remote-endpoint = <>;
>+data-lanes = <1 2>;
>+link-frequencies = /bits/ 64 <162000 27
>+ 54 81>;
> };
> };
> };
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH v4 08/13] drm/msm/dp: Implement hpd_notify()
On 5 December 2022 20:44:28 GMT+03:00, Bjorn Andersson
wrote:
>From: Bjorn Andersson
>
>The DisplayPort controller's hot-plug mechanism is based on pinmuxing a
>physical signal on a GPIO pin into the controller. This is not always
>possible, either because there aren't dedicated GPIOs available or
>because the hot-plug signal is a virtual notification, in cases such as
>USB Type-C.
>
>For these cases, by implementing the hpd_notify() callback for the
>DisplayPort controller's drm_bridge, a downstream drm_bridge
>(next_bridge) can be used to track and signal the connection status
>changes.
>
>This makes it possible to use downstream drm_bridges such as
>display-connector or any virtual mechanism, as long as they are
>implemented as a drm_bridge.
>
>Signed-off-by: Bjorn Andersson
>[bjorn: Drop connector->fwnode assignment and dev from struct msm_dp]
>Signed-off-by: Bjorn Andersson
Reviewed-by: Dmitry Baryshkov
Minor nit: if for the next revision you reorder the patches to have hpd_enable
first, then missing conditions, then this patch, it will look more logical.
>---
>
>Changes since v3:
>- None
>
> drivers/gpu/drm/msm/dp/dp_display.c | 22 ++
> drivers/gpu/drm/msm/dp/dp_drm.c | 1 +
> drivers/gpu/drm/msm/dp/dp_drm.h | 2 ++
> 3 files changed, 25 insertions(+)
>
>diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
>b/drivers/gpu/drm/msm/dp/dp_display.c
>index 666b45c8ab80..17fcf8cd84cd 100644
>--- a/drivers/gpu/drm/msm/dp/dp_display.c
>+++ b/drivers/gpu/drm/msm/dp/dp_display.c
>@@ -1772,3 +1772,25 @@ void dp_bridge_mode_set(struct drm_bridge *drm_bridge,
> dp_display->dp_mode.h_active_low =
> !!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC);
> }
>+
>+void dp_bridge_hpd_notify(struct drm_bridge *bridge,
>+enum drm_connector_status status)
>+{
>+ struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge);
>+ struct msm_dp *dp_display = dp_bridge->dp_display;
>+ struct dp_display_private *dp = container_of(dp_display, struct
>dp_display_private, dp_display);
>+
>+ /* Without next_bridge interrupts are handled by the DP core directly */
>+ if (!dp_display->next_bridge)
>+ return;
>+
>+ if (!dp->core_initialized) {
>+ drm_dbg_dp(dp->drm_dev, "not initialized\n");
>+ return;
>+ }
>+
>+ if (!dp_display->is_connected && status == connector_status_connected)
>+ dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0);
>+ else if (dp_display->is_connected && status ==
>connector_status_disconnected)
>+ dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0);
>+}
>diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
>index 6db82f9b03af..3898366ebd5e 100644
>--- a/drivers/gpu/drm/msm/dp/dp_drm.c
>+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
>@@ -102,6 +102,7 @@ static const struct drm_bridge_funcs dp_bridge_ops = {
> .get_modes= dp_bridge_get_modes,
> .detect = dp_bridge_detect,
> .atomic_check = dp_bridge_atomic_check,
>+ .hpd_notify = dp_bridge_hpd_notify,
> };
>
> struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct
> drm_device *dev,
>diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h
>index 82035dbb0578..79e6b2cf2d25 100644
>--- a/drivers/gpu/drm/msm/dp/dp_drm.h
>+++ b/drivers/gpu/drm/msm/dp/dp_drm.h
>@@ -32,5 +32,7 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge
>*bridge,
> void dp_bridge_mode_set(struct drm_bridge *drm_bridge,
> const struct drm_display_mode *mode,
> const struct drm_display_mode *adjusted_mode);
>+void dp_bridge_hpd_notify(struct drm_bridge *bridge,
>+enum drm_connector_status status);
>
> #endif /* _DP_DRM_H_ */
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH v4 12/13] arm64: dts: qcom: sc8280xp-crd: Enable EDP
On 5 December 2022 20:44:32 GMT+03:00, Bjorn Andersson
wrote:
>From: Bjorn Andersson
>
>The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes
>and link it together with the backlight control.
>
>Signed-off-by: Bjorn Andersson
>Signed-off-by: Bjorn Andersson
>---
>
>Changes since v3:
>- Added description of the regulator that powers the panel.
>
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 72 ++-
> 1 file changed, 71 insertions(+), 1 deletion(-)
>
>diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
>b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
>index f09810e3d956..a7d2384cbbe8 100644
>--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
>+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
>@@ -20,7 +20,7 @@ aliases {
> serial0 = _uart17;
> };
>
>- backlight {
>+ backlight: backlight {
> compatible = "pwm-backlight";
> pwms = <_lpg 3 100>;
> enable-gpios = <_1_gpios 8 GPIO_ACTIVE_HIGH>;
>@@ -34,6 +34,22 @@ chosen {
> stdout-path = "serial0:115200n8";
> };
>
>+ vreg_edp_3p3: regulator-edp-3p3 {
>+ compatible = "regulator-fixed";
>+
>+ regulator-name = "VREG_EDP_3P3";
>+ regulator-min-microvolt = <330>;
>+ regulator-max-microvolt = <330>;
>+
>+ gpio = < 25 GPIO_ACTIVE_HIGH>;
>+ enable-active-high;
>+
>+ pinctrl-names = "default";
>+ pinctrl-0 = <_reg_en>;
>+
>+ regulator-boot-on;
>+ };
>+
> vreg_edp_bl: regulator-edp-bl {
> compatible = "regulator-fixed";
>
>@@ -230,6 +246,54 @@ vreg_l9d: ldo9 {
> };
> };
>
>+ {
>+ status = "okay";
>+};
>+
>+ {
>+ status = "okay";
>+};
>+
>+_dp3 {
>+ compatible = "qcom,sc8280xp-edp";
>+ status = "okay";
>+
>+ data-lanes = <0 1 2 3>;
>+
>+ aux-bus {
>+ panel {
>+ compatible = "edp-panel";
>+ power-supply = <_edp_3p3>;
>+
>+ backlight = <>;
>+
>+ ports {
>+ port {
>+ edp_panel_in: endpoint {
>+ remote-endpoint =
><_dp3_out>;
>+ };
>+ };
>+ };
>+ };
>+ };
>+
>+ ports {
>+ port@1 {
>+ reg = <1>;
You already have reg assignment in the SoC dtsi.
>+ mdss0_dp3_out: endpoint {
>+ remote-endpoint = <_panel_in>;
>+ };
>+ };
>+ };
>+};
>+
>+_dp3_phy {
>+ status = "okay";
>+
>+ vdda-phy-supply = <_l6b>;
>+ vdda-pll-supply = <_l3b>;
>+};
>+
> {
> perst-gpios = < 143 GPIO_ACTIVE_LOW>;
> wake-gpios = < 145 GPIO_ACTIVE_LOW>;
>@@ -496,6 +560,12 @@ hastings_reg_en: hastings-reg-en-state {
> {
> gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
>
>+ edp_reg_en: edp-reg-en-state {
>+ pins = "gpio25";
>+ function = "gpio";
>+ output-enable;
>+ };
>+
> kybd_default: kybd-default-state {
> disable-pins {
> pins = "gpio102";
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH v4 09/13] drm/msm/dp: Don't enable HPD interrupts for edp
On 6 December 2022 00:07:12 GMT+03:00, Dmitry Baryshkov wrote: > > >On 5 December 2022 20:44:29 GMT+03:00, Bjorn Andersson > wrote: >>From: Bjorn Andersson >> >>Most instances where HPD interrupts are masked and unmasked are guareded >>by the presence of an EDP panel being connected, but not all. Extend >>this to cover the last few places, as HPD interrupt handling is not used >>for the EDP case. > >I don't remember whether I asked that or not. Would it be possible to move hpd >irq enablement to bridge's hpd_enable() / hpd_disable() callbacks ? I think >this would allow us to drop the is_edp checks. Ignore this. I should read the series carefully. > >> >>Signed-off-by: Bjorn Andersson >>Reviewed-by: Dmitry Baryshkov >>Signed-off-by: Bjorn Andersson >>--- >> >>Changes since v3: >>- None >> >> drivers/gpu/drm/msm/dp/dp_display.c | 15 ++- >> 1 file changed, 10 insertions(+), 5 deletions(-) >> >>diff --git a/drivers/gpu/drm/msm/dp/dp_display.c >>b/drivers/gpu/drm/msm/dp/dp_display.c >>index 17fcf8cd84cd..bb92c33beff8 100644 >>--- a/drivers/gpu/drm/msm/dp/dp_display.c >>+++ b/drivers/gpu/drm/msm/dp/dp_display.c >>@@ -610,8 +610,10 @@ static int dp_hpd_plug_handle(struct dp_display_private >>*dp, u32 data) >> } >> >> /* enable HDP irq_hpd/replug interrupt */ >>- dp_catalog_hpd_config_intr(dp->catalog, >>- DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true); >>+ if (!dp->dp_display.is_edp) >>+ dp_catalog_hpd_config_intr(dp->catalog, >>+DP_DP_IRQ_HPD_INT_MASK | >>DP_DP_HPD_REPLUG_INT_MASK, >>+true); >> >> drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n", >> dp->dp_display.connector_type, state); >>@@ -651,8 +653,10 @@ static int dp_hpd_unplug_handle(struct >>dp_display_private *dp, u32 data) >> dp->dp_display.connector_type, state); >> >> /* disable irq_hpd/replug interrupts */ >>- dp_catalog_hpd_config_intr(dp->catalog, >>- DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, false); >>+ if (!dp->dp_display.is_edp) >>+ dp_catalog_hpd_config_intr(dp->catalog, >>+DP_DP_IRQ_HPD_INT_MASK | >>DP_DP_HPD_REPLUG_INT_MASK, >>+false); >> >> /* unplugged, no more irq_hpd handle */ >> dp_del_event(dp, EV_IRQ_HPD_INT); >>@@ -678,7 +682,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private >>*dp, u32 data) >> } >> >> /* disable HPD plug interrupts */ >>- dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, false); >>+ if (!dp->dp_display.is_edp) >>+ dp_catalog_hpd_config_intr(dp->catalog, >>DP_DP_HPD_PLUG_INT_MASK, false); >> >> /* >> * We don't need separate work for disconnect as > -- With best wishes Dmitry
Re: [Freedreno] [PATCH v4 10/13] drm/msm/dp: Rely on hpd_enable/disable callbacks
On 5 December 2022 20:44:30 GMT+03:00, Bjorn Andersson
wrote:
>From: Bjorn Andersson
>
>The DisplayPort controller's internal HPD interrupt handling is used for
>cases where the HPD signal is connected to a GPIO which is pinmuxed into
>the DisplayPort controller. In other configurations the HPD notification
>might be delivered by the DRM framework from an associated bridge.
>
>This difference is not appropriately represented by the "is_edp"
>boolean, but is properly represented by the frameworks invocation of the
>hpd_enable() and hpd_disable() callbacks. Switch the current condition
>to rely on these callbacks instead.
>
>This ensures appropriate handling of the three cases; no bridge
>connected, a bridge without DRM_BRIDGE_OP_HPD and a bridge with
>DRM_BRIDGE_OP_HPD.
>
>Signed-off-by: Bjorn Andersson
>Signed-off-by: Bjorn Andersson
>---
>
>Worth mentioning, I did look into moving the HPD enablement/disablement
>completely into these new callbacks, but that affect the entire power
>management model of the driver, so I think it's worth to tackle that in
>subsequent changes. It seems also reasonable to expect that we by such
>modifications could leave the block unclocked until the external HPD
>notification arrives...
I see... I still suppose this is the way to go in the long term.
For now:
Reviewed-by: Dmitry Baryshkov
>
>Changes since v3:
>- Introduced reliance on hpd_enable/disable callbacks instead of next_bridge
>
> drivers/gpu/drm/msm/dp/dp_display.c | 35 -
> drivers/gpu/drm/msm/dp/dp_display.h | 1 +
> drivers/gpu/drm/msm/dp/dp_drm.c | 2 ++
> drivers/gpu/drm/msm/dp/dp_drm.h | 2 ++
> 4 files changed, 30 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
>b/drivers/gpu/drm/msm/dp/dp_display.c
>index bb92c33beff8..3e464c33ff11 100644
>--- a/drivers/gpu/drm/msm/dp/dp_display.c
>+++ b/drivers/gpu/drm/msm/dp/dp_display.c
>@@ -610,7 +610,7 @@ static int dp_hpd_plug_handle(struct dp_display_private
>*dp, u32 data)
> }
>
> /* enable HDP irq_hpd/replug interrupt */
>- if (!dp->dp_display.is_edp)
>+ if (dp->dp_display.internal_hpd)
> dp_catalog_hpd_config_intr(dp->catalog,
> DP_DP_IRQ_HPD_INT_MASK |
> DP_DP_HPD_REPLUG_INT_MASK,
> true);
>@@ -653,7 +653,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private
>*dp, u32 data)
> dp->dp_display.connector_type, state);
>
> /* disable irq_hpd/replug interrupts */
>- if (!dp->dp_display.is_edp)
>+ if (dp->dp_display.internal_hpd)
> dp_catalog_hpd_config_intr(dp->catalog,
> DP_DP_IRQ_HPD_INT_MASK |
> DP_DP_HPD_REPLUG_INT_MASK,
> false);
>@@ -682,7 +682,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private
>*dp, u32 data)
> }
>
> /* disable HPD plug interrupts */
>- if (!dp->dp_display.is_edp)
>+ if (dp->dp_display.internal_hpd)
> dp_catalog_hpd_config_intr(dp->catalog,
> DP_DP_HPD_PLUG_INT_MASK, false);
>
> /*
>@@ -701,7 +701,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private
>*dp, u32 data)
> dp_display_handle_plugged_change(>dp_display, false);
>
> /* enable HDP plug interrupt to prepare for next plugin */
>- if (!dp->dp_display.is_edp)
>+ if (dp->dp_display.internal_hpd)
> dp_catalog_hpd_config_intr(dp->catalog,
> DP_DP_HPD_PLUG_INT_MASK, true);
>
> drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n",
>@@ -1086,8 +1086,8 @@ static void dp_display_config_hpd(struct
>dp_display_private *dp)
> dp_display_host_init(dp);
> dp_catalog_ctrl_hpd_config(dp->catalog);
>
>- /* Enable plug and unplug interrupts only for external DisplayPort */
>- if (!dp->dp_display.is_edp)
>+ /* Enable plug and unplug interrupts only if requested */
>+ if (dp->dp_display.internal_hpd)
> dp_catalog_hpd_config_intr(dp->catalog,
> DP_DP_HPD_PLUG_INT_MASK |
> DP_DP_HPD_UNPLUG_INT_MASK,
>@@ -1379,8 +1379,7 @@ static int dp_pm_resume(struct device *dev)
>
> dp_catalog_ctrl_hpd_config(dp->catalog);
>
>-
>- if (!dp->dp_display.is_edp)
>+ if (dp->dp_display.internal_hpd)
> dp_catalog_hpd_config_intr(dp->catalog,
> DP_DP_HPD_PLUG_INT_MASK |
> DP_DP_HPD_UNPLUG_INT_MASK,
>@@ -1778,6 +1777,22 @@ void dp_bridge_mode_set(struct drm_bridge *drm_bridge,
> !!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC);
> }
>
>+void dp_bridge_hpd_enable(struct drm_bridge *bridge)
>+{
>+ struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge);
>+ struct msm_dp *dp_display = dp_bridge->dp_display;
>+
>+ dp_display->internal_hpd =
Re: [Freedreno] [PATCH v4 01/13] dt-bindings: display/msm: Add binding for SC8280XP MDSS
On Mon, 05 Dec 2022 09:44:21 -0800, Bjorn Andersson wrote: > From: Bjorn Andersson > > Add binding for the display subsystem and display processing unit in the > Qualcomm SC8280XP platform. > > Signed-off-by: Bjorn Andersson > Signed-off-by: Bjorn Andersson > --- > > Changes since v3: > - Reworked on top of redesigned common yaml. > > .../display/msm/qcom,sc8280xp-dpu.yaml| 122 +++ > .../display/msm/qcom,sc8280xp-mdss.yaml | 143 ++ > 2 files changed, 265 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml > create mode 100644 > Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml > Reviewed-by: Rob Herring
Re: [Freedreno] [PATCH v3 02/11] dt-bindings: display: msm: Add qcom, sm8350-mdss binding
On Mon, 05 Dec 2022 17:37:45 +0100, Robert Foss wrote: > Mobile Display Subsystem (MDSS) encapsulates sub-blocks > like DPU display controller, DSI etc. Add YAML schema for MDSS device > tree bindings > > Signed-off-by: Robert Foss > --- > .../display/msm/qcom,sm8350-mdss.yaml | 221 ++ > 1 file changed, 221 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml > Reviewed-by: Rob Herring
Re: [Freedreno] [PATCH v4 09/13] drm/msm/dp: Don't enable HPD interrupts for edp
On 5 December 2022 20:44:29 GMT+03:00, Bjorn Andersson wrote: >From: Bjorn Andersson > >Most instances where HPD interrupts are masked and unmasked are guareded >by the presence of an EDP panel being connected, but not all. Extend >this to cover the last few places, as HPD interrupt handling is not used >for the EDP case. I don't remember whether I asked that or not. Would it be possible to move hpd irq enablement to bridge's hpd_enable() / hpd_disable() callbacks ? I think this would allow us to drop the is_edp checks. > >Signed-off-by: Bjorn Andersson >Reviewed-by: Dmitry Baryshkov >Signed-off-by: Bjorn Andersson >--- > >Changes since v3: >- None > > drivers/gpu/drm/msm/dp/dp_display.c | 15 ++- > 1 file changed, 10 insertions(+), 5 deletions(-) > >diff --git a/drivers/gpu/drm/msm/dp/dp_display.c >b/drivers/gpu/drm/msm/dp/dp_display.c >index 17fcf8cd84cd..bb92c33beff8 100644 >--- a/drivers/gpu/drm/msm/dp/dp_display.c >+++ b/drivers/gpu/drm/msm/dp/dp_display.c >@@ -610,8 +610,10 @@ static int dp_hpd_plug_handle(struct dp_display_private >*dp, u32 data) > } > > /* enable HDP irq_hpd/replug interrupt */ >- dp_catalog_hpd_config_intr(dp->catalog, >- DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true); >+ if (!dp->dp_display.is_edp) >+ dp_catalog_hpd_config_intr(dp->catalog, >+ DP_DP_IRQ_HPD_INT_MASK | >DP_DP_HPD_REPLUG_INT_MASK, >+ true); > > drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n", > dp->dp_display.connector_type, state); >@@ -651,8 +653,10 @@ static int dp_hpd_unplug_handle(struct dp_display_private >*dp, u32 data) > dp->dp_display.connector_type, state); > > /* disable irq_hpd/replug interrupts */ >- dp_catalog_hpd_config_intr(dp->catalog, >- DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, false); >+ if (!dp->dp_display.is_edp) >+ dp_catalog_hpd_config_intr(dp->catalog, >+ DP_DP_IRQ_HPD_INT_MASK | >DP_DP_HPD_REPLUG_INT_MASK, >+ false); > > /* unplugged, no more irq_hpd handle */ > dp_del_event(dp, EV_IRQ_HPD_INT); >@@ -678,7 +682,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private >*dp, u32 data) > } > > /* disable HPD plug interrupts */ >- dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, false); >+ if (!dp->dp_display.is_edp) >+ dp_catalog_hpd_config_intr(dp->catalog, >DP_DP_HPD_PLUG_INT_MASK, false); > > /* >* We don't need separate work for disconnect as -- With best wishes Dmitry
Re: [Freedreno] [PATCH v8 2/5] dt-bindings: msm/dp: add data-lanes and link-frequencies property
On Mon, 05 Dec 2022 11:14:27 -0800, Kuogee Hsieh wrote:
> Add both data-lanes and link-frequencies property into endpoint
>
> Changes in v7:
> -- split yaml out of dtsi patch
> -- link-frequencies from link rate to symbol rate
> -- deprecation of old data-lanes property
>
> Changes in v8:
> -- correct Bjorn mail address to kernel.org
>
> Signed-off-by: Kuogee Hsieh
> ---
> .../bindings/display/msm/dp-controller.yaml| 22
> --
> 1 file changed, 16 insertions(+), 6 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dp-controller.yaml:
properties:ports:properties:port@1:properties: 'properties' should not be
valid under {'$ref': '#/definitions/json-schema-prop-names'}
hint: A json-schema keyword was found instead of a DT property name.
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dp-controller.yaml:
properties:ports:properties:port@1:properties: 'additionalProperties' should
not be valid under {'$ref': '#/definitions/json-schema-prop-names'}
hint: A json-schema keyword was found instead of a DT property name.
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dp-controller.yaml:
properties:ports:properties:port@1:properties:properties: 'anyOf' conditional
failed, one must be fixed:
'data-lanes' is not one of ['$ref', 'additionalItems',
'additionalProperties', 'allOf', 'anyOf', 'const', 'contains', 'default',
'dependencies', 'dependentRequired', 'dependentSchemas', 'deprecated',
'description', 'else', 'enum', 'exclusiveMaximum', 'exclusiveMinimum', 'items',
'if', 'minItems', 'minimum', 'maxItems', 'maximum', 'multipleOf', 'not',
'oneOf', 'pattern', 'patternProperties', 'properties', 'required', 'then',
'typeSize', 'unevaluatedProperties', 'uniqueItems']
'type' was expected
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dp-controller.yaml:
properties:ports:properties:port@1:properties:properties: 'anyOf' conditional
failed, one must be fixed:
'link-frequencies' is not one of ['$ref', 'additionalItems',
'additionalProperties', 'allOf', 'anyOf', 'const', 'contains', 'default',
'dependencies', 'dependentRequired', 'dependentSchemas', 'deprecated',
'description', 'else', 'enum', 'exclusiveMaximum', 'exclusiveMinimum', 'items',
'if', 'minItems', 'minimum', 'maxItems', 'maximum', 'multipleOf', 'not',
'oneOf', 'pattern', 'patternProperties', 'properties', 'required', 'then',
'typeSize', 'unevaluatedProperties', 'uniqueItems']
'type' was expected
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dp-controller.example.dtb:
displayport-controller@ae9: ports:port@1:endpoint: Unevaluated properties
are not allowed ('data-lanes', 'link-frequencies' were unexpected)
From schema:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
doc reference errors (make refcheckdocs):
See
https://patchwork.ozlabs.org/project/devicetree-bindings/patch/1670267670-15832-3-git-send-email-quic_khs...@quicinc.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
Re: [Freedreno] [PATCH v4 08/13] drm/msm/dp: Implement hpd_notify()
On 5 December 2022 20:44:28 GMT+03:00, Bjorn Andersson
wrote:
>From: Bjorn Andersson
>
>The DisplayPort controller's hot-plug mechanism is based on pinmuxing a
>physical signal on a GPIO pin into the controller. This is not always
>possible, either because there aren't dedicated GPIOs available or
>because the hot-plug signal is a virtual notification, in cases such as
>USB Type-C.
>
>For these cases, by implementing the hpd_notify() callback for the
>DisplayPort controller's drm_bridge, a downstream drm_bridge
>(next_bridge) can be used to track and signal the connection status
>changes.
>
>This makes it possible to use downstream drm_bridges such as
>display-connector or any virtual mechanism, as long as they are
>implemented as a drm_bridge.
>
>Signed-off-by: Bjorn Andersson
>[bjorn: Drop connector->fwnode assignment and dev from struct msm_dp]
>Signed-off-by: Bjorn Andersson
>---
>
>Changes since v3:
>- None
>
> drivers/gpu/drm/msm/dp/dp_display.c | 22 ++
> drivers/gpu/drm/msm/dp/dp_drm.c | 1 +
> drivers/gpu/drm/msm/dp/dp_drm.h | 2 ++
> 3 files changed, 25 insertions(+)
>
>diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
>b/drivers/gpu/drm/msm/dp/dp_display.c
>index 666b45c8ab80..17fcf8cd84cd 100644
>--- a/drivers/gpu/drm/msm/dp/dp_display.c
>+++ b/drivers/gpu/drm/msm/dp/dp_display.c
>@@ -1772,3 +1772,25 @@ void dp_bridge_mode_set(struct drm_bridge *drm_bridge,
> dp_display->dp_mode.h_active_low =
> !!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC);
> }
>+
>+void dp_bridge_hpd_notify(struct drm_bridge *bridge,
>+enum drm_connector_status status)
>+{
>+ struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge);
>+ struct msm_dp *dp_display = dp_bridge->dp_display;
>+ struct dp_display_private *dp = container_of(dp_display, struct
>dp_display_private, dp_display);
>+
>+ /* Without next_bridge interrupts are handled by the DP core directly */
>+ if (!dp_display->next_bridge)
>+ return;
Can we use hpd_notify in all the cases by dropping the corresponding piece of
code from the core driver?
>+
>+ if (!dp->core_initialized) {
>+ drm_dbg_dp(dp->drm_dev, "not initialized\n");
>+ return;
>+ }
>+
>+ if (!dp_display->is_connected && status == connector_status_connected)
>+ dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0);
>+ else if (dp_display->is_connected && status ==
>connector_status_disconnected)
>+ dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0);
>+}
>diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
>index 6db82f9b03af..3898366ebd5e 100644
>--- a/drivers/gpu/drm/msm/dp/dp_drm.c
>+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
>@@ -102,6 +102,7 @@ static const struct drm_bridge_funcs dp_bridge_ops = {
> .get_modes= dp_bridge_get_modes,
> .detect = dp_bridge_detect,
> .atomic_check = dp_bridge_atomic_check,
>+ .hpd_notify = dp_bridge_hpd_notify,
> };
>
> struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct
> drm_device *dev,
>diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h
>index 82035dbb0578..79e6b2cf2d25 100644
>--- a/drivers/gpu/drm/msm/dp/dp_drm.h
>+++ b/drivers/gpu/drm/msm/dp/dp_drm.h
>@@ -32,5 +32,7 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge
>*bridge,
> void dp_bridge_mode_set(struct drm_bridge *drm_bridge,
> const struct drm_display_mode *mode,
> const struct drm_display_mode *adjusted_mode);
>+void dp_bridge_hpd_notify(struct drm_bridge *bridge,
>+enum drm_connector_status status);
>
> #endif /* _DP_DRM_H_ */
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH v4 03/13] drm/msm: Introduce SC8280XP MDSS
On 5 December 2022 20:44:23 GMT+03:00, Bjorn Andersson wrote: >From: Bjorn Andersson > >Add compatible for the SC8280XP Mobile Display Subsystem and >initialization for version 8.0.0. > >Signed-off-by: Bjorn Andersson >Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov >--- -- With best wishes Dmitry
Re: [Freedreno] [PATCH v8 5/5] drm/msm/dp: add support of max dp link rate
On 5 December 2022 22:14:30 GMT+03:00, Kuogee Hsieh
wrote:
>By default, HBR2 (5.4G) is the max link link be supported. This patch add
>the capability to support max link rate at HBR3 (8.1G).
This patch uses the actual limit specified by DT and removes the artificial
limitation to 5.4 Gbps. Supporting HBR3 is a consequence of that.
>
>Changes in v2:
>-- add max link rate from dtsi
>
>Changes in v3:
>-- parser max_data_lanes and max_dp_link_rate from dp_out endpoint
>
>Changes in v4:
>-- delete unnecessary pr_err
>
>Changes in v5:
>-- split parser function into different patch
>
>Signed-off-by: Kuogee Hsieh
>Reviewed-by: Dmitry Baryshkov
>---
> drivers/gpu/drm/msm/dp/dp_display.c | 4
> drivers/gpu/drm/msm/dp/dp_panel.c | 7 ---
> drivers/gpu/drm/msm/dp/dp_panel.h | 1 +
> 3 files changed, 9 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
>b/drivers/gpu/drm/msm/dp/dp_display.c
>index bfd0aef..edee550 100644
>--- a/drivers/gpu/drm/msm/dp/dp_display.c
>+++ b/drivers/gpu/drm/msm/dp/dp_display.c
>@@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct
>dp_display_private *dp)
> struct edid *edid;
>
> dp->panel->max_dp_lanes = dp->parser->max_dp_lanes;
>+ dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate;
>+
>+ drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n",
>+ dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate);
>
> rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector);
> if (rc)
>diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c
>b/drivers/gpu/drm/msm/dp/dp_panel.c
>index 5149ceb..933fa9c 100644
>--- a/drivers/gpu/drm/msm/dp/dp_panel.c
>+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
>@@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
> link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
> link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
>
>+ /* Limit data lanes from data-lanes of endpoint properity of dtsi */
> if (link_info->num_lanes > dp_panel->max_dp_lanes)
> link_info->num_lanes = dp_panel->max_dp_lanes;
>
>- /* Limit support upto HBR2 until HBR3 support is added */
>- if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4)))
>- link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4);
>+ /* Limit link rate from link-frequencies of endpoint properity of dtsi
>*/
>+ if (link_info->rate > dp_panel->max_dp_link_rate)
>+ link_info->rate = dp_panel->max_dp_link_rate;
>
> drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor);
> drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate);
>diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h
>b/drivers/gpu/drm/msm/dp/dp_panel.h
>index d861197a..f04d021 100644
>--- a/drivers/gpu/drm/msm/dp/dp_panel.h
>+++ b/drivers/gpu/drm/msm/dp/dp_panel.h
>@@ -50,6 +50,7 @@ struct dp_panel {
>
> u32 vic;
> u32 max_dp_lanes;
>+ u32 max_dp_link_rate;
>
> u32 max_bw_code;
> };
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH v8 4/5] drm/msm/dp: parser link-frequencies as property of dp_out endpoint
On 5 December 2022 22:14:29 GMT+03:00, Kuogee Hsieh
wrote:
>Add capability to parser and retrieve max DP link supported rate from
>link-frequencies property of dp_out endpoint.
>
>Changes in v6:
>-- second patch after split parser patch into two patches
>
>Changes in v7:
>-- without checking cnt against DP_MAX_NUM_DP_LANES to retrieve link rate
>
>Signed-off-by: Kuogee Hsieh
>---
> drivers/gpu/drm/msm/dp/dp_parser.c | 19 +--
> drivers/gpu/drm/msm/dp/dp_parser.h | 2 ++
> 2 files changed, 19 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c
>b/drivers/gpu/drm/msm/dp/dp_parser.c
>index b5f7e70..037dad8 100644
>--- a/drivers/gpu/drm/msm/dp/dp_parser.c
>+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
>@@ -94,15 +94,28 @@ static int dp_parser_ctrl_res(struct dp_parser *parser)
> static int dp_parser_misc(struct dp_parser *parser)
> {
> struct device_node *of_node = parser->pdev->dev.of_node;
>+ struct device_node *endpoint;
>+ u64 frequency;
> int cnt;
>
> /*
>* data-lanes is the property of dp_out endpoint
>*/
> cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1,
> DP_MAX_NUM_DP_LANES);
>- if (cnt > 0)
>+ if (cnt > 0) {
> parser->max_dp_lanes = cnt;
>- else {
>+
>+ endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /*
>port@1 */
>+ cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
Missing of_node_put()
>+ if (cnt > 0) {
>+ of_property_read_u64_index(endpoint, "link-frequencies",
>+ cnt - 1, );
>+ frequency /= 10;/* from symbol rate to link
>rate */
>+ parser->max_dp_link_rate = (frequency / 1000); /* kbits
>*/
>+ } else {
>+ parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 54
>khz */
>+ }
>+ } else {
> /*
>* legacy code, data-lanes is the property of mdss_dp node
>*/
>@@ -111,6 +124,8 @@ static int dp_parser_misc(struct dp_parser *parser)
> parser->max_dp_lanes = cnt;
> else
> parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes
> */
>+
>+ parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 54 khz */
Please, don't mix the dp lanes and dp link rate code. It would be much easier
to read. And you can remove the duplicate assignment statements too.
> }
>
> return 0;
>diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h
>b/drivers/gpu/drm/msm/dp/dp_parser.h
>index 866c1a8..3ddf639 100644
>--- a/drivers/gpu/drm/msm/dp/dp_parser.h
>+++ b/drivers/gpu/drm/msm/dp/dp_parser.h
>@@ -15,6 +15,7 @@
> #define DP_LABEL "MDSS DP DISPLAY"
> #define DP_MAX_PIXEL_CLK_KHZ 675000
> #define DP_MAX_NUM_DP_LANES 4
>+#define DP_LINK_RATE_HBR2 54
>
> enum dp_pm_type {
> DP_CORE_PM,
>@@ -119,6 +120,7 @@ struct dp_parser {
> struct dp_io io;
> struct dp_display_data disp_data;
> u32 max_dp_lanes;
>+ u32 max_dp_link_rate;
> struct drm_bridge *next_bridge;
>
> int (*parse)(struct dp_parser *parser);
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH v8 1/5] arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpoint
On 5 December 2022 22:14:26 GMT+03:00, Kuogee Hsieh
wrote:
>Move data-lanes property from mdss_dp node to dp_out endpoint. Also
>add link-frequencies property into dp_out endpoint as well. The last
>frequency specified at link-frequencies will be the max link rate
>supported by DP.
>
>Changes in v5:
>-- revert changes at sc7180.dtsi and sc7280.dtsi
>-- add _out to sc7180-trogdor.dtsi and sc7280-herobrine.dtsi
>
>Changes in v6:
>-- add data-lanes and link-frequencies to yaml
>
>Changes in v7:
>-- change 16000 to 162000
>-- separate yaml to different patch
>
>Changes in v8:
>-- correct Bjorn mail address to kernel.org
>
>Signed-off-by: Kuogee Hsieh
>---
> arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 6 +-
> arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 +-
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
>diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
>b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
>index eae22e6..0ad50e2 100644
>--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
>+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
>@@ -814,7 +814,11 @@ hp_i2c: {
> status = "okay";
> pinctrl-names = "default";
> pinctrl-0 = <_hot_plug_det>;
>- data-lanes = <0 1>;
>+};
>+
>+_out {
>+data-lanes = <0 1>;
>+link-frequencies = /bits/ 64 <16200 27000 54000>;
This property still uses old values, it was not updated to Hz.
> };
>
> _adc {
>diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
>b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
>index c11e371..3c7a9d8 100644
>--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
>+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
>@@ -442,7 +442,11 @@ ap_i2c_tpm: {
> status = "okay";
> pinctrl-names = "default";
> pinctrl-0 = <_hot_plug_det>;
>- data-lanes = <0 1>;
>+};
>+
>+_out {
>+ data-lanes = <0 1>;
>+ link-frequencies = /bits/ 64 <162000 27 54
>81>;
> };
>
> _mdp {
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH v8 3/5] drm/msm/dp: parser data-lanes as property of dp_out endpoint
On 5 December 2022 22:14:28 GMT+03:00, Kuogee Hsieh wrote: >Add capability to parser data-lanes as property of dp_out endpoint. >Also retain the original capability to parser data-lanes as property >of mdss_dp node to handle legacy case. > >Changes in v6: >-- first patch after split parser patch into two > >Changes in v7: >-- check "data-lanes" from endpoint first > >Signed-off-by: Kuogee Hsieh Reviewed-by: Dmitry Baryshkov >--- -- With best wishes Dmitry
Re: [Freedreno] [PATCH v4 13/13] arm64: dts: qcom: sa8295-adp: Enable DP instances
On 05/12/2022 21:02, Bjorn Andersson wrote:
On Mon, Dec 05, 2022 at 07:09:45PM +0100, Konrad Dybcio wrote:
On 05/12/2022 18:44, Bjorn Andersson wrote:
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
[..]
+_dp2 {
+ status = "okay";
status should go last.
Thanks for pointing that out. Would be nice if the computer told me
that...somehow...
+
+ data-lanes = <0 1 2 3>;
+
+ ports {
+ port@1 {
+ reg = <1>;
+ mdss0_dp2_phy_out: endpoint {
That's quite a lot of indentation.. couldn't these endpoints be defined in
the SoC DT?
The alternative would be to have the description of each DP controller
split over multiple nodes and rely on the reader to stitch together the
view of the node based on the label.
Based on the naming of these labels they would at least be adjacent, so
it wouldn't be that bad.
But I feel that there is enough DP-controller nodes in this board
already; I've yet to describe the two USB Type-C controllers or the two
DSI-DP bridges.
So I don't know if it's worth optimizing indentation-level within each
node like this.
And we will end up mixing this optimization between DP controllers, USB
Type-C nodes, QMP nodes, DSI-DP bridges.
Oh okay, I see, let's keep it as-is then.
Konrad
Regards,
Bjorn
Re: [Freedreno] [PATCH v4 13/13] arm64: dts: qcom: sa8295-adp: Enable DP instances
On Mon, Dec 05, 2022 at 07:09:45PM +0100, Konrad Dybcio wrote:
> On 05/12/2022 18:44, Bjorn Andersson wrote:
> > diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
> > b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
[..]
> > +_dp2 {
> > + status = "okay";
> status should go last.
>
Thanks for pointing that out. Would be nice if the computer told me
that...somehow...
> > +
> > + data-lanes = <0 1 2 3>;
> > +
> > + ports {
> > + port@1 {
> > + reg = <1>;
> > + mdss0_dp2_phy_out: endpoint {
> That's quite a lot of indentation.. couldn't these endpoints be defined in
> the SoC DT?
>
The alternative would be to have the description of each DP controller
split over multiple nodes and rely on the reader to stitch together the
view of the node based on the label.
Based on the naming of these labels they would at least be adjacent, so
it wouldn't be that bad.
But I feel that there is enough DP-controller nodes in this board
already; I've yet to describe the two USB Type-C controllers or the two
DSI-DP bridges.
So I don't know if it's worth optimizing indentation-level within each
node like this.
And we will end up mixing this optimization between DP controllers, USB
Type-C nodes, QMP nodes, DSI-DP bridges.
Regards,
Bjorn
Re: [Freedreno] [PATCH v4 08/18] dt-bindings: msm: dsi-controller-main: Add vdd* descriptions back in
On Fri, 25 Nov 2022 12:36:28 +, Bryan O'Donoghue wrote:
> When converting from .txt to .yaml we didn't include descriptions for the
> existing regulator supplies.
>
> - vdd
> - vdda
> - vddio
>
> Add those descriptions into the yaml now as they were prior to the
> conversion. In the .txt description we marked these regulators as required,
> however, that requirement appears to have been in error.
>
> Taking the example of sc7180-trogdor-wormdingler.dtsi. The avdd and avee
> come from GPIO controlled external regulators, not the SoC and in this case
> there's no need for vddio to power an I/O bus. Similarly the regulators for
> the LCD are controlled by the panel driver not by the dsi-ctrl driver.
>
> It would be possible to connect a different type of panel to the DSI bus
> here in which case we may or may not want to make use of vdd, vdda or
> vddio.
>
> This is also the case for older chipsets like apq8064, msm8916 etc the vdd*
> regulators in the dsi-ctrl block are helpers not dependencies.
>
> Add the description of vdd, vdda and vddio back in for the existing
> upstream dts where vdd, vdda or vddio are already declared but, don't
> declare those regulators required - they are not SoC requirements.
>
> Fixes: 4dbe55c97741 ("dt-bindings: msm: dsi: add yaml schemas for DSI
> bindings")
> Signed-off-by: Bryan O'Donoghue
> ---
> .../bindings/display/msm/dsi-controller-main.yaml| 12
> 1 file changed, 12 insertions(+)
>
Acked-by: Rob Herring
Re: [Freedreno] [PATCH v4 07/18] dt-bindings: msm: dsi-controller-main: Fix clock declarations
On Fri, 25 Nov 2022 12:36:27 +, Bryan O'Donoghue wrote:
> When converting from .txt to .yaml dt-binding descriptions we appear to
> have missed some of the previous detail on the number and names of
> permissible clocks.
>
> Fix this by listing the clock descriptions against the clock names at a
> high level.
>
> Fixes: 4dbe55c97741 ("dt-bindings: msm: dsi: add yaml schemas for DSI
> bindings")
> Signed-off-by: Bryan O'Donoghue
> ---
> .../display/msm/dsi-controller-main.yaml | 20 ---
> 1 file changed, 13 insertions(+), 7 deletions(-)
>
Acked-by: Rob Herring
Re: [Freedreno] [PATCH v4 05/18] dt-bindings: msm: dsi-controller-main: Document clocks on a per compatible basis
On Fri, 25 Nov 2022 12:36:25 +, Bryan O'Donoghue wrote: > Each compatible has a different set of clocks which are associated with it. > Add in the list of clocks for each compatible. > > Signed-off-by: Bryan O'Donoghue > --- > .../display/msm/dsi-controller-main.yaml | 152 -- > 1 file changed, 142 insertions(+), 10 deletions(-) > Acked-by: Rob Herring
Re: [Freedreno] [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells
Hi Robert,
On 5.12.22 18:37, Robert Foss wrote:
Use two interconnect cells in order to optionally
support a path tag.
Signed-off-by: Robert Foss
Reviewed-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 805d53d91952..434f8e8b12c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1543,56 +1543,56 @@ apps_smmu: iommu@1500 {
config_noc: interconnect@150 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x0150 0 0xa580>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <_bcm_voter>;
};
mc_virt: interconnect@158 {
compatible = "qcom,sm8350-mc-virt";
reg = <0 0x0158 0 0x1000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <_bcm_voter>;
};
[..]
@@ -1620,8 +1620,8 @@ ipa: ipa@1e4 {
clocks = < RPMH_IPA_CLK>;
clock-names = "core";
- interconnects = <_noc MASTER_IPA _virt SLAVE_EBI1>,
- <_noc MASTER_APPSS_PROC _noc
SLAVE_IPA_CFG>;
+ interconnects = <_noc MASTER_IPA 0 _virt
SLAVE_EBI1 0>,
+ <_noc MASTER_APPSS_PROC 0 _noc
SLAVE_IPA_CFG 0>;
interconnect-names = "memory",
"config";
@@ -1661,7 +1661,7 @@ mpss: remoteproc@408 {
< SM8350_MSS>;
power-domain-names = "cx", "mss";
- interconnects = <_virt MASTER_LLCC _virt SLAVE_EBI1>;
+ interconnects = <_virt MASTER_LLCC _virt SLAVE_EBI1
0>;
The second cell for the first endpoint is missing, so this should be:
interconnects = <_virt MASTER_LLCC 0 _virt SLAVE_EBI1 0>;
Thanks,
Georgi
memory-region = <_modem_mem>;
@@ -2239,7 +2239,7 @@ cdsp: remoteproc@9890 {
< SM8350_MXC>;
power-domain-names = "cx", "mxc";
- interconnects = <_noc MASTER_CDSP_PROC _virt SLAVE_EBI1>;
+ interconnects = <_noc MASTER_CDSP_PROC 0 _virt
SLAVE_EBI1 0>;
memory-region = <_cdsp_mem>;
@@ -2421,14 +2421,14 @@ usb_2_ssphy: phy@88ebe00 {
dc_noc: interconnect@90c {
compatible = "qcom,sm8350-dc-noc";
reg = <0 0x090c 0 0x4200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <_bcm_voter>;
};
gem_noc: interconnect@910 {
compatible = "qcom,sm8350-gem-noc";
reg = <0 0x0910 0 0xb4000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <_bcm_voter>;
};
[Freedreno] [PATCH v8 5/5] drm/msm/dp: add support of max dp link rate
By default, HBR2 (5.4G) is the max link link be supported. This patch add
the capability to support max link rate at HBR3 (8.1G).
Changes in v2:
-- add max link rate from dtsi
Changes in v3:
-- parser max_data_lanes and max_dp_link_rate from dp_out endpoint
Changes in v4:
-- delete unnecessary pr_err
Changes in v5:
-- split parser function into different patch
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_display.c | 4
drivers/gpu/drm/msm/dp/dp_panel.c | 7 ---
drivers/gpu/drm/msm/dp/dp_panel.h | 1 +
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index bfd0aef..edee550 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct
dp_display_private *dp)
struct edid *edid;
dp->panel->max_dp_lanes = dp->parser->max_dp_lanes;
+ dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate;
+
+ drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n",
+ dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate);
rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector);
if (rc)
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c
b/drivers/gpu/drm/msm/dp/dp_panel.c
index 5149ceb..933fa9c 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
+ /* Limit data lanes from data-lanes of endpoint properity of dtsi */
if (link_info->num_lanes > dp_panel->max_dp_lanes)
link_info->num_lanes = dp_panel->max_dp_lanes;
- /* Limit support upto HBR2 until HBR3 support is added */
- if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4)))
- link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4);
+ /* Limit link rate from link-frequencies of endpoint properity of dtsi
*/
+ if (link_info->rate > dp_panel->max_dp_link_rate)
+ link_info->rate = dp_panel->max_dp_link_rate;
drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor);
drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate);
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h
b/drivers/gpu/drm/msm/dp/dp_panel.h
index d861197a..f04d021 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.h
+++ b/drivers/gpu/drm/msm/dp/dp_panel.h
@@ -50,6 +50,7 @@ struct dp_panel {
u32 vic;
u32 max_dp_lanes;
+ u32 max_dp_link_rate;
u32 max_bw_code;
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v8 4/5] drm/msm/dp: parser link-frequencies as property of dp_out endpoint
Add capability to parser and retrieve max DP link supported rate from
link-frequencies property of dp_out endpoint.
Changes in v6:
-- second patch after split parser patch into two patches
Changes in v7:
-- without checking cnt against DP_MAX_NUM_DP_LANES to retrieve link rate
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_parser.c | 19 +--
drivers/gpu/drm/msm/dp/dp_parser.h | 2 ++
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c
b/drivers/gpu/drm/msm/dp/dp_parser.c
index b5f7e70..037dad8 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.c
+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
@@ -94,15 +94,28 @@ static int dp_parser_ctrl_res(struct dp_parser *parser)
static int dp_parser_misc(struct dp_parser *parser)
{
struct device_node *of_node = parser->pdev->dev.of_node;
+ struct device_node *endpoint;
+ u64 frequency;
int cnt;
/*
* data-lanes is the property of dp_out endpoint
*/
cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1,
DP_MAX_NUM_DP_LANES);
- if (cnt > 0)
+ if (cnt > 0) {
parser->max_dp_lanes = cnt;
- else {
+
+ endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /*
port@1 */
+ cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
+ if (cnt > 0) {
+ of_property_read_u64_index(endpoint, "link-frequencies",
+ cnt - 1, );
+ frequency /= 10;/* from symbol rate to link
rate */
+ parser->max_dp_link_rate = (frequency / 1000); /* kbits
*/
+ } else {
+ parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 54
khz */
+ }
+ } else {
/*
* legacy code, data-lanes is the property of mdss_dp node
*/
@@ -111,6 +124,8 @@ static int dp_parser_misc(struct dp_parser *parser)
parser->max_dp_lanes = cnt;
else
parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes
*/
+
+ parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 54 khz */
}
return 0;
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h
b/drivers/gpu/drm/msm/dp/dp_parser.h
index 866c1a8..3ddf639 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.h
+++ b/drivers/gpu/drm/msm/dp/dp_parser.h
@@ -15,6 +15,7 @@
#define DP_LABEL "MDSS DP DISPLAY"
#define DP_MAX_PIXEL_CLK_KHZ 675000
#define DP_MAX_NUM_DP_LANES4
+#define DP_LINK_RATE_HBR2 54
enum dp_pm_type {
DP_CORE_PM,
@@ -119,6 +120,7 @@ struct dp_parser {
struct dp_io io;
struct dp_display_data disp_data;
u32 max_dp_lanes;
+ u32 max_dp_link_rate;
struct drm_bridge *next_bridge;
int (*parse)(struct dp_parser *parser);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v8 3/5] drm/msm/dp: parser data-lanes as property of dp_out endpoint
Add capability to parser data-lanes as property of dp_out endpoint.
Also retain the original capability to parser data-lanes as property
of mdss_dp node to handle legacy case.
Changes in v6:
-- first patch after split parser patch into two
Changes in v7:
-- check "data-lanes" from endpoint first
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_parser.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c
b/drivers/gpu/drm/msm/dp/dp_parser.c
index dd73221..b5f7e70 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.c
+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
@@ -94,16 +94,25 @@ static int dp_parser_ctrl_res(struct dp_parser *parser)
static int dp_parser_misc(struct dp_parser *parser)
{
struct device_node *of_node = parser->pdev->dev.of_node;
- int len;
-
- len = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
- if (len < 0) {
- DRM_WARN("Invalid property \"data-lanes\", default max DP lanes
= %d\n",
-DP_MAX_NUM_DP_LANES);
- len = DP_MAX_NUM_DP_LANES;
+ int cnt;
+
+ /*
+* data-lanes is the property of dp_out endpoint
+*/
+ cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1,
DP_MAX_NUM_DP_LANES);
+ if (cnt > 0)
+ parser->max_dp_lanes = cnt;
+ else {
+ /*
+* legacy code, data-lanes is the property of mdss_dp node
+*/
+ cnt = drm_of_get_data_lanes_count(of_node, 1,
DP_MAX_NUM_DP_LANES);
+ if (cnt > 0)
+ parser->max_dp_lanes = cnt;
+ else
+ parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes
*/
}
- parser->max_dp_lanes = len;
return 0;
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v8 2/5] dt-bindings: msm/dp: add data-lanes and link-frequencies property
Add both data-lanes and link-frequencies property into endpoint
Changes in v7:
-- split yaml out of dtsi patch
-- link-frequencies from link rate to symbol rate
-- deprecation of old data-lanes property
Changes in v8:
-- correct Bjorn mail address to kernel.org
Signed-off-by: Kuogee Hsieh
---
.../bindings/display/msm/dp-controller.yaml| 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index f2515af..13d2c3c 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -79,12 +79,6 @@ properties:
aux-bus:
$ref: /schemas/display/dp-aux-bus.yaml#
- data-lanes:
-$ref: /schemas/types.yaml#/definitions/uint32-array
-minItems: 1
-maxItems: 4
-items:
- maximum: 3
"#sound-dai-cells":
const: 0
@@ -105,6 +99,19 @@ properties:
$ref: /schemas/graph.yaml#/properties/port
description: Output endpoint of the controller
+properties:
+ endpoint:
+$ref: /schemas/media/video-interfaces.yaml#
+
+ properties:
+data-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+link-frequencies:
+ $ref: /schemas/types.yaml#/definitions/uint64-array
+
+ additionalProperties: false
+
required:
- compatible
- reg
@@ -193,6 +200,9 @@ examples:
reg = <1>;
endpoint {
remote-endpoint = <>;
+data-lanes = <1 2>;
+link-frequencies = /bits/ 64 <162000 27
+ 54 81>;
};
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v8 1/5] arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpoint
Move data-lanes property from mdss_dp node to dp_out endpoint. Also
add link-frequencies property into dp_out endpoint as well. The last
frequency specified at link-frequencies will be the max link rate
supported by DP.
Changes in v5:
-- revert changes at sc7180.dtsi and sc7280.dtsi
-- add _out to sc7180-trogdor.dtsi and sc7280-herobrine.dtsi
Changes in v6:
-- add data-lanes and link-frequencies to yaml
Changes in v7:
-- change 16000 to 162000
-- separate yaml to different patch
Changes in v8:
-- correct Bjorn mail address to kernel.org
Signed-off-by: Kuogee Hsieh
---
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 6 +-
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index eae22e6..0ad50e2 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -814,7 +814,11 @@ hp_i2c: {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_hot_plug_det>;
- data-lanes = <0 1>;
+};
+
+_out {
+data-lanes = <0 1>;
+link-frequencies = /bits/ 64 <16200 27000 54000>;
};
_adc {
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index c11e371..3c7a9d8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -442,7 +442,11 @@ ap_i2c_tpm: {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_hot_plug_det>;
- data-lanes = <0 1>;
+};
+
+_out {
+ data-lanes = <0 1>;
+ link-frequencies = /bits/ 64 <162000 27 54
81>;
};
_mdp {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v8 0/5] Add data-lanes and link-frequencies to dp_out endpoint
Add DP both data-lanes and link-frequencies property to dp_out endpoint and support functions to DP driver. Kuogee Hsieh (5): arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpoint dt-bindings: msm/dp: add data-lanes and link-frequencies property drm/msm/dp: parser data-lanes as property of dp_out endpoint drm/msm/dp: parser link-frequencies as property of dp_out endpoint drm/msm/dp: add support of max dp link rate .../bindings/display/msm/dp-controller.yaml| 22 + arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 6 +++- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 +++- drivers/gpu/drm/msm/dp/dp_display.c| 4 +++ drivers/gpu/drm/msm/dp/dp_panel.c | 7 ++-- drivers/gpu/drm/msm/dp/dp_panel.h | 1 + drivers/gpu/drm/msm/dp/dp_parser.c | 38 ++ drivers/gpu/drm/msm/dp/dp_parser.h | 2 ++ 8 files changed, 68 insertions(+), 18 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [Freedreno] [PATCH v4 13/13] arm64: dts: qcom: sa8295-adp: Enable DP instances
On 05/12/2022 18:44, Bjorn Andersson wrote:
From: Bjorn Andersson
The SA8295P ADP has, among other interfaces, six MiniDP connectors which
are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3.
Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers,
DP PHYs and link them all together.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v3:
- None
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 243 ++-
1 file changed, 241 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index 6c29d7d757e0..d55c8c5304cc 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -23,6 +23,90 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ dp2-connector {
+ compatible = "dp-connector";
+ label = "DP2";
+ type = "mini";
+
+ hpd-gpios = < 20 GPIO_ACTIVE_HIGH>;
+
+ port {
+ dp2_connector_in: endpoint {
+ remote-endpoint = <_dp0_phy_out>;
+ };
+ };
+ };
+
+ dp3-connector {
+ compatible = "dp-connector";
+ label = "DP3";
+ type = "mini";
+
+ hpd-gpios = < 45 GPIO_ACTIVE_HIGH>;
+
+ port {
+ dp3_connector_in: endpoint {
+ remote-endpoint = <_dp1_phy_out>;
+ };
+ };
+ };
+
+ edp0-connector {
+ compatible = "dp-connector";
+ label = "EDP0";
+ type = "mini";
+
+ hpd-gpios = < 2 GPIO_ACTIVE_HIGH>;
+
+ port {
+ edp0_connector_in: endpoint {
+ remote-endpoint = <_dp2_phy_out>;
+ };
+ };
+ };
+
+ edp1-connector {
+ compatible = "dp-connector";
+ label = "EDP1";
+ type = "mini";
+
+ hpd-gpios = < 3 GPIO_ACTIVE_HIGH>;
+
+ port {
+ edp1_connector_in: endpoint {
+ remote-endpoint = <_dp3_phy_out>;
+ };
+ };
+ };
+
+ edp2-connector {
+ compatible = "dp-connector";
+ label = "EDP2";
+ type = "mini";
+
+ hpd-gpios = < 7 GPIO_ACTIVE_HIGH>;
+
+ port {
+ edp2_connector_in: endpoint {
+ remote-endpoint = <_dp2_phy_out>;
+ };
+ };
+ };
+
+ edp3-connector {
+ compatible = "dp-connector";
+ label = "EDP3";
+ type = "mini";
+
+ hpd-gpios = < 6 GPIO_ACTIVE_HIGH>;
+
+ port {
+ edp3_connector_in: endpoint {
+ remote-endpoint = <_dp3_phy_out>;
+ };
+ };
+ };
};
_rsc {
@@ -163,13 +247,168 @@ vreg_l7g: ldo7 {
vreg_l8g: ldo8 {
regulator-name = "vreg_l8g";
- regulator-min-microvolt = <88>;
- regulator-max-microvolt = <88>;
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = ;
+ };
+
+ vreg_l11g: ldo11 {
+ regulator-name = "vreg_l11g";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
regulator-initial-mode = ;
};
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_dp2 {
+ status = "okay";
status should go last.
+
+ data-lanes = <0 1 2 3>;
+
+ ports {
+ port@1 {
+ reg = <1>;
+ mdss0_dp2_phy_out: endpoint {
That's quite a lot of indentation.. couldn't these endpoints be defined
in the SoC DT?
Konrad
+ remote-endpoint = <_connector_in>;
+ };
+ };
+ };
+};
+
+_dp2_phy {
+ status = "okay";
+
+ vdda-phy-supply = <_l8g>;
+ vdda-pll-supply = <_l3g>;
+};
+
+_dp3 {
+ status = "okay";
+
+ data-lanes = <0 1 2 3>;
+
+ ports {
+ port@1 {
+ reg = <1>;
+ mdss0_dp3_phy_out: endpoint {
+ remote-endpoint = <_connector_in>;
+ };
+ };
+ };
+};
+
+_dp3_phy {
+ status = "okay";
[Freedreno] [PATCH v7 5/5] drm/msm/dp: add support of max dp link rate
By default, HBR2 (5.4G) is the max link link be supported. This patch add
the capability to support max link rate at HBR3 (8.1G).
Changes in v2:
-- add max link rate from dtsi
Changes in v3:
-- parser max_data_lanes and max_dp_link_rate from dp_out endpoint
Changes in v4:
-- delete unnecessary pr_err
Changes in v5:
-- split parser function into different patch
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dp/dp_display.c | 4
drivers/gpu/drm/msm/dp/dp_panel.c | 7 ---
drivers/gpu/drm/msm/dp/dp_panel.h | 1 +
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index bfd0aef..edee550 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -390,6 +390,10 @@ static int dp_display_process_hpd_high(struct
dp_display_private *dp)
struct edid *edid;
dp->panel->max_dp_lanes = dp->parser->max_dp_lanes;
+ dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate;
+
+ drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n",
+ dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate);
rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector);
if (rc)
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c
b/drivers/gpu/drm/msm/dp/dp_panel.c
index 5149ceb..933fa9c 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -75,12 +75,13 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
+ /* Limit data lanes from data-lanes of endpoint properity of dtsi */
if (link_info->num_lanes > dp_panel->max_dp_lanes)
link_info->num_lanes = dp_panel->max_dp_lanes;
- /* Limit support upto HBR2 until HBR3 support is added */
- if (link_info->rate >= (drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4)))
- link_info->rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_5_4);
+ /* Limit link rate from link-frequencies of endpoint properity of dtsi
*/
+ if (link_info->rate > dp_panel->max_dp_link_rate)
+ link_info->rate = dp_panel->max_dp_link_rate;
drm_dbg_dp(panel->drm_dev, "version: %d.%d\n", major, minor);
drm_dbg_dp(panel->drm_dev, "link_rate=%d\n", link_info->rate);
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h
b/drivers/gpu/drm/msm/dp/dp_panel.h
index d861197a..f04d021 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.h
+++ b/drivers/gpu/drm/msm/dp/dp_panel.h
@@ -50,6 +50,7 @@ struct dp_panel {
u32 vic;
u32 max_dp_lanes;
+ u32 max_dp_link_rate;
u32 max_bw_code;
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v7 4/5] drm/msm/dp: parser link-frequencies as property of dp_out endpoint
Add capability to parser and retrieve max DP link supported rate from
link-frequencies property of dp_out endpoint.
Changes in v6:
-- second patch after split parser patch into two patches
Changes in v7:
-- without checking cnt against DP_MAX_NUM_DP_LANES to retrieve link rate
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_parser.c | 19 +--
drivers/gpu/drm/msm/dp/dp_parser.h | 2 ++
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c
b/drivers/gpu/drm/msm/dp/dp_parser.c
index b5f7e70..037dad8 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.c
+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
@@ -94,15 +94,28 @@ static int dp_parser_ctrl_res(struct dp_parser *parser)
static int dp_parser_misc(struct dp_parser *parser)
{
struct device_node *of_node = parser->pdev->dev.of_node;
+ struct device_node *endpoint;
+ u64 frequency;
int cnt;
/*
* data-lanes is the property of dp_out endpoint
*/
cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1,
DP_MAX_NUM_DP_LANES);
- if (cnt > 0)
+ if (cnt > 0) {
parser->max_dp_lanes = cnt;
- else {
+
+ endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /*
port@1 */
+ cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
+ if (cnt > 0) {
+ of_property_read_u64_index(endpoint, "link-frequencies",
+ cnt - 1, );
+ frequency /= 10;/* from symbol rate to link
rate */
+ parser->max_dp_link_rate = (frequency / 1000); /* kbits
*/
+ } else {
+ parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 54
khz */
+ }
+ } else {
/*
* legacy code, data-lanes is the property of mdss_dp node
*/
@@ -111,6 +124,8 @@ static int dp_parser_misc(struct dp_parser *parser)
parser->max_dp_lanes = cnt;
else
parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes
*/
+
+ parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 54 khz */
}
return 0;
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h
b/drivers/gpu/drm/msm/dp/dp_parser.h
index 866c1a8..3ddf639 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.h
+++ b/drivers/gpu/drm/msm/dp/dp_parser.h
@@ -15,6 +15,7 @@
#define DP_LABEL "MDSS DP DISPLAY"
#define DP_MAX_PIXEL_CLK_KHZ 675000
#define DP_MAX_NUM_DP_LANES4
+#define DP_LINK_RATE_HBR2 54
enum dp_pm_type {
DP_CORE_PM,
@@ -119,6 +120,7 @@ struct dp_parser {
struct dp_io io;
struct dp_display_data disp_data;
u32 max_dp_lanes;
+ u32 max_dp_link_rate;
struct drm_bridge *next_bridge;
int (*parse)(struct dp_parser *parser);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v7 3/5] drm/msm/dp: parser data-lanes as property of dp_out endpoint
Add capability to parser data-lanes as property of dp_out endpoint.
Also retain the original capability to parser data-lanes as property
of mdss_dp node to handle legacy case.
Changes in v6:
-- first patch after split parser patch into two
Changes in v7:
-- check "data-lanes" from endpoint first
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_parser.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c
b/drivers/gpu/drm/msm/dp/dp_parser.c
index dd73221..b5f7e70 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.c
+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
@@ -94,16 +94,25 @@ static int dp_parser_ctrl_res(struct dp_parser *parser)
static int dp_parser_misc(struct dp_parser *parser)
{
struct device_node *of_node = parser->pdev->dev.of_node;
- int len;
-
- len = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
- if (len < 0) {
- DRM_WARN("Invalid property \"data-lanes\", default max DP lanes
= %d\n",
-DP_MAX_NUM_DP_LANES);
- len = DP_MAX_NUM_DP_LANES;
+ int cnt;
+
+ /*
+* data-lanes is the property of dp_out endpoint
+*/
+ cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1,
DP_MAX_NUM_DP_LANES);
+ if (cnt > 0)
+ parser->max_dp_lanes = cnt;
+ else {
+ /*
+* legacy code, data-lanes is the property of mdss_dp node
+*/
+ cnt = drm_of_get_data_lanes_count(of_node, 1,
DP_MAX_NUM_DP_LANES);
+ if (cnt > 0)
+ parser->max_dp_lanes = cnt;
+ else
+ parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes
*/
}
- parser->max_dp_lanes = len;
return 0;
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v7 2/5] dt-bindings: msm/dp: add data-lanes and link-frequencies property
Add both data-lanes and link-frequencies property into endpoint
changes in v7:
-- split yaml out of dtsi patch
-- link-frequencies from link rate to symbol rate
-- deprecation of old data-lanes property
Signed-off-by: Kuogee Hsieh
---
.../bindings/display/msm/dp-controller.yaml| 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index f2515af..13d2c3c 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -79,12 +79,6 @@ properties:
aux-bus:
$ref: /schemas/display/dp-aux-bus.yaml#
- data-lanes:
-$ref: /schemas/types.yaml#/definitions/uint32-array
-minItems: 1
-maxItems: 4
-items:
- maximum: 3
"#sound-dai-cells":
const: 0
@@ -105,6 +99,19 @@ properties:
$ref: /schemas/graph.yaml#/properties/port
description: Output endpoint of the controller
+properties:
+ endpoint:
+$ref: /schemas/media/video-interfaces.yaml#
+
+ properties:
+data-lanes:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+link-frequencies:
+ $ref: /schemas/types.yaml#/definitions/uint64-array
+
+ additionalProperties: false
+
required:
- compatible
- reg
@@ -193,6 +200,9 @@ examples:
reg = <1>;
endpoint {
remote-endpoint = <>;
+data-lanes = <1 2>;
+link-frequencies = /bits/ 64 <162000 27
+ 54 81>;
};
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v7 1/5] arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpoint
Move data-lanes property from mdss_dp node to dp_out endpoint. Also
add link-frequencies property into dp_out endpoint as well. The last
frequency specified at link-frequencies will be the max link rate
supported by DP.
Changes in v5:
-- revert changes at sc7180.dtsi and sc7280.dtsi
-- add _out to sc7180-trogdor.dtsi and sc7280-herobrine.dtsi
Changes in v6:
-- add data-lanes and link-frequencies to yaml
Changes in v7:
-- change 16000 to 162000
-- separate yaml to different patch
Signed-off-by: Kuogee Hsieh
---
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 6 +-
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index eae22e6..0ad50e2 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -814,7 +814,11 @@ hp_i2c: {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_hot_plug_det>;
- data-lanes = <0 1>;
+};
+
+_out {
+data-lanes = <0 1>;
+link-frequencies = /bits/ 64 <16200 27000 54000>;
};
_adc {
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index c11e371..3c7a9d8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -442,7 +442,11 @@ ap_i2c_tpm: {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_hot_plug_det>;
- data-lanes = <0 1>;
+};
+
+_out {
+ data-lanes = <0 1>;
+ link-frequencies = /bits/ 64 <162000 27 54
81>;
};
_mdp {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[Freedreno] [PATCH v7 0/5] Add data-lanes and link-frequencies to dp_out endpoint
Add DP both data-lanes and link-frequencies property to dp_out endpoint and support functions to DP driver. Kuogee Hsieh (5): arm64: dts: qcom: add data-lanes and link-freuencies into dp_out endpoint dt-bindings: msm/dp: add data-lanes and link-frequencies property drm/msm/dp: parser data-lanes as property of dp_out endpoint drm/msm/dp: parser link-frequencies as property of dp_out endpoint drm/msm/dp: add support of max dp link rate .../bindings/display/msm/dp-controller.yaml| 22 + arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 6 +++- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 +++- drivers/gpu/drm/msm/dp/dp_display.c| 4 +++ drivers/gpu/drm/msm/dp/dp_panel.c | 7 ++-- drivers/gpu/drm/msm/dp/dp_panel.h | 1 + drivers/gpu/drm/msm/dp/dp_parser.c | 38 ++ drivers/gpu/drm/msm/dp/dp_parser.h | 2 ++ 8 files changed, 68 insertions(+), 18 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
[Freedreno] [PATCH v4 13/13] arm64: dts: qcom: sa8295-adp: Enable DP instances
From: Bjorn Andersson
The SA8295P ADP has, among other interfaces, six MiniDP connectors which
are connected to MDSS0 DP2 and DP3, and MDSS1 DP0 through DP3.
Enable Display Clock controllers, MDSS instanced, MDPs, DP controllers,
DP PHYs and link them all together.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v3:
- None
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 243 ++-
1 file changed, 241 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index 6c29d7d757e0..d55c8c5304cc 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -23,6 +23,90 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ dp2-connector {
+ compatible = "dp-connector";
+ label = "DP2";
+ type = "mini";
+
+ hpd-gpios = < 20 GPIO_ACTIVE_HIGH>;
+
+ port {
+ dp2_connector_in: endpoint {
+ remote-endpoint = <_dp0_phy_out>;
+ };
+ };
+ };
+
+ dp3-connector {
+ compatible = "dp-connector";
+ label = "DP3";
+ type = "mini";
+
+ hpd-gpios = < 45 GPIO_ACTIVE_HIGH>;
+
+ port {
+ dp3_connector_in: endpoint {
+ remote-endpoint = <_dp1_phy_out>;
+ };
+ };
+ };
+
+ edp0-connector {
+ compatible = "dp-connector";
+ label = "EDP0";
+ type = "mini";
+
+ hpd-gpios = < 2 GPIO_ACTIVE_HIGH>;
+
+ port {
+ edp0_connector_in: endpoint {
+ remote-endpoint = <_dp2_phy_out>;
+ };
+ };
+ };
+
+ edp1-connector {
+ compatible = "dp-connector";
+ label = "EDP1";
+ type = "mini";
+
+ hpd-gpios = < 3 GPIO_ACTIVE_HIGH>;
+
+ port {
+ edp1_connector_in: endpoint {
+ remote-endpoint = <_dp3_phy_out>;
+ };
+ };
+ };
+
+ edp2-connector {
+ compatible = "dp-connector";
+ label = "EDP2";
+ type = "mini";
+
+ hpd-gpios = < 7 GPIO_ACTIVE_HIGH>;
+
+ port {
+ edp2_connector_in: endpoint {
+ remote-endpoint = <_dp2_phy_out>;
+ };
+ };
+ };
+
+ edp3-connector {
+ compatible = "dp-connector";
+ label = "EDP3";
+ type = "mini";
+
+ hpd-gpios = < 6 GPIO_ACTIVE_HIGH>;
+
+ port {
+ edp3_connector_in: endpoint {
+ remote-endpoint = <_dp3_phy_out>;
+ };
+ };
+ };
};
_rsc {
@@ -163,13 +247,168 @@ vreg_l7g: ldo7 {
vreg_l8g: ldo8 {
regulator-name = "vreg_l8g";
- regulator-min-microvolt = <88>;
- regulator-max-microvolt = <88>;
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = ;
+ };
+
+ vreg_l11g: ldo11 {
+ regulator-name = "vreg_l11g";
+ regulator-min-microvolt = <912000>;
+ regulator-max-microvolt = <912000>;
regulator-initial-mode = ;
};
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_dp2 {
+ status = "okay";
+
+ data-lanes = <0 1 2 3>;
+
+ ports {
+ port@1 {
+ reg = <1>;
+ mdss0_dp2_phy_out: endpoint {
+ remote-endpoint = <_connector_in>;
+ };
+ };
+ };
+};
+
+_dp2_phy {
+ status = "okay";
+
+ vdda-phy-supply = <_l8g>;
+ vdda-pll-supply = <_l3g>;
+};
+
+_dp3 {
+ status = "okay";
+
+ data-lanes = <0 1 2 3>;
+
+ ports {
+ port@1 {
+ reg = <1>;
+ mdss0_dp3_phy_out: endpoint {
+ remote-endpoint = <_connector_in>;
+ };
+ };
+ };
+};
+
+_dp3_phy {
+ status = "okay";
+
+ vdda-phy-supply = <_l8g>;
+ vdda-pll-supply = <_l3g>;
+};
+
+ {
+ status = "okay";
+};
+
+_dp0 {
+ status = "okay";
+
+ data-lanes = <0 1
[Freedreno] [PATCH v4 11/13] arm64: dts: qcom: sc8280xp: Define some of the display blocks
From: Bjorn Andersson
Define the display clock controllers, the MDSS instances, the DP phys
and connect these together.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
I did not add the USB-related DP controllers back into this patch. Will send
that separately once I've validated those again.
Changes since v3:
- None
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 838 +
1 file changed, 838 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 9f3132ac2857..c2f186495506 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4,6 +4,7 @@
* Copyright (c) 2022, Linaro Limited
*/
+#include
#include
#include
#include
@@ -1698,6 +1699,44 @@ usb_1_qmpphy: phy@8903000 {
status = "disabled";
};
+ mdss1_dp0_phy: phy@8909a00 {
+ compatible = "qcom,sc8280xp-dp-phy";
+ reg = <0 0x08909a00 0 0x19c>,
+ <0 0x08909200 0 0xec>,
+ <0 0x08909600 0 0xec>,
+ <0 0x08909000 0 0x1c8>;
+
+ clocks = < DISP_CC_MDSS_DPTX0_AUX_CLK>,
+< DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+
+ power-domains = < SC8280XP_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss1_dp1_phy: phy@890ca00 {
+ compatible = "qcom,sc8280xp-dp-phy";
+ reg = <0 0x0890ca00 0 0x19c>,
+ <0 0x0890c200 0 0xec>,
+ <0 0x0890c600 0 0xec>,
+ <0 0x0890c000 0 0x1c8>;
+
+ clocks = < DISP_CC_MDSS_DPTX1_AUX_CLK>,
+< DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+
+ power-domains = < SC8280XP_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
system-cache-controller@920 {
compatible = "qcom,sc8280xp-llcc";
reg = <0 0x0920 0 0x58000>, <0 0x0960 0
0x58000>;
@@ -1813,6 +1852,326 @@ usb_1_dwc3: usb@a80 {
};
};
+ mdss0: display-subsystem@ae0 {
+ compatible = "qcom,sc8280xp-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = < MDSS_GDSC>;
+
+ clocks = < GCC_DISP_AHB_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface",
+ "ahb",
+ "core";
+
+ resets = < DISP_CC_MDSS_CORE_BCR>;
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interconnects = <_noc MASTER_MDP0 0 _virt
SLAVE_EBI1 0>,
+ <_noc MASTER_MDP1 0 _virt
SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ iommus = <_smmu 0x1000 0x402>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss0_mdp: display-controller@ae01000 {
+ compatible = "qcom,sc8280xp-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = < GCC_DISP_HF_AXI_CLK>,
+< GCC_DISP_SF_AXI_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< DISP_CC_MDSS_MDP_LUT_CLK>,
+< DISP_CC_MDSS_MDP_CLK>,
+< DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <
DISP_CC_MDSS_MDP_CLK>,
+
[Freedreno] [PATCH v4 12/13] arm64: dts: qcom: sc8280xp-crd: Enable EDP
From: Bjorn Andersson
The SC8280XP CRD has a EDP display on MDSS0 DP3, enable relevant nodes
and link it together with the backlight control.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v3:
- Added description of the regulator that powers the panel.
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 72 ++-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index f09810e3d956..a7d2384cbbe8 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -20,7 +20,7 @@ aliases {
serial0 = _uart17;
};
- backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
pwms = <_lpg 3 100>;
enable-gpios = <_1_gpios 8 GPIO_ACTIVE_HIGH>;
@@ -34,6 +34,22 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ vreg_edp_3p3: regulator-edp-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_EDP_3P3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+
+ gpio = < 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_en>;
+
+ regulator-boot-on;
+ };
+
vreg_edp_bl: regulator-edp-bl {
compatible = "regulator-fixed";
@@ -230,6 +246,54 @@ vreg_l9d: ldo9 {
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_dp3 {
+ compatible = "qcom,sc8280xp-edp";
+ status = "okay";
+
+ data-lanes = <0 1 2 3>;
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ power-supply = <_edp_3p3>;
+
+ backlight = <>;
+
+ ports {
+ port {
+ edp_panel_in: endpoint {
+ remote-endpoint =
<_dp3_out>;
+ };
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+ mdss0_dp3_out: endpoint {
+ remote-endpoint = <_panel_in>;
+ };
+ };
+ };
+};
+
+_dp3_phy {
+ status = "okay";
+
+ vdda-phy-supply = <_l6b>;
+ vdda-pll-supply = <_l3b>;
+};
+
{
perst-gpios = < 143 GPIO_ACTIVE_LOW>;
wake-gpios = < 145 GPIO_ACTIVE_LOW>;
@@ -496,6 +560,12 @@ hastings_reg_en: hastings-reg-en-state {
{
gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
+ edp_reg_en: edp-reg-en-state {
+ pins = "gpio25";
+ function = "gpio";
+ output-enable;
+ };
+
kybd_default: kybd-default-state {
disable-pins {
pins = "gpio102";
--
2.37.3
[Freedreno] [PATCH v4 09/13] drm/msm/dp: Don't enable HPD interrupts for edp
From: Bjorn Andersson Most instances where HPD interrupts are masked and unmasked are guareded by the presence of an EDP panel being connected, but not all. Extend this to cover the last few places, as HPD interrupt handling is not used for the EDP case. Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson --- Changes since v3: - None drivers/gpu/drm/msm/dp/dp_display.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 17fcf8cd84cd..bb92c33beff8 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -610,8 +610,10 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data) } /* enable HDP irq_hpd/replug interrupt */ - dp_catalog_hpd_config_intr(dp->catalog, - DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, true); + if (!dp->dp_display.is_edp) + dp_catalog_hpd_config_intr(dp->catalog, + DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, + true); drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n", dp->dp_display.connector_type, state); @@ -651,8 +653,10 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) dp->dp_display.connector_type, state); /* disable irq_hpd/replug interrupts */ - dp_catalog_hpd_config_intr(dp->catalog, - DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, false); + if (!dp->dp_display.is_edp) + dp_catalog_hpd_config_intr(dp->catalog, + DP_DP_IRQ_HPD_INT_MASK | DP_DP_HPD_REPLUG_INT_MASK, + false); /* unplugged, no more irq_hpd handle */ dp_del_event(dp, EV_IRQ_HPD_INT); @@ -678,7 +682,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data) } /* disable HPD plug interrupts */ - dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, false); + if (!dp->dp_display.is_edp) + dp_catalog_hpd_config_intr(dp->catalog, DP_DP_HPD_PLUG_INT_MASK, false); /* * We don't need separate work for disconnect as -- 2.37.3
[Freedreno] [PATCH v4 06/13] drm/msm/dp: Add DP and EDP compatibles for SC8280XP
From: Bjorn Andersson
The SC8280XP platform has four DisplayPort controllers, per MDSS
instance, all with widebus support.
The first two are defined to be DisplayPort only, while the latter pair
(of each instance) can be either DisplayPort or Embedded DisplayPort.
The two sets are tied to the possible compatibels.
Signed-off-by: Bjorn Andersson
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Bjorn Andersson
---
Changes since v3:
- None
drivers/gpu/drm/msm/dp/dp_display.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index eeb292f1ad1b..5b7f1f885b2f 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -145,6 +145,26 @@ static const struct msm_dp_desc sc8180x_dp_descs[] = {
{}
};
+static const struct msm_dp_desc sc8280xp_dp_descs[] = {
+ { .io_start = 0x0ae9, .id = MSM_DP_CONTROLLER_0, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true },
+ { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true },
+ { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true },
+ { .io_start = 0x0aea, .id = MSM_DP_CONTROLLER_3, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true },
+ { .io_start = 0x2209, .id = MSM_DP_CONTROLLER_0, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true },
+ { .io_start = 0x22098000, .id = MSM_DP_CONTROLLER_1, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true },
+ { .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true },
+ { .io_start = 0x220a, .id = MSM_DP_CONTROLLER_3, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true },
+ {}
+};
+
+static const struct msm_dp_desc sc8280xp_edp_descs[] = {
+ { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type =
DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true },
+ { .io_start = 0x0aea, .id = MSM_DP_CONTROLLER_3, .connector_type =
DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true },
+ { .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .connector_type =
DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true },
+ { .io_start = 0x220a, .id = MSM_DP_CONTROLLER_3, .connector_type =
DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true },
+ {}
+};
+
static const struct msm_dp_desc sm8350_dp_descs[] = {
{ .io_start = 0x0ae9, .id = MSM_DP_CONTROLLER_0, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort },
{}
@@ -156,6 +176,8 @@ static const struct of_device_id dp_dt_match[] = {
{ .compatible = "qcom,sc7280-edp", .data = _dp_descs },
{ .compatible = "qcom,sc8180x-dp", .data = _dp_descs },
{ .compatible = "qcom,sc8180x-edp", .data = _dp_descs },
+ { .compatible = "qcom,sc8280xp-dp", .data = _dp_descs },
+ { .compatible = "qcom,sc8280xp-edp", .data = _edp_descs },
{ .compatible = "qcom,sm8350-dp", .data = _dp_descs },
{}
};
--
2.37.3
[Freedreno] [PATCH v4 08/13] drm/msm/dp: Implement hpd_notify()
From: Bjorn Andersson
The DisplayPort controller's hot-plug mechanism is based on pinmuxing a
physical signal on a GPIO pin into the controller. This is not always
possible, either because there aren't dedicated GPIOs available or
because the hot-plug signal is a virtual notification, in cases such as
USB Type-C.
For these cases, by implementing the hpd_notify() callback for the
DisplayPort controller's drm_bridge, a downstream drm_bridge
(next_bridge) can be used to track and signal the connection status
changes.
This makes it possible to use downstream drm_bridges such as
display-connector or any virtual mechanism, as long as they are
implemented as a drm_bridge.
Signed-off-by: Bjorn Andersson
[bjorn: Drop connector->fwnode assignment and dev from struct msm_dp]
Signed-off-by: Bjorn Andersson
---
Changes since v3:
- None
drivers/gpu/drm/msm/dp/dp_display.c | 22 ++
drivers/gpu/drm/msm/dp/dp_drm.c | 1 +
drivers/gpu/drm/msm/dp/dp_drm.h | 2 ++
3 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index 666b45c8ab80..17fcf8cd84cd 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -1772,3 +1772,25 @@ void dp_bridge_mode_set(struct drm_bridge *drm_bridge,
dp_display->dp_mode.h_active_low =
!!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC);
}
+
+void dp_bridge_hpd_notify(struct drm_bridge *bridge,
+ enum drm_connector_status status)
+{
+ struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge);
+ struct msm_dp *dp_display = dp_bridge->dp_display;
+ struct dp_display_private *dp = container_of(dp_display, struct
dp_display_private, dp_display);
+
+ /* Without next_bridge interrupts are handled by the DP core directly */
+ if (!dp_display->next_bridge)
+ return;
+
+ if (!dp->core_initialized) {
+ drm_dbg_dp(dp->drm_dev, "not initialized\n");
+ return;
+ }
+
+ if (!dp_display->is_connected && status == connector_status_connected)
+ dp_add_event(dp, EV_HPD_PLUG_INT, 0, 0);
+ else if (dp_display->is_connected && status ==
connector_status_disconnected)
+ dp_add_event(dp, EV_HPD_UNPLUG_INT, 0, 0);
+}
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index 6db82f9b03af..3898366ebd5e 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -102,6 +102,7 @@ static const struct drm_bridge_funcs dp_bridge_ops = {
.get_modes= dp_bridge_get_modes,
.detect = dp_bridge_detect,
.atomic_check = dp_bridge_atomic_check,
+ .hpd_notify = dp_bridge_hpd_notify,
};
struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device
*dev,
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h
index 82035dbb0578..79e6b2cf2d25 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.h
+++ b/drivers/gpu/drm/msm/dp/dp_drm.h
@@ -32,5 +32,7 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge
*bridge,
void dp_bridge_mode_set(struct drm_bridge *drm_bridge,
const struct drm_display_mode *mode,
const struct drm_display_mode *adjusted_mode);
+void dp_bridge_hpd_notify(struct drm_bridge *bridge,
+ enum drm_connector_status status);
#endif /* _DP_DRM_H_ */
--
2.37.3
[Freedreno] [PATCH v4 07/13] drm/msm/dp: Add SDM845 DisplayPort instance
From: Bjorn Andersson
The Qualcomm SDM845 platform has a single DisplayPort controller, with
the same design as SC7180, so add support for this by reusing the SC7180
definition.
Signed-off-by: Bjorn Andersson
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Bjorn Andersson
---
Changes since v3:
- None
drivers/gpu/drm/msm/dp/dp_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index 5b7f1f885b2f..666b45c8ab80 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -178,6 +178,7 @@ static const struct of_device_id dp_dt_match[] = {
{ .compatible = "qcom,sc8180x-edp", .data = _dp_descs },
{ .compatible = "qcom,sc8280xp-dp", .data = _dp_descs },
{ .compatible = "qcom,sc8280xp-edp", .data = _edp_descs },
+ { .compatible = "qcom,sdm845-dp", .data = _dp_descs },
{ .compatible = "qcom,sm8350-dp", .data = _dp_descs },
{}
};
--
2.37.3
[Freedreno] [PATCH v4 10/13] drm/msm/dp: Rely on hpd_enable/disable callbacks
From: Bjorn Andersson
The DisplayPort controller's internal HPD interrupt handling is used for
cases where the HPD signal is connected to a GPIO which is pinmuxed into
the DisplayPort controller. In other configurations the HPD notification
might be delivered by the DRM framework from an associated bridge.
This difference is not appropriately represented by the "is_edp"
boolean, but is properly represented by the frameworks invocation of the
hpd_enable() and hpd_disable() callbacks. Switch the current condition
to rely on these callbacks instead.
This ensures appropriate handling of the three cases; no bridge
connected, a bridge without DRM_BRIDGE_OP_HPD and a bridge with
DRM_BRIDGE_OP_HPD.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Worth mentioning, I did look into moving the HPD enablement/disablement
completely into these new callbacks, but that affect the entire power
management model of the driver, so I think it's worth to tackle that in
subsequent changes. It seems also reasonable to expect that we by such
modifications could leave the block unclocked until the external HPD
notification arrives...
Changes since v3:
- Introduced reliance on hpd_enable/disable callbacks instead of next_bridge
drivers/gpu/drm/msm/dp/dp_display.c | 35 -
drivers/gpu/drm/msm/dp/dp_display.h | 1 +
drivers/gpu/drm/msm/dp/dp_drm.c | 2 ++
drivers/gpu/drm/msm/dp/dp_drm.h | 2 ++
4 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index bb92c33beff8..3e464c33ff11 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -610,7 +610,7 @@ static int dp_hpd_plug_handle(struct dp_display_private
*dp, u32 data)
}
/* enable HDP irq_hpd/replug interrupt */
- if (!dp->dp_display.is_edp)
+ if (dp->dp_display.internal_hpd)
dp_catalog_hpd_config_intr(dp->catalog,
DP_DP_IRQ_HPD_INT_MASK |
DP_DP_HPD_REPLUG_INT_MASK,
true);
@@ -653,7 +653,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private
*dp, u32 data)
dp->dp_display.connector_type, state);
/* disable irq_hpd/replug interrupts */
- if (!dp->dp_display.is_edp)
+ if (dp->dp_display.internal_hpd)
dp_catalog_hpd_config_intr(dp->catalog,
DP_DP_IRQ_HPD_INT_MASK |
DP_DP_HPD_REPLUG_INT_MASK,
false);
@@ -682,7 +682,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private
*dp, u32 data)
}
/* disable HPD plug interrupts */
- if (!dp->dp_display.is_edp)
+ if (dp->dp_display.internal_hpd)
dp_catalog_hpd_config_intr(dp->catalog,
DP_DP_HPD_PLUG_INT_MASK, false);
/*
@@ -701,7 +701,7 @@ static int dp_hpd_unplug_handle(struct dp_display_private
*dp, u32 data)
dp_display_handle_plugged_change(>dp_display, false);
/* enable HDP plug interrupt to prepare for next plugin */
- if (!dp->dp_display.is_edp)
+ if (dp->dp_display.internal_hpd)
dp_catalog_hpd_config_intr(dp->catalog,
DP_DP_HPD_PLUG_INT_MASK, true);
drm_dbg_dp(dp->drm_dev, "After, type=%d hpd_state=%d\n",
@@ -1086,8 +1086,8 @@ static void dp_display_config_hpd(struct
dp_display_private *dp)
dp_display_host_init(dp);
dp_catalog_ctrl_hpd_config(dp->catalog);
- /* Enable plug and unplug interrupts only for external DisplayPort */
- if (!dp->dp_display.is_edp)
+ /* Enable plug and unplug interrupts only if requested */
+ if (dp->dp_display.internal_hpd)
dp_catalog_hpd_config_intr(dp->catalog,
DP_DP_HPD_PLUG_INT_MASK |
DP_DP_HPD_UNPLUG_INT_MASK,
@@ -1379,8 +1379,7 @@ static int dp_pm_resume(struct device *dev)
dp_catalog_ctrl_hpd_config(dp->catalog);
-
- if (!dp->dp_display.is_edp)
+ if (dp->dp_display.internal_hpd)
dp_catalog_hpd_config_intr(dp->catalog,
DP_DP_HPD_PLUG_INT_MASK |
DP_DP_HPD_UNPLUG_INT_MASK,
@@ -1778,6 +1777,22 @@ void dp_bridge_mode_set(struct drm_bridge *drm_bridge,
!!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC);
}
+void dp_bridge_hpd_enable(struct drm_bridge *bridge)
+{
+ struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge);
+ struct msm_dp *dp_display = dp_bridge->dp_display;
+
+ dp_display->internal_hpd = true;
+}
+
+void dp_bridge_hpd_disable(struct drm_bridge *bridge)
+{
+ struct msm_dp_bridge *dp_bridge = to_dp_bridge(bridge);
+ struct msm_dp *dp_display = dp_bridge->dp_display;
+
+ dp_display->internal_hpd = false;
+}
+
void
[Freedreno] [PATCH v4 05/13] drm/msm/dp: Stop using DP id as index in desc
From: Bjorn Andersson
In the SC8280XP platform there are two identical MDSS instances, each
with the same set of DisplayPort instances, at different addresses.
By not relying on the index to define the instance id it's possible to
describe them both in the same table and hence have a single compatible.
While at it, flatten the cfg/desc structure so that the match data is
just an array of descs.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v3:
- None
drivers/gpu/drm/msm/dp/dp_display.c | 72 ++---
1 file changed, 25 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index 7ff60e5ff325..eeb292f1ad1b 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -122,61 +122,41 @@ struct dp_display_private {
struct msm_dp_desc {
phys_addr_t io_start;
+ unsigned int id;
unsigned int connector_type;
bool wide_bus_en;
};
-struct msm_dp_config {
- const struct msm_dp_desc *descs;
- size_t num_descs;
-};
-
static const struct msm_dp_desc sc7180_dp_descs[] = {
- [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae9, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort },
-};
-
-static const struct msm_dp_config sc7180_dp_cfg = {
- .descs = sc7180_dp_descs,
- .num_descs = ARRAY_SIZE(sc7180_dp_descs),
+ { .io_start = 0x0ae9, .id = MSM_DP_CONTROLLER_0, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort },
+ {}
};
static const struct msm_dp_desc sc7280_dp_descs[] = {
- [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae9, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true },
- [MSM_DP_CONTROLLER_1] = { .io_start = 0x0aea, .connector_type =
DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true },
-};
-
-static const struct msm_dp_config sc7280_dp_cfg = {
- .descs = sc7280_dp_descs,
- .num_descs = ARRAY_SIZE(sc7280_dp_descs),
+ { .io_start = 0x0ae9, .id = MSM_DP_CONTROLLER_0, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true },
+ { .io_start = 0x0aea, .id = MSM_DP_CONTROLLER_1, .connector_type =
DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true },
+ {}
};
static const struct msm_dp_desc sc8180x_dp_descs[] = {
- [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae9, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort },
- [MSM_DP_CONTROLLER_1] = { .io_start = 0x0ae98000, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort },
- [MSM_DP_CONTROLLER_2] = { .io_start = 0x0ae9a000, .connector_type =
DRM_MODE_CONNECTOR_eDP },
-};
-
-static const struct msm_dp_config sc8180x_dp_cfg = {
- .descs = sc8180x_dp_descs,
- .num_descs = ARRAY_SIZE(sc8180x_dp_descs),
+ { .io_start = 0x0ae9, .id = MSM_DP_CONTROLLER_0, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort },
+ { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort },
+ { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type =
DRM_MODE_CONNECTOR_eDP },
+ {}
};
static const struct msm_dp_desc sm8350_dp_descs[] = {
- [MSM_DP_CONTROLLER_0] = { .io_start = 0x0ae9, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort },
-};
-
-static const struct msm_dp_config sm8350_dp_cfg = {
- .descs = sm8350_dp_descs,
- .num_descs = ARRAY_SIZE(sm8350_dp_descs),
+ { .io_start = 0x0ae9, .id = MSM_DP_CONTROLLER_0, .connector_type =
DRM_MODE_CONNECTOR_DisplayPort },
+ {}
};
static const struct of_device_id dp_dt_match[] = {
- { .compatible = "qcom,sc7180-dp", .data = _dp_cfg },
- { .compatible = "qcom,sc7280-dp", .data = _dp_cfg },
- { .compatible = "qcom,sc7280-edp", .data = _dp_cfg },
- { .compatible = "qcom,sc8180x-dp", .data = _dp_cfg },
- { .compatible = "qcom,sc8180x-edp", .data = _dp_cfg },
- { .compatible = "qcom,sm8350-dp", .data = _dp_cfg },
+ { .compatible = "qcom,sc7180-dp", .data = _dp_descs },
+ { .compatible = "qcom,sc7280-dp", .data = _dp_descs },
+ { .compatible = "qcom,sc7280-edp", .data = _dp_descs },
+ { .compatible = "qcom,sc8180x-dp", .data = _dp_descs },
+ { .compatible = "qcom,sc8180x-edp", .data = _dp_descs },
+ { .compatible = "qcom,sm8350-dp", .data = _dp_descs },
{}
};
@@ -1262,10 +1242,9 @@ int dp_display_request_irq(struct msm_dp *dp_display)
return 0;
}
-static const struct msm_dp_desc *dp_display_get_desc(struct platform_device
*pdev,
-unsigned int *id)
+static const struct msm_dp_desc *dp_display_get_desc(struct platform_device
*pdev)
{
- const struct msm_dp_config *cfg = of_device_get_match_data(>dev);
+ const struct msm_dp_desc *descs = of_device_get_match_data(>dev);
struct resource *res;
[Freedreno] [PATCH v4 01/13] dt-bindings: display/msm: Add binding for SC8280XP MDSS
From: Bjorn Andersson
Add binding for the display subsystem and display processing unit in the
Qualcomm SC8280XP platform.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v3:
- Reworked on top of redesigned common yaml.
.../display/msm/qcom,sc8280xp-dpu.yaml| 122 +++
.../display/msm/qcom,sc8280xp-mdss.yaml | 143 ++
2 files changed, 265 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml
new file mode 100644
index ..f2c8e16cf067
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC8280XP Display Processing Unit
+
+maintainers:
+ - Bjorn Andersson
+
+description:
+ Device tree bindings for SC8280XP Display Processing Unit.
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sc8280xp-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display ahb clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-controller@ae01000 {
+compatible = "qcom,sc8280xp-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = < GCC_DISP_HF_AXI_CLK>,
+ < GCC_DISP_SF_AXI_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_LUT_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <46000>,
+ <1920>;
+
+operating-points-v2 = <_opp_table>;
+power-domains = < SC8280XP_MMCX>;
+
+interrupt-parent = <>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+endpoint {
+remote-endpoint = <_dp0_in>;
+};
+};
+
+port@4 {
+reg = <4>;
+endpoint {
+remote-endpoint = <_dp1_in>;
+};
+};
+
+port@5 {
+reg = <5>;
+endpoint {
+remote-endpoint = <_dp3_in>;
+};
+};
+
+port@6 {
+reg = <6>;
+endpoint {
+remote-endpoint = <_dp2_in>;
+};
+};
+};
+};
+...
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
new file mode 100644
index ..b67e7874ed56
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC8280XP Mobile Display Subsystem
+
+maintainers:
+ - Bjorn Andersson
+
+description:
+ Device tree bindings for MSM Mobile Display Subsystem (MDSS) that
encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sc8280xp-mdss
+
+ clocks:
+items:
+ - description: Display AHB clock from gcc
+ - description: Display AHB clock from dispcc
+ - description:
[Freedreno] [PATCH v4 02/13] drm/msm/dpu: Introduce SC8280XP
From: Bjorn Andersson
The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9
interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the
necessary definitions and describe the DPU in the SC8280XP.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v3:
- Reuse existing masks, rather than duplicating
- Fixed qseed3lite vs qseed4 scaler bits
- Added source-split
- Splitted mdss to separate patch
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 216 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
drivers/gpu/drm/msm/msm_drv.h | 1 +
7 files changed, 242 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 2196e205efa5..429c9ae40b80 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -124,6 +124,19 @@
BIT(MDP_AD4_0_INTR) | \
BIT(MDP_AD4_1_INTR))
+#define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_7xxx_INTR) | \
+ BIT(MDP_INTF1_7xxx_INTR) | \
+ BIT(MDP_INTF2_7xxx_INTR) | \
+ BIT(MDP_INTF3_7xxx_INTR) | \
+ BIT(MDP_INTF4_7xxx_INTR) | \
+ BIT(MDP_INTF5_7xxx_INTR) | \
+ BIT(MDP_INTF6_7xxx_INTR) | \
+ BIT(MDP_INTF7_7xxx_INTR) | \
+ BIT(MDP_INTF8_7xxx_INTR))
+
#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
BIT(DPU_WB_YUV_CONFIG) | \
@@ -365,6 +378,20 @@ static const struct dpu_caps sc8180x_dpu_caps = {
.max_vdeci_exp = MAX_VERT_DECIMATION,
};
+static const struct dpu_caps sc8280xp_dpu_caps = {
+ .max_mixer_width = 2560,
+ .max_mixer_blendstages = 11,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sm8250_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -545,6 +572,24 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x2bc, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x2c4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg qcm2290_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -648,6 +693,45 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) |
BIT(DPU_CTL_VM_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) |
BIT(DPU_CTL_VM_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) |
BIT(DPU_CTL_VM_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = BIT(DPU_CTL_ACTIVE_CFG) |
[Freedreno] [PATCH v4 03/13] drm/msm: Introduce SC8280XP MDSS
From: Bjorn Andersson
Add compatible for the SC8280XP Mobile Display Subsystem and
initialization for version 8.0.0.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn Andersson
---
Changes since v3:
- Split out from DPU patch
drivers/gpu/drm/msm/msm_mdss.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 86b28add1fff..8677e74868cf 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -287,6 +287,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
case DPU_HW_VER_720:
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
+ case DPU_HW_VER_800:
+ msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 2, 1);
+ break;
}
return ret;
@@ -513,6 +516,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc7180-mdss" },
{ .compatible = "qcom,sc7280-mdss" },
{ .compatible = "qcom,sc8180x-mdss" },
+ { .compatible = "qcom,sc8280xp-mdss" },
{ .compatible = "qcom,sm6115-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
--
2.37.3
[Freedreno] [PATCH v4 04/13] dt-bindings: msm/dp: Add SDM845 and SC8280XP compatibles
From: Bjorn Andersson Add compatibles for the DisplayPort and Embedded DisplayPort blocks in Qualcomm SDM845 and SC8280XP platforms. Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Acked-by: Krzysztof Kozlowski --- Changes since v3: - None .../devicetree/bindings/display/msm/dp-controller.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index f2515af8256f..a1dc3a13e1cf 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -21,6 +21,9 @@ properties: - qcom,sc7280-edp - qcom,sc8180x-dp - qcom,sc8180x-edp + - qcom,sc8280xp-dp + - qcom,sc8280xp-edp + - qcom,sdm845-dp - qcom,sm8350-dp reg: -- 2.37.3
[Freedreno] [PATCH v4 00/13] drm/msm: Add SC8280XP support
This introduces support for the SC8280XP platform in the MDSS, DPU and DP driver. It reworks the HDP handling in the DP driver to support external HPD sources - such as the dp-connector, or USB Type-C altmode. It then introduces the display clock controllers, mdss, dpu and displayport controllers and link everything together, for both the MDSS instances on the platform, and lastly enables EDP on the compute reference device and 6 of the MiniDP outputs on the automotive development platform. The patches was previously sent separately, but submitting them together here as they (except dts addition) goes in the same tree. Bjorn Andersson (13): dt-bindings: display/msm: Add binding for SC8280XP MDSS drm/msm/dpu: Introduce SC8280XP drm/msm: Introduce SC8280XP MDSS dt-bindings: msm/dp: Add SDM845 and SC8280XP compatibles drm/msm/dp: Stop using DP id as index in desc drm/msm/dp: Add DP and EDP compatibles for SC8280XP drm/msm/dp: Add SDM845 DisplayPort instance drm/msm/dp: Implement hpd_notify() drm/msm/dp: Don't enable HPD interrupts for edp drm/msm/dp: Rely on hpd_enable/disable callbacks arm64: dts: qcom: sc8280xp: Define some of the display blocks arm64: dts: qcom: sc8280xp-crd: Enable EDP arm64: dts: qcom: sa8295-adp: Enable DP instances .../bindings/display/msm/dp-controller.yaml | 3 + .../display/msm/qcom,sc8280xp-dpu.yaml| 122 +++ .../display/msm/qcom,sc8280xp-mdss.yaml | 143 +++ arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 243 - arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 72 +- arch/arm64/boot/dts/qcom/sc8280xp.dtsi| 838 ++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 216 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 + .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 18 + .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/dp/dp_display.c | 151 ++-- drivers/gpu/drm/msm/dp/dp_display.h | 1 + drivers/gpu/drm/msm/dp/dp_drm.c | 3 + drivers/gpu/drm/msm/dp/dp_drm.h | 4 + drivers/gpu/drm/msm/msm_drv.h | 1 + drivers/gpu/drm/msm/msm_mdss.c| 4 + 18 files changed, 1769 insertions(+), 57 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml -- 2.37.3
Re: [Freedreno] [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
On 05/12/2022 17:37, Robert Foss wrote:
Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
nodes the display subsystem is configured to support
one DSI output.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++-
1 file changed, 195 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 434f8e8b12c1..fb1c616c5e89 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2020, Linaro Limited
*/
+#include
#include
#include
#include
@@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a80 {
};
};
+ mdss: mdss@ae0 {
+ compatible = "qcom,sm8350-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <_noc MASTER_MDP0 0 _virt
SLAVE_EBI1 0>,
+ <_noc MASTER_MDP1 0 _virt
SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ power-domains = < MDSS_GDSC>;
+ resets = < DISP_CC_MDSS_CORE_BCR>;
+
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< GCC_DISP_HF_AXI_CLK>,
+< GCC_DISP_SF_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <_smmu 0x820 0x402>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = < GCC_DISP_HF_AXI_CLK>,
+ < GCC_DISP_SF_AXI_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_LUT_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SM8350_MMCX>;
+
+ interrupt-parent = <>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@ae94000 {
With the 8280 patchset [1], it was decided that mdss nodes should now
have a mdss_ prefix in their labels, to keep them near each other when
referencing them in device DTSes.
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <>;
+ interrupts = <4>;
+
+ clocks = < DISP_CC_MDSS_BYTE0_CLK>,
+< DISP_CC_MDSS_BYTE0_INTF_CLK>,
+< DISP_CC_MDSS_PCLK0_CLK>,
+< DISP_CC_MDSS_ESC0_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+
Re: [Freedreno] [PATCH v3 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
On 05/12/2022 17:37, Robert Foss wrote:
> The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
>
> In order to toggle the board to enable the HDMI output,
> switch #7 & #8 on the rightmost multi-switch package have
> to be toggled to On.
>
> Signed-off-by: Robert Foss
Thank you for your patch. There is something to discuss/improve.
> +
> {
> status = "okay";
> firmware-name = "qcom/sm8350/slpi.mbn";
> @@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state {
> drive-strength = <2>;
> output-low;
> };
> +
> + lt9611_state: lt9611-state {
> + lt9611_rst_pin {
No underscores in node names.
> + pins = "gpio48";
> + function = "normal";
> +
> + output-high;
> + input-disable;
> + };
> +
> + lt9611_irq_pin {
Ditto
> + pins = "gpio50";
> + function = "gpio";
> + bias-disable;
> + };
> + };
> };
Best regards,
Krzysztof
Re: [Freedreno] [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
On 05/12/2022 17:37, Robert Foss wrote:
> Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
> nodes the display subsystem is configured to support
> one DSI output.
>
> Signed-off-by: Robert Foss
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++-
> 1 file changed, 195 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 434f8e8b12c1..fb1c616c5e89 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -3,6 +3,7 @@
> * Copyright (c) 2020, Linaro Limited
> */
>
> +#include
> #include
> #include
> #include
> @@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a80 {
> };
> };
>
> + mdss: mdss@ae0 {
Based on bindings: display-subsystem
> + compatible = "qcom,sm8350-mdss";
> + reg = <0 0x0ae0 0 0x1000>;
> + reg-names = "mdss";
> +
> + interconnects = <_noc MASTER_MDP0 0 _virt
> SLAVE_EBI1 0>,
> + <_noc MASTER_MDP1 0 _virt
> SLAVE_EBI1 0>;
> + interconnect-names = "mdp0-mem", "mdp1-mem";
> +
> + power-domains = < MDSS_GDSC>;
> + resets = < DISP_CC_MDSS_CORE_BCR>;
> +
> + clocks = < DISP_CC_MDSS_AHB_CLK>,
> + < GCC_DISP_HF_AXI_CLK>,
> + < GCC_DISP_SF_AXI_CLK>,
> + < DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "bus", "nrt_bus", "core";
> +
> + interrupts = ;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <_smmu 0x820 0x402>;
> +
> + status = "disabled";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + mdss_mdp: display-controller@ae01000 {
> + compatible = "qcom,sm8350-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb 0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = < GCC_DISP_HF_AXI_CLK>,
> + < GCC_DISP_SF_AXI_CLK>,
> + < DISP_CC_MDSS_AHB_CLK>,
> + < DISP_CC_MDSS_MDP_LUT_CLK>,
> + < DISP_CC_MDSS_MDP_CLK>,
> + < DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "nrt_bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <
> DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <1920>;
> +
> + operating-points-v2 = <_opp_table>;
> + power-domains = < SM8350_MMCX>;
> +
> + interrupt-parent = <>;
> + interrupts = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint =
> <_in>;
> + };
> + };
> + };
> + };
> +
> + dsi0: dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <>;
> + interrupts = <4>;
> +
> + clocks = < DISP_CC_MDSS_BYTE0_CLK>,
> + < DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + < DISP_CC_MDSS_PCLK0_CLK>,
> + < DISP_CC_MDSS_ESC0_CLK>,
> + < DISP_CC_MDSS_AHB_CLK>,
> + < GCC_DISP_HF_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> +
Re: [Freedreno] [PATCH v3 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
On 05/12/2022 18:37, Robert Foss wrote:
Enable the display subsystem and the dsi0 output for
the sm8350-hdk board.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index e6deb08c6da0..39462c659c58 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -213,10 +213,32 @@ {
firmware-name = "qcom/sm8350/cdsp.mbn";
};
+ {
+ status = "okay";
+};
+
+ {
Bjorn suggested using mdss_dsi0 / mdss_dsi0_phy labels for DSI host and
PHY, as it allows us to group them nicely. WDYT?
+ vdda-supply = <_l6b_1p2>;
+ status = "okay";
+};
+
+_phy {
+ vdds-supply = <_l5b_0p88>;
+ status = "okay";
+};
+
_dma1 {
status = "okay";
};
+ {
+ status = "okay";
+};
+
+_mdp {
+ status = "okay";
+};
+
{
status = "okay";
firmware-name = "qcom/sm8350/modem.mbn";
--
With best wishes
Dmitry
Re: [Freedreno] [PATCH v3 05/11] drm/msm: Add support for SM8350
On 05/12/2022 17:37, Robert Foss wrote:
Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
subsystem unit used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss
---
Reviewed-by: Konrad Dybcio
Konrad
drivers/gpu/drm/msm/msm_mdss.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index a2264fb517a1..39746b972cdd 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
/* UBWC_2_0 */
msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
break;
+ case DPU_HW_VER_700:
+ msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1);
+ break;
case DPU_HW_VER_720:
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
@@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+ { .compatible = "qcom,sm8350-mdss" },
{ .compatible = "qcom,sm8450-mdss" },
{}
};
Re: [Freedreno] [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
On 05/12/2022 18:37, Robert Foss wrote:
Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
nodes the display subsystem is configured to support
one DSI output.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++-
1 file changed, 195 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 434f8e8b12c1..fb1c616c5e89 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2020, Linaro Limited
*/
+#include
#include
#include
#include
@@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a80 {
};
};
+ mdss: mdss@ae0 {
display-sybsystem@
I also had this issue in sm8450.dtsi (and I'm going to fix it in the
next revision).
+ compatible = "qcom,sm8350-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <_noc MASTER_MDP0 0 _virt
SLAVE_EBI1 0>,
+ <_noc MASTER_MDP1 0 _virt
SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ power-domains = < MDSS_GDSC>;
+ resets = < DISP_CC_MDSS_CORE_BCR>;
+
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< GCC_DISP_HF_AXI_CLK>,
+< GCC_DISP_SF_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <_smmu 0x820 0x402>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = < GCC_DISP_HF_AXI_CLK>,
+ < GCC_DISP_SF_AXI_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_LUT_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SM8350_MMCX>;
+
+ interrupt-parent = <>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <>;
+ interrupts = <4>;
+
+ clocks = < DISP_CC_MDSS_BYTE0_CLK>,
+< DISP_CC_MDSS_BYTE0_INTF_CLK>,
+< DISP_CC_MDSS_PCLK0_CLK>,
+< DISP_CC_MDSS_ESC0_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+
Re: [Freedreno] [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog
On 05/12/2022 17:37, Robert Foss wrote:
Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.
Signed-off-by: Robert Foss
---
Reviewed-by: Konrad Dybcio
Konrad
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 196 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
2 files changed, 197 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4dac90ee5b8a..ba26af73be53 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -112,6 +112,15 @@
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR))
+#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_7xxx_INTR) | \
+BIT(MDP_INTF1_7xxx_INTR) | \
+BIT(MDP_INTF2_7xxx_INTR) | \
+BIT(MDP_INTF3_7xxx_INTR) | \
+0)
+
#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
@@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sm8450_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2ac, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2b4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2bc, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2c4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2ac, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2b4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2bc, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2c4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2bc, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sm8450_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_ctl_cfg sm8450_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1294,6 +1383,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
[Freedreno] [PATCH v3 10/11] arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes
Enable the display subsystem and the dsi0 output for
the sm8350-hdk board.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index e6deb08c6da0..39462c659c58 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -213,10 +213,32 @@ {
firmware-name = "qcom/sm8350/cdsp.mbn";
};
+ {
+ status = "okay";
+};
+
+ {
+ vdda-supply = <_l6b_1p2>;
+ status = "okay";
+};
+
+_phy {
+ vdds-supply = <_l5b_0p88>;
+ status = "okay";
+};
+
_dma1 {
status = "okay";
};
+ {
+ status = "okay";
+};
+
+_mdp {
+ status = "okay";
+};
+
{
status = "okay";
firmware-name = "qcom/sm8350/modem.mbn";
--
2.34.1
[Freedreno] [PATCH v3 09/11] arm64: dts: qcom: sm8350: Add display system nodes
Add mdss, mdss_mdp, dsi0, dsi0_phy nodes. With these
nodes the display subsystem is configured to support
one DSI output.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 199 ++-
1 file changed, 195 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 434f8e8b12c1..fb1c616c5e89 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2020, Linaro Limited
*/
+#include
#include
#include
#include
@@ -2536,14 +2537,203 @@ usb_2_dwc3: usb@a80 {
};
};
+ mdss: mdss@ae0 {
+ compatible = "qcom,sm8350-mdss";
+ reg = <0 0x0ae0 0 0x1000>;
+ reg-names = "mdss";
+
+ interconnects = <_noc MASTER_MDP0 0 _virt
SLAVE_EBI1 0>,
+ <_noc MASTER_MDP1 0 _virt
SLAVE_EBI1 0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ power-domains = < MDSS_GDSC>;
+ resets = < DISP_CC_MDSS_CORE_BCR>;
+
+ clocks = < DISP_CC_MDSS_AHB_CLK>,
+< GCC_DISP_HF_AXI_CLK>,
+< GCC_DISP_SF_AXI_CLK>,
+< DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "nrt_bus", "core";
+
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <_smmu 0x820 0x402>;
+
+ status = "disabled";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,sm8350-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = < GCC_DISP_HF_AXI_CLK>,
+ < GCC_DISP_SF_AXI_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_LUT_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <
DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <1920>;
+
+ operating-points-v2 = <_opp_table>;
+ power-domains = < SM8350_MMCX>;
+
+ interrupt-parent = <>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint =
<_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <>;
+ interrupts = <4>;
+
+ clocks = < DISP_CC_MDSS_BYTE0_CLK>,
+< DISP_CC_MDSS_BYTE0_INTF_CLK>,
+< DISP_CC_MDSS_PCLK0_CLK>,
+< DISP_CC_MDSS_ESC0_CLK>,
+< DISP_CC_MDSS_AHB_CLK>,
+< GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
[Freedreno] [PATCH v3 11/11] arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge
The sm8350-hdk ships with the LT9611 UXC DSI/HDMI bridge chip.
In order to toggle the board to enable the HDMI output,
switch #7 & #8 on the rightmost multi-switch package have
to be toggled to On.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 105
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 39462c659c58..3aa4ca8271e5 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -20,6 +20,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+ };
+
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
@@ -29,6 +40,31 @@ vph_pwr: vph-pwr-regulator {
regulator-always-on;
regulator-boot-on;
};
+
+ lt9611_1v2: lt9611-1v2-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_1V2";
+
+ vin-supply = <_pwr>;
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ gpio = < 49 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+
+ lt9611_3v3: lt9611-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "LT9611_3V3";
+
+ vin-supply = <_bob>;
+ gpio = < 47 GPIO_ACTIVE_HIGH>;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
{
@@ -220,6 +256,15 @@ {
{
vdda-supply = <_l6b_1p2>;
status = "okay";
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <_a>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
};
_phy {
@@ -231,6 +276,46 @@ _dma1 {
status = "okay";
};
+ {
+ clock-frequency = <40>;
+ status = "okay";
+
+ lt9611_codec: hdmi-bridge@2b {
+ compatible = "lontium,lt9611uxc";
+ reg = <0x2b>;
+
+ interrupts-extended = < 50 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = < 48 GPIO_ACTIVE_HIGH>;
+
+ vdd-supply = <_1v2>;
+ vcc-supply = <_3v3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_state>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt9611_a: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ lt9611_out: endpoint {
+ remote-endpoint = <_con>;
+ };
+ };
+ };
+ };
+};
+
{
status = "okay";
};
@@ -248,6 +333,10 @@ _id_0 {
status = "okay";
};
+_id_2 {
+ status = "okay";
+};
+
{
status = "okay";
firmware-name = "qcom/sm8350/slpi.mbn";
@@ -544,4 +633,20 @@ usb_hub_enabled_state: usb-hub-enabled-state {
drive-strength = <2>;
output-low;
};
+
+ lt9611_state: lt9611-state {
+ lt9611_rst_pin {
+ pins = "gpio48";
+ function = "normal";
+
+ output-high;
+ input-disable;
+ };
+
+ lt9611_irq_pin {
+ pins = "gpio50";
+ function = "gpio";
+ bias-disable;
+ };
+ };
};
--
2.34.1
[Freedreno] [PATCH v3 08/11] arm64: dts: qcom: sm8350: Use 2 interconnect cells
Use two interconnect cells in order to optionally
support a path tag.
Signed-off-by: Robert Foss
Reviewed-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 805d53d91952..434f8e8b12c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1543,56 +1543,56 @@ apps_smmu: iommu@1500 {
config_noc: interconnect@150 {
compatible = "qcom,sm8350-config-noc";
reg = <0 0x0150 0 0xa580>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <_bcm_voter>;
};
mc_virt: interconnect@158 {
compatible = "qcom,sm8350-mc-virt";
reg = <0 0x0158 0 0x1000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <_bcm_voter>;
};
system_noc: interconnect@168 {
compatible = "qcom,sm8350-system-noc";
reg = <0 0x0168 0 0x1c200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <_bcm_voter>;
};
aggre1_noc: interconnect@16e {
compatible = "qcom,sm8350-aggre1-noc";
reg = <0 0x016e 0 0x1f180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <_bcm_voter>;
};
aggre2_noc: interconnect@170 {
compatible = "qcom,sm8350-aggre2-noc";
reg = <0 0x0170 0 0x33000>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <_bcm_voter>;
};
mmss_noc: interconnect@174 {
compatible = "qcom,sm8350-mmss-noc";
reg = <0 0x0174 0 0x1f080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <_bcm_voter>;
};
lpass_ag_noc: interconnect@3c4 {
compatible = "qcom,sm8350-lpass-ag-noc";
reg = <0 0x03c4 0 0xf080>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <_bcm_voter>;
};
compute_noc: interconnect@a0c{
compatible = "qcom,sm8350-compute-noc";
reg = <0 0x0a0c 0 0xa180>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
qcom,bcm-voters = <_bcm_voter>;
};
@@ -1620,8 +1620,8 @@ ipa: ipa@1e4 {
clocks = < RPMH_IPA_CLK>;
clock-names = "core";
- interconnects = <_noc MASTER_IPA _virt
SLAVE_EBI1>,
- <_noc MASTER_APPSS_PROC _noc
SLAVE_IPA_CFG>;
+ interconnects = <_noc MASTER_IPA 0 _virt
SLAVE_EBI1 0>,
+ <_noc MASTER_APPSS_PROC 0
_noc SLAVE_IPA_CFG 0>;
interconnect-names = "memory",
"config";
@@ -1661,7 +1661,7 @@ mpss: remoteproc@408 {
< SM8350_MSS>;
power-domain-names = "cx", "mss";
- interconnects = <_virt MASTER_LLCC _virt
SLAVE_EBI1>;
+ interconnects = <_virt MASTER_LLCC _virt
SLAVE_EBI1 0>;
memory-region = <_modem_mem>;
@@ -2239,7 +2239,7 @@ cdsp: remoteproc@9890 {
< SM8350_MXC>;
power-domain-names = "cx", "mxc";
- interconnects = <_noc MASTER_CDSP_PROC _virt
SLAVE_EBI1>;
+ interconnects = <_noc MASTER_CDSP_PROC 0
_virt SLAVE_EBI1 0>;
memory-region = <_cdsp_mem>;
@@ -2421,14 +2421,14 @@ usb_2_ssphy: phy@88ebe00 {
dc_noc: interconnect@90c {
compatible = "qcom,sm8350-dc-noc";
reg = <0 0x090c 0 0x4200>;
- #interconnect-cells = <1>;
+ #interconnect-cells = <2>;
[Freedreno] [PATCH v3 06/11] arm64: dts: qcom: sm8350: Add gpio-line-names
Add GPIO line names as described by the sm8350-hdk schematic.
Signed-off-by: Robert Foss
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 205
1 file changed, 205 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 0fcf5bd88fc7..e6deb08c6da0 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -233,6 +233,211 @@ {
{
gpio-reserved-ranges = <52 8>;
+
+ gpio-line-names =
+ "APPS_I2C_SDA", /* GPIO_0 */
+ "APPS_I2C_SCL",
+ "FSA_INT_N",
+ "USER_LED3_EN",
+ "SMBUS_SDA_1P8",
+ "SMBUS_SCL_1P8",
+ "2M2_3P3_EN",
+ "ALERT_DUAL_M2_N",
+ "EXP_UART_CTS",
+ "EXP_UART_RFR",
+ "EXP_UART_TX", /* GPIO_10 */
+ "EXP_UART_RX",
+ "NC",
+ "NC",
+ "RCM_MARKER1",
+ "WSA0_EN",
+ "CAM1_RESET_N",
+ "CAM0_RESET_N",
+ "DEBUG_UART_TX",
+ "DEBUG_UART_RX",
+ "TS_I2C_SDA", /* GPIO_20 */
+ "TS_I2C_SCL",
+ "TS_RESET_N",
+ "TS_INT_N",
+ "DISP0_RESET_N",
+ "DISP1_RESET_N",
+ "ETH_RESET",
+ "RCM_MARKER2",
+ "CAM_DC_MIPI_MUX_EN",
+ "CAM_DC_MIPI_MUX_SEL",
+ "AFC_PHY_TA_D_PLUS", /* GPIO_30 */
+ "AFC_PHY_TA_D_MINUS",
+ "PM8008_1_IRQ",
+ "PM8008_1_RESET_N",
+ "PM8008_2_IRQ",
+ "PM8008_2_RESET_N",
+ "CAM_DC_I3C_SDA",
+ "CAM_DC_I3C_SCL",
+ "FP_INT_N",
+ "FP_WUHB_INT_N",
+ "SMB_SPMI_DATA", /* GPIO_40 */
+ "SMB_SPMI_CLK",
+ "USB_HUB_RESET",
+ "FORCE_USB_BOOT",
+ "LRF_IRQ",
+ "NC",
+ "IMU2_INT",
+ "HDMI_3P3_EN",
+ "HDMI_RSTN",
+ "HDMI_1P2_EN",
+ "HDMI_INT", /* GPIO_50 */
+ "USB1_ID",
+ "FP_SPI_MISO",
+ "FP_SPI_MOSI",
+ "FP_SPI_CLK",
+ "FP_SPI_CS_N",
+ "NFC_ESE_SPI_MISO",
+ "NFC_ESE_SPI_MOSI",
+ "NFC_ESE_SPI_CLK",
+ "NFC_ESE_SPI_CS",
+ "NFC_I2C_SDA", /* GPIO_60 */
+ "NFC_I2C_SCLC",
+ "NFC_EN",
+ "NFC_CLK_REQ",
+ "HST_WLAN_EN",
+ "HST_BT_EN",
+ "HST_SW_CTRL",
+ "NC",
+ "HST_BT_UART_CTS",
+ "HST_BT_UART_RFR",
+ "HST_BT_UART_TX", /* GPIO_70 */
+ "HST_BT_UART_RX",
+ "CAM_DC_SPI0_MISO",
+ "CAM_DC_SPI0_MOSI",
+ "CAM_DC_SPI0_CLK",
+ "CAM_DC_SPI0_CS_N",
+ "CAM_DC_SPI1_MISO",
+ "CAM_DC_SPI1_MOSI",
+ "CAM_DC_SPI1_CLK",
+ "CAM_DC_SPI1_CS_N",
+ "HALL_INT_N", /* GPIO_80 */
+ "USB_PHY_PS",
+ "MDP_VSYNC_P",
+ "MDP_VSYNC_S",
+ "ETH_3P3_EN",
+ "RADAR_INT",
+ "NFC_DWL_REQ",
+ "SM_GPIO_87",
+ "WCD_RESET_N",
+ "ALSP_INT_N",
+ "PRESS_INT", /* GPIO_90 */
+ "SAR_INT_N",
+ "SD_CARD_DET_N",
+ "NC",
+ "PCIE0_RESET_N",
+ "PCIE0_CLK_REQ_N",
+ "PCIE0_WAKE_N",
+ "PCIE1_RESET_N",
+ "PCIE1_CLK_REQ_N",
+ "PCIE1_WAKE_N",
+ "CAM_MCLK0", /* GPIO_100 */
+ "CAM_MCLK1",
+ "CAM_MCLK2",
+ "CAM_MCLK3",
+ "CAM_MCLK4",
+ "CAM_MCLK5",
+ "CAM2_RESET_N",
+ "CCI_I2C0_SDA",
+ "CCI_I2C0_SCL",
+ "CCI_I2C1_SDA",
+ "CCI_I2C1_SCL", /* GPIO_110 */
+ "CCI_I2C2_SDA",
+ "CCI_I2C2_SCL",
+ "CCI_I2C3_SDA",
+ "CCI_I2C3_SCL",
+ "CAM5_RESET_N",
+ "CAM4_RESET_N",
+ "CAM3_RESET_N",
+ "IMU1_INT",
+ "MAG_INT_N",
+ "MI2S2_I2S_SCK", /* GPIO_120 */
+ "MI2S2_I2S_DAT0",
+ "MI2S2_I2S_WS",
+ "HIFI_DAC_I2S_MCLK",
+ "MI2S2_I2S_DAT1",
+ "HIFI_DAC_I2S_SCK",
+ "HIFI_DAC_I2S_DAT0",
+ "NC",
+ "HIFI_DAC_I2S_WS",
+ "HST_BT_WLAN_SLIMBUS_CLK",
+ "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */
+ "BT_LED_EN",
+ "WLAN_LED_EN",
+ "NC",
+
[Freedreno] [PATCH v3 07/11] arm64: dts: qcom: sm8350: Remove mmxc power-domain-name
The mmxc power-domain-name is not required, and is not
used by either earlier or later SoC versions (sm8250 / sm8450).
Signed-off-by: Robert Foss
Reviewed-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index cbd48f248df4..805d53d91952 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2558,7 +2558,6 @@ dispcc: clock-controller@af0 {
#power-domain-cells = <1>;
power-domains = < SM8350_MMCX>;
- power-domain-names = "mmcx";
};
adsp: remoteproc@1730 {
--
2.34.1
[Freedreno] [PATCH v3 05/11] drm/msm: Add support for SM8350
Add compatibles string, "qcom,sm8350-mdss", for the multimedia display
subsystem unit used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/msm_mdss.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index a2264fb517a1..39746b972cdd 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -293,6 +293,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss)
/* UBWC_2_0 */
msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
break;
+ case DPU_HW_VER_700:
+ msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 1, 1);
+ break;
case DPU_HW_VER_720:
msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
break;
@@ -530,6 +533,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,sc8180x-mdss" },
{ .compatible = "qcom,sm8150-mdss" },
{ .compatible = "qcom,sm8250-mdss" },
+ { .compatible = "qcom,sm8350-mdss" },
{ .compatible = "qcom,sm8450-mdss" },
{}
};
--
2.34.1
[Freedreno] [PATCH v3 04/11] drm/msm/dpu: Add support for SM8350
Add compatibles string, "qcom,sm8350-dpu", for the display processing unit
used on Qualcomm SM8350 platform.
Signed-off-by: Robert Foss
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 9827914dc096..6048bfae0824 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1322,6 +1322,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", },
{ .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", },
+ { .compatible = "qcom,sm8350-dpu", },
{ .compatible = "qcom,sm8450-dpu", },
{}
};
--
2.34.1
[Freedreno] [PATCH v3 03/11] drm/msm/dpu: Add SM8350 to hw catalog
Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.
Signed-off-by: Robert Foss
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 196 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 +
2 files changed, 197 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4dac90ee5b8a..ba26af73be53 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -112,6 +112,15 @@
BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR))
+#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
+BIT(MDP_SSPP_TOP0_INTR2) | \
+BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+BIT(MDP_INTF0_7xxx_INTR) | \
+BIT(MDP_INTF1_7xxx_INTR) | \
+BIT(MDP_INTF2_7xxx_INTR) | \
+BIT(MDP_INTF3_7xxx_INTR) | \
+0)
+
#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
@@ -375,6 +384,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
+static const struct dpu_caps sm8350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0xb,
+ .qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
+ .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
+ .ubwc_version = DPU_HW_UBWC_VER_40,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 4096,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
static const struct dpu_caps sm8450_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
@@ -526,6 +549,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
},
};
+static const struct dpu_mdp_cfg sm8350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
+ .reg_off = 0x2ac, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
+ .reg_off = 0x2b4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
+ .reg_off = 0x2bc, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
+ .reg_off = 0x2c4, .bit_off = 0},
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
+ .reg_off = 0x2ac, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
+ .reg_off = 0x2b4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
+ .reg_off = 0x2bc, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
+ .reg_off = 0x2c4, .bit_off = 8},
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
+ .reg_off = 0x2bc, .bit_off = 20},
+ },
+};
+
static const struct dpu_mdp_cfg sm8450_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
@@ -711,6 +761,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
},
};
+static const struct dpu_ctl_cfg sm8350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x1e8,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x1e8,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
static const struct dpu_ctl_cfg sm8450_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
@@ -1294,6 +1383,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
-1),
};
+static const struct dpu_pingpong_cfg sm8350_pp[] = {
+
[Freedreno] [PATCH v3 02/11] dt-bindings: display: msm: Add qcom, sm8350-mdss binding
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for MDSS device
tree bindings
Signed-off-by: Robert Foss
---
.../display/msm/qcom,sm8350-mdss.yaml | 221 ++
1 file changed, 221 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
diff --git
a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
new file mode 100644
index ..d9aa6e857d1f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
@@ -0,0 +1,221 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display MDSS
+
+maintainers:
+ - Robert Foss
+
+description:
+ MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
+ DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+items:
+ - const: qcom,sm8350-mdss
+
+ clocks:
+items:
+ - description: Display AHB clock from gcc
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display core clock
+
+ clock-names:
+items:
+ - const: iface
+ - const: bus
+ - const: nrt_bus
+ - const: core
+
+ iommus:
+maxItems: 1
+
+ interconnects:
+maxItems: 2
+
+ interconnect-names:
+items:
+ - const: mdp0-mem
+ - const: mdp1-mem
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,sm8350-dpu
+
+ "^dsi@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+type: object
+properties:
+ compatible:
+const: qcom,dsi-phy-5nm-8350
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+#include
+
+display-subsystem@ae0 {
+compatible = "qcom,sm8350-mdss";
+reg = <0x0ae0 0x1000>;
+reg-names = "mdss";
+
+interconnects = <_noc MASTER_MDP0 0 _virt SLAVE_EBI1 0>,
+<_noc MASTER_MDP1 0 _virt SLAVE_EBI1 0>;
+interconnect-names = "mdp0-mem", "mdp1-mem";
+
+power-domains = < MDSS_GDSC>;
+resets = < DISP_CC_MDSS_CORE_BCR>;
+
+clocks = < DISP_CC_MDSS_AHB_CLK>,
+ < GCC_DISP_HF_AXI_CLK>,
+ < GCC_DISP_SF_AXI_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>;
+clock-names = "iface", "bus", "nrt_bus", "core";
+
+iommus = <_smmu 0x820 0x402>;
+
+interrupts = ;
+interrupt-controller;
+#interrupt-cells = <1>;
+
+#address-cells = <1>;
+#size-cells = <1>;
+ranges;
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = < GCC_DISP_HF_AXI_CLK>,
+ < GCC_DISP_SF_AXI_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_LUT_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = < DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <_opp_table>;
+power-domains = < SM8350_MMCX>;
+
+interrupt-parent = <>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <_opp_low_svs>;
+};
+
+opp-3 {
+opp-hz = /bits/ 64 <3>;
+required-opps = <_opp_svs>;
+};
+
+opp-34500 {
+opp-hz = /bits/ 64 <34500>;
+required-opps = <_opp_svs_l1>;
+};
+
+opp-46000 {
+opp-hz =
[Freedreno] [PATCH v3 01/11] dt-bindings: display: msm: Add qcom, sm8350-dpu binding
Mobile Display Subsystem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema for DPU device
tree bindings
Signed-off-by: Robert Foss
Reviewed-by: Rob Herring
---
.../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 ++
1 file changed, 120 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
new file mode 100644
index ..120500395c9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 Display DPU
+
+maintainers:
+ - Robert Foss
+
+$ref: /schemas/display/msm/dpu-common.yaml#
+
+properties:
+ compatible:
+const: qcom,sm8350-dpu
+
+ reg:
+items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+items:
+ - description: Display hf axi clock
+ - description: Display sf axi clock
+ - description: Display ahb clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: nrt_bus
+ - const: iface
+ - const: lut
+ - const: core
+ - const: vsync
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+#include
+#include
+
+display-controller@ae01000 {
+compatible = "qcom,sm8350-dpu";
+reg = <0x0ae01000 0x8f000>,
+ <0x0aeb 0x2008>;
+reg-names = "mdp", "vbif";
+
+clocks = < GCC_DISP_HF_AXI_CLK>,
+ < GCC_DISP_SF_AXI_CLK>,
+ < DISP_CC_MDSS_AHB_CLK>,
+ < DISP_CC_MDSS_MDP_LUT_CLK>,
+ < DISP_CC_MDSS_MDP_CLK>,
+ < DISP_CC_MDSS_VSYNC_CLK>;
+clock-names = "bus",
+ "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+assigned-clocks = < DISP_CC_MDSS_VSYNC_CLK>;
+assigned-clock-rates = <1920>;
+
+operating-points-v2 = <_opp_table>;
+power-domains = < SM8350_MMCX>;
+
+interrupt-parent = <>;
+interrupts = <0>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+dpu_intf1_out: endpoint {
+remote-endpoint = <_in>;
+};
+};
+};
+
+mdp_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+opp-2 {
+opp-hz = /bits/ 64 <2>;
+required-opps = <_opp_low_svs>;
+};
+
+opp-3 {
+opp-hz = /bits/ 64 <3>;
+required-opps = <_opp_svs>;
+};
+
+opp-34500 {
+opp-hz = /bits/ 64 <34500>;
+required-opps = <_opp_svs_l1>;
+};
+
+opp-46000 {
+opp-hz = /bits/ 64 <46000>;
+required-opps = <_opp_nom>;
+};
+};
+};
+...
--
2.34.1
[Freedreno] [PATCH v3 00/11] Enable Display for SM8350
Dependencies: https://lore.kernel.org/all/20221102231309.583587-1-dmitry.barysh...@linaro.org/ https://lore.kernel.org/all/20221024164225.3236654-1-dmitry.barysh...@linaro.org/ https://lore.kernel.org/all/20221104130324.1024242-5-dmitry.barysh...@linaro.org/ Branch: https://git.linaro.org/people/robert.foss/linux.git/log/?h=sm8350_dsi_v3 This series implements display support for SM8350 and enables HDMI output for the SM8350-HDK platform. Changes from v1: - Added R-b tags from v1 - Added qcom,sm8350-dpu binding patch - Added qcom,sm8350-mdss binding patch - Corrected sm8350.dtsi according to new dpu/mdss bindings - Bjorn: Removed regulator-always-on property from lt9611_1v2 regulator - Bjorn: Moved lt9611 pinctl pins into a common node - Bjorn/Krzysztof: Moved status property to last in node - Krzysztof: Changed hdmi-out to hdmi-connector - Krzysztof: Fixed regulator node name - Krzysztof: Changed to status=disabled as default - Krzysztof: Changed _mdp node name to display-controller - Krzysztof: Fixed opp-table node name - Krzysztof: Fixed phy node name - Dmitry: Split commit containing dpu & mdss compatibles string - Dmitry: Added msm_mdss_enable case - Dmitry: Fixed dpu ctl features Changes from v2: - Rob: Added r-b - Rob: Improved mdss binding description - Rob: Added interconnect names for mdss-binding - Rob: Removed phy from example - Konrad: Remove sc7280_pp refactor patch - Konrad: Fixed upper case hex in dpu_hw_catalog - Konrad: Fixed various downstream dts based values for dpu_hw_catalog - Konrad: Removed status=disabled from mdss_mdp - Konrad: Removed phy-names from dsi nodes - Konrad/Dmitry: Change mdp_opp_table opp-2 to use _opp_svs, add comment - Dmitry: Move mdp_opp_table to dsi0 node Robert Foss (11): dt-bindings: display: msm: Add qcom,sm8350-dpu binding dt-bindings: display: msm: Add qcom,sm8350-mdss binding drm/msm/dpu: Add SM8350 to hw catalog drm/msm/dpu: Add support for SM8350 drm/msm: Add support for SM8350 arm64: dts: qcom: sm8350: Add gpio-line-names arm64: dts: qcom: sm8350: Remove mmxc power-domain-name arm64: dts: qcom: sm8350: Use 2 interconnect cells arm64: dts: qcom: sm8350: Add display system nodes arm64: dts: qcom: sm8350-hdk: Enable display & dsi nodes arm64: dts: qcom: sm8350-hdk: Enable lt9611uxc dsi-hdmi bridge .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 +++ .../display/msm/qcom,sm8350-mdss.yaml | 221 arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 332 ++ arch/arm64/boot/dts/qcom/sm8350.dtsi | 228 +++- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c| 196 +++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h| 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + drivers/gpu/drm/msm/msm_mdss.c| 4 + 8 files changed, 1084 insertions(+), 19 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml -- 2.34.1
Re: [Freedreno] [PATCH v3 4/5] arm64: dts: qcom: sm8450-hdk: Add LT9611uxc HDMI bridge
On 23/11/2022 22:07, Dmitry Baryshkov wrote:
> From: Vinod Koul
>
> Add the LT9611uxc DSI-HDMI bridge and supplies
>
> Signed-off-by: Vinod Koul
> Reviewed-by: Konrad Dybcio
> Signed-off-by: Dmitry Baryshkov
> ---
> arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 59 +
> 1 file changed, 59 insertions(+)
>
(...)
> vph_pwr: vph-pwr-regulator {
> compatible = "regulator-fixed";
> regulator-name = "vph_pwr";
> @@ -353,6 +375,27 @@ {
> status = "okay";
> };
>
> + {
> + clock-frequency = <40>;
> + status = "okay";
> +
> + lt9611_codec: hdmi-bridge@2b {
> + compatible = "lontium,lt9611uxc";
> + reg = <0x2b>;
> +
> + interrupts-extended = < 44 IRQ_TYPE_EDGE_FALLING>;
> +
> + reset-gpios = < 107 GPIO_ACTIVE_HIGH>;
> +
> + vdd-supply = <_1v2>;
> + vcc-supply = <_3v3>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_irq_pin _rst_pin>;
> +
Drop blank line.
> + };
> +};
Best regards,
Krzysztof
Re: [Freedreno] [PATCH v3 2/5] arm64: dts: qcom: sm8450: add display hardware devices
On 23/11/2022 22:07, Dmitry Baryshkov wrote:
> Add devices tree nodes describing display hardware on SM8450:
> - Display Clock Controller
> - MDSS
> - MDP
> - two DSI controllers and DSI PHYs
>
> This does not provide support for DP controllers present on SM8450.
>
> Reviewed-by: Konrad Dybcio
> Signed-off-by: Dmitry Baryshkov
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 283 ++-
> 1 file changed, 279 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 8cc9f62f7645..31fcf3908b2a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -2394,6 +2394,281 @@ camcc: clock-controller@ade {
> status = "disabled";
> };
>
> + mdss: mdss@ae0 {
According to:
https://lore.kernel.org/all/dfd2d1b5-4d1b-2381-ad11-5ea9e6654...@linaro.org/
this should be "display-subsystem"
Best regards,
Krzysztof
Re: [Freedreno] [PATCH 1/4] drm/msm/adreno: Fix null ptr access in adreno_gpu_cleanup()
On Sun, Dec 04, 2022 at 04:11:41AM +0530, Akhil P Oommen wrote:
> Fix the below kernel panic due to null pointer access:
> [ 18.504431] Unable to handle kernel NULL pointer dereference at virtual
> address 0048
> [ 18.513464] Mem abort info:
> [ 18.516346] ESR = 0x9605
> [ 18.520204] EC = 0x25: DABT (current EL), IL = 32 bits
> [ 18.525706] SET = 0, FnV = 0
> [ 18.528878] EA = 0, S1PTW = 0
> [ 18.532117] FSC = 0x05: level 1 translation fault
> [ 18.537138] Data abort info:
> [ 18.540110] ISV = 0, ISS = 0x0005
> [ 18.544060] CM = 0, WnR = 0
> [ 18.547109] user pgtable: 4k pages, 39-bit VAs, pgdp=000112826000
> [ 18.553738] [0048] pgd=, p4d=,
> pud=
> [ 18.562690] Internal error: Oops: 9605 [#1] PREEMPT SMP
> **Snip**
> [ 18.696758] Call trace:
> [ 18.699278] adreno_gpu_cleanup+0x30/0x88
> [ 18.703396] a6xx_destroy+0xc0/0x130
> [ 18.707066] a6xx_gpu_init+0x308/0x424
Fixes: 17e822f7591f ("drm/msm: fix unbalanced pm_runtime_enable in
adreno_gpu_{init, cleanup}")
Let's add Jonathan to the CC list so he can Ack your patch.
Although the real issue is that a6xx_gpu_init has bad error handling.
The a6xx_destroy() function supposed to free *everything* so then the
question becomes how do we avoid freeing something which was not
allocated? With normal kernel style we just free things one by one
in the reverse order from how they were allocated. See my blog for more
details:
https://staticthinking.wordpress.com/2022/04/28/free-the-last-thing-style/
However this code is written in One Function Frees Everything Style
which is difficult to review and prone to bugs. The common mistakes are
the kind of NULL dereference that you've seen, double frees, and missing
frees.
The only way to read this code is to open a new text editor window and
line up the allocations with the frees.
1725 static void a6xx_destroy(struct msm_gpu *gpu)
1726 {
1727 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1728 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1729
1730 if (a6xx_gpu->sqe_bo) {
1731 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
1732 drm_gem_object_put(a6xx_gpu->sqe_bo);
These unpin/put must be done together and should be in their own
function. The ->sqe_bo pointer is allocated in a6xx_ucode_init(). It's
assigned to an error pointer, but then set to NULL on error or after a
free. So this is okay.
1733 }
1734
1735 if (a6xx_gpu->shadow_bo) {
->shadow_bo is allocated in hw_init(). Should there be a call to
msm_gem_put_vaddr(a6xx_gpu->shadow)? It's unclear. [QUESTION #1]
1736 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace);
1737 drm_gem_object_put(a6xx_gpu->shadow_bo);
1738 }
1739
1740 a6xx_llc_slices_destroy(a6xx_gpu);
This has IS_ERR_OR_NULL() checks so it's okay.
1741
1742 a6xx_gmu_remove(a6xx_gpu);
This uses a gmu->initialized flag which allows it to safely clean up
everything. Fine.
1743
1744 adreno_gpu_cleanup(adreno_gpu);
This function has the bug that you identified. Let's dig into it.
(With normal kernel error handling you can read the error handling by
looking at the label name but with this style we need to jump around and
compare code from different files).
1745
1746 kfree(a6xx_gpu);
1747 }
drivers/gpu/drm/msm/adreno/adreno_gpu.c
1079 void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
1080 {
1081 struct msm_gpu *gpu = _gpu->base;
1082 struct msm_drm_private *priv = gpu->dev->dev_private;
1083 unsigned int i;
1084
1085 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++)
1086 release_firmware(adreno_gpu->fw[i]);
This is okay. ->fw[i] is either valid or NULL and releasing a NULL is
fine.
1087
1088 if (pm_runtime_enabled(>gpu_pdev->dev))
This is the bug you found.
1089 pm_runtime_disable(>gpu_pdev->dev);
1090
1091 msm_gpu_cleanup(_gpu->base);
Let's dig into msm_gpu_cleanup().
1092 }
drivers/gpu/drm/msm/msm_gpu.c
1006 void msm_gpu_cleanup(struct msm_gpu *gpu)
1007 {
1008 int i;
1009
1010 DBG("%s", gpu->name);
1011
1012 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
1013 msm_ringbuffer_destroy(gpu->rb[i]);
Destroying an error pointer is fine so this is okay.
1014 gpu->rb[i] = NULL;
1015 }
1016
1017 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace);
^^^
[QUESTION #2] Passing an error pointer here will trigger a stack trace
so this is bug. The drivers->aspace pointer is allocted in
