[Freedreno] [PATCH v3 07/13] drm/msm/dpu: avoid querying for hw intf before assignment

[Jeykumar Sankaran]

hw intf blocks are needed only during encoder enable to program
timing engines(for video panels). encoder->enable is triggered
only after atomic_modeset at which point we assign the
resources for the display pipeline. This patch defers the
hw_intf look-up until encoder enable.

changes in v2:
- none
changes in v3:
- none

Change-Id: Ib0a2253431468151355e50cbad7b91e2b77b6e54
Signed-off-by: Jeykumar Sankaran 
---
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 53 +++---
 1 file changed, 16 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index c0221cc..a0b3744 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -462,7 +462,7 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
 {
struct msm_drm_private *priv;
struct dpu_encoder_phys_vid *vid_enc;
-   struct dpu_hw_intf *intf;
+   struct dpu_rm_hw_iter iter;
struct dpu_hw_ctl *ctl;
u32 flush_mask = 0;
 
@@ -474,11 +474,20 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
priv = phys_enc->parent->dev->dev_private;
 
vid_enc = to_dpu_encoder_phys_vid(phys_enc);
-   intf = vid_enc->hw_intf;
ctl = phys_enc->hw_ctl;
-   if (!vid_enc->hw_intf || !phys_enc->hw_ctl) {
-   DPU_ERROR("invalid hw_intf %d hw_ctl %d\n",
-   vid_enc->hw_intf != 0, phys_enc->hw_ctl != 0);
+
+   dpu_rm_init_hw_iter(, phys_enc->parent->base.id, DPU_HW_BLK_INTF);
+   while (dpu_rm_get_hw(_enc->dpu_kms->rm, )) {
+   struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
+
+   if (hw_intf->idx == phys_enc->intf_idx) {
+   vid_enc->hw_intf = hw_intf;
+   break;
+   }
+   }
+
+   if (!vid_enc->hw_intf) {
+   DPU_ERROR("hw_intf not assigned\n");
return;
}
 
@@ -500,7 +509,7 @@ static void dpu_encoder_phys_vid_enable(struct 
dpu_encoder_phys *phys_enc)
!dpu_encoder_phys_vid_is_master(phys_enc))
goto skip_flush;
 
-   ctl->ops.get_bitmask_intf(ctl, _mask, intf->idx);
+   ctl->ops.get_bitmask_intf(ctl, _mask, vid_enc->hw_intf->idx);
ctl->ops.update_pending_flush(ctl, flush_mask);
 
 skip_flush:
@@ -531,22 +540,13 @@ static void dpu_encoder_phys_vid_get_hw_resources(
struct dpu_encoder_hw_resources *hw_res,
struct drm_connector_state *conn_state)
 {
-   struct dpu_encoder_phys_vid *vid_enc;
-
if (!phys_enc || !hw_res) {
DPU_ERROR("invalid arg(s), enc %d hw_res %d conn_state %d\n",
phys_enc != 0, hw_res != 0, conn_state != 0);
return;
}
 
-   vid_enc = to_dpu_encoder_phys_vid(phys_enc);
-   if (!vid_enc->hw_intf) {
-   DPU_ERROR("invalid arg(s), hw_intf\n");
-   return;
-   }
-
-   DPU_DEBUG_VIDENC(vid_enc, "\n");
-   hw_res->intfs[vid_enc->hw_intf->idx - INTF_0] = INTF_MODE_VIDEO;
+   hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;
 }
 
 static int _dpu_encoder_phys_vid_wait_for_vblank(
@@ -809,7 +809,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
 {
struct dpu_encoder_phys *phys_enc = NULL;
struct dpu_encoder_phys_vid *vid_enc = NULL;
-   struct dpu_rm_hw_iter iter;
struct dpu_encoder_irq *irq;
int i, ret = 0;
 
@@ -829,26 +828,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
phys_enc->intf_idx = p->intf_idx;
 
-   /**
-* hw_intf resource permanently assigned to this encoder
-* Other resources allocated at atomic commit time by use case
-*/
-   dpu_rm_init_hw_iter(, 0, DPU_HW_BLK_INTF);
-   while (dpu_rm_get_hw(>dpu_kms->rm, )) {
-   struct dpu_hw_intf *hw_intf = (struct dpu_hw_intf *)iter.hw;
-
-   if (hw_intf->idx == p->intf_idx) {
-   vid_enc->hw_intf = hw_intf;
-   break;
-   }
-   }
-
-   if (!vid_enc->hw_intf) {
-   ret = -EINVAL;
-   DPU_ERROR("failed to get hw_intf\n");
-   goto fail;
-   }
-
DPU_DEBUG_VIDENC(vid_enc, "\n");
 
dpu_encoder_phys_vid_init_ops(_enc->ops);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[Freedreno] [PATCH v3 06/13] drm/msm/dpu: iterate for assigned hw ctl in virtual encoder

[Jeykumar Sankaran]

Instead of iterating for hw ctrl per physical encoder, this
patch moves the iterations and assignment to the virtual encoder.

changes in v2:
- none
changes in v3:
- none

Change-Id: I896a8c36d6353986582e9d0fe3da9b2293579d4b
Signed-off-by: Jeykumar Sankaran 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 22 --
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 19 ---
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   | 19 ---
 3 files changed, 20 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index a0ced79..7b82e2d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1017,9 +1017,11 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder 
*drm_enc,
struct dpu_kms *dpu_kms;
struct list_head *connector_list;
struct drm_connector *conn = NULL, *conn_iter;
-   struct dpu_rm_hw_iter pp_iter;
+   struct dpu_rm_hw_iter pp_iter, ctl_iter;
struct msm_display_topology topology;
enum dpu_rm_topology_name topology_name;
+   struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC];
+
int i = 0, ret;
 
if (!drm_enc) {
@@ -1067,6 +1069,14 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder 
*drm_enc,
dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
}
 
+   dpu_rm_init_hw_iter(_iter, drm_enc->base.id, DPU_HW_BLK_CTL);
+   for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
+   hw_ctl[i] = NULL;
+   if (!dpu_rm_get_hw(_kms->rm, _iter))
+   break;
+   hw_ctl[i] = (struct dpu_hw_ctl *)ctl_iter.hw;
+   }
+
topology_name = dpu_rm_get_topology_name(topology);
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
@@ -1074,10 +1084,18 @@ static void dpu_encoder_virt_mode_set(struct 
drm_encoder *drm_enc,
if (phys) {
if (!dpu_enc->hw_pp[i]) {
DPU_ERROR_ENC(dpu_enc,
-   "invalid pingpong block for the encoder\n");
+   "no pp block assigned at idx: %d\n", i);
return;
}
phys->hw_pp = dpu_enc->hw_pp[i];
+
+   if (!hw_ctl[i]) {
+   DPU_ERROR_ENC(dpu_enc,
+   "no ctl block assigned at idx: %d\n", i);
+   return;
+   }
+   phys->hw_ctl = hw_ctl[i];
+
phys->connector = conn->state->connector;
phys->topology_name = topology_name;
if (phys->ops.mode_set)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index c8c4612..5c89868 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -196,9 +196,6 @@ static void dpu_encoder_phys_cmd_mode_set(
 {
struct dpu_encoder_phys_cmd *cmd_enc =
to_dpu_encoder_phys_cmd(phys_enc);
-   struct dpu_rm *rm = _enc->dpu_kms->rm;
-   struct dpu_rm_hw_iter iter;
-   int i, instance;
 
if (!phys_enc || !mode || !adj_mode) {
DPU_ERROR("invalid args\n");
@@ -208,22 +205,6 @@ static void dpu_encoder_phys_cmd_mode_set(
DPU_DEBUG_CMDENC(cmd_enc, "caching mode:\n");
drm_mode_debug_printmodeline(adj_mode);
 
-   instance = phys_enc->split_role == ENC_ROLE_SLAVE ? 1 : 0;
-
-   /* Retrieve previously allocated HW Resources. Shouldn't fail */
-   dpu_rm_init_hw_iter(, phys_enc->parent->base.id, DPU_HW_BLK_CTL);
-   for (i = 0; i <= instance; i++) {
-   if (dpu_rm_get_hw(rm, ))
-   phys_enc->hw_ctl = (struct dpu_hw_ctl *)iter.hw;
-   }
-
-   if (IS_ERR_OR_NULL(phys_enc->hw_ctl)) {
-   DPU_ERROR_CMDENC(cmd_enc, "failed to init ctl: %ld\n",
-   PTR_ERR(phys_enc->hw_ctl));
-   phys_enc->hw_ctl = NULL;
-   return;
-   }
-
_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 57ece03..c0221cc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -395,9 +395,6 @@ static void dpu_encoder_phys_vid_mode_set(
struct drm_display_mode *mode,
  

[Freedreno] [PATCH v3 05/13] drm/msm/dpu: use kms stored hw mdp block

[Jeykumar Sankaran]

Avoid querying RM for hw mdp block. Use the one
stored in KMS during initialization.

changes in v2:
- none
changes in v3:
- none

Change-Id: I52129b96bd561a5547507d7f567bcaa3dbe554aa
Signed-off-by: Jeykumar Sankaran 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 12 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c |  9 +
 2 files changed, 2 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 3084675..c8c4612 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -823,7 +823,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
 {
struct dpu_encoder_phys *phys_enc = NULL;
struct dpu_encoder_phys_cmd *cmd_enc = NULL;
-   struct dpu_hw_mdp *hw_mdp;
struct dpu_encoder_irq *irq;
int i, ret = 0;
 
@@ -836,14 +835,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
goto fail;
}
phys_enc = _enc->base;
-
-   hw_mdp = dpu_rm_get_mdp(>dpu_kms->rm);
-   if (IS_ERR_OR_NULL(hw_mdp)) {
-   ret = PTR_ERR(hw_mdp);
-   DPU_ERROR("failed to get mdptop\n");
-   goto fail_mdp_init;
-   }
-   phys_enc->hw_mdptop = hw_mdp;
+   phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
phys_enc->intf_idx = p->intf_idx;
 
dpu_encoder_phys_cmd_init_ops(_enc->ops);
@@ -898,8 +890,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
 
return phys_enc;
 
-fail_mdp_init:
-   kfree(cmd_enc);
 fail:
return ERR_PTR(ret);
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 14fc7c2..57ece03 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -829,7 +829,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
struct dpu_encoder_phys *phys_enc = NULL;
struct dpu_encoder_phys_vid *vid_enc = NULL;
struct dpu_rm_hw_iter iter;
-   struct dpu_hw_mdp *hw_mdp;
struct dpu_encoder_irq *irq;
int i, ret = 0;
 
@@ -846,13 +845,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
 
phys_enc = _enc->base;
 
-   hw_mdp = dpu_rm_get_mdp(>dpu_kms->rm);
-   if (IS_ERR_OR_NULL(hw_mdp)) {
-   ret = PTR_ERR(hw_mdp);
-   DPU_ERROR("failed to get mdptop\n");
-   goto fail;
-   }
-   phys_enc->hw_mdptop = hw_mdp;
+   phys_enc->hw_mdptop = p->dpu_kms->hw_mdp;
phys_enc->intf_idx = p->intf_idx;
 
/**
-- 
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a Linux Foundation Collaborative Project

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[Freedreno] [PATCH v3 02/13] drm/msm/dpu: remove resource pool manager

[Jeykumar Sankaran]

resource pool manager utility was introduced to manage
rotator sessions. Removing the support as the rotator
feature doesn't exist.

changes in v2:
- none
changes in v3:
- rebase on [1]

[1] https://gitlab.freedesktop.org/seanpaul/dpu-staging/commits/for-next

Change-Id: Ib045f1c66269be650bce5896c459f59e1047a53f
Signed-off-by: Jeykumar Sankaran 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 205 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |  56 -
 2 files changed, 261 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 80cbf75..1f2d223 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -99,187 +99,6 @@ static inline int _dpu_crtc_power_enable(struct dpu_crtc 
*dpu_crtc, bool enable)
return 0;
 }
 
-/**
- * _dpu_crtc_rp_to_crtc - get crtc from resource pool object
- * @rp: Pointer to resource pool
- * return: Pointer to drm crtc if success; null otherwise
- */
-static struct drm_crtc *_dpu_crtc_rp_to_crtc(struct dpu_crtc_respool *rp)
-{
-   if (!rp)
-   return NULL;
-
-   return container_of(rp, struct dpu_crtc_state, rp)->base.crtc;
-}
-
-/**
- * _dpu_crtc_rp_reclaim - reclaim unused, or all if forced, resources in pool
- * @rp: Pointer to resource pool
- * @force: True to reclaim all resources; otherwise, reclaim only unused ones
- * return: None
- */
-static void _dpu_crtc_rp_reclaim(struct dpu_crtc_respool *rp, bool force)
-{
-   struct dpu_crtc_res *res, *next;
-   struct drm_crtc *crtc;
-
-   crtc = _dpu_crtc_rp_to_crtc(rp);
-   if (!crtc) {
-   DPU_ERROR("invalid crtc\n");
-   return;
-   }
-
-   DPU_DEBUG("crtc%d.%u %s\n", crtc->base.id, rp->sequence_id,
-   force ? "destroy" : "free_unused");
-
-   list_for_each_entry_safe(res, next, >res_list, list) {
-   if (!force && !(res->flags & DPU_CRTC_RES_FLAG_FREE))
-   continue;
-   DPU_DEBUG("crtc%d.%u reclaim res:0x%x/0x%llx/%pK/%d\n",
-   crtc->base.id, rp->sequence_id,
-   res->type, res->tag, res->val,
-   atomic_read(>refcount));
-   list_del(>list);
-   if (res->ops.put)
-   res->ops.put(res->val);
-   kfree(res);
-   }
-}
-
-/**
- * _dpu_crtc_rp_free_unused - free unused resource in pool
- * @rp: Pointer to resource pool
- * return: none
- */
-static void _dpu_crtc_rp_free_unused(struct dpu_crtc_respool *rp)
-{
-   mutex_lock(rp->rp_lock);
-   _dpu_crtc_rp_reclaim(rp, false);
-   mutex_unlock(rp->rp_lock);
-}
-
-/**
- * _dpu_crtc_rp_destroy - destroy resource pool
- * @rp: Pointer to resource pool
- * return: None
- */
-static void _dpu_crtc_rp_destroy(struct dpu_crtc_respool *rp)
-{
-   mutex_lock(rp->rp_lock);
-   list_del_init(>rp_list);
-   _dpu_crtc_rp_reclaim(rp, true);
-   mutex_unlock(rp->rp_lock);
-}
-
-/**
- * _dpu_crtc_hw_blk_get - get callback for hardware block
- * @val: Resource handle
- * @type: Resource type
- * @tag: Search tag for given resource
- * return: Resource handle
- */
-static void *_dpu_crtc_hw_blk_get(void *val, u32 type, u64 tag)
-{
-   DPU_DEBUG("res:%d/0x%llx/%pK\n", type, tag, val);
-   return dpu_hw_blk_get(val, type, tag);
-}
-
-/**
- * _dpu_crtc_hw_blk_put - put callback for hardware block
- * @val: Resource handle
- * return: None
- */
-static void _dpu_crtc_hw_blk_put(void *val)
-{
-   DPU_DEBUG("res://%pK\n", val);
-   dpu_hw_blk_put(val);
-}
-
-/**
- * _dpu_crtc_rp_duplicate - duplicate resource pool and reset reference count
- * @rp: Pointer to original resource pool
- * @dup_rp: Pointer to duplicated resource pool
- * return: None
- */
-static void _dpu_crtc_rp_duplicate(struct dpu_crtc_respool *rp,
-   struct dpu_crtc_respool *dup_rp)
-{
-   struct dpu_crtc_res *res, *dup_res;
-   struct drm_crtc *crtc;
-
-   if (!rp || !dup_rp || !rp->rp_head) {
-   DPU_ERROR("invalid resource pool\n");
-   return;
-   }
-
-   crtc = _dpu_crtc_rp_to_crtc(rp);
-   if (!crtc) {
-   DPU_ERROR("invalid crtc\n");
-   return;
-   }
-
-   DPU_DEBUG("crtc%d.%u duplicate\n", crtc->base.id, rp->sequence_id);
-
-   mutex_lock(rp->rp_lock);
-   dup_rp->sequence_id = rp->sequence_id + 1;
-   INIT_LIST_HEAD(_rp->res_list);
-   dup_rp->ops = rp->ops;
-   list_for_each_entry(res, >res_list, list) {
-   dup_res = kzalloc(sizeof(struct dpu_crtc_res), GFP_KERNEL);
-   if (!dup_res) {
-   m

[Freedreno] [PATCH v3 03/13] drm/msm/dpu: remove ping pong split topology variables

[Jeykumar Sankaran]

removes left out variables of previous ping pong
split topology cleanup.

changes in v2:
- none
changes in v3:
- none

Change-Id: I1bf9d242039ce7cfd271233fa27840e83184fb95
Signed-off-by: Jeykumar Sankaran 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index e84da78..e632651 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -219,7 +219,6 @@ struct dpu_crtc {
 /**
  * struct dpu_crtc_state - dpu container for atomic crtc state
  * @base: Base drm crtc state structure
- * @is_ppsplit: Whether current topology requires PPSplit special handling
  * @bw_control: true if bw/clk controlled by core bw/clk properties
  * @bw_split_vote : true if bw controlled by llcc/dram bw properties
  * @lm_bounds : LM boundaries based on current mode full resolution, no 
ROI.
@@ -234,8 +233,6 @@ struct dpu_crtc_state {
 
bool bw_control;
bool bw_split_vote;
-
-   bool is_ppsplit;
struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];
 
uint64_t input_fence_timeout_ns;
-- 
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a Linux Foundation Collaborative Project

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[Freedreno] [PATCH v3 00/13] Atomic resource management

[Jeykumar Sankaran]

This patchset series introduces drm private object in KMS to manage HW resource
management. It modifies the resource manager by introducing API's to do per DRM
object resource allocation/cleanups.

Patches 00/13 to 11/13 are clean up patches to prepare DPU for the above
migration.

major changes in v2:
- Fix return values in kms (Jordan)
- Split irrelevant changes from master patch
  into separate patches (Sean)

changes in v3:
- Rebase on [1]
- Fix control path bug in split LM topology

[1] https://gitlab.freedesktop.org/seanpaul/dpu-staging/commits/for-next

Jeykumar Sankaran (13):
  drm/msm/dpu: remove scalar config definitions
  drm/msm/dpu: remove resource pool manager
  drm/msm/dpu: remove ping pong split topology variables
  drm/msm/dpu: program master-slave encoders explicitly
  drm/msm/dpu: use kms stored hw mdp block
  drm/msm/dpu: iterate for assigned hw ctl in virtual encoder
  drm/msm/dpu: avoid querying for hw intf before assignment
  drm/msm/dpu: move hw resource tracking to crtc state
  drm/msm/dpu: rename hw_ctl to lm_ctl
  drm/msm/dpu: remove topology name
  drm/msm/dpu: remove display H_TILE from encoder
  drm/msm/dpu: add atomic private object to dpu kms
  drm/msm/dpu: use private obj to track hw resources

 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   | 427 +++
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   | 120 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 162 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   9 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |  31 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  88 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h|  10 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  80 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|  23 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 796 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 149 ++--
 12 files changed, 612 insertions(+), 1287 deletions(-)

-- 
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a Linux Foundation Collaborative Project

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[Freedreno] [PATCH v3 01/13] drm/msm/dpu: remove scalar config definitions

[Jeykumar Sankaran]

cleans up left out scalar config definitions from headers

changes in v2:
- none
changes in v3:
- none

Change-Id: Id824dd5075c666f97b964573c97215bb786eac75
Signed-off-by: Jeykumar Sankaran 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  2 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 10 --
 2 files changed, 12 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index e87109e..0e9aafa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -164,7 +164,6 @@ struct dpu_crtc_frame_event {
  * @cur_perf  : current performance committed to clock/bandwidth driver
  * @rp_lock   : serialization lock for resource pool
  * @rp_head   : list of active resource pool
- * @scl3_cfg_lut  : qseed3 lut config
  */
 struct dpu_crtc {
struct drm_crtc base;
@@ -175,7 +174,6 @@ struct dpu_crtc {
u32 num_mixers;
bool mixers_swapped;
struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
-   struct dpu_hw_scaler3_lut_cfg *scl3_lut_cfg;
 
struct drm_pending_vblank_event *event;
u32 vsync_count;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 1240f50..c5c8f60 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -148,16 +148,6 @@ struct dpu_hw_scaler3_cfg {
struct dpu_hw_scaler3_de_cfg de;
 };
 
-struct dpu_hw_scaler3_lut_cfg {
-   bool is_configured;
-   u32 *dir_lut;
-   size_t dir_len;
-   u32 *cir_lut;
-   size_t cir_len;
-   u32 *sep_lut;
-   size_t sep_len;
-};
-
 /**
  * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
  * @num_ext_pxls_lr: Number of total horizontal pixels
-- 
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[Freedreno] [PATCH] drm/msm/disp/dpu: fix early dereference of physical encoder

[Jeykumar Sankaran]

This change validates the physical encoder before it
is dereferenced.

Signed-off-by: Jeykumar Sankaran 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 0922d35..1b4de34 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2444,6 +2444,8 @@ int dpu_encoder_wait_for_event(struct drm_encoder 
*drm_enc,
 
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
+   if (!phys)
+   continue;
 
switch (event) {
case MSM_ENC_COMMIT_DONE:
@@ -2461,7 +2463,7 @@ int dpu_encoder_wait_for_event(struct drm_encoder 
*drm_enc,
return -EINVAL;
};
 
-   if (phys && fn_wait) {
+   if (fn_wait) {
DPU_ATRACE_BEGIN("wait_for_completion_event");
ret = fn_wait(phys);
DPU_ATRACE_END("wait_for_completion_event");
-- 
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Re: [Freedreno] [bug report] drm/msm: Add SDM845 DPU support

[Jeykumar Sankaran]

On 2018-08-07 05:09, Dan Carpenter wrote:

Hello Jeykumar Sankaran,

This is a semi-automatic email about new static checker warnings.

The patch 25fdd5933e4c: "drm/msm: Add SDM845 DPU support" from Jun
27, 2018, leads to the following Smatch complaint:

./drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c:2464
dpu_encoder_wait_for_event()
 warn: variable dereferenced before check 'phys' (see line 2456)

./drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
  2455  case MSM_ENC_VBLANK:
  2456  fn_wait = phys->ops.wait_for_vblank;
  
We always dereference "phys"
  2457  break;
  2458  default:
  2459  DPU_ERROR_ENC(dpu_enc, "unknown wait event
%d\n",
  2460  event);
  2461  return -EINVAL;
^^
or we return

  2462  };
  2463
  2464  if (phys && fn_wait) {

This check is too late.

  2465
DPU_ATRACE_BEGIN("wait_for_completion_event");
  2466  ret = fn_wait(phys);

regards,
dan carpenter
Thanks for bringing to our attention Dan. Will post a fix for the 
warning soon.

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Re: [Freedreno] [PATCH v3 03/19] drm: add msm compressed format modifiers

[Jeykumar Sankaran]

On 2018-07-25 07:09, Stanimir Varbanov wrote:

Hi,

On 07/20/2018 11:42 PM, Sean Paul wrote:

From: Jeykumar Sankaran 

Qualcomm Snapdragon chipsets uses compressed format
to optimize BW across multiple IP's. This change adds
needed modifier support in drm for a simple 4x4 tile
based compressed variants of base formats.

Changes in v3:
- Removed duplicate entry for DRM_FORMAT_MOD_QCOM_COMPRESSED (Rob 
Clark)


Signed-off-by: Jeykumar Sankaran 
Signed-off-by: Sean Paul 
---
 include/uapi/drm/drm_fourcc.h | 37 
+++

 1 file changed, 37 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h 
b/include/uapi/drm/drm_fourcc.h

index e04613d30a13..1c9a6bf8c81e 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -298,6 +298,43 @@ extern "C" {
  */
 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE  fourcc_mod_code(SAMSUNG, 1)

+/*
+ * Qualcomm Compressed Format
+ *
+ * Refers to a compressed variant of the base format that is 
compressed.

+ * Implementation may be platform and base-format specific.
+ *
+ * Each macrotile consists of m x n (mostly 4 x 4) tiles.
+ * Pixel data pitch/stride is aligned with macrotile width.
+ * Pixel data height is aligned with macrotile height.
+ * Entire pixel data buffer is aligned with 4k(bytes).
+ */
+#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
+
+/*
+ * QTI DX Format
+ *
+ * Refers to a DX variant of the base format.
+ * Implementation may be platform and base-format specific.
+ */
+#define DRM_FORMAT_MOD_QCOM_DX fourcc_mod_code(QCOM, 0x2)


What DX stands for?


_DX is QCOM modifier for identifying 10bit version of NV12 format since 
there is no fourcc_code for the same.


--
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Re: [Freedreno] [DPU PATCH 4/4] drm/msm/dpu: use private obj to track hw resources

[Jeykumar Sankaran]

On 2018-06-13 09:44, Jordan Crouse wrote:

On Tue, Jun 12, 2018 at 06:17:47PM -0700, Jeykumar Sankaran wrote:

Switch to state based resource management. This patch
overhauls the resource manager and HW allocation methods by
maintaining the global resource pool and allocated hw
blocks in respective drm component states.

Global resource manager(RM) is tracked in private object.
Allocation strategy is switched from single point allocation
of HW resources for the display pipeline to per component
based allocation, where each drm component allocates HW
blocks mapped to it's domain and tracks them in their respective
state objects.

Fixes resource contention due to race conditions between
user space and display thread by reserving resources
only in atomic check.

Signed-off-by: Jeykumar Sankaran 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   | 210 +++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |  59 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 223 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   9 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |  32 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  86 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  19 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|   8 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 805

++---

 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 149 ++--
 11 files changed, 534 insertions(+), 1070 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

index 426e2ad..a484c06 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -47,6 +47,8 @@
 #define RIGHT_MIXER 1

 #define MISR_BUFF_SIZE 256
+#define MAX_VDISPLAY_SPLIT 1080
+

 static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc 
*crtc)

 {
@@ -142,9 +144,9 @@ static void _dpu_crtc_program_lm_output_roi(struct

drm_crtc *crtc)

crtc_state = to_dpu_crtc_state(crtc->state);

lm_horiz_position = 0;
-   for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
+   for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
const struct dpu_rect *lm_roi =

_state->lm_bounds[lm_idx];

-   struct dpu_hw_mixer *hw_lm =

dpu_crtc->mixers[lm_idx].hw_lm;

+   struct dpu_hw_mixer *hw_lm =

crtc_state->mixers[lm_idx].hw_lm;

struct dpu_hw_mixer_cfg cfg;

if (dpu_kms_rect_is_null(lm_roi))
@@ -182,7 +184,7 @@ static void _dpu_crtc_blend_setup_mixer(struct

drm_crtc *crtc,

return;
}

-   ctl = mixer->hw_ctl;
+   ctl = mixer->lm_ctl;
lm = mixer->hw_lm;
stage_cfg = _crtc->stage_cfg;
cstate = to_dpu_crtc_state(crtc->state);
@@ -237,7 +239,7 @@ static void _dpu_crtc_blend_setup_mixer(struct

drm_crtc *crtc,

format->base.pixel_format, fb ? fb->modifier : 0);

/* blend config update */
-   for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++)

{

+   for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate);

mixer[lm_idx].flush_mask |= flush_mask;
@@ -260,7 +262,7 @@ static void _dpu_crtc_blend_setup_mixer(struct

drm_crtc *crtc,

 static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
 {
struct dpu_crtc *dpu_crtc;
-   struct dpu_crtc_state *dpu_crtc_state;
+   struct dpu_crtc_state *cstate;
struct dpu_crtc_mixer *mixer;
struct dpu_hw_ctl *ctl;
struct dpu_hw_mixer *lm;
@@ -271,26 +273,26 @@ static void _dpu_crtc_blend_setup(struct 
drm_crtc

*crtc)

return;

dpu_crtc = to_dpu_crtc(crtc);
-   dpu_crtc_state = to_dpu_crtc_state(crtc->state);
-   mixer = dpu_crtc->mixers;
+   cstate = to_dpu_crtc_state(crtc->state);
+   mixer = cstate->mixers;

DPU_DEBUG("%s\n", dpu_crtc->name);

-   if (dpu_crtc->num_mixers > CRTC_DUAL_MIXERS) {
-   DPU_ERROR("invalid number mixers: %d\n",

dpu_crtc->num_mixers);

+   if (cstate->num_mixers > CRTC_DUAL_MIXERS) {
+   DPU_ERROR("invalid number mixers: %d\n",

cstate->num_mixers);

Nit - this could be worded a bit better - "too many mixers" would be
better, but
I have to ask - under what circumstances would the number of mixers be
larger
than CRTC_DUAL_MIXERS and/or why don't we support a dynamic number of
mixers?


Comes from downstream driver implementation where CRTC iterates through
RM free pool to identify mixers tagged with the current crtc id. If the
previous clean up was screwed up this may have mo

Re: [Freedreno] [DPU PATCH 1/4] drm/msm/dpu: add atomic private object to dpu kms

[Jeykumar Sankaran]

On 2018-06-13 09:29, Jordan Crouse wrote:

On Tue, Jun 12, 2018 at 06:17:44PM -0700, Jeykumar Sankaran wrote:

Subclass drm private state for DPU for handling driver
specific data. Adds atomic private object and private object
lock to dpu kms. Provides helper function to retrieve DPU
private data from current atomic state.

Signed-off-by: Jeykumar Sankaran 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 66

+

 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 15 
 2 files changed, 81 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

index fe614c0..a4ab783 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1076,6 +1076,10 @@ static void dpu_kms_destroy(struct msm_kms 
*kms)


dpu_kms = to_dpu_kms(kms);
_dpu_kms_hw_destroy(dpu_kms);
+
+   drm_atomic_private_obj_fini(_kms->priv_obj);
+   drm_modeset_lock_fini(_kms->priv_obj_lock);
+
 }

 static void dpu_kms_preclose(struct msm_kms *kms, struct drm_file

*file)
@@ -1618,10 +1622,59 @@ static int dpu_kms_hw_init(struct msm_kms 
*kms)

return rc;
 }

+struct dpu_private_state *dpu_get_private_state(struct 
drm_atomic_state

*state)

+{
+   struct msm_drm_private *priv = state->dev->dev_private;
+   struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
+   struct drm_private_state *priv_state;
+   int rc = 0;
+
+   rc = drm_modeset_lock(_kms->priv_obj_lock,

state->acquire_ctx);

+   if (rc)
+   return ERR_PTR(rc);
+
+   priv_state = drm_atomic_get_private_obj_state(state,
+   _kms->priv_obj);
+   if (!priv_state)
+   return NULL;


I'll have to see later when this function is used, but I generally 
don't

like it
when functions return both ERR_PTR and NULL on error but I'm leaving 
open

the
possibility that this could NULL for legitimate reasons. If not, please
convert
to a ERR_PTR.

I see drm_atomic_get_private_obj_state returns ERR_PTR(-ENOMEM) on error 
cases. So I should

be good with IS_ERR/ERR_PTR.

+   return to_dpu_private_state(priv_state);
+}
+
+static struct drm_private_state *
+dpu_private_obj_duplicate_state(struct drm_private_obj *obj)
+{
+   struct dpu_private_state *dpu_priv_state;
+
+   dpu_priv_state = kmemdup(obj->state,
+   sizeof(*dpu_priv_state), GFP_KERNEL);
+   if (!dpu_priv_state)
+   return NULL;
+
+   __drm_atomic_helper_private_obj_duplicate_state(obj,
+   _priv_state->base);
+
+   return _priv_state->base;
+}
+
+static void dpu_private_obj_destroy_state(struct drm_private_obj 
*obj,

+ struct drm_private_state *state)
+{
+   struct dpu_private_state *dpu_priv_state =

to_dpu_private_state(state);

+
+   kfree(dpu_priv_state);
+}
+
+static const struct drm_private_state_funcs priv_obj_funcs = {
+   .atomic_duplicate_state = dpu_private_obj_duplicate_state,
+   .atomic_destroy_state = dpu_private_obj_destroy_state,
+};
+
 struct msm_kms *dpu_kms_init(struct drm_device *dev)
 {
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
+   struct dpu_private_state *dpu_priv_state;
int irq;

if (!dev || !dev->dev_private) {
@@ -1639,6 +1692,19 @@ struct msm_kms *dpu_kms_init(struct drm_device

*dev)

}
dpu_kms->base.irq = irq;

+   /* Initialize private obj's */
+   drm_modeset_lock_init(_kms->priv_obj_lock);
+
+   dpu_priv_state = kzalloc(sizeof(*dpu_priv_state), GFP_KERNEL);
+   if (!dpu_priv_state) {
+   DPU_ERROR("failed to allocate dpu priv obj\n");


We don't need an error message on memory failure - you will have no
problem
identifying when this went boom if it goes boom.


Will remove

+   return ERR_PTR(-ENOMEM);
+   }
+
+   drm_atomic_private_obj_init(_kms->priv_obj,
+   _priv_state->base,
+   _obj_funcs);
+
return _kms->base;
 }

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h

index 046e6f7..924d8967 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -190,6 +190,9 @@ struct dpu_kms {
struct dpu_hw_vbif *hw_vbif[VBIF_MAX];
struct dpu_hw_mdp *hw_mdp;

+   struct drm_modeset_lock priv_obj_lock;
+   struct drm_private_obj priv_obj;
+
bool has_danger_ctrl;

struct platform_device *pdev;
@@ -197,12 +200,24 @@ struct dpu_kms {
struct dss_module_power mp;
 };

+struct dpu_private_state {
+   struct drm_private_state base;
+};
+
 struct vsync_info {
u32 frame_count;
u32 line_count;
 };

 #define to_dpu_kms(x) container_of(x, struct dpu_kms, base)
+#define to_dpu_pri

[Freedreno] [DPU PATCH 4/4] drm/msm/dpu: use private obj to track hw resources

[Jeykumar Sankaran]

Switch to state based resource management. This patch
overhauls the resource manager and HW allocation methods by
maintaining the global resource pool and allocated hw
blocks in respective drm component states.

Global resource manager(RM) is tracked in private object.
Allocation strategy is switched from single point allocation
of HW resources for the display pipeline to per component
based allocation, where each drm component allocates HW
blocks mapped to it's domain and tracks them in their respective
state objects.

Fixes resource contention due to race conditions between
user space and display thread by reserving resources
only in atomic check.

Signed-off-by: Jeykumar Sankaran 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   | 210 +++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |  59 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 223 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   9 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |  32 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  86 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  19 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|   8 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 805 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 149 ++--
 11 files changed, 534 insertions(+), 1070 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 426e2ad..a484c06 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -47,6 +47,8 @@
 #define RIGHT_MIXER 1
 
 #define MISR_BUFF_SIZE 256
+#define MAX_VDISPLAY_SPLIT 1080
+
 
 static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
 {
@@ -142,9 +144,9 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc 
*crtc)
crtc_state = to_dpu_crtc_state(crtc->state);
 
lm_horiz_position = 0;
-   for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
+   for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
const struct dpu_rect *lm_roi = _state->lm_bounds[lm_idx];
-   struct dpu_hw_mixer *hw_lm = dpu_crtc->mixers[lm_idx].hw_lm;
+   struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;
struct dpu_hw_mixer_cfg cfg;
 
if (dpu_kms_rect_is_null(lm_roi))
@@ -182,7 +184,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc 
*crtc,
return;
}
 
-   ctl = mixer->hw_ctl;
+   ctl = mixer->lm_ctl;
lm = mixer->hw_lm;
stage_cfg = _crtc->stage_cfg;
cstate = to_dpu_crtc_state(crtc->state);
@@ -237,7 +239,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc 
*crtc,
format->base.pixel_format, fb ? fb->modifier : 0);
 
/* blend config update */
-   for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) {
+   for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
_dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate);
 
mixer[lm_idx].flush_mask |= flush_mask;
@@ -260,7 +262,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc 
*crtc,
 static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
 {
struct dpu_crtc *dpu_crtc;
-   struct dpu_crtc_state *dpu_crtc_state;
+   struct dpu_crtc_state *cstate;
struct dpu_crtc_mixer *mixer;
struct dpu_hw_ctl *ctl;
struct dpu_hw_mixer *lm;
@@ -271,26 +273,26 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
return;
 
dpu_crtc = to_dpu_crtc(crtc);
-   dpu_crtc_state = to_dpu_crtc_state(crtc->state);
-   mixer = dpu_crtc->mixers;
+   cstate = to_dpu_crtc_state(crtc->state);
+   mixer = cstate->mixers;
 
DPU_DEBUG("%s\n", dpu_crtc->name);
 
-   if (dpu_crtc->num_mixers > CRTC_DUAL_MIXERS) {
-   DPU_ERROR("invalid number mixers: %d\n", dpu_crtc->num_mixers);
+   if (cstate->num_mixers > CRTC_DUAL_MIXERS) {
+   DPU_ERROR("invalid number mixers: %d\n", cstate->num_mixers);
return;
}
 
-   for (i = 0; i < dpu_crtc->num_mixers; i++) {
-   if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
+   for (i = 0; i < cstate->num_mixers; i++) {
+   if (!mixer[i].hw_lm || !mixer[i].lm_ctl) {
DPU_ERROR("invalid lm or ctl assigned to mixer\n");
return;
}
mixer[i].mixer_op_mode = 0;
mixer[i].flush_mask = 0;
-   if (mixer[i].hw_ctl->ops.clear_all_blendstages)
-   

[Freedreno] [DPU PATCH 1/4] drm/msm/dpu: add atomic private object to dpu kms

[Jeykumar Sankaran]

Subclass drm private state for DPU for handling driver
specific data. Adds atomic private object and private object
lock to dpu kms. Provides helper function to retrieve DPU
private data from current atomic state.

Signed-off-by: Jeykumar Sankaran 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 66 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 15 
 2 files changed, 81 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index fe614c0..a4ab783 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1076,6 +1076,10 @@ static void dpu_kms_destroy(struct msm_kms *kms)
 
dpu_kms = to_dpu_kms(kms);
_dpu_kms_hw_destroy(dpu_kms);
+
+   drm_atomic_private_obj_fini(_kms->priv_obj);
+   drm_modeset_lock_fini(_kms->priv_obj_lock);
+
 }
 
 static void dpu_kms_preclose(struct msm_kms *kms, struct drm_file *file)
@@ -1618,10 +1622,59 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
return rc;
 }
 
+struct dpu_private_state *dpu_get_private_state(struct drm_atomic_state *state)
+{
+   struct msm_drm_private *priv = state->dev->dev_private;
+   struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
+   struct drm_private_state *priv_state;
+   int rc = 0;
+
+   rc = drm_modeset_lock(_kms->priv_obj_lock, state->acquire_ctx);
+   if (rc)
+   return ERR_PTR(rc);
+
+   priv_state = drm_atomic_get_private_obj_state(state,
+   _kms->priv_obj);
+   if (!priv_state)
+   return NULL;
+
+   return to_dpu_private_state(priv_state);
+}
+
+static struct drm_private_state *
+dpu_private_obj_duplicate_state(struct drm_private_obj *obj)
+{
+   struct dpu_private_state *dpu_priv_state;
+
+   dpu_priv_state = kmemdup(obj->state,
+   sizeof(*dpu_priv_state), GFP_KERNEL);
+   if (!dpu_priv_state)
+   return NULL;
+
+   __drm_atomic_helper_private_obj_duplicate_state(obj,
+   _priv_state->base);
+
+   return _priv_state->base;
+}
+
+static void dpu_private_obj_destroy_state(struct drm_private_obj *obj,
+ struct drm_private_state *state)
+{
+   struct dpu_private_state *dpu_priv_state = to_dpu_private_state(state);
+
+   kfree(dpu_priv_state);
+}
+
+static const struct drm_private_state_funcs priv_obj_funcs = {
+   .atomic_duplicate_state = dpu_private_obj_duplicate_state,
+   .atomic_destroy_state = dpu_private_obj_destroy_state,
+};
+
 struct msm_kms *dpu_kms_init(struct drm_device *dev)
 {
struct msm_drm_private *priv;
struct dpu_kms *dpu_kms;
+   struct dpu_private_state *dpu_priv_state;
int irq;
 
if (!dev || !dev->dev_private) {
@@ -1639,6 +1692,19 @@ struct msm_kms *dpu_kms_init(struct drm_device *dev)
}
dpu_kms->base.irq = irq;
 
+   /* Initialize private obj's */
+   drm_modeset_lock_init(_kms->priv_obj_lock);
+
+   dpu_priv_state = kzalloc(sizeof(*dpu_priv_state), GFP_KERNEL);
+   if (!dpu_priv_state) {
+   DPU_ERROR("failed to allocate dpu priv obj\n");
+   return ERR_PTR(-ENOMEM);
+   }
+
+   drm_atomic_private_obj_init(_kms->priv_obj,
+   _priv_state->base,
+   _obj_funcs);
+
return _kms->base;
 }
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index 046e6f7..924d8967 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -190,6 +190,9 @@ struct dpu_kms {
struct dpu_hw_vbif *hw_vbif[VBIF_MAX];
struct dpu_hw_mdp *hw_mdp;
 
+   struct drm_modeset_lock priv_obj_lock;
+   struct drm_private_obj priv_obj;
+
bool has_danger_ctrl;
 
struct platform_device *pdev;
@@ -197,12 +200,24 @@ struct dpu_kms {
struct dss_module_power mp;
 };
 
+struct dpu_private_state {
+   struct drm_private_state base;
+};
+
 struct vsync_info {
u32 frame_count;
u32 line_count;
 };
 
 #define to_dpu_kms(x) container_of(x, struct dpu_kms, base)
+#define to_dpu_private_state(x) container_of(x, struct dpu_private_state, base)
+
+/**
+ * dpu_get_private_state - get dpu private state from atomic state
+ * @state: drm atomic state
+ * Return: pointer to dpu private state object
+ */
+struct dpu_private_state *dpu_get_private_state(struct drm_atomic_state 
*state);
 
 /**
  * dpu_is_custom_client - whether or not to enable non-standard customizations
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[Freedreno] [DPU PATCH 3/4] drm/msm/dpu: remove resource pool manager

[Jeykumar Sankaran]

resource pool manager utility was introduced to manage
rotator sessions. Removing the support as the rotator
feature doesn't exist.

Signed-off-by: Jeykumar Sankaran 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 494 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |  84 --
 2 files changed, 578 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 9ca8325..426e2ad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -98,476 +98,6 @@ static inline int _dpu_crtc_power_enable(struct dpu_crtc 
*dpu_crtc, bool enable)
return 0;
 }
 
-/**
- * _dpu_crtc_rp_to_crtc - get crtc from resource pool object
- * @rp: Pointer to resource pool
- * return: Pointer to drm crtc if success; null otherwise
- */
-static struct drm_crtc *_dpu_crtc_rp_to_crtc(struct dpu_crtc_respool *rp)
-{
-   if (!rp)
-   return NULL;
-
-   return container_of(rp, struct dpu_crtc_state, rp)->base.crtc;
-}
-
-/**
- * _dpu_crtc_rp_reclaim - reclaim unused, or all if forced, resources in pool
- * @rp: Pointer to resource pool
- * @force: True to reclaim all resources; otherwise, reclaim only unused ones
- * return: None
- */
-static void _dpu_crtc_rp_reclaim(struct dpu_crtc_respool *rp, bool force)
-{
-   struct dpu_crtc_res *res, *next;
-   struct drm_crtc *crtc;
-
-   crtc = _dpu_crtc_rp_to_crtc(rp);
-   if (!crtc) {
-   DPU_ERROR("invalid crtc\n");
-   return;
-   }
-
-   DPU_DEBUG("crtc%d.%u %s\n", crtc->base.id, rp->sequence_id,
-   force ? "destroy" : "free_unused");
-
-   list_for_each_entry_safe(res, next, >res_list, list) {
-   if (!force && !(res->flags & DPU_CRTC_RES_FLAG_FREE))
-   continue;
-   DPU_DEBUG("crtc%d.%u reclaim res:0x%x/0x%llx/%pK/%d\n",
-   crtc->base.id, rp->sequence_id,
-   res->type, res->tag, res->val,
-   atomic_read(>refcount));
-   list_del(>list);
-   if (res->ops.put)
-   res->ops.put(res->val);
-   kfree(res);
-   }
-}
-
-/**
- * _dpu_crtc_rp_free_unused - free unused resource in pool
- * @rp: Pointer to resource pool
- * return: none
- */
-static void _dpu_crtc_rp_free_unused(struct dpu_crtc_respool *rp)
-{
-   mutex_lock(rp->rp_lock);
-   _dpu_crtc_rp_reclaim(rp, false);
-   mutex_unlock(rp->rp_lock);
-}
-
-/**
- * _dpu_crtc_rp_destroy - destroy resource pool
- * @rp: Pointer to resource pool
- * return: None
- */
-static void _dpu_crtc_rp_destroy(struct dpu_crtc_respool *rp)
-{
-   mutex_lock(rp->rp_lock);
-   list_del_init(>rp_list);
-   _dpu_crtc_rp_reclaim(rp, true);
-   mutex_unlock(rp->rp_lock);
-}
-
-/**
- * _dpu_crtc_hw_blk_get - get callback for hardware block
- * @val: Resource handle
- * @type: Resource type
- * @tag: Search tag for given resource
- * return: Resource handle
- */
-static void *_dpu_crtc_hw_blk_get(void *val, u32 type, u64 tag)
-{
-   DPU_DEBUG("res:%d/0x%llx/%pK\n", type, tag, val);
-   return dpu_hw_blk_get(val, type, tag);
-}
-
-/**
- * _dpu_crtc_hw_blk_put - put callback for hardware block
- * @val: Resource handle
- * return: None
- */
-static void _dpu_crtc_hw_blk_put(void *val)
-{
-   DPU_DEBUG("res://%pK\n", val);
-   dpu_hw_blk_put(val);
-}
-
-/**
- * _dpu_crtc_rp_duplicate - duplicate resource pool and reset reference count
- * @rp: Pointer to original resource pool
- * @dup_rp: Pointer to duplicated resource pool
- * return: None
- */
-static void _dpu_crtc_rp_duplicate(struct dpu_crtc_respool *rp,
-   struct dpu_crtc_respool *dup_rp)
-{
-   struct dpu_crtc_res *res, *dup_res;
-   struct drm_crtc *crtc;
-
-   if (!rp || !dup_rp || !rp->rp_head) {
-   DPU_ERROR("invalid resource pool\n");
-   return;
-   }
-
-   crtc = _dpu_crtc_rp_to_crtc(rp);
-   if (!crtc) {
-   DPU_ERROR("invalid crtc\n");
-   return;
-   }
-
-   DPU_DEBUG("crtc%d.%u duplicate\n", crtc->base.id, rp->sequence_id);
-
-   mutex_lock(rp->rp_lock);
-   dup_rp->sequence_id = rp->sequence_id + 1;
-   INIT_LIST_HEAD(_rp->res_list);
-   dup_rp->ops = rp->ops;
-   list_for_each_entry(res, >res_list, list) {
-   dup_res = kzalloc(sizeof(struct dpu_crtc_res), GFP_KERNEL);
-   if (!dup_res) {
-   mutex_unlock(rp->rp_lock);
-   return;
-   }
-   INIT_LIST_HEAD(_res->list);
-   atomic_set(_res->refcount, 0);
- 

[Freedreno] [DPU PATCH 2/4] drm/msm/dpu: remove scalar config definitions

[Jeykumar Sankaran]

cleans up left out scalar config definitions from headers

Signed-off-by: Jeykumar Sankaran 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h|  1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 10 --
 2 files changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 39def93..099e58b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -194,7 +194,6 @@ struct dpu_crtc {
u32 num_mixers;
bool mixers_swapped;
struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
-   struct dpu_hw_scaler3_lut_cfg *scl3_lut_cfg;
 
struct drm_pending_vblank_event *event;
u32 vsync_count;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 42f1b22..71e8dd1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -148,16 +148,6 @@ struct dpu_hw_scaler3_cfg {
struct dpu_hw_scaler3_de_cfg de;
 };
 
-struct dpu_hw_scaler3_lut_cfg {
-   bool is_configured;
-   u32 *dir_lut;
-   size_t dir_len;
-   u32 *cir_lut;
-   size_t cir_len;
-   u32 *sep_lut;
-   size_t sep_len;
-};
-
 /**
  * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
  * @num_ext_pxls_lr: Number of total horizontal pixels
-- 
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a Linux Foundation Collaborative Project

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[Freedreno] [DPU PATCH 0/4] Atomic resource management

[Jeykumar Sankaran]

This patchset introduces drm private object in KMS to manage HW
resource management. It modifies the resource manager by
introducing API's to do per DRM object resource allocation/cleanups.

The patchset is based on: https://patchwork.kernel.org/patch/10461375/

Jeykumar Sankaran (4):
  drm/msm/dpu: add atomic private object to dpu kms
  drm/msm/dpu: remove scalar config definitions
  drm/msm/dpu: remove resource pool manager
  drm/msm/dpu: use private obj to track hw resources

 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   | 704 +++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   | 144 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 223 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   9 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |  32 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  86 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h|  10 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  85 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|  23 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 805 ++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 149 ++--
 12 files changed, 615 insertions(+), 1659 deletions(-)

-- 
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a Linux Foundation Collaborative Project

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[Freedreno] [DPU PATCH v3 3/7] drm/msm: enable zpos normalization

[Jeykumar Sankaran]

Enable drm core zpos normalization for planes.

changes in v2:
- none
changes in v3:
- rebased on https://gitlab.freedesktop.org/seanpaul/
  dpu-staging/commit/481d29d31cd629fd216381b53de5695f645465d5

Signed-off-by: Jeykumar Sankaran 
Reviewed-by: Sean Paul 
---
 drivers/gpu/drm/msm/msm_drv.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index acfda2a..ffea915 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -567,6 +567,9 @@ static int msm_drm_init(struct device *dev, struct 
drm_driver *drv)
ddev->mode_config.funcs = _config_funcs;
ddev->mode_config.helper_private = _config_helper_funcs;
 
+   /* Enable normalization of plane zpos */
+   ddev->mode_config.normalize_zpos = true;
+
if (kms) {
ret = kms->funcs->hw_init(kms);
if (ret) {
-- 
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a Linux Foundation Collaborative Project

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[Freedreno] [DPU PATCH v3 0/7] clean up DPU custom properties

[Jeykumar Sankaran]

Submitting a series of patches to further clean up DPU driver by stripping
down a list of custom properties supporting proprietary features. It 
removes the property installers/handlers and cleans up relevant files of
of some of the advanced features. This series is based on the patch[1] 
available on the drm-next tip.

[1]https://patchwork.kernel.org/patch/10202847/

Thanks.

changes in v2:
- remove stale code in blend config
- move unrelated code while updating zpos property
- Makefile changes
changes in v3:
- rebase on https://gitlab.freedesktop.org/seanpaul/
  dpu-staging/commit/481d29d31cd629fd216381b53de5695f645465d5

Thanks.

Jeykumar Sankaran (7):
  drm/msm: remove connector custom properties
  drm/msm/dpu: clean up dpu plane custom properties
  drm/msm: enable zpos normalization
  drm/msm/dpu: switch to drm zpos property
  Remove dpu crtc custom properties and its handlers.
  drm/msm: remove msm_prop files
  drm/msm: remove dpu specific uapi header

 drivers/gpu/drm/msm/Makefile   |9 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h|   99 --
 .../gpu/drm/msm/disp/dpu1/dpu_color_processing.c   | 1521 
 .../gpu/drm/msm/disp/dpu1/dpu_color_processing.h   |  120 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c  |   30 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   | 1328 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |   45 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|   14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c | 1443 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   72 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   89 --
 .../msm/disp/dpu1/dpu_hw_color_proc_common_v4.h|   69 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c   |  242 
 .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h   |   40 -
 .../drm/msm/disp/dpu1/dpu_hw_color_processing.h|   20 -
 .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.c   |  565 
 .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.h   |   92 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c |   44 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |   15 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c  |  149 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h  |  111 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c|  209 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h|  220 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c  |   67 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h  |   14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|   58 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|   68 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c  |  757 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h  |   27 -
 .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c   |  943 
 .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h   |   75 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c|  220 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h|   73 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c|1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h|  156 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|   11 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  | 1404 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h  |   43 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c|  139 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h|  310 
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  149 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |2 -
 drivers/gpu/drm/msm/msm_drv.c  |3 +
 drivers/gpu/drm/msm/msm_drv.h  |   86 +-
 drivers/gpu/drm/msm/msm_prop.c |  688 -
 drivers/gpu/drm/msm/msm_prop.h |  438 --
 include/uapi/drm/dpu_drm.h |  407 --
 include/uapi/drm/msm_drm.h |1 -
 include/uapi/drm/msm_drm_pp.h  |  345 -
 51 files changed, 297 insertions(+), 12742 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_common_v4.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.c
 delete mode 100644 drivers/gpu/drm/msm

[Freedreno] [DPU PATCH v3 1/7] drm/msm: remove connector custom properties

[Jeykumar Sankaran]

Cleanup residual connector property enumerations.

changes in v2:
- none
changes in v3:
- rebased on https://gitlab.freedesktop.org/seanpaul/
  dpu-staging/commit/481d29d31cd629fd216381b53de5695f645465d5

Signed-off-by: Jeykumar Sankaran 
Reviewed-by: Sean Paul 
---
 drivers/gpu/drm/msm/msm_drv.h | 27 ---
 1 file changed, 27 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 52a026d..b73112a 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -137,32 +137,6 @@ enum msm_mdp_crtc_property {
CRTC_PROP_COUNT
 };
 
-enum msm_mdp_conn_property {
-   /* blob properties, always put these first */
-   CONNECTOR_PROP_DPU_INFO,
-   CONNECTOR_PROP_HDR_INFO,
-   CONNECTOR_PROP_PP_DITHER,
-
-   /* # of blob properties */
-   CONNECTOR_PROP_BLOBCOUNT,
-
-   /* range properties */
-   CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT,
-   CONNECTOR_PROP_DST_X,
-   CONNECTOR_PROP_DST_Y,
-   CONNECTOR_PROP_DST_W,
-   CONNECTOR_PROP_DST_H,
-   CONNECTOR_PROP_BL_SCALE,
-   CONNECTOR_PROP_AD_BL_SCALE,
-
-   /* enum/bitmask properties */
-   CONNECTOR_PROP_AUTOREFRESH,
-   CONNECTOR_PROP_LP,
-
-   /* total # of properties */
-   CONNECTOR_PROP_COUNT
-};
-
 struct msm_vblank_ctrl {
struct kthread_work work;
struct list_head event_list;
@@ -428,7 +402,6 @@ struct msm_drm_private {
/* Properties */
struct drm_property *plane_property[PLANE_PROP_COUNT];
struct drm_property *crtc_property[CRTC_PROP_COUNT];
-   struct drm_property *conn_property[CONNECTOR_PROP_COUNT];
 
/* Color processing properties for the crtc */
struct drm_property **cp_property;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

___
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Freedreno@lists.freedesktop.org
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[Freedreno] [DPU PATCH v3 5/7] Remove dpu crtc custom properties and its handlers.

[Jeykumar Sankaran]

changes in v2:
- none
changes in v3:
- rebased on https://gitlab.freedesktop.org/seanpaul/
  dpu-staging/commit/481d29d31cd629fd216381b53de5695f645465d5

Signed-off-by: Jeykumar Sankaran 
Reviewed-by: Sean Paul 
---
 drivers/gpu/drm/msm/Makefile  |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |  28 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 856 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |  27 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   |  12 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c | 149 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h | 111 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c |  67 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h |  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h   |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c|  71 +--
 drivers/gpu/drm/msm/msm_drv.h |  15 -
 12 files changed, 11 insertions(+), 1356 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 8ec0bff..dc56904 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -57,7 +57,6 @@ msm-y := \
disp/dpu1/dpu_hw_catalog.o \
disp/dpu1/dpu_hw_cdm.o \
disp/dpu1/dpu_hw_ctl.o \
-   disp/dpu1/dpu_hw_ds.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
disp/dpu1/dpu_hw_lm.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 85c0229..7eafca3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -102,34 +102,6 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
dpu_cstate = to_dpu_crtc_state(state);
memset(perf, 0, sizeof(struct dpu_core_perf_params));
 
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-
-   if (dpu_cstate->bw_split_vote) {
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_LLCC_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_LLCC_IB);
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_DRAM_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_DRAM_IB);
-   } else {
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-   }
-
-   perf->core_clk_rate =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_CLK);
-
if (!dpu_cstate->bw_control) {
for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index a7d9aff..8254cd6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -574,18 +574,6 @@ static void _dpu_crtc_deinit_events(struct dpu_crtc 
*dpu_crtc)
return;
 }
 
-/**
- * dpu_crtc_destroy_dest_scaler - free memory allocated for scaler lut
- * @dpu_crtc: Pointer to dpu crtc
- */
-static void _dpu_crtc_destroy_dest_scaler(struct dpu_crtc *dpu_crtc)
-{
-   if (!dpu_crtc)
-   return;
-
-   kfree(dpu_crtc->scl3_lut_cfg);
-}
-
 static void dpu_crtc_destroy(struct drm_crtc *crtc)
 {
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
@@ -598,7 +586,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
if (dpu_crtc->blob_info)
drm_property_blob_put(dpu_crtc->blob_info);
msm_property_destroy(_crtc->property_info);
-   _dpu_crtc_destroy_dest_scaler(dpu_crtc);
 
_dpu_crtc_deinit_events(dpu_crtc);
dpu_crtc->phandle = NULL;
@@ -635,71 +622,6 @@ static void _dpu_crtc_setup_blend_cfg(struct 
dpu_crtc_mixer *mixer,
 

[Freedreno] [DPU PATCH v3 7/7] drm/msm: remove dpu specific uapi header

[Jeykumar Sankaran]

remove unwanted dpu uapi headers exposing custom
payload layouts for custom properties

changs in v2:
- none
changes in v3:
- rebased on https://gitlab.freedesktop.org/seanpaul/
  dpu-staging/commit/481d29d31cd629fd216381b53de5695f645465d5

Signed-off-by: Jeykumar Sankaran 
Reviewed-by: Sean Paul 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c |   1 -
 include/uapi/drm/dpu_drm.h| 220 ---
 include/uapi/drm/msm_drm_pp.h | 345 --
 4 files changed, 567 deletions(-)
 delete mode 100644 include/uapi/drm/dpu_drm.h
 delete mode 100644 include/uapi/drm/msm_drm_pp.h

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index cc23b33..39def93 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -20,7 +20,6 @@
 #define _DPU_CRTC_H_
 
 #include 
-#include 
 #include 
 #include "dpu_kms.h"
 #include "dpu_core_perf.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 830b69e..5b4d529 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -10,7 +10,6 @@
  * GNU General Public License for more details.
  */
 
-#include 
 #include "dpu_kms.h"
 #include "dpu_hw_catalog.h"
 #include "dpu_hwio.h"
diff --git a/include/uapi/drm/dpu_drm.h b/include/uapi/drm/dpu_drm.h
deleted file mode 100644
index 93af1fb..000
--- a/include/uapi/drm/dpu_drm.h
+++ /dev/null
@@ -1,220 +0,0 @@
-#ifndef _DPU_DRM_H_
-#define _DPU_DRM_H_
-
-#include "drm.h"
-
-/* Total number of supported color planes */
-#define DPU_MAX_PLANES  4
-
-/* Total number of parameterized detail enhancer mapping curves */
-#define DPU_MAX_DE_CURVES 3
-
- /* Y/RGB and UV filter configuration */
-#define FILTER_EDGE_DIRECTED_2D0x0
-#define FILTER_CIRCULAR_2D 0x1
-#define FILTER_SEPARABLE_1D0x2
-#define FILTER_BILINEAR0x3
-
-/* Alpha filters */
-#define FILTER_ALPHA_DROP_REPEAT   0x0
-#define FILTER_ALPHA_BILINEAR  0x1
-#define FILTER_ALPHA_2D0x3
-
-/* Blend filters */
-#define FILTER_BLEND_CIRCULAR_2D   0x0
-#define FILTER_BLEND_SEPARABLE_1D  0x1
-
-/* LUT configuration flags */
-#define SCALER_LUT_SWAP0x1
-#define SCALER_LUT_DIR_WR  0x2
-#define SCALER_LUT_Y_CIR_WR0x4
-#define SCALER_LUT_UV_CIR_WR   0x8
-#define SCALER_LUT_Y_SEP_WR0x10
-#define SCALER_LUT_UV_SEP_WR   0x20
-
-/**
- * Blend operations for "blend_op" property
- *
- * @DPU_DRM_BLEND_OP_NOT_DEFINED:   No blend operation defined for the layer.
- * @DPU_DRM_BLEND_OP_OPAQUE:Apply a constant blend operation. The layer
- *  would appear opaque in case fg plane alpha
- *  is 0xff.
- * @DPU_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already
- *  has alpha pre-multiplication done. If the 
fg
- *  plane alpha is less than 0xff, apply
- *  modulation as well. This operation is
- *  intended on layers having alpha channel.
- * @DPU_DRM_BLEND_OP_COVERAGE:  Apply source over blend rule. Layer is not
- *  alpha pre-multiplied. Apply
- *  pre-multiplication. If fg plane alpha is
- *  less than 0xff, apply modulation as well.
- * @DPU_DRM_BLEND_OP_MAX:   Used to track maximum blend operation
- *  possible by mdp.
- */
-#define DPU_DRM_BLEND_OP_NOT_DEFINED0
-#define DPU_DRM_BLEND_OP_OPAQUE 1
-#define DPU_DRM_BLEND_OP_PREMULTIPLIED  2
-#define DPU_DRM_BLEND_OP_COVERAGE   3
-#define DPU_DRM_BLEND_OP_MAX4
-
-/**
- * Bit masks for "src_config" property
- * construct bitmask via (1UL << DPU_DRM_)
- */
-#define DPU_DRM_DEINTERLACE 0   /* Specifies interlaced input */
-
-/* DRM bitmasks are restricted to 0..63 */
-#define DPU_DRM_BITMASK_COUNT   64
-
-/* Number of dest scalers supported */
-#define DPU_MAX_DS_COUNT 2
-
-/*
- * Destination scaler flag config
- */
-#define DPU_DRM_DESTSCALER_ENABLE   0x1
-#define DPU_DRM_DESTSCALER_SCALE_UPDATE 0x2
-#define DPU_DRM_DESTSCALER_ENHANCER_UPDATE  0x4
-#define DPU_DRM_DESTSCALER_PU_ENABLE0x8
-
-/**
- * struct dpu_drm_dest_scaler_cfg - destination scaler config structure
- * @flags:  Flag to switch between mode for destination scaler
- *  refer to destination scaler flag config
- * @index:  Destination scaler selection index
- * @lm_width:   Layer mixer

[Freedreno] [DPU PATCH v2 7/7] drm/msm: remove dpu specific uapi header

[Jeykumar Sankaran]

remove unwanted dpu uapi headers exposing custom
payload layouts for custom properties

changs in v2:
- none

Signed-off-by: Jeykumar Sankaran 
Reviewed-by: Sean Paul 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c |   1 -
 include/uapi/drm/dpu_drm.h| 220 ---
 include/uapi/drm/msm_drm_pp.h | 345 --
 4 files changed, 567 deletions(-)
 delete mode 100644 include/uapi/drm/dpu_drm.h
 delete mode 100644 include/uapi/drm/msm_drm_pp.h

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index f752101..9c89102 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -20,7 +20,6 @@
 #define _DPU_CRTC_H_
 
 #include 
-#include 
 #include 
 #include "dpu_kms.h"
 #include "dpu_core_perf.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 830b69e..5b4d529 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -10,7 +10,6 @@
  * GNU General Public License for more details.
  */
 
-#include 
 #include "dpu_kms.h"
 #include "dpu_hw_catalog.h"
 #include "dpu_hwio.h"
diff --git a/include/uapi/drm/dpu_drm.h b/include/uapi/drm/dpu_drm.h
deleted file mode 100644
index 93af1fb..000
--- a/include/uapi/drm/dpu_drm.h
+++ /dev/null
@@ -1,220 +0,0 @@
-#ifndef _DPU_DRM_H_
-#define _DPU_DRM_H_
-
-#include "drm.h"
-
-/* Total number of supported color planes */
-#define DPU_MAX_PLANES  4
-
-/* Total number of parameterized detail enhancer mapping curves */
-#define DPU_MAX_DE_CURVES 3
-
- /* Y/RGB and UV filter configuration */
-#define FILTER_EDGE_DIRECTED_2D0x0
-#define FILTER_CIRCULAR_2D 0x1
-#define FILTER_SEPARABLE_1D0x2
-#define FILTER_BILINEAR0x3
-
-/* Alpha filters */
-#define FILTER_ALPHA_DROP_REPEAT   0x0
-#define FILTER_ALPHA_BILINEAR  0x1
-#define FILTER_ALPHA_2D0x3
-
-/* Blend filters */
-#define FILTER_BLEND_CIRCULAR_2D   0x0
-#define FILTER_BLEND_SEPARABLE_1D  0x1
-
-/* LUT configuration flags */
-#define SCALER_LUT_SWAP0x1
-#define SCALER_LUT_DIR_WR  0x2
-#define SCALER_LUT_Y_CIR_WR0x4
-#define SCALER_LUT_UV_CIR_WR   0x8
-#define SCALER_LUT_Y_SEP_WR0x10
-#define SCALER_LUT_UV_SEP_WR   0x20
-
-/**
- * Blend operations for "blend_op" property
- *
- * @DPU_DRM_BLEND_OP_NOT_DEFINED:   No blend operation defined for the layer.
- * @DPU_DRM_BLEND_OP_OPAQUE:Apply a constant blend operation. The layer
- *  would appear opaque in case fg plane alpha
- *  is 0xff.
- * @DPU_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already
- *  has alpha pre-multiplication done. If the 
fg
- *  plane alpha is less than 0xff, apply
- *  modulation as well. This operation is
- *  intended on layers having alpha channel.
- * @DPU_DRM_BLEND_OP_COVERAGE:  Apply source over blend rule. Layer is not
- *  alpha pre-multiplied. Apply
- *  pre-multiplication. If fg plane alpha is
- *  less than 0xff, apply modulation as well.
- * @DPU_DRM_BLEND_OP_MAX:   Used to track maximum blend operation
- *  possible by mdp.
- */
-#define DPU_DRM_BLEND_OP_NOT_DEFINED0
-#define DPU_DRM_BLEND_OP_OPAQUE 1
-#define DPU_DRM_BLEND_OP_PREMULTIPLIED  2
-#define DPU_DRM_BLEND_OP_COVERAGE   3
-#define DPU_DRM_BLEND_OP_MAX4
-
-/**
- * Bit masks for "src_config" property
- * construct bitmask via (1UL << DPU_DRM_)
- */
-#define DPU_DRM_DEINTERLACE 0   /* Specifies interlaced input */
-
-/* DRM bitmasks are restricted to 0..63 */
-#define DPU_DRM_BITMASK_COUNT   64
-
-/* Number of dest scalers supported */
-#define DPU_MAX_DS_COUNT 2
-
-/*
- * Destination scaler flag config
- */
-#define DPU_DRM_DESTSCALER_ENABLE   0x1
-#define DPU_DRM_DESTSCALER_SCALE_UPDATE 0x2
-#define DPU_DRM_DESTSCALER_ENHANCER_UPDATE  0x4
-#define DPU_DRM_DESTSCALER_PU_ENABLE0x8
-
-/**
- * struct dpu_drm_dest_scaler_cfg - destination scaler config structure
- * @flags:  Flag to switch between mode for destination scaler
- *  refer to destination scaler flag config
- * @index:  Destination scaler selection index
- * @lm_width:   Layer mixer width configuration
- * @lm_height:  Layer mixer height configuration
- * @scaler_cfg: The scaling parameters for all the mode exce

[Freedreno] [DPU PATCH v2 5/7] drm/msm/dpu: clean up dpu crtc custom properties

[Jeykumar Sankaran]

Remove dpu crtc custom properties and its handlers.

changes in v2:
- none

Signed-off-by: Jeykumar Sankaran 
Reviewed-by: Sean Paul 
---
 drivers/gpu/drm/msm/Makefile  |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |  28 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 856 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |  27 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   |  12 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c | 149 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h | 111 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c |  67 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h |  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h   |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c|  71 +--
 drivers/gpu/drm/msm/msm_drv.h |  15 -
 12 files changed, 11 insertions(+), 1356 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 7bc3921..d289503 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -57,7 +57,6 @@ msm-y := \
disp/dpu1/dpu_hw_catalog.o \
disp/dpu1/dpu_hw_cdm.o \
disp/dpu1/dpu_hw_ctl.o \
-   disp/dpu1/dpu_hw_ds.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
disp/dpu1/dpu_hw_lm.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 981f77f..c4820de 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -102,34 +102,6 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
dpu_cstate = to_dpu_crtc_state(state);
memset(perf, 0, sizeof(struct dpu_core_perf_params));
 
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-
-   if (dpu_cstate->bw_split_vote) {
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_LLCC_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_LLCC_IB);
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_DRAM_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_DRAM_IB);
-   } else {
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-   }
-
-   perf->core_clk_rate =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_CLK);
-
if (!dpu_cstate->bw_control) {
for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 48361fb..0c25c45 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -570,18 +570,6 @@ static void _dpu_crtc_deinit_events(struct dpu_crtc 
*dpu_crtc)
return;
 }
 
-/**
- * dpu_crtc_destroy_dest_scaler - free memory allocated for scaler lut
- * @dpu_crtc: Pointer to dpu crtc
- */
-static void _dpu_crtc_destroy_dest_scaler(struct dpu_crtc *dpu_crtc)
-{
-   if (!dpu_crtc)
-   return;
-
-   kfree(dpu_crtc->scl3_lut_cfg);
-}
-
 static void dpu_crtc_destroy(struct drm_crtc *crtc)
 {
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
@@ -594,7 +582,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
if (dpu_crtc->blob_info)
drm_property_blob_put(dpu_crtc->blob_info);
msm_property_destroy(_crtc->property_info);
-   _dpu_crtc_destroy_dest_scaler(dpu_crtc);
 
_dpu_crtc_deinit_events(dpu_crtc);
 
@@ -630,71 +617,6 @@ static void _dpu_crtc_setup_blend_cfg(struct 
dpu_crtc_mixer *mixer,
DPU_BLEND_BG_ALPHA_BG_CONST);
 }
 
-static void _dpu_crtc_setup_dim_layer_cfg(struct dr

[Freedreno] [DPU PATCH v2 6/7] drm/msm: remove msm_prop files

[Jeykumar Sankaran]

Remove hand rolled msm property caching to handle DPU
custom properties. This change also cleans up all its
dependencies to cache and restore respective drm
states.

changs in v2:
- none

Signed-off-by: Jeykumar Sankaran 
Reviewed-by: Sean Paul 
---
 drivers/gpu/drm/msm/Makefile  |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 239 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 123 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |  12 -
 drivers/gpu/drm/msm/msm_drv.h |  16 +-
 drivers/gpu/drm/msm/msm_prop.c| 688 --
 drivers/gpu/drm/msm/msm_prop.h| 438 
 10 files changed, 8 insertions(+), 1529 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/msm_prop.c
 delete mode 100644 drivers/gpu/drm/msm/msm_prop.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index d289503..5331188 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -76,7 +76,6 @@ msm-y := \
dpu_io_util.o \
dpu_dbg_evtlog.o \
dpu_power_handle.o \
-   msm_prop.o \
msm_atomic.o \
msm_debugfs.o \
msm_drv.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index c4820de..e4b82d5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -19,8 +19,6 @@
 #include 
 #include 
 
-#include "msm_prop.h"
-
 #include "dpu_kms.h"
 #include "dpu_trace.h"
 #include "dpu_crtc.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 0c25c45..dd8c91e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -579,10 +579,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
if (!crtc)
return;
 
-   if (dpu_crtc->blob_info)
-   drm_property_blob_put(dpu_crtc->blob_info);
-   msm_property_destroy(_crtc->property_info);
-
_dpu_crtc_deinit_events(dpu_crtc);
 
drm_crtc_cleanup(crtc);
@@ -1341,9 +1337,7 @@ static void dpu_crtc_destroy_state(struct drm_crtc *crtc,
 
__drm_atomic_helper_crtc_destroy_state(state);
 
-   /* destroy value helper */
-   msm_property_destroy_state(_crtc->property_info, cstate,
-   >property_state);
+   kfree(cstate);
 }
 
 static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)
@@ -1592,17 +1586,12 @@ static struct drm_crtc_state 
*dpu_crtc_duplicate_state(struct drm_crtc *crtc)
 
dpu_crtc = to_dpu_crtc(crtc);
old_cstate = to_dpu_crtc_state(crtc->state);
-   cstate = msm_property_alloc_state(_crtc->property_info);
+   cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL);
if (!cstate) {
DPU_ERROR("failed to allocate state\n");
return NULL;
}
 
-   /* duplicate value helper */
-   msm_property_duplicate_state(_crtc->property_info,
-   old_cstate, cstate,
-   >property_state, cstate->property_values);
-
/* duplicate base helper */
__drm_atomic_helper_crtc_duplicate_state(crtc, >base);
 
@@ -1638,17 +1627,12 @@ static void dpu_crtc_reset(struct drm_crtc *crtc)
}
 
dpu_crtc = to_dpu_crtc(crtc);
-   cstate = msm_property_alloc_state(_crtc->property_info);
+   cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
if (!cstate) {
DPU_ERROR("failed to allocate state\n");
return;
}
 
-   /* reset value helper */
-   msm_property_reset_state(_crtc->property_info, cstate,
-   >property_state,
-   cstate->property_values);
-
_dpu_crtc_rp_reset(>rp, _crtc->rp_lock,
_crtc->rp_head);
 
@@ -2145,212 +2129,6 @@ void dpu_crtc_cancel_pending_flip(struct drm_crtc 
*crtc, struct drm_file *file)
_dpu_crtc_complete_flip(crtc, file);
 }
 
-/**
- * dpu_crtc_install_properties - install all drm properties for crtc
- * @crtc: Pointer to drm crtc structure
- */
-static void dpu_crtc_install_properties(struct drm_crtc *crtc,
-   struct dpu_mdss_cfg *catalog)
-{
-   struct dpu_crtc *dpu_crtc;
-   struct drm_device *dev;
-   struct dpu_kms_info *info;
-   struct dpu_kms *dpu_kms;
-
-   DPU_DEBUG("\n");
-
-   if (!crtc || !catalog) {
-   DPU_ERROR("invalid crtc or catalog\n");
-   return;
-   }
-
-   dpu_crtc = to_dpu_crtc(crtc);
-

[Freedreno] [DPU PATCH v2 1/7] drm/msm: remove connector custom properties

[Jeykumar Sankaran]

Cleanup residual connector property enumerations.

changs in v2:
- none

Signed-off-by: Jeykumar Sankaran 
Reviewed-by: Sean Paul 
---
 drivers/gpu/drm/msm/msm_drv.h | 27 ---
 1 file changed, 27 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 90a2521..954ac12 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -140,32 +140,6 @@ enum msm_mdp_crtc_property {
CRTC_PROP_COUNT
 };
 
-enum msm_mdp_conn_property {
-   /* blob properties, always put these first */
-   CONNECTOR_PROP_DPU_INFO,
-   CONNECTOR_PROP_HDR_INFO,
-   CONNECTOR_PROP_PP_DITHER,
-
-   /* # of blob properties */
-   CONNECTOR_PROP_BLOBCOUNT,
-
-   /* range properties */
-   CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT,
-   CONNECTOR_PROP_DST_X,
-   CONNECTOR_PROP_DST_Y,
-   CONNECTOR_PROP_DST_W,
-   CONNECTOR_PROP_DST_H,
-   CONNECTOR_PROP_BL_SCALE,
-   CONNECTOR_PROP_AD_BL_SCALE,
-
-   /* enum/bitmask properties */
-   CONNECTOR_PROP_AUTOREFRESH,
-   CONNECTOR_PROP_LP,
-
-   /* total # of properties */
-   CONNECTOR_PROP_COUNT
-};
-
 struct msm_vblank_ctrl {
struct kthread_work work;
struct list_head event_list;
@@ -434,7 +408,6 @@ struct msm_drm_private {
/* Properties */
struct drm_property *plane_property[PLANE_PROP_COUNT];
struct drm_property *crtc_property[CRTC_PROP_COUNT];
-   struct drm_property *conn_property[CONNECTOR_PROP_COUNT];
 
/* Color processing properties for the crtc */
struct drm_property **cp_property;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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Re: [Freedreno] [DPU PATCH 2/7] drm/msm/dpu: clean up dpu plane custom properties

[Jeykumar Sankaran]

On 2018-06-04 12:53, Sean Paul wrote:

On Wed, May 23, 2018 at 12:30:57PM -0700, Jeykumar Sankaran wrote:

This change removes all the dpu plane custom properties
and its handlers.

Signed-off-by: Jeykumar Sankaran 
---
 Makefile   |2 +-
 drivers/gpu/drm/msm/Makefile   |8 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h|   99 --
 .../gpu/drm/msm/disp/dpu1/dpu_color_processing.c   | 1521



 .../gpu/drm/msm/disp/dpu1/dpu_color_processing.h   |  120 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  148 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |3 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|2 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c|1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c | 1443

---

 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   72 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   89 --
 .../msm/disp/dpu1/dpu_hw_color_proc_common_v4.h|   69 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c   |  242 
 .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h   |   40 -
 .../drm/msm/disp/dpu1/dpu_hw_color_processing.h|   20 -
 .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.c   |  565 
 .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.h   |   92 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c |   44 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |   15 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c|  209 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h|  220 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c  |1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|   44 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|   68 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c  |  757 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h  |   27 -
 .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c   |  943 


 .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h   |   75 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c|  219 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h|   73 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c|1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h|  156 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|3 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  | 1267

+---

 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h  |   31 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c|  139 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h|  310 
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  102 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c |2 -
 drivers/gpu/drm/msm/msm_drv.h  |   28 -
 include/uapi/drm/dpu_drm.h |  187 ---
 include/uapi/drm/msm_drm.h |1 -
 45 files changed, 277 insertions(+), 9189 deletions(-)


Doing all of this at once is really hard to review. I would have 
preferred

to
review each feature removal in a separate patch. However, since this is
just
going to be squashed into the DPU megapatch anyways, I guess it's fine.


Sure. I thought I was helping by squashing them beforehand.
Will take care by spliting them for review on future patches.

I only paid close attention to the additions, there are some unrelated
whitespace changes, but also meh on account of the squash (and non seem
objectionable).


 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h
 delete mode 100644 
drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
 delete mode 100644 
drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.h

 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c
 delete mode 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_common_v4.h
 delete mode 100644 
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c
 delete mode 100644 
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h

 delete mode 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing.h

 delete mode 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.c

 delete mode 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.h

 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h
 delete mode 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c

 delete mode 100644

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h

 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h

diff --git a/Makefile b/Makefile

[Freedreno] [DPU PATCH v4 0/6] Switch DPU to use upstream DSI driver for SDM845

[Jeykumar Sankaran]

SDM845 DPU driver was talking to dsi-staging driver for its dsi 
operations through the customized dpu_connector layer. The following 
series of patches removes DPU dependency from various dpu
connector API's before purging the dpu_connector altogether. It
also completes the switch to upstream DSI driver by removing
the dsi-staging driver and it's dependent sources.

The patch series is based on:
[1]https://www.spinics.net/lists/dri-devel/msg172315.html
[2]https://www.spinics.net/lists/dri-devel/msg172395.html

changes in v2:
- addressed comments on indentation (Sean Paul)
- removed compiled out non-dsi display init (Sean Paul)
- removed file changes not applicable upstream (Sean Paul)
- Split unrelated changes into seperate patch sets (Sean Paul)
changes in v3:
- fix warnings
- compile out dsi-staging with upstream dsi hook up
changes in v4:
- remove top_ctrl in rm release

Jeykumar Sankaran (6):
  drm/msm: remove display stream compression(DSC) support for SM845
  drm/msm: remove support for ping pong split topology
  drm/msm: remove panel autorefresh support for SDM845
  drm/msm: strip down custom event ioctl's
  drm/msm: hook up DPU with upstream DSI
  drm/msm: remove dsi-staging driver

 drivers/gpu/drm/msm/Kconfig|   12 -
 drivers/gpu/drm/msm/Makefile   |   23 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  | 1196 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h  |  555 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  246 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  867 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   24 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   38 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |  409 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |   32 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   30 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   18 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c |  252 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h |  100 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|   17 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|   89 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|   40 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |   46 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |   18 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h   |4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  519 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  157 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   21 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c |2 -
 drivers/gpu/drm/msm/dpu_dbg.c  |3 -
 drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c  |  241 --
 drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h  |  201 -
 drivers/gpu/drm/msm/dsi-staging/dsi_clk.h  |  276 --
 drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c  | 1235 --
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c | 2846 -
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h |  623 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h  |  752 
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_1_4.c  |  480 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_0.c  |  234 --
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_2.c  |   42 -
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c  | 1312 --
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg.h |  196 -
 drivers/gpu/drm/msm/dsi-staging/dsi_defs.h |  579 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_display.c  | 4221 
 drivers/gpu/drm/msm/dsi-staging/dsi_display.h  |  556 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_display_test.c |  114 -
 drivers/gpu/drm/msm/dsi-staging/dsi_display_test.h |   31 -
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.c  |  688 
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.h  |  127 -
 drivers/gpu/drm/msm/dsi-staging/dsi_hw.h   |   48 -
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.c| 3321 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.h|  257 --
 drivers/gpu/drm/msm/dsi-staging/dsi_phy.c  |  937 -
 drivers/gpu/drm/msm/dsi-staging/dsi_phy.h  |  235 --
 drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h   |  260 --
 drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v2_0.c  |  252 --
 drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c  |  447 ---
 .../gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.c  |  676 
 .../gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.h  |  144 -
 .../gpu/drm/msm/dsi-staging/dsi_phy_timing_v2_0.c  |  126 -
 .../gpu/drm/msm/dsi-staging/dsi_phy_timing_v3_0.c  |  107 -
 drivers/gpu/drm/msm/dsi-staging/dsi_pwr.c  |  365 --
 drivers/gpu/drm/msm/dsi-staging/dsi_pwr.h

[Freedreno] [DPU PATCH v4 5/6] drm/msm: hook up DPU with upstream DSI

[Jeykumar Sankaran]

Switch DPU from dsi-staging to upstream dsi driver. To make
the switch atomic, this change includes:
- remove dpu connector layers
- clean up dpu connector dependencies in encoder/crtc
- compile out writeback and display port drivers
- compile out dsi-staging driver (separate patch submitted to
  remove the driver)
- adapt upstream device hierarchy

changes in v2:
- remove files not applicable upstream (Sean Paul)
- remove compiled out non-dsi display init (Sean Paul)
- split unrelated changes into separate patch set (Sean Paul)
changes in v3:
- fix compilation warning
- compile out dsi staging
changes in v4:
- remove top_ctrl check in rm release

Signed-off-by: Jeykumar Sankaran 
Signed-off-by: Sean Paul 
Signed-off-by: Rajesh Yadav 
---
 drivers/gpu/drm/msm/Makefile   |   22 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  | 1185 
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h  |  555 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |9 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  179 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   10 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |8 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |6 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  488 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |   65 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   11 +
 drivers/gpu/drm/msm/dpu_dbg.c  |3 -
 drivers/gpu/drm/msm/msm_drv.c  |   47 +-
 drivers/gpu/drm/msm/msm_drv.h  |   39 -
 15 files changed, 159 insertions(+), 2474 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index d947f2a..d7558ed 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -1,7 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 ccflags-y := -Idrivers/gpu/drm/msm
 ccflags-y += -Idrivers/gpu/drm/msm/disp/dpu1
-ccflags-y += -Idrivers/gpu/drm/msm/dsi-staging
 ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
 
 msm-y := \
@@ -48,7 +47,6 @@ msm-y := \
disp/mdp5/mdp5_plane.o \
disp/mdp5/mdp5_smp.o \
disp/dpu1/dpu_color_processing.o \
-   disp/dpu1/dpu_connector.o \
disp/dpu1/dpu_core_irq.o \
disp/dpu1/dpu_core_perf.o \
disp/dpu1/dpu_crtc.o \
@@ -141,26 +139,6 @@ msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
dsi/phy/dsi_phy.o \
disp/mdp5/mdp5_cmd_encoder.o
 
-msm-$(CONFIG_DRM_MSM_DSI_STAGING) += dsi-staging/dsi_phy.o \
-   dsi-staging/dsi_pwr.o \
-   dsi-staging/dsi_phy.o \
-   dsi-staging/dsi_phy_hw_v2_0.o \
-   dsi-staging/dsi_phy_hw_v3_0.o \
-   dsi-staging/dsi_phy_timing_calc.o \
-   dsi-staging/dsi_phy_timing_v2_0.o \
-   dsi-staging/dsi_phy_timing_v3_0.o \
-   dsi-staging/dsi_ctrl_hw_cmn.o \
-   dsi-staging/dsi_ctrl_hw_1_4.o \
-   dsi-staging/dsi_ctrl_hw_2_0.o \
-   dsi-staging/dsi_ctrl_hw_2_2.o \
-   dsi-staging/dsi_ctrl.o \
-   dsi-staging/dsi_catalog.o \
-   dsi-staging/dsi_drm.o \
-   dsi-staging/dsi_display.o \
-   dsi-staging/dsi_panel.o \
-   dsi-staging/dsi_clk_manager.o \
-   dsi-staging/dsi_display_test.o
-
 msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
 msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
 msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
deleted file mode 100644
index 969919f..000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ /dev/null
@@ -1,1185 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define pr_fmt(fmt

[Freedreno] [DPU PATCH v4 2/6] drm/msm: remove support for ping pong split topology

[Jeykumar Sankaran]

ping pong split topology was meant for low end soc's which
doesn't have enough layer mixers to support split panels.
Considering how uncommon the topology is for current chipset's and
also to simply the driver programming, striping off the support
for SDM845.

changes in v2:
- none
changes in v3:
- none
changes in v4:
- none

Reviewed-by: Sean Paul 
Signed-off-by: Jeykumar Sankaran 
Signed-off-by: Sean Paul 
Signed-off-by: Rajesh Yadav 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  19 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 179 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   5 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 110 +
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  21 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |  33 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |  11 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h   |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  37 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   2 -
 13 files changed, 15 insertions(+), 415 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index 5f3efe5..a89392e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -38,8 +38,8 @@
{DPU_RM_TOPOLOGY_SINGLEPIPE,"dpu_singlepipe"},
{DPU_RM_TOPOLOGY_DUALPIPE,  "dpu_dualpipe"},
{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,  "dpu_dualpipemerge"},
-   {DPU_RM_TOPOLOGY_PPSPLIT,   "dpu_ppsplit"},
 };
+
 static const struct drm_prop_enum_list e_topology_control[] = {
{DPU_RM_TOPCTL_RESERVE_LOCK,"reserve_lock"},
{DPU_RM_TOPCTL_RESERVE_CLEAR,   "reserve_clear"},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 24d1582..d571af2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1914,23 +1914,6 @@ static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
mutex_unlock(_crtc->crtc_lock);
 }
 
-static void _dpu_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
-{
-   int i;
-   struct dpu_crtc_state *cstate;
-
-   cstate = to_dpu_crtc_state(state);
-
-   cstate->is_ppsplit = false;
-   for (i = 0; i < cstate->num_connectors; i++) {
-   struct drm_connector *conn = cstate->connectors[i];
-
-   if (dpu_connector_get_topology_name(conn) ==
-   DPU_RM_TOPOLOGY_PPSPLIT)
-   cstate->is_ppsplit = true;
-   }
-}
-
 static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
struct drm_crtc_state *state)
 {
@@ -1993,7 +1976,6 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 
if (!dpu_crtc->num_mixers) {
_dpu_crtc_setup_mixers(crtc);
-   _dpu_crtc_setup_is_ppsplit(crtc->state);
_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
}
 
@@ -2899,7 +2881,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
 
-   _dpu_crtc_setup_is_ppsplit(state);
_dpu_crtc_setup_lm_bounds(crtc, state);
 
 /* get plane state for all drm planes associated with crtc state */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 151889b..d04095b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -545,7 +545,6 @@ void dpu_encoder_helper_split_config(
struct dpu_encoder_virt *dpu_enc;
struct split_pipe_cfg cfg = { 0 };
struct dpu_hw_mdp *hw_mdptop;
-   enum dpu_rm_topology_name topology;
struct msm_display_info *disp_info;
 
if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
@@ -569,8 +568,6 @@ void dpu_encoder_helper_split_config(
if (phys_enc->split_role == ENC_ROLE_SOLO) {
if (hw_mdptop->ops.setup_split_pipe)
hw_mdptop->ops.setup_split_pipe(hw_mdptop, );
-   if (hw_mdptop->ops.setup_pp_split)
-   hw_mdptop->ops.setup_pp_split(hw_mdptop, );
return;
}
 
@@ -582,29 +579,11 @@ void dpu_encoder_helper_split_config(
phys_enc->ops.needs_single_flush(phys_enc))
cfg.split_flush_en = true;
 
-   topology = dpu_connector_get_topology_name(phys_enc->connector);
-   if (topology == DPU_R

[Freedreno] [DPU PATCH v4 4/6] drm/msm: strip down custom event ioctl's

[Jeykumar Sankaran]

Remove custom ioctl support in SDM845 which allows
user space to register/unregister for hw events.

changes in v2:
- none
changes in v3:
- none
changes in v4:
- none

Reviewed-by: Sean Paul 
Signed-off-by: Jeykumar Sankaran 
Signed-off-by: Sean Paul 
Signed-off-by: Rajesh Yadav 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 218 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |  31 -
 drivers/gpu/drm/msm/msm_drv.c| 201 
 drivers/gpu/drm/msm/msm_kms.h|   2 -
 5 files changed, 1 insertion(+), 452 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d571af2..c0e8035 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -39,31 +39,6 @@
 #include "dpu_core_perf.h"
 #include "dpu_trace.h"
 
-struct dpu_crtc_irq_info {
-   struct dpu_irq_callback irq;
-   u32 event;
-   int (*func)(struct drm_crtc *crtc, bool en,
-   struct dpu_irq_callback *irq);
-   struct list_head list;
-};
-
-struct dpu_crtc_custom_events {
-   u32 event;
-   int (*func)(struct drm_crtc *crtc, bool en,
-   struct dpu_irq_callback *irq);
-};
-
-static int dpu_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
-   bool en, struct dpu_irq_callback *ad_irq);
-static int dpu_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
-   bool en, struct dpu_irq_callback *idle_irq);
-
-static struct dpu_crtc_custom_events custom_events[] = {
-   {DRM_EVENT_AD_BACKLIGHT, dpu_cp_ad_interrupt},
-   {DRM_EVENT_CRTC_POWER, dpu_crtc_power_interrupt_handler},
-   {DRM_EVENT_IDLE_NOTIFY, dpu_crtc_idle_interrupt_handler}
-};
-
 /* layer mixer index on dpu_crtc */
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1
@@ -2455,9 +2430,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
struct drm_encoder *encoder;
struct dpu_crtc_mixer *m;
u32 i, misr_status;
-   unsigned long flags;
-   struct dpu_crtc_irq_info *node = NULL;
-   int ret = 0;
 
if (!crtc) {
DPU_ERROR("invalid crtc\n");
@@ -2479,17 +2451,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
dpu_encoder_virt_restore(encoder);
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, true, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to enable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrestore(_crtc->spin_lock, flags);
-
dpu_cp_crtc_post_ipc(crtc);
 
for (i = 0; i < dpu_crtc->num_mixers; ++i) {
@@ -2514,18 +2475,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
dpu_crtc->misr_data[i];
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   node = NULL;
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, false, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to disable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrestore(_crtc->spin_lock, flags);
-
dpu_cp_crtc_pre_ipc(crtc);
break;
case DPU_POWER_EVENT_POST_DISABLE:
@@ -2553,8 +2502,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
struct drm_display_mode *mode;
struct drm_encoder *encoder;
struct msm_drm_private *priv;
-   unsigned long flags;
-   struct dpu_crtc_irq_info *node = NULL;
struct drm_event event;
u32 power_on;
int ret;
@@ -2614,17 +2561,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
atomic_set(_crtc->frame_pending, 0);
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, false, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to disable event %x\n",
-   dpu_crtc-&g

[Freedreno] [DPU PATCH v4 3/6] drm/msm: remove panel autorefresh support for SDM845

[Jeykumar Sankaran]

Remove autorefresh support for smart panels in SDM845 for now.
It needs more discussion to figure out the user space
communication to set preference for the feature.

changes in v2:
- none
changes in v3:
- none
changes in v4:
- none

Reviewed-by: Sean Paul 
Signed-off-by: Jeykumar Sankaran 
Signed-off-by: Sean Paul 
Signed-off-by: Rajesh Yadav 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  37 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  20 --
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 298 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|  41 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|  18 --
 6 files changed, 11 insertions(+), 410 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index a89392e..969919f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -24,9 +24,6 @@
 
 #define BL_NODE_NAME_SIZE 32
 
-/* Autorefresh will occur after FRAME_CNT frames. Large values are unlikely */
-#define AUTOREFRESH_MAX_FRAME_CNT 6
-
 #define DPU_DEBUG_CONN(c, fmt, ...) DPU_DEBUG("conn%d " fmt,\
(c) ? (c)->base.base.id : -1, ##__VA_ARGS__)
 
@@ -1127,10 +1124,6 @@ struct drm_connector *dpu_connector_init(struct 
drm_device *dev,
CONNECTOR_PROP_AD_BL_SCALE);
 #endif
 
-   msm_property_install_range(_conn->property_info, "autorefresh",
-   0x0, 0, AUTOREFRESH_MAX_FRAME_CNT, 0,
-   CONNECTOR_PROP_AUTOREFRESH);
-
/* enum/bitmask properties */
msm_property_install_enum(_conn->property_info, "topology_name",
DRM_MODE_PROP_IMMUTABLE, 0, e_topology_name,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d04095b..3854410 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -813,7 +813,6 @@ static void _dpu_encoder_resource_control_helper(struct 
drm_encoder *drm_enc,
 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
u32 sw_event)
 {
-   bool autorefresh_enabled = false;
unsigned int lp, idle_timeout;
struct dpu_encoder_virt *dpu_enc;
struct msm_drm_private *priv;
@@ -920,13 +919,6 @@ static int dpu_encoder_resource_control(struct drm_encoder 
*drm_enc,
return 0;
}
 
-   /* schedule delayed off work if autorefresh is disabled */
-   if (dpu_enc->cur_master &&
-   dpu_enc->cur_master->ops.is_autorefresh_enabled)
-   autorefresh_enabled =
-   dpu_enc->cur_master->ops.is_autorefresh_enabled(
-   dpu_enc->cur_master);
-
/* set idle timeout based on master connector's lp value */
if (dpu_enc->cur_master)
lp = dpu_connector_get_lp(
@@ -939,13 +931,12 @@ static int dpu_encoder_resource_control(struct 
drm_encoder *drm_enc,
else
idle_timeout = dpu_enc->idle_timeout;
 
-   if (!autorefresh_enabled)
-   kthread_queue_delayed_work(
-   _thread->worker,
-   _enc->delayed_off_work,
-   msecs_to_jiffies(idle_timeout));
+   kthread_queue_delayed_work(
+   _thread->worker,
+   _enc->delayed_off_work,
+   msecs_to_jiffies(idle_timeout));
+
DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
-   autorefresh_enabled,
idle_timeout, DPU_EVTLOG_FUNC_CASE2);
DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work scheduled\n",
sw_event);
@@ -1988,7 +1979,6 @@ static void dpu_encoder_vsync_event_handler(struct 
timer_list *t)
struct drm_encoder *drm_enc = _enc->base;
struct msm_drm_private *priv;
struct msm_drm_thread *event_thread;
-   bool autorefresh_enabled = false;
 
if (!drm_enc->dev || !drm_enc->dev->dev_private ||
!drm_enc->crtc) {
@@ -2009,22 +1999,7 @@ static void dpu_encoder_vsync_event_handler(struct 
timer_list *t)
return;
}
 
-   if (dpu_enc->cur_master &&
-   dpu_enc->cur_master->ops.is_autorefresh_enabled)
-   autorefresh_enabled =
-   dpu_enc->cur_master->ops.is_autorefresh_enabled(
-  

[Freedreno] [DPU PATCH v4 1/6] drm/msm: remove display stream compression(DSC) support for SM845

[Jeykumar Sankaran]

Upstream DSI driver doesn't support DSC panels yet. Remove
the support for compression from DPU for now.

changes in v2:
- indents and unrelated change clean up (Sean Paul)
- fix compilation dependency in dsi-staging
changes in v3:
-none
changes in v4:
-none

Signed-off-by: Jeykumar Sankaran 
Signed-off-by: Sean Paul 
Signed-off-by: Rajesh Yadav 
---
 drivers/gpu/drm/msm/Makefile   |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 476 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   7 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |   1 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |   7 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  25 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 252 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 100 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|  17 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|  48 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|  22 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |  13 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  55 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   8 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c |   2 -
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.c  |   7 -
 drivers/gpu/drm/msm/msm_drv.h  |  16 -
 21 files changed, 5 insertions(+), 1093 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index a458b36..d947f2a 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -64,7 +64,6 @@ msm-y := \
disp/dpu1/dpu_hw_color_processing_v1_7.o \
disp/dpu1/dpu_hw_ctl.o \
disp/dpu1/dpu_hw_ds.o \
-   disp/dpu1/dpu_hw_dsc.o \
disp/dpu1/dpu_hw_dspp.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index a57495f..5f3efe5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -36,12 +36,8 @@
 static const struct drm_prop_enum_list e_topology_name[] = {
{DPU_RM_TOPOLOGY_NONE,  "dpu_none"},
{DPU_RM_TOPOLOGY_SINGLEPIPE,"dpu_singlepipe"},
-   {DPU_RM_TOPOLOGY_SINGLEPIPE_DSC,"dpu_singlepipe_dsc"},
{DPU_RM_TOPOLOGY_DUALPIPE,  "dpu_dualpipe"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_DSC,  "dpu_dualpipe_dsc"},
{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,  "dpu_dualpipemerge"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC,  "dpu_dualpipemerge_dsc"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE, "dpu_dualpipe_dscmerge"},
{DPU_RM_TOPOLOGY_PPSPLIT,   "dpu_ppsplit"},
 };
 static const struct drm_prop_enum_list e_topology_control[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 198c618..151889b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -32,7 +32,6 @@
 #include "dpu_formats.h"
 #include "dpu_encoder_phys.h"
 #include "dpu_power_handle.h"
-#include "dpu_hw_dsc.h"
 #include "dpu_crtc.h"
 #include "dpu_trace.h"
 #include "dpu_core_irq.h"
@@ -152,7 +151,6 @@ enum dpu_enc_rc_states {
  * Only valid after enable. Cleared as disable.
  * @hw_pp  Handle to the pingpong blocks used for the display. No.
  * pingpong blocks can be different than num_phys_encs.
- * @hw_dsc:Array of DSC block handles used for the display.
  * @intfs_swapped  Whether or not the phys_enc interfaces have been swapped
  * for partial update right-only cases, such as pingpong
  * split where virtual pingpong does not generate IRQs
@@ -199,7 +197,6 @@ struct dpu_encoder_virt {
struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
struct dpu_encoder_phys *cur_master;
struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
-   struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
 
bool intfs_swapped;
 
@@ -234,21 +231,6 @@ struct dpu_encoder_virt {
 
 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
 
-bool dpu_encoder_is_dsc_enabled(struct drm_encoder *drm_enc)
-
-{
-

Re: [Freedreno] [DPU PATCH v3 5/6] drm/msm: hook up DPU with upstream DSI

[Jeykumar Sankaran]

On 2018-06-01 09:21, Sean Paul wrote:

On Fri, May 25, 2018 at 02:26:06PM -0700, Jeykumar Sankaran wrote:

Switch DPU from dsi-staging to upstream dsi driver. To make
the switch atomic, this change includes:
- remove dpu connector layers
- clean up dpu connector dependencies in encoder/crtc
- compile out writeback and display port drivers
- compile out dsi-staging driver (separate patch submitted to
  remove the driver)
- adapt upstream device hierarchy

changes in v2:
- remove files not applicable upstream (Sean Paul)
- remove compiled out non-dsi display init (Sean Paul)
- split unrelated changes into separate patch set (Sean Paul)
changes in v3:
- fix compilation warning
- compile out dsi staging

Signed-off-by: Jeykumar Sankaran 
Signed-off-by: Sean Paul 
Signed-off-by: Rajesh Yadav 
---


/snip


@@ -1089,7 +1095,7 @@ void dpu_rm_release(struct dpu_rm *rm, struct

drm_encoder *enc)

 {
struct dpu_rm_rsvp *rsvp;
struct drm_connector *conn;
-   uint64_t top_ctrl;
+   uint64_t top_ctrl = 0;


This will always just force the else path. Just remove it all.

Sean

/snip
Sure. Taking care of it in the next patch set. FYI, most of the RSVP 
handling and custom top_ctrl are stripped down in the next series of 
clean up's.

--
Jeykumar S
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno

[Freedreno] [DPU PATCH v3 2/6] drm/msm: remove support for ping pong split topology

[Jeykumar Sankaran]

ping pong split topology was meant for low end soc's which
doesn't have enough layer mixers to support split panels.
Considering how uncommon the topology is for current chipset's and
also to simply the driver programming, striping off the support
for SDM845.

changes in v2:
- none
changes in v3:
- none

Reviewed-by: Sean Paul <seanp...@chromium.org>
Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  19 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 179 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   5 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 110 +
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  21 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |  33 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |  11 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h   |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  37 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   2 -
 13 files changed, 15 insertions(+), 415 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index 5f3efe5..a89392e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -38,8 +38,8 @@
{DPU_RM_TOPOLOGY_SINGLEPIPE,"dpu_singlepipe"},
{DPU_RM_TOPOLOGY_DUALPIPE,  "dpu_dualpipe"},
{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,  "dpu_dualpipemerge"},
-   {DPU_RM_TOPOLOGY_PPSPLIT,   "dpu_ppsplit"},
 };
+
 static const struct drm_prop_enum_list e_topology_control[] = {
{DPU_RM_TOPCTL_RESERVE_LOCK,"reserve_lock"},
{DPU_RM_TOPCTL_RESERVE_CLEAR,   "reserve_clear"},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 24d1582..d571af2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1914,23 +1914,6 @@ static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
mutex_unlock(_crtc->crtc_lock);
 }
 
-static void _dpu_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
-{
-   int i;
-   struct dpu_crtc_state *cstate;
-
-   cstate = to_dpu_crtc_state(state);
-
-   cstate->is_ppsplit = false;
-   for (i = 0; i < cstate->num_connectors; i++) {
-   struct drm_connector *conn = cstate->connectors[i];
-
-   if (dpu_connector_get_topology_name(conn) ==
-   DPU_RM_TOPOLOGY_PPSPLIT)
-   cstate->is_ppsplit = true;
-   }
-}
-
 static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
struct drm_crtc_state *state)
 {
@@ -1993,7 +1976,6 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 
if (!dpu_crtc->num_mixers) {
_dpu_crtc_setup_mixers(crtc);
-   _dpu_crtc_setup_is_ppsplit(crtc->state);
_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
}
 
@@ -2899,7 +2881,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
 
-   _dpu_crtc_setup_is_ppsplit(state);
_dpu_crtc_setup_lm_bounds(crtc, state);
 
 /* get plane state for all drm planes associated with crtc state */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 151889b..d04095b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -545,7 +545,6 @@ void dpu_encoder_helper_split_config(
struct dpu_encoder_virt *dpu_enc;
struct split_pipe_cfg cfg = { 0 };
struct dpu_hw_mdp *hw_mdptop;
-   enum dpu_rm_topology_name topology;
struct msm_display_info *disp_info;
 
if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
@@ -569,8 +568,6 @@ void dpu_encoder_helper_split_config(
if (phys_enc->split_role == ENC_ROLE_SOLO) {
if (hw_mdptop->ops.setup_split_pipe)
hw_mdptop->ops.setup_split_pipe(hw_mdptop, );
-   if (hw_mdptop->ops.setup_pp_split)
-   hw_mdptop->ops.setup_pp_split(hw_mdptop, );
return;
}
 
@@ -582,29 +579,11 @@ void dpu_encoder_helper_split_config(
phys_enc->ops.needs_single_flush(phys_enc))
cfg.split_flush_en = true;
 
-   topology = dp

[Freedreno] [DPU PATCH v3 3/6] drm/msm: remove panel autorefresh support for SDM845

[Jeykumar Sankaran]

Remove autorefresh support for smart panels in SDM845 for now.
It needs more discussion to figure out the user space
communication to set preference for the feature.

changes in v2:
- none
changes in v3:
- none

Reviewed-by: Sean Paul <seanp...@chromium.org>
Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  37 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  20 --
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 298 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|  41 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|  18 --
 6 files changed, 11 insertions(+), 410 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index a89392e..969919f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -24,9 +24,6 @@
 
 #define BL_NODE_NAME_SIZE 32
 
-/* Autorefresh will occur after FRAME_CNT frames. Large values are unlikely */
-#define AUTOREFRESH_MAX_FRAME_CNT 6
-
 #define DPU_DEBUG_CONN(c, fmt, ...) DPU_DEBUG("conn%d " fmt,\
(c) ? (c)->base.base.id : -1, ##__VA_ARGS__)
 
@@ -1127,10 +1124,6 @@ struct drm_connector *dpu_connector_init(struct 
drm_device *dev,
CONNECTOR_PROP_AD_BL_SCALE);
 #endif
 
-   msm_property_install_range(_conn->property_info, "autorefresh",
-   0x0, 0, AUTOREFRESH_MAX_FRAME_CNT, 0,
-   CONNECTOR_PROP_AUTOREFRESH);
-
/* enum/bitmask properties */
msm_property_install_enum(_conn->property_info, "topology_name",
DRM_MODE_PROP_IMMUTABLE, 0, e_topology_name,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d04095b..3854410 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -813,7 +813,6 @@ static void _dpu_encoder_resource_control_helper(struct 
drm_encoder *drm_enc,
 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
u32 sw_event)
 {
-   bool autorefresh_enabled = false;
unsigned int lp, idle_timeout;
struct dpu_encoder_virt *dpu_enc;
struct msm_drm_private *priv;
@@ -920,13 +919,6 @@ static int dpu_encoder_resource_control(struct drm_encoder 
*drm_enc,
return 0;
}
 
-   /* schedule delayed off work if autorefresh is disabled */
-   if (dpu_enc->cur_master &&
-   dpu_enc->cur_master->ops.is_autorefresh_enabled)
-   autorefresh_enabled =
-   dpu_enc->cur_master->ops.is_autorefresh_enabled(
-   dpu_enc->cur_master);
-
/* set idle timeout based on master connector's lp value */
if (dpu_enc->cur_master)
lp = dpu_connector_get_lp(
@@ -939,13 +931,12 @@ static int dpu_encoder_resource_control(struct 
drm_encoder *drm_enc,
else
idle_timeout = dpu_enc->idle_timeout;
 
-   if (!autorefresh_enabled)
-   kthread_queue_delayed_work(
-   _thread->worker,
-   _enc->delayed_off_work,
-   msecs_to_jiffies(idle_timeout));
+   kthread_queue_delayed_work(
+   _thread->worker,
+   _enc->delayed_off_work,
+   msecs_to_jiffies(idle_timeout));
+
DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
-   autorefresh_enabled,
idle_timeout, DPU_EVTLOG_FUNC_CASE2);
DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work scheduled\n",
sw_event);
@@ -1988,7 +1979,6 @@ static void dpu_encoder_vsync_event_handler(struct 
timer_list *t)
struct drm_encoder *drm_enc = _enc->base;
struct msm_drm_private *priv;
struct msm_drm_thread *event_thread;
-   bool autorefresh_enabled = false;
 
if (!drm_enc->dev || !drm_enc->dev->dev_private ||
!drm_enc->crtc) {
@@ -2009,22 +1999,7 @@ static void dpu_encoder_vsync_event_handler(struct 
timer_list *t)
return;
}
 
-   if (dpu_enc->cur_master &&
-   dpu_enc->cur_master->ops.is_autorefresh_enabled)
-   autorefresh_enabled =
-   dpu_enc->

[Freedreno] [DPU PATCH v3 5/6] drm/msm: hook up DPU with upstream DSI

[Jeykumar Sankaran]

Switch DPU from dsi-staging to upstream dsi driver. To make
the switch atomic, this change includes:
- remove dpu connector layers
- clean up dpu connector dependencies in encoder/crtc
- compile out writeback and display port drivers
- compile out dsi-staging driver (separate patch submitted to
  remove the driver)
- adapt upstream device hierarchy

changes in v2:
- remove files not applicable upstream (Sean Paul)
- remove compiled out non-dsi display init (Sean Paul)
- split unrelated changes into separate patch set (Sean Paul)
changes in v3:
- fix compilation warning
- compile out dsi staging

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
 drivers/gpu/drm/msm/Makefile   |   22 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  | 1185 
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h  |  555 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |9 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  179 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   10 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |8 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |6 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  488 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |   56 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   11 +
 drivers/gpu/drm/msm/dpu_dbg.c  |3 -
 drivers/gpu/drm/msm/msm_drv.c  |   47 +-
 drivers/gpu/drm/msm/msm_drv.h  |   39 -
 15 files changed, 159 insertions(+), 2465 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index d947f2a..d7558ed 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -1,7 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 ccflags-y := -Idrivers/gpu/drm/msm
 ccflags-y += -Idrivers/gpu/drm/msm/disp/dpu1
-ccflags-y += -Idrivers/gpu/drm/msm/dsi-staging
 ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
 
 msm-y := \
@@ -48,7 +47,6 @@ msm-y := \
disp/mdp5/mdp5_plane.o \
disp/mdp5/mdp5_smp.o \
disp/dpu1/dpu_color_processing.o \
-   disp/dpu1/dpu_connector.o \
disp/dpu1/dpu_core_irq.o \
disp/dpu1/dpu_core_perf.o \
disp/dpu1/dpu_crtc.o \
@@ -141,26 +139,6 @@ msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
dsi/phy/dsi_phy.o \
disp/mdp5/mdp5_cmd_encoder.o
 
-msm-$(CONFIG_DRM_MSM_DSI_STAGING) += dsi-staging/dsi_phy.o \
-   dsi-staging/dsi_pwr.o \
-   dsi-staging/dsi_phy.o \
-   dsi-staging/dsi_phy_hw_v2_0.o \
-   dsi-staging/dsi_phy_hw_v3_0.o \
-   dsi-staging/dsi_phy_timing_calc.o \
-   dsi-staging/dsi_phy_timing_v2_0.o \
-   dsi-staging/dsi_phy_timing_v3_0.o \
-   dsi-staging/dsi_ctrl_hw_cmn.o \
-   dsi-staging/dsi_ctrl_hw_1_4.o \
-   dsi-staging/dsi_ctrl_hw_2_0.o \
-   dsi-staging/dsi_ctrl_hw_2_2.o \
-   dsi-staging/dsi_ctrl.o \
-   dsi-staging/dsi_catalog.o \
-   dsi-staging/dsi_drm.o \
-   dsi-staging/dsi_display.o \
-   dsi-staging/dsi_panel.o \
-   dsi-staging/dsi_clk_manager.o \
-   dsi-staging/dsi_display_test.o
-
 msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
 msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
 msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
deleted file mode 100644
index 969919f..000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ /dev/null
@@ -1,1185 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-

[Freedreno] [DPU PATCH v3 1/6] drm/msm: remove display stream compression(DSC) support for SM845

[Jeykumar Sankaran]

Upstream DSI driver doesn't support DSC panels yet. Remove
the support for compression from DPU for now.

changes in v2:
- indents and unrelated change clean up (Sean Paul)
- fix compilation dependency in dsi-staging
changes in v3:
- none

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
 drivers/gpu/drm/msm/Makefile   |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 476 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   7 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |   1 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |   7 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  25 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 252 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 100 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|  17 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|  48 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|  22 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |  13 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  55 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   8 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c |   2 -
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.c  |   7 -
 drivers/gpu/drm/msm/msm_drv.h  |  16 -
 21 files changed, 5 insertions(+), 1093 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index a458b36..d947f2a 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -64,7 +64,6 @@ msm-y := \
disp/dpu1/dpu_hw_color_processing_v1_7.o \
disp/dpu1/dpu_hw_ctl.o \
disp/dpu1/dpu_hw_ds.o \
-   disp/dpu1/dpu_hw_dsc.o \
disp/dpu1/dpu_hw_dspp.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index a57495f..5f3efe5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -36,12 +36,8 @@
 static const struct drm_prop_enum_list e_topology_name[] = {
{DPU_RM_TOPOLOGY_NONE,  "dpu_none"},
{DPU_RM_TOPOLOGY_SINGLEPIPE,"dpu_singlepipe"},
-   {DPU_RM_TOPOLOGY_SINGLEPIPE_DSC,"dpu_singlepipe_dsc"},
{DPU_RM_TOPOLOGY_DUALPIPE,  "dpu_dualpipe"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_DSC,  "dpu_dualpipe_dsc"},
{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,  "dpu_dualpipemerge"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC,  "dpu_dualpipemerge_dsc"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE, "dpu_dualpipe_dscmerge"},
{DPU_RM_TOPOLOGY_PPSPLIT,   "dpu_ppsplit"},
 };
 static const struct drm_prop_enum_list e_topology_control[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 198c618..151889b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -32,7 +32,6 @@
 #include "dpu_formats.h"
 #include "dpu_encoder_phys.h"
 #include "dpu_power_handle.h"
-#include "dpu_hw_dsc.h"
 #include "dpu_crtc.h"
 #include "dpu_trace.h"
 #include "dpu_core_irq.h"
@@ -152,7 +151,6 @@ enum dpu_enc_rc_states {
  * Only valid after enable. Cleared as disable.
  * @hw_pp  Handle to the pingpong blocks used for the display. No.
  * pingpong blocks can be different than num_phys_encs.
- * @hw_dsc:Array of DSC block handles used for the display.
  * @intfs_swapped  Whether or not the phys_enc interfaces have been swapped
  * for partial update right-only cases, such as pingpong
  * split where virtual pingpong does not generate IRQs
@@ -199,7 +197,6 @@ struct dpu_encoder_virt {
struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
struct dpu_encoder_phys *cur_master;
struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
-   struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
 
bool intfs_swapped;
 
@@ -234,21 +231,6 @@ struct dpu_encoder_virt {
 
 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
 
-bool dpu_encoder_is_dsc_

[Freedreno] [DPU PATCH v3 4/6] drm/msm: strip down custom event ioctl's

[Jeykumar Sankaran]

Remove custom ioctl support in SDM845 which allows
user space to register/unregister for hw events.

changes in v2:
- none
changes in v3:
- none

Reviewed-by: Sean Paul <seanp...@chromium.org>
Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
Signed-off-by: Rajesh Yadav <rya...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 218 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |  31 -
 drivers/gpu/drm/msm/msm_drv.c| 201 
 drivers/gpu/drm/msm/msm_kms.h|   2 -
 5 files changed, 1 insertion(+), 452 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d571af2..c0e8035 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -39,31 +39,6 @@
 #include "dpu_core_perf.h"
 #include "dpu_trace.h"
 
-struct dpu_crtc_irq_info {
-   struct dpu_irq_callback irq;
-   u32 event;
-   int (*func)(struct drm_crtc *crtc, bool en,
-   struct dpu_irq_callback *irq);
-   struct list_head list;
-};
-
-struct dpu_crtc_custom_events {
-   u32 event;
-   int (*func)(struct drm_crtc *crtc, bool en,
-   struct dpu_irq_callback *irq);
-};
-
-static int dpu_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
-   bool en, struct dpu_irq_callback *ad_irq);
-static int dpu_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
-   bool en, struct dpu_irq_callback *idle_irq);
-
-static struct dpu_crtc_custom_events custom_events[] = {
-   {DRM_EVENT_AD_BACKLIGHT, dpu_cp_ad_interrupt},
-   {DRM_EVENT_CRTC_POWER, dpu_crtc_power_interrupt_handler},
-   {DRM_EVENT_IDLE_NOTIFY, dpu_crtc_idle_interrupt_handler}
-};
-
 /* layer mixer index on dpu_crtc */
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1
@@ -2455,9 +2430,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
struct drm_encoder *encoder;
struct dpu_crtc_mixer *m;
u32 i, misr_status;
-   unsigned long flags;
-   struct dpu_crtc_irq_info *node = NULL;
-   int ret = 0;
 
if (!crtc) {
DPU_ERROR("invalid crtc\n");
@@ -2479,17 +2451,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
dpu_encoder_virt_restore(encoder);
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, true, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to enable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrestore(_crtc->spin_lock, flags);
-
dpu_cp_crtc_post_ipc(crtc);
 
for (i = 0; i < dpu_crtc->num_mixers; ++i) {
@@ -2514,18 +2475,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
dpu_crtc->misr_data[i];
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   node = NULL;
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, false, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to disable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrestore(_crtc->spin_lock, flags);
-
dpu_cp_crtc_pre_ipc(crtc);
break;
case DPU_POWER_EVENT_POST_DISABLE:
@@ -2553,8 +2502,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
struct drm_display_mode *mode;
struct drm_encoder *encoder;
struct msm_drm_private *priv;
-   unsigned long flags;
-   struct dpu_crtc_irq_info *node = NULL;
struct drm_event event;
u32 power_on;
int ret;
@@ -2614,17 +2561,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
atomic_set(_crtc->frame_pending, 0);
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, false, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to d

Re: [Freedreno] [DPU PATCH v3] drm/msm: Use atomic private_obj instead of subclassing

[Jeykumar Sankaran]

On 2018-03-20 04:01, Archit Taneja wrote:

Hi,

On Tuesday 20 March 2018 01:28 AM, Sean Paul wrote:

Instead of subclassing atomic state, store driver private data in
private_obj/state. This allows us to remove the swap_state driver hook
for mdp5 and get closer to using the atomic helpers entirely.

Changes in v2:
  - Use state->state in disp duplicate_state callback (Jeykumar)
Changes in v3:
  - Update comment describing msm_kms_state (Jeykumar)



One difference w.r.t the patchset
"drm/msm/mdp5: Use the new private_obj state" is that this
adds the atomic private_obj for all kms backends, whereas the one
I'd done originally just added it for mdp5, so this patch set
is better in that respect.

The other difference is how we 'get' the private state. In this patch,
the helper drm_atomic_get_private_obj_state() is used every time to
get the private object state.

I'd tried to do the same initially, but I noticed that
drm_atomic_get_private_obj_state() doesn't return the correct
state post swapping of states. So, instead of relying on the helper,
I created a helper called mdp5_get_existing_global_state() that
returns the desired state(the state pointer in 
msm_kms>state->base.state

in this patch) in all funcs that are called post-swap.


You could read about the issue on the the thread: "[RFC 1/3]
drm/msm/mdp5: Add global state as a private atomic object"

The problem was quite apparent with db410c, where SMP blocks are
assigned to planes. If the latest SMP state isn't referred when
configuring SMP registers, we see underruns immediately.

An easy way to reproduce this is to use modset on db410c. I think
it might occur with this patch too. It might be worth trying it
out.

Thanks,
Archit

Hello Archit, Now that I am trying to use the private obj to maintain 
resource pool in DPU, I realize the need for retrieving existing / new 
state API's. Don't you think this support is missing in the DRM core 
fwk, considering how drm_atomic_get_existing__state, 
drm_atomic_get_old__state, drm_atomic_get_new__state API's are 
available for CRTC/PLANE and CONNECTORS but not for private_obj's?


Thanks,
Jeykumar S.

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>
---
  drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 37 ++
  drivers/gpu/drm/msm/msm_atomic.c | 30 ---
  drivers/gpu/drm/msm/msm_drv.c| 65 
++--

  drivers/gpu/drm/msm/msm_drv.h|  4 +-
  drivers/gpu/drm/msm/msm_kms.h| 27 +-
  5 files changed, 94 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c

index 6d8e3a9a6fc0..f1a248419655 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -74,36 +74,32 @@ struct mdp5_state *mdp5_get_state(struct 
drm_atomic_state *s)

  {
struct msm_drm_private *priv = s->dev->dev_private;
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
-   struct msm_kms_state *state = to_kms_state(s);
-   struct mdp5_state *new_state;
+   struct msm_kms_state *kms_state;
int ret;

-   if (state->state)
-   return state->state;
-
ret = drm_modeset_lock(_kms->state_lock, s->acquire_ctx);
if (ret)
return ERR_PTR(ret);

-   new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
-   if (!new_state)
-   return ERR_PTR(-ENOMEM);
+   kms_state = msm_kms_get_state(s);
+   if (IS_ERR_OR_NULL(kms_state))
+   return (struct mdp5_state *)kms_state; /* casting ERR_PTR */

-   /* Copy state: */
-   new_state->hwpipe = mdp5_kms->state->hwpipe;
-   new_state->hwmixer = mdp5_kms->state->hwmixer;
-   if (mdp5_kms->smp)
-   new_state->smp = mdp5_kms->state->smp;
+   return kms_state->state;
+}

-   state->state = new_state;
+static void *mdp5_duplicate_state(void *state)
+{
+   if (!state)
+   return kzalloc(sizeof(struct mdp5_state), GFP_KERNEL);

-   return new_state;
+   return kmemdup(state, sizeof(struct mdp5_state), GFP_KERNEL);
  }

-static void mdp5_swap_state(struct msm_kms *kms, struct 
drm_atomic_state *state)

+static void mdp5_destroy_state(void *state)
  {
-   struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
-   swap(to_kms_state(state)->state, mdp5_kms->state);
+   struct mdp5_state *mdp_state = state;
+   kfree(mdp_state);
  }

  static void mdp5_prepare_commit(struct msm_kms *kms, struct 
drm_atomic_state *state)

@@ -229,7 +225,8 @@ static const struct mdp_kms_funcs kms_funcs = {
.irq = mdp5_irq,
.enable_vblank   = mdp5_enable_v

[Freedreno] [DPU PATCH 6/7] drm/msm: remove msm_prop files

[Jeykumar Sankaran]

Remove hand rolled msm property caching to handle DPU
custom properties. This change also cleans up all its
dependencies to cache and restore respective drm
states.

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/Makefile  |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 239 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h   |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 123 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h |  12 -
 drivers/gpu/drm/msm/msm_drv.h |  16 +-
 drivers/gpu/drm/msm/msm_prop.c| 688 --
 drivers/gpu/drm/msm/msm_prop.h| 438 
 10 files changed, 8 insertions(+), 1529 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/msm_prop.c
 delete mode 100644 drivers/gpu/drm/msm/msm_prop.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index d289503..5331188 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -76,7 +76,6 @@ msm-y := \
dpu_io_util.o \
dpu_dbg_evtlog.o \
dpu_power_handle.o \
-   msm_prop.o \
msm_atomic.o \
msm_debugfs.o \
msm_drv.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index c4820de..e4b82d5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -19,8 +19,6 @@
 #include 
 #include 
 
-#include "msm_prop.h"
-
 #include "dpu_kms.h"
 #include "dpu_trace.h"
 #include "dpu_crtc.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index b0a3a30..43d9985 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -579,10 +579,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
if (!crtc)
return;
 
-   if (dpu_crtc->blob_info)
-   drm_property_blob_put(dpu_crtc->blob_info);
-   msm_property_destroy(_crtc->property_info);
-
_dpu_crtc_deinit_events(dpu_crtc);
 
drm_crtc_cleanup(crtc);
@@ -1390,9 +1386,7 @@ static void dpu_crtc_destroy_state(struct drm_crtc *crtc,
 
__drm_atomic_helper_crtc_destroy_state(state);
 
-   /* destroy value helper */
-   msm_property_destroy_state(_crtc->property_info, cstate,
-   >property_state);
+   kfree(cstate);
 }
 
 static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)
@@ -1641,17 +1635,12 @@ static struct drm_crtc_state 
*dpu_crtc_duplicate_state(struct drm_crtc *crtc)
 
dpu_crtc = to_dpu_crtc(crtc);
old_cstate = to_dpu_crtc_state(crtc->state);
-   cstate = msm_property_alloc_state(_crtc->property_info);
+   cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL);
if (!cstate) {
DPU_ERROR("failed to allocate state\n");
return NULL;
}
 
-   /* duplicate value helper */
-   msm_property_duplicate_state(_crtc->property_info,
-   old_cstate, cstate,
-   >property_state, cstate->property_values);
-
/* duplicate base helper */
__drm_atomic_helper_crtc_duplicate_state(crtc, >base);
 
@@ -1687,17 +1676,12 @@ static void dpu_crtc_reset(struct drm_crtc *crtc)
}
 
dpu_crtc = to_dpu_crtc(crtc);
-   cstate = msm_property_alloc_state(_crtc->property_info);
+   cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
if (!cstate) {
DPU_ERROR("failed to allocate state\n");
return;
}
 
-   /* reset value helper */
-   msm_property_reset_state(_crtc->property_info, cstate,
-   >property_state,
-   cstate->property_values);
-
_dpu_crtc_rp_reset(>rp, _crtc->rp_lock,
_crtc->rp_head);
 
@@ -2194,212 +2178,6 @@ void dpu_crtc_cancel_pending_flip(struct drm_crtc 
*crtc, struct drm_file *file)
_dpu_crtc_complete_flip(crtc, file);
 }
 
-/**
- * dpu_crtc_install_properties - install all drm properties for crtc
- * @crtc: Pointer to drm crtc structure
- */
-static void dpu_crtc_install_properties(struct drm_crtc *crtc,
-   struct dpu_mdss_cfg *catalog)
-{
-   struct dpu_crtc *dpu_crtc;
-   struct drm_device *dev;
-   struct dpu_kms_info *info;
-   struct dpu_kms *dpu_kms;
-
-   DPU_DEBUG("\n");
-
-   if (!crtc || !catalog) {
-   DPU_ERROR("invalid crtc or catalog\n");
-   return;
-   }
-
-   dpu_crtc = to_dpu_crtc(crtc);
-   dev = crtc->de

[Freedreno] [DPU PATCH 4/7] drm/msm/dpu: switch to drm zpos property

[Jeykumar Sankaran]

Replace custom plane zpos property with drm core zpos
property. CRTC relies on the normalized zpos values
to configure blend stages of each plane.

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 36 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +---
 2 files changed, 16 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index d439a9e..a0b702f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -2631,24 +2631,6 @@ struct plane_state {
u32 pipe_id;
 };
 
-static int pstate_cmp(const void *a, const void *b)
-{
-   struct plane_state *pa = (struct plane_state *)a;
-   struct plane_state *pb = (struct plane_state *)b;
-   int rc = 0;
-   int pa_zpos, pb_zpos;
-
-   pa_zpos = dpu_plane_get_property(pa->dpu_pstate, PLANE_PROP_ZPOS);
-   pb_zpos = dpu_plane_get_property(pb->dpu_pstate, PLANE_PROP_ZPOS);
-
-   if (pa_zpos != pb_zpos)
-   rc = pa_zpos - pb_zpos;
-   else
-   rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
-
-   return rc;
-}
-
 static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *state)
 {
@@ -2714,8 +2696,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate);
pstates[cnt].drm_pstate = pstate;
-   pstates[cnt].stage = dpu_plane_get_property(
-   pstates[cnt].dpu_pstate, PLANE_PROP_ZPOS);
+   pstates[cnt].stage = pstate->normalized_zpos;
pstates[cnt].pipe_id = dpu_plane_pipe(plane);
 
/* check dim layer stage with every plane */
@@ -2771,21 +2752,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
}
}
 
-   /* assign mixer stages based on sorted zpos property */
-   sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
-
-   if (!dpu_is_custom_client()) {
-   int stage_old = pstates[0].stage;
-
-   z_pos = 0;
-   for (i = 0; i < cnt; i++) {
-   if (stage_old != pstates[i].stage)
-   ++z_pos;
-   stage_old = pstates[i].stage;
-   pstates[i].stage = z_pos;
-   }
-   }
-
z_pos = -1;
for (i = 0; i < cnt; i++) {
/* reset counts at every new blend stage */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index b033653..28735c8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -59,6 +59,7 @@
 #define DPU_NAME_SIZE  12
 
 #define DPU_PLANE_COLOR_FILL_FLAG  BIT(31)
+#define DPU_ZPOS_MAX 255
 
 /* multirect rect index */
 enum {
@@ -1518,9 +1519,6 @@ static void _dpu_plane_install_properties(struct 
drm_plane *plane,
/* reserve zpos == 0 for primary planes */
zpos_def = drm_plane_index(plane) + 1;
}
-
-   msm_property_install_range(>property_info, "zpos",
-   0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
 }
 
 static int dpu_plane_atomic_set_property(struct drm_plane *plane,
@@ -1958,6 +1956,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
struct msm_drm_private *priv;
struct dpu_kms *kms;
enum drm_plane_type type;
+   int zpos_max = DPU_ZPOS_MAX;
int ret = -EINVAL;
 
if (!dev) {
@@ -2049,6 +2048,19 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev,
if (ret)
goto clean_sspp;
 
+   pdpu->catalog = kms->catalog;
+
+   if (kms->catalog->mixer_count &&
+   kms->catalog->mixer[0].sblk->maxblendstages) {
+   zpos_max = kms->catalog->mixer[0].sblk->maxblendstages - 1;
+   if (zpos_max > DPU_STAGE_MAX - DPU_STAGE_0 - 1)
+   zpos_max = DPU_STAGE_MAX - DPU_STAGE_0 - 1;
+   }
+
+   ret = drm_plane_create_zpos_property(plane, 0, 0, zpos_max);
+   if (ret)
+   DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
+
/* success! finalize initialization */
drm_plane_helper_add(plane, _plane_helper_funcs);
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

___
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[Freedreno] [DPU PATCH 7/7] drm/msm: remove dpu specific uapi header

[Jeykumar Sankaran]

remove unwanted dpu uapi headers exposing custom
payload layouts for custom properties

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 include/uapi/drm/dpu_drm.h| 220 ---
 include/uapi/drm/msm_drm_pp.h | 345 --
 2 files changed, 565 deletions(-)
 delete mode 100644 include/uapi/drm/dpu_drm.h
 delete mode 100644 include/uapi/drm/msm_drm_pp.h

diff --git a/include/uapi/drm/dpu_drm.h b/include/uapi/drm/dpu_drm.h
deleted file mode 100644
index 93af1fb..000
--- a/include/uapi/drm/dpu_drm.h
+++ /dev/null
@@ -1,220 +0,0 @@
-#ifndef _DPU_DRM_H_
-#define _DPU_DRM_H_
-
-#include "drm.h"
-
-/* Total number of supported color planes */
-#define DPU_MAX_PLANES  4
-
-/* Total number of parameterized detail enhancer mapping curves */
-#define DPU_MAX_DE_CURVES 3
-
- /* Y/RGB and UV filter configuration */
-#define FILTER_EDGE_DIRECTED_2D0x0
-#define FILTER_CIRCULAR_2D 0x1
-#define FILTER_SEPARABLE_1D0x2
-#define FILTER_BILINEAR0x3
-
-/* Alpha filters */
-#define FILTER_ALPHA_DROP_REPEAT   0x0
-#define FILTER_ALPHA_BILINEAR  0x1
-#define FILTER_ALPHA_2D0x3
-
-/* Blend filters */
-#define FILTER_BLEND_CIRCULAR_2D   0x0
-#define FILTER_BLEND_SEPARABLE_1D  0x1
-
-/* LUT configuration flags */
-#define SCALER_LUT_SWAP0x1
-#define SCALER_LUT_DIR_WR  0x2
-#define SCALER_LUT_Y_CIR_WR0x4
-#define SCALER_LUT_UV_CIR_WR   0x8
-#define SCALER_LUT_Y_SEP_WR0x10
-#define SCALER_LUT_UV_SEP_WR   0x20
-
-/**
- * Blend operations for "blend_op" property
- *
- * @DPU_DRM_BLEND_OP_NOT_DEFINED:   No blend operation defined for the layer.
- * @DPU_DRM_BLEND_OP_OPAQUE:Apply a constant blend operation. The layer
- *  would appear opaque in case fg plane alpha
- *  is 0xff.
- * @DPU_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already
- *  has alpha pre-multiplication done. If the 
fg
- *  plane alpha is less than 0xff, apply
- *  modulation as well. This operation is
- *  intended on layers having alpha channel.
- * @DPU_DRM_BLEND_OP_COVERAGE:  Apply source over blend rule. Layer is not
- *  alpha pre-multiplied. Apply
- *  pre-multiplication. If fg plane alpha is
- *  less than 0xff, apply modulation as well.
- * @DPU_DRM_BLEND_OP_MAX:   Used to track maximum blend operation
- *  possible by mdp.
- */
-#define DPU_DRM_BLEND_OP_NOT_DEFINED0
-#define DPU_DRM_BLEND_OP_OPAQUE 1
-#define DPU_DRM_BLEND_OP_PREMULTIPLIED  2
-#define DPU_DRM_BLEND_OP_COVERAGE   3
-#define DPU_DRM_BLEND_OP_MAX4
-
-/**
- * Bit masks for "src_config" property
- * construct bitmask via (1UL << DPU_DRM_)
- */
-#define DPU_DRM_DEINTERLACE 0   /* Specifies interlaced input */
-
-/* DRM bitmasks are restricted to 0..63 */
-#define DPU_DRM_BITMASK_COUNT   64
-
-/* Number of dest scalers supported */
-#define DPU_MAX_DS_COUNT 2
-
-/*
- * Destination scaler flag config
- */
-#define DPU_DRM_DESTSCALER_ENABLE   0x1
-#define DPU_DRM_DESTSCALER_SCALE_UPDATE 0x2
-#define DPU_DRM_DESTSCALER_ENHANCER_UPDATE  0x4
-#define DPU_DRM_DESTSCALER_PU_ENABLE0x8
-
-/**
- * struct dpu_drm_dest_scaler_cfg - destination scaler config structure
- * @flags:  Flag to switch between mode for destination scaler
- *  refer to destination scaler flag config
- * @index:  Destination scaler selection index
- * @lm_width:   Layer mixer width configuration
- * @lm_height:  Layer mixer height configuration
- * @scaler_cfg: The scaling parameters for all the mode except disable
- *  Userspace pointer to struct dpu_drm_scaler_v2
- */
-struct dpu_drm_dest_scaler_cfg {
-   uint32_t flags;
-   uint32_t index;
-   uint32_t lm_width;
-   uint32_t lm_height;
-   uint64_t scaler_cfg;
-};
-
-/**
- * struct dpu_drm_dest_scaler_data - destination scaler data struct
- * @num_dest_scaler: Number of dest scalers to be configured
- * @ds_cfg:  Destination scaler block configuration
- */
-struct dpu_drm_dest_scaler_data {
-   uint32_t num_dest_scaler;
-   struct dpu_drm_dest_scaler_cfg ds_cfg[DPU_MAX_DS_COUNT];
-};
-
-/*
- * Define constants for struct dpu_drm_csc
- */
-#define DPU_CSC_MATRIX_COEFF_SIZE   9
-#define DPU_CSC_CLAMP_SIZE  6
-#define DPU_CSC_BIAS_SIZE   3
-
-/**
- * struct dpu_drm_csc_v1 - version 1 of struct dpu_drm_csc
- * @ctm_coeff:  Matrix coefficients, in S31.32 format
- * @pre_bias: 

[Freedreno] [DPU PATCH 0/7] clean up DPU custom properties

[Jeykumar Sankaran]

Submitting a series of patches to further clean up DPU driver by stripping
down a list of custom properties supporting proprietary features. It 
removes the property installers/handlers and cleans up relevant files of
of some of the advanced features. This series is based on the patch[1] 
available on the drm-next tip.

[1]https://patchwork.kernel.org/patch/10202847/

Thanks.

Jeykumar Sankaran (7):
  drm/msm: remove connector custom properties
  drm/msm/dpu: clean up dpu plane custom properties
  drm/msm: enable zpos normalization
  drm/msm/dpu: switch to drm zpos property
  drm/msm/dpu: clean up dpu crtc custom properties
  drm/msm: remove msm_prop files
  drm/msm: remove dpu specific uapi header

 Makefile   |2 +-
 drivers/gpu/drm/msm/Makefile   |   10 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h|   99 --
 .../gpu/drm/msm/disp/dpu1/dpu_color_processing.c   | 1521 
 .../gpu/drm/msm/disp/dpu1/dpu_color_processing.h   |  120 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c  |   30 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   | 1271 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |   46 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|   14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|2 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c|1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c | 1443 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   72 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   89 --
 .../msm/disp/dpu1/dpu_hw_color_proc_common_v4.h|   69 -
 .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c   |  242 
 .../gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h   |   40 -
 .../drm/msm/disp/dpu1/dpu_hw_color_processing.h|   20 -
 .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.c   |  565 
 .../msm/disp/dpu1/dpu_hw_color_processing_v1_7.h   |   92 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c |   44 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |   15 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c  |  149 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h  |  111 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c|  209 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h|  220 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c  |   68 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h  |   14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|   58 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|   68 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c  |  757 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.h  |   27 -
 .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.c   |  943 
 .../msm/disp/dpu1/dpu_hw_reg_dma_v1_color_proc.h   |   75 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c|  219 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h|   73 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c|1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h|  156 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|3 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  | 1404 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h  |   43 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.c|  139 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_reg_dma.h|  310 
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  149 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c |2 -
 drivers/gpu/drm/msm/msm_drv.c  |3 +
 drivers/gpu/drm/msm/msm_drv.h  |   86 +-
 drivers/gpu/drm/msm/msm_prop.c |  688 -
 drivers/gpu/drm/msm/msm_prop.h |  438 --
 include/uapi/drm/dpu_drm.h |  407 --
 include/uapi/drm/msm_drm.h |1 -
 include/uapi/drm/msm_drm_pp.h  |  345 -
 54 files changed, 296 insertions(+), 12685 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_ad4.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ad4.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_common_v4.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_proc_v4.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_color_processing_v1_7.h
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1

[Freedreno] [DPU PATCH 5/7] drm/msm/dpu: clean up dpu crtc custom properties

[Jeykumar Sankaran]

Remove dpu crtc custom properties and its handlers.

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/Makefile  |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |  28 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 856 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |  27 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   |  12 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c | 149 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h | 111 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c |  67 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h |  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h   |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c|  71 +--
 drivers/gpu/drm/msm/msm_drv.h |  15 -
 12 files changed, 11 insertions(+), 1356 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ds.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 7bc3921..d289503 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -57,7 +57,6 @@ msm-y := \
disp/dpu1/dpu_hw_catalog.o \
disp/dpu1/dpu_hw_cdm.o \
disp/dpu1/dpu_hw_ctl.o \
-   disp/dpu1/dpu_hw_ds.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
disp/dpu1/dpu_hw_lm.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 981f77f..c4820de 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -102,34 +102,6 @@ static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms,
dpu_cstate = to_dpu_crtc_state(state);
memset(perf, 0, sizeof(struct dpu_core_perf_params));
 
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_MNOC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_MNOC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-
-   if (dpu_cstate->bw_split_vote) {
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_LLCC_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_LLCC_IB);
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_DRAM_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_DRAM_IB);
-   } else {
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_LLCC] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-   perf->bw_ctl[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_AB);
-   perf->max_per_pipe_ib[DPU_POWER_HANDLE_DBUS_ID_EBI] =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_IB);
-   }
-
-   perf->core_clk_rate =
-   dpu_crtc_get_property(dpu_cstate, CRTC_PROP_CORE_CLK);
-
if (!dpu_cstate->bw_control) {
for (i = 0; i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) {
perf->bw_ctl[i] = kms->catalog->perf.max_bw_high *
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index a0b702f..b0a3a30 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -570,18 +570,6 @@ static void _dpu_crtc_deinit_events(struct dpu_crtc 
*dpu_crtc)
return;
 }
 
-/**
- * dpu_crtc_destroy_dest_scaler - free memory allocated for scaler lut
- * @dpu_crtc: Pointer to dpu crtc
- */
-static void _dpu_crtc_destroy_dest_scaler(struct dpu_crtc *dpu_crtc)
-{
-   if (!dpu_crtc)
-   return;
-
-   kfree(dpu_crtc->scl3_lut_cfg);
-}
-
 static void dpu_crtc_destroy(struct drm_crtc *crtc)
 {
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
@@ -594,7 +582,6 @@ static void dpu_crtc_destroy(struct drm_crtc *crtc)
if (dpu_crtc->blob_info)
drm_property_blob_put(dpu_crtc->blob_info);
msm_property_destroy(_crtc->property_info);
-   _dpu_crtc_destroy_dest_scaler(dpu_crtc);
 
_dpu_crtc_deinit_events(dpu_crtc);
 
@@ -679,71 +666,6 @@ static void _dpu_crtc_setup_blend_cfg(struct 
dpu_crtc_mixer *mixer,
format->alpha_enable, fg_alpha, bg_alpha, blend_op);
 }
 
-static void _dpu_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc,

[Freedreno] [DPU PATCH 1/7] drm/msm: remove connector custom properties

[Jeykumar Sankaran]

Cleanup residual connector property enumerations.

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/msm_drv.h | 27 ---
 1 file changed, 27 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 90a2521..954ac12 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -140,32 +140,6 @@ enum msm_mdp_crtc_property {
CRTC_PROP_COUNT
 };
 
-enum msm_mdp_conn_property {
-   /* blob properties, always put these first */
-   CONNECTOR_PROP_DPU_INFO,
-   CONNECTOR_PROP_HDR_INFO,
-   CONNECTOR_PROP_PP_DITHER,
-
-   /* # of blob properties */
-   CONNECTOR_PROP_BLOBCOUNT,
-
-   /* range properties */
-   CONNECTOR_PROP_OUT_FB = CONNECTOR_PROP_BLOBCOUNT,
-   CONNECTOR_PROP_DST_X,
-   CONNECTOR_PROP_DST_Y,
-   CONNECTOR_PROP_DST_W,
-   CONNECTOR_PROP_DST_H,
-   CONNECTOR_PROP_BL_SCALE,
-   CONNECTOR_PROP_AD_BL_SCALE,
-
-   /* enum/bitmask properties */
-   CONNECTOR_PROP_AUTOREFRESH,
-   CONNECTOR_PROP_LP,
-
-   /* total # of properties */
-   CONNECTOR_PROP_COUNT
-};
-
 struct msm_vblank_ctrl {
struct kthread_work work;
struct list_head event_list;
@@ -434,7 +408,6 @@ struct msm_drm_private {
/* Properties */
struct drm_property *plane_property[PLANE_PROP_COUNT];
struct drm_property *crtc_property[CRTC_PROP_COUNT];
-   struct drm_property *conn_property[CONNECTOR_PROP_COUNT];
 
/* Color processing properties for the crtc */
struct drm_property **cp_property;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[Freedreno] [DPU PATCH 3/7] drm/msm: enable zpos normalization

[Jeykumar Sankaran]

Enable drm core zpos normalization for planes.

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/msm_drv.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index ebc40a9..549359e 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -592,6 +592,9 @@ static int msm_drm_init(struct device *dev, struct 
drm_driver *drv)
ddev->mode_config.funcs = _config_funcs;
ddev->mode_config.helper_private = _config_helper_funcs;
 
+   /* Enable normalization of plane zpos */
+   ddev->mode_config.normalize_zpos = true;
+
if (kms) {
ret = kms->funcs->hw_init(kms);
if (ret) {
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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Re: [Freedreno] [DPU PATCH] drm/msm: dpu: Fix build warnings

[Jeykumar Sankaran]

On 2018-04-20 09:07, Sean Paul wrote:

Signed-off-by: Sean Paul <seanp...@chromium.org>
---


Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>


 .../gpu/drm/msm/disp/dpu1/dpu_color_processing.c   |  5 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c  | 14 +++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  |  9 +
 drivers/gpu/drm/msm/dpu_dbg.c  | 14 --
 drivers/gpu/drm/msm/dsi/dsi_manager.c  |  2 +-
 6 files changed, 26 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
index c6fc0a28d76f..f13d1cc8f635 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_color_processing.c
@@ -244,7 +244,8 @@ static int dpu_cp_handle_range_property(struct
dpu_cp_node *prop_node,
return 0;
}

-   ret = copy_from_user(blob_ptr->data, (void *)val,
blob_ptr->length);
+   ret = copy_from_user(blob_ptr->data, u64_to_user_ptr(val),
+blob_ptr->length);
if (ret) {
DRM_ERROR("failed to get the property info ret %d", ret);
ret = -EFAULT;
@@ -910,7 +911,7 @@ int dpu_cp_crtc_set_property(struct drm_crtc *crtc,
 */
if (!dpu_crtc->num_mixers ||
dpu_crtc->num_mixers > ARRAY_SIZE(dpu_crtc->mixers)) {
-   DRM_ERROR("Invalid mixer config act cnt %d max cnt %ld\n",
+   DRM_ERROR("Invalid mixer config act cnt %d max cnt %zd\n",
dpu_crtc->num_mixers,
ARRAY_SIZE(dpu_crtc->mixers));
return -EINVAL;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 631ba7ebf596..f7ac9c85c336 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -3366,11 +3366,11 @@ static int dpu_crtc_atomic_set_property(struct
drm_crtc *crtc,
switch (idx) {
case CRTC_PROP_DIM_LAYER_V1:
_dpu_crtc_set_dim_layer_v1(cstate,
-   (void __user
*)val);
+
u64_to_user_ptr(val));
break;
case CRTC_PROP_DEST_SCALER:
ret = _dpu_crtc_set_dest_scaler(dpu_crtc,
-   cstate, (void __user
*)val);
+   cstate,
u64_to_user_ptr(val));
break;
case CRTC_PROP_DEST_SCALER_LUT_ED:
case CRTC_PROP_DEST_SCALER_LUT_CIR:
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
index e0d46c545c14..7c2772f7219f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_reg_dma_v1.c
@@ -171,7 +171,7 @@ static void get_decode_sel(unsigned long blk, u32
*decode_sel)
*decode_sel |= BIT(21);
break;
default:
-   DRM_ERROR("block not supported %zx\n", BIT(i));
+   DRM_ERROR("block not supported %lx\n", BIT(i));
break;
}
}
@@ -275,7 +275,7 @@ static int validate_write_multi_lut_reg(struct
dpu_reg_dma_setup_ops_cfg *cfg)
return rc;

if (cfg->wrap_size < WRAP_MIN_SIZE || cfg->wrap_size >
WRAP_MAX_SIZE) {
-   DRM_ERROR("invalid wrap sz %d min %d max %zd\n",
+   DRM_ERROR("invalid wrap sz %d min %d max %ld\n",
cfg->wrap_size, WRAP_MIN_SIZE, WRAP_MAX_SIZE);
rc = -EINVAL;
}
@@ -302,7 +302,7 @@ static int validate_write_reg(struct
dpu_reg_dma_setup_ops_cfg *cfg)
}
if ((SIZE_DWORD(cfg->data_size)) > MAX_DWORDS_SZ ||
NOT_WORD_ALIGNED(cfg->data_size)) {
-   DRM_ERROR("Invalid data size %d max %zd align %x\n",
+   DRM_ERROR("Invalid data size %d max %ld align %x\n",
cfg->data_size, MAX_DWORDS_SZ,
NOT_WORD_ALIGNED(cfg->data_size));
return -EINVAL;
@@ -310,7 +310,7 @@ static int validate_write_reg(struct
dpu_reg_dma_setup_ops_cfg *cfg)

if (cfg->blk_offset > MAX_RELATIVE_OFF ||
NOT_WORD_ALIGNED(cfg->blk_offset)) {
-   DRM_ERROR("invalid offset %d max %zd align %x\n",
+   DRM_ERROR("invalid offset %d max %ld align %x\n",
  

[Freedreno] [DPU PATCH v2 1/6] drm/msm: remove display stream compression(DSC) support for SM845

[Jeykumar Sankaran]

Upstream DSI driver doesn't support DSC panels yet. Remove
the support for compression from DPU for now.

changes in v2:
- indents and unrelated change clean up (Sean Paul)
- fix compilation dependency in dsi-staging

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/Makefile   |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 476 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   7 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |   1 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |   7 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  25 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 252 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 100 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|  17 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|  48 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|  22 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |  13 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  55 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   8 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c |   2 -
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.c  |   7 -
 drivers/gpu/drm/msm/msm_drv.h  |  16 -
 21 files changed, 5 insertions(+), 1093 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 9c27991..b23a001 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -64,7 +64,6 @@ msm-y := \
disp/dpu1/dpu_hw_color_processing_v1_7.o \
disp/dpu1/dpu_hw_ctl.o \
disp/dpu1/dpu_hw_ds.o \
-   disp/dpu1/dpu_hw_dsc.o \
disp/dpu1/dpu_hw_dspp.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index 36607e3..1237efc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -39,12 +39,8 @@
 static const struct drm_prop_enum_list e_topology_name[] = {
{DPU_RM_TOPOLOGY_NONE,  "dpu_none"},
{DPU_RM_TOPOLOGY_SINGLEPIPE,"dpu_singlepipe"},
-   {DPU_RM_TOPOLOGY_SINGLEPIPE_DSC,"dpu_singlepipe_dsc"},
{DPU_RM_TOPOLOGY_DUALPIPE,  "dpu_dualpipe"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_DSC,  "dpu_dualpipe_dsc"},
{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,  "dpu_dualpipemerge"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC,  "dpu_dualpipemerge_dsc"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE, "dpu_dualpipe_dscmerge"},
{DPU_RM_TOPOLOGY_PPSPLIT,   "dpu_ppsplit"},
 };
 static const struct drm_prop_enum_list e_topology_control[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 198c618..151889b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -32,7 +32,6 @@
 #include "dpu_formats.h"
 #include "dpu_encoder_phys.h"
 #include "dpu_power_handle.h"
-#include "dpu_hw_dsc.h"
 #include "dpu_crtc.h"
 #include "dpu_trace.h"
 #include "dpu_core_irq.h"
@@ -152,7 +151,6 @@ enum dpu_enc_rc_states {
  * Only valid after enable. Cleared as disable.
  * @hw_pp  Handle to the pingpong blocks used for the display. No.
  * pingpong blocks can be different than num_phys_encs.
- * @hw_dsc:Array of DSC block handles used for the display.
  * @intfs_swapped  Whether or not the phys_enc interfaces have been swapped
  * for partial update right-only cases, such as pingpong
  * split where virtual pingpong does not generate IRQs
@@ -199,7 +197,6 @@ struct dpu_encoder_virt {
struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
struct dpu_encoder_phys *cur_master;
struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
-   struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
 
bool intfs_swapped;
 
@@ -234,21 +231,6 @@ struct dpu_encoder_virt {
 
 #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
 
-bool dpu_encoder_is_dsc_enabled(struct drm_encoder *drm_enc)
-
-{
-   struct dpu_encoder_virt *dpu_enc;
-   struct msm_compression_info *comp_info;
-
-   if

[Freedreno] [DPU PATCH v2 3/6] drm/msm: remove panel autorefresh support for SDM845

[Jeykumar Sankaran]

Remove autorefresh support for smart panels in SDM845 for now.
It needs more discussion to figure out the user space
communication to set preference for the feature.

changes in v2:
- none

Reviewed-by: Sean Paul <seanp...@chromium.org>
Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  37 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  20 --
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 298 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|  41 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|  18 --
 6 files changed, 11 insertions(+), 410 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index f7e9f76..dc0978d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -24,9 +24,6 @@
 
 #define BL_NODE_NAME_SIZE 32
 
-/* Autorefresh will occur after FRAME_CNT frames. Large values are unlikely */
-#define AUTOREFRESH_MAX_FRAME_CNT 6
-
 #define DPU_DEBUG_CONN(c, fmt, ...) DPU_DEBUG("conn%d " fmt,\
(c) ? (c)->base.base.id : -1, ##__VA_ARGS__)
 
@@ -1126,10 +1123,6 @@ struct drm_connector *dpu_connector_init(struct 
drm_device *dev,
CONNECTOR_PROP_AD_BL_SCALE);
 #endif
 
-   msm_property_install_range(_conn->property_info, "autorefresh",
-   0x0, 0, AUTOREFRESH_MAX_FRAME_CNT, 0,
-   CONNECTOR_PROP_AUTOREFRESH);
-
/* enum/bitmask properties */
msm_property_install_enum(_conn->property_info, "topology_name",
DRM_MODE_PROP_IMMUTABLE, 0, e_topology_name,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d04095b..3854410 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -813,7 +813,6 @@ static void _dpu_encoder_resource_control_helper(struct 
drm_encoder *drm_enc,
 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
u32 sw_event)
 {
-   bool autorefresh_enabled = false;
unsigned int lp, idle_timeout;
struct dpu_encoder_virt *dpu_enc;
struct msm_drm_private *priv;
@@ -920,13 +919,6 @@ static int dpu_encoder_resource_control(struct drm_encoder 
*drm_enc,
return 0;
}
 
-   /* schedule delayed off work if autorefresh is disabled */
-   if (dpu_enc->cur_master &&
-   dpu_enc->cur_master->ops.is_autorefresh_enabled)
-   autorefresh_enabled =
-   dpu_enc->cur_master->ops.is_autorefresh_enabled(
-   dpu_enc->cur_master);
-
/* set idle timeout based on master connector's lp value */
if (dpu_enc->cur_master)
lp = dpu_connector_get_lp(
@@ -939,13 +931,12 @@ static int dpu_encoder_resource_control(struct 
drm_encoder *drm_enc,
else
idle_timeout = dpu_enc->idle_timeout;
 
-   if (!autorefresh_enabled)
-   kthread_queue_delayed_work(
-   _thread->worker,
-   _enc->delayed_off_work,
-   msecs_to_jiffies(idle_timeout));
+   kthread_queue_delayed_work(
+   _thread->worker,
+   _enc->delayed_off_work,
+   msecs_to_jiffies(idle_timeout));
+
DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
-   autorefresh_enabled,
idle_timeout, DPU_EVTLOG_FUNC_CASE2);
DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work scheduled\n",
sw_event);
@@ -1988,7 +1979,6 @@ static void dpu_encoder_vsync_event_handler(struct 
timer_list *t)
struct drm_encoder *drm_enc = _enc->base;
struct msm_drm_private *priv;
struct msm_drm_thread *event_thread;
-   bool autorefresh_enabled = false;
 
if (!drm_enc->dev || !drm_enc->dev->dev_private ||
!drm_enc->crtc) {
@@ -2009,22 +1999,7 @@ static void dpu_encoder_vsync_event_handler(struct 
timer_list *t)
return;
}
 
-   if (dpu_enc->cur_master &&
-   dpu_enc->cur_master->ops.is_autorefresh_enabled)
-   autorefresh_enabled =
-   dpu_enc->cur_master->ops.is_autorefresh_enabled(
-   dpu_enc->cur_master);
-
-   /*

[Freedreno] [DPU PATCH v2 4/6] drm/msm: strip down custom event ioctl's

[Jeykumar Sankaran]

Remove custom ioctl support in SDM845 which allows
user space to register/unregister for hw events.

changes in v2:
- none

Reviewed-by: Sean Paul <seanp...@chromium.org>
Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 218 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |  31 -
 drivers/gpu/drm/msm/msm_drv.c| 201 
 drivers/gpu/drm/msm/msm_kms.h|   2 -
 5 files changed, 1 insertion(+), 452 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 8e464fa..387919a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -39,31 +39,6 @@
 #include "dpu_core_perf.h"
 #include "dpu_trace.h"
 
-struct dpu_crtc_irq_info {
-   struct dpu_irq_callback irq;
-   u32 event;
-   int (*func)(struct drm_crtc *crtc, bool en,
-   struct dpu_irq_callback *irq);
-   struct list_head list;
-};
-
-struct dpu_crtc_custom_events {
-   u32 event;
-   int (*func)(struct drm_crtc *crtc, bool en,
-   struct dpu_irq_callback *irq);
-};
-
-static int dpu_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
-   bool en, struct dpu_irq_callback *ad_irq);
-static int dpu_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
-   bool en, struct dpu_irq_callback *idle_irq);
-
-static struct dpu_crtc_custom_events custom_events[] = {
-   {DRM_EVENT_AD_BACKLIGHT, dpu_cp_ad_interrupt},
-   {DRM_EVENT_CRTC_POWER, dpu_crtc_power_interrupt_handler},
-   {DRM_EVENT_IDLE_NOTIFY, dpu_crtc_idle_interrupt_handler}
-};
-
 /* layer mixer index on dpu_crtc */
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1
@@ -2455,9 +2430,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
struct drm_encoder *encoder;
struct dpu_crtc_mixer *m;
u32 i, misr_status;
-   unsigned long flags;
-   struct dpu_crtc_irq_info *node = NULL;
-   int ret = 0;
 
if (!crtc) {
DPU_ERROR("invalid crtc\n");
@@ -2479,17 +2451,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
dpu_encoder_virt_restore(encoder);
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, true, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to enable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrestore(_crtc->spin_lock, flags);
-
dpu_cp_crtc_post_ipc(crtc);
 
for (i = 0; i < dpu_crtc->num_mixers; ++i) {
@@ -2514,18 +2475,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
dpu_crtc->misr_data[i];
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   node = NULL;
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, false, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to disable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrestore(_crtc->spin_lock, flags);
-
dpu_cp_crtc_pre_ipc(crtc);
break;
case DPU_POWER_EVENT_POST_DISABLE:
@@ -2553,8 +2502,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
struct drm_display_mode *mode;
struct drm_encoder *encoder;
struct msm_drm_private *priv;
-   unsigned long flags;
-   struct dpu_crtc_irq_info *node = NULL;
struct drm_event event;
u32 power_on;
int ret;
@@ -2614,17 +2561,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
atomic_set(_crtc->frame_pending, 0);
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, false, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to disable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrest

[Freedreno] [DPU PATCH v2 2/6] drm/msm: remove support for ping pong split topology

[Jeykumar Sankaran]

ping pong split topology was meant for low end soc's which
doesn't have enough layer mixers to support split panels.
Considering how uncommon the topology is for current chipset's and
also to simply the driver programming, striping off the support
for SDM845.

changes in v2:
- none

Reviewed-by: Sean Paul <seanp...@chromium.org>
Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  19 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 179 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   5 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 110 +
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  21 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |  33 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |  11 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h   |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  37 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   2 -
 13 files changed, 15 insertions(+), 415 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index 1237efc..f7e9f76 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -41,8 +41,8 @@
{DPU_RM_TOPOLOGY_SINGLEPIPE,"dpu_singlepipe"},
{DPU_RM_TOPOLOGY_DUALPIPE,  "dpu_dualpipe"},
{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,  "dpu_dualpipemerge"},
-   {DPU_RM_TOPOLOGY_PPSPLIT,   "dpu_ppsplit"},
 };
+
 static const struct drm_prop_enum_list e_topology_control[] = {
{DPU_RM_TOPCTL_RESERVE_LOCK,"reserve_lock"},
{DPU_RM_TOPCTL_RESERVE_CLEAR,   "reserve_clear"},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 516458e..8e464fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1914,23 +1914,6 @@ static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
mutex_unlock(_crtc->crtc_lock);
 }
 
-static void _dpu_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
-{
-   int i;
-   struct dpu_crtc_state *cstate;
-
-   cstate = to_dpu_crtc_state(state);
-
-   cstate->is_ppsplit = false;
-   for (i = 0; i < cstate->num_connectors; i++) {
-   struct drm_connector *conn = cstate->connectors[i];
-
-   if (dpu_connector_get_topology_name(conn) ==
-   DPU_RM_TOPOLOGY_PPSPLIT)
-   cstate->is_ppsplit = true;
-   }
-}
-
 static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
struct drm_crtc_state *state)
 {
@@ -1993,7 +1976,6 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 
if (!dpu_crtc->num_mixers) {
_dpu_crtc_setup_mixers(crtc);
-   _dpu_crtc_setup_is_ppsplit(crtc->state);
_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
}
 
@@ -2901,7 +2883,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
 
-   _dpu_crtc_setup_is_ppsplit(state);
_dpu_crtc_setup_lm_bounds(crtc, state);
 
 /* get plane state for all drm planes associated with crtc state */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 151889b..d04095b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -545,7 +545,6 @@ void dpu_encoder_helper_split_config(
struct dpu_encoder_virt *dpu_enc;
struct split_pipe_cfg cfg = { 0 };
struct dpu_hw_mdp *hw_mdptop;
-   enum dpu_rm_topology_name topology;
struct msm_display_info *disp_info;
 
if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
@@ -569,8 +568,6 @@ void dpu_encoder_helper_split_config(
if (phys_enc->split_role == ENC_ROLE_SOLO) {
if (hw_mdptop->ops.setup_split_pipe)
hw_mdptop->ops.setup_split_pipe(hw_mdptop, );
-   if (hw_mdptop->ops.setup_pp_split)
-   hw_mdptop->ops.setup_pp_split(hw_mdptop, );
return;
}
 
@@ -582,29 +579,11 @@ void dpu_encoder_helper_split_config(
phys_enc->ops.needs_single_flush(phys_enc))
cfg.split_flush_en = true;
 
-   topology = dpu_connector_get_topology_name(phys_enc->connector);
-   if (topology == DPU_RM_TOPOLOGY_PPSPLIT)
-   cfg.pp_split_slave

[Freedreno] [DPU PATCH v2 0/6] Switch DPU to use upstream DSI driver for SDM845

[Jeykumar Sankaran]

SDM845 DPU driver was talking to dsi-staging driver for its dsi 
operations through the customized dpu_connector layer. The following 
series of patches removes DPU dependency from various dpu
connector API's before purging the dpu_connector altogether. It
also completes the switch to upstream DSI driver by removing
the dsi-staging driver and it's dependent sources.

The patch series is based on:
[1]https://www.spinics.net/lists/dri-devel/msg172315.html
[2]https://www.spinics.net/lists/dri-devel/msg172395.html

changes in v2:
- addressed comments on indentation (Sean Paul)
- removed compiled out non-dsi display init (Sean Paul)
- removed file changes not applicable upstream (Sean Paul)
- Split unrelated changes into seperate patch sets (Sean Paul)

Jeykumar Sankaran (6):
  drm/msm: remove display stream compression(DSC) support for SM845
  drm/msm: remove support for ping pong split topology
  drm/msm: remove panel autorefresh support for SDM845
  drm/msm: strip down custom event ioctl's
  drm/msm: hook up DPU with upstream DSI
  drm/msm: remove dsi-staging driver

 drivers/gpu/drm/msm/Kconfig|   12 -
 drivers/gpu/drm/msm/Makefile   |   23 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  | 1195 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h  |  555 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  246 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  867 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   24 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   38 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |  409 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |   32 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   30 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   18 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c |  252 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h |  100 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|   17 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|   89 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|   40 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |   46 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |   18 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h   |4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  520 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|6 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  146 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   21 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_wb.c |2 -
 drivers/gpu/drm/msm/dpu_dbg.c  |3 -
 drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c  |  241 --
 drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h  |  201 -
 drivers/gpu/drm/msm/dsi-staging/dsi_clk.h  |  276 --
 drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c  | 1235 --
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c | 2846 -
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h |  623 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h  |  752 
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_1_4.c  |  480 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_0.c  |  234 --
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_2.c  |   42 -
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c  | 1312 --
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg.h |  196 -
 drivers/gpu/drm/msm/dsi-staging/dsi_defs.h |  579 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_display.c  | 4221 
 drivers/gpu/drm/msm/dsi-staging/dsi_display.h  |  556 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_display_test.c |  114 -
 drivers/gpu/drm/msm/dsi-staging/dsi_display_test.h |   31 -
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.c  |  688 
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.h  |  127 -
 drivers/gpu/drm/msm/dsi-staging/dsi_hw.h   |   48 -
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.c| 3321 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.h|  257 --
 drivers/gpu/drm/msm/dsi-staging/dsi_phy.c  |  937 -
 drivers/gpu/drm/msm/dsi-staging/dsi_phy.h  |  235 --
 drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h   |  260 --
 drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v2_0.c  |  252 --
 drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c  |  447 ---
 .../gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.c  |  676 
 .../gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.h  |  144 -
 .../gpu/drm/msm/dsi-staging/dsi_phy_timing_v2_0.c  |  126 -
 .../gpu/drm/msm/dsi-staging/dsi_phy_timing_v3_0.c  |  107 -
 drivers/gpu/drm/msm/dsi-staging/dsi_pwr.c  |  365 --
 drivers/gpu/drm/msm/dsi-staging/dsi_pwr.h  |   93 -
 drivers/gpu/drm/msm/msm_drv.c  |  248 +-
 drivers/gpu/drm/msm/msm_drv.h

[Freedreno] [DPU PATCH] drm/msm: populate aspace in msm_kms

[Jeykumar Sankaran]

display drivers may need to access aspace to
allocate internal buffers (e.g. DSI to allocate cmd buffer)
This change populates the needed info.

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 2c187e9..f6fea21 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1835,8 +1835,6 @@ static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
goto fail;
}
 
-   dpu_kms->aspace[0] = aspace;
-
ret = aspace->mmu->funcs->attach(aspace->mmu,
(const char **)iommu_ports,
ARRAY_SIZE(iommu_ports));
@@ -1845,7 +1843,9 @@ static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
msm_gem_address_space_put(aspace);
goto fail;
}
+
aspace->domain_attached = true;
+   dpu_kms->aspace[0] = aspace;
 #endif
return 0;
 fail:
@@ -2004,6 +2004,9 @@ static int dpu_kms_hw_init(struct msm_kms *kms)
goto power_error;
}
 
+   if (dpu_kms->aspace[0])
+   kms->aspace = dpu_kms->aspace[0];
+
 #ifdef CONFIG_CHROME_REGDMA
/* Initialize reg dma block which is a singleton */
rc = dpu_reg_dma_init(dpu_kms->reg_dma, dpu_kms->catalog,
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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Re: [Freedreno] [DPU PATCH 5/6] drm/msm: hook up DPU with upstream DSI

[Jeykumar Sankaran]

On 2018-04-19 08:38, Sean Paul wrote:

On Mon, Apr 16, 2018 at 11:22:20AM -0700, Jeykumar Sankaran wrote:

Switch DPU from dsi-staging to upstream dsi driver. To make
the switch atomic, this change includes:
- remove dpu connector layers
- clean up dpu connector dependencies in encoder/crtc
- compile out writeback and display port drivers
- compile out dsi-staging driver (separate patch submitted to
  remove the driver)
- adapt upstream device hierarchy

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 .../config/arm64/chromiumos-arm64.flavour.config   |4 +-
 .../arm64/chromiumos-qualcomm.flavour.config   |4 +-


These files aren't in upstream.




+
+struct drm_encoder *dpu_encoder_init(struct drm_device *dev,
+   int drm_enc_mode)
+{
+   struct dpu_encoder_virt *dpu_enc = NULL;
+
+   dpu_enc = kzalloc(sizeof(*dpu_enc), GFP_KERNEL);


You should probably use devm_kzalloc.


+   if (!dpu_enc)
+   return ERR_PTR(ENOMEM);
+
+   drm_encoder_init(dev, _enc->base, _encoder_funcs,
+   drm_enc_mode, NULL);


Check the return value?



-#ifdef CONFIG_DRM_MSM_DSI_STAGING
 static void _dpu_kms_initialize_dsi(struct drm_device *dev,
struct msm_drm_private *priv,
-   struct dpu_kms *dpu_kms,
-   unsigned max_encoders)
+   struct dpu_kms *dpu_kms)
 {
-   static const struct dpu_connector_ops dsi_ops = {
-   .post_init =  dsi_conn_post_init,
-   .detect = dsi_conn_detect,
-   .get_modes =  dsi_connector_get_modes,
-   .put_modes =  dsi_connector_put_modes,
-   .mode_valid = dsi_conn_mode_valid,
-   .get_info =   dsi_display_get_info,
-   .set_backlight = dsi_display_set_backlight,
-   .soft_reset   = dsi_display_soft_reset,
-   .pre_kickoff  = dsi_conn_pre_kickoff,
-   .clk_ctrl = dsi_display_clk_ctrl,
-   .set_power = dsi_display_set_power,
-   .get_mode_info = dsi_conn_get_mode_info,
-   .get_dst_format = dsi_display_get_dst_format,
-   .post_kickoff = dsi_conn_post_kickoff
-   };
-   struct msm_display_info info;
-   struct drm_encoder *encoder;
-   void *display, *connector;
+   struct drm_encoder *encoder = NULL;
int i, rc;

-   /* dsi */
-   for (i = 0; i < dpu_kms->dsi_display_count &&
-   priv->num_encoders < max_encoders; ++i) {
-   display = dpu_kms->dsi_displays[i];
-   encoder = NULL;
+   /*TODO: Support two independent DSI connectors */
+   encoder = dpu_encoder_init(dev, DRM_MODE_CONNECTOR_DSI);
+   if (IS_ERR_OR_NULL(encoder)) {
+   DPU_ERROR("encoder init failed for dsi %d\n", i);


Is i meaningful here? It seems like it's uninitialized...


+   return;
+   }

-   memset(, 0x0, sizeof(info));
-   rc = dsi_display_get_info(, display);
-   if (rc) {
-   DPU_ERROR("dsi get_info %d failed\n", i);
-   continue;
-   }
+   priv->encoders[priv->num_encoders++] = encoder;

-   encoder = dpu_encoder_init(dev, );
-   if (IS_ERR_OR_NULL(encoder)) {
-   DPU_ERROR("encoder init failed for dsi %d\n", i);
-   continue;
+   for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
+   if (!priv->dsi[i]) {
+   DPU_DEBUG("invalid msm_dsi for ctrl %d\n", i);
+   return;
}

-   rc = dsi_display_drm_bridge_init(display, encoder);
+   rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder);
if (rc) {
-   DPU_ERROR("dsi bridge %d init failed, %d\n", i,

rc);

-   dpu_encoder_destroy(encoder);
+   DPU_ERROR("modeset_init failed for dsi[%d]\n", i);


Printing rc would be nice here, same for above.


continue;
}
-
-   connector = dpu_connector_init(dev,
-   encoder,
-   0,
-   display,
-   _ops,
-   DRM_CONNECTOR_POLL_HPD,
-   DRM_MODE_CONNECTOR_DSI);
-   if (connector) {
-   priv->encoders[priv->num_encoders++] = encoder;
-   } else {
-   DPU_ERROR("dsi %d connector init failed\n", i);
-   dsi_display_drm_bridge_deinit(display);
-  

[Freedreno] [DPU PATCH 3/6] drm/msm: remove panel autorefresh support for SDM845

[Jeykumar Sankaran]

Remove autorefresh support for smart panels in SDM845 for now.
It needs more discussion to figure out the user space
communication to set preference for the feature.

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  37 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |  20 --
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 298 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|  41 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|  18 --
 6 files changed, 11 insertions(+), 410 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index f7e9f76..dc0978d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -24,9 +24,6 @@
 
 #define BL_NODE_NAME_SIZE 32
 
-/* Autorefresh will occur after FRAME_CNT frames. Large values are unlikely */
-#define AUTOREFRESH_MAX_FRAME_CNT 6
-
 #define DPU_DEBUG_CONN(c, fmt, ...) DPU_DEBUG("conn%d " fmt,\
(c) ? (c)->base.base.id : -1, ##__VA_ARGS__)
 
@@ -1126,10 +1123,6 @@ struct drm_connector *dpu_connector_init(struct 
drm_device *dev,
CONNECTOR_PROP_AD_BL_SCALE);
 #endif
 
-   msm_property_install_range(_conn->property_info, "autorefresh",
-   0x0, 0, AUTOREFRESH_MAX_FRAME_CNT, 0,
-   CONNECTOR_PROP_AUTOREFRESH);
-
/* enum/bitmask properties */
msm_property_install_enum(_conn->property_info, "topology_name",
DRM_MODE_PROP_IMMUTABLE, 0, e_topology_name,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 32375b1..3004569 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -815,7 +815,6 @@ static void _dpu_encoder_resource_control_helper(struct 
drm_encoder *drm_enc,
 static int dpu_encoder_resource_control(struct drm_encoder *drm_enc,
u32 sw_event)
 {
-   bool autorefresh_enabled = false;
unsigned int lp, idle_timeout;
struct dpu_encoder_virt *dpu_enc;
struct msm_drm_private *priv;
@@ -922,13 +921,6 @@ static int dpu_encoder_resource_control(struct drm_encoder 
*drm_enc,
return 0;
}
 
-   /* schedule delayed off work if autorefresh is disabled */
-   if (dpu_enc->cur_master &&
-   dpu_enc->cur_master->ops.is_autorefresh_enabled)
-   autorefresh_enabled =
-   dpu_enc->cur_master->ops.is_autorefresh_enabled(
-   dpu_enc->cur_master);
-
/* set idle timeout based on master connector's lp value */
if (dpu_enc->cur_master)
lp = dpu_connector_get_lp(
@@ -941,13 +933,12 @@ static int dpu_encoder_resource_control(struct 
drm_encoder *drm_enc,
else
idle_timeout = dpu_enc->idle_timeout;
 
-   if (!autorefresh_enabled)
-   kthread_queue_delayed_work(
-   _thread->worker,
-   _enc->delayed_off_work,
-   msecs_to_jiffies(idle_timeout));
+   kthread_queue_delayed_work(
+   _thread->worker,
+   _enc->delayed_off_work,
+   msecs_to_jiffies(idle_timeout));
+
DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state,
-   autorefresh_enabled,
idle_timeout, DPU_EVTLOG_FUNC_CASE2);
DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work scheduled\n",
sw_event);
@@ -1990,7 +1981,6 @@ static void dpu_encoder_vsync_event_handler(struct 
timer_list *t)
struct drm_encoder *drm_enc = _enc->base;
struct msm_drm_private *priv;
struct msm_drm_thread *event_thread;
-   bool autorefresh_enabled = false;
 
if (!drm_enc->dev || !drm_enc->dev->dev_private ||
!drm_enc->crtc) {
@@ -2011,22 +2001,7 @@ static void dpu_encoder_vsync_event_handler(struct 
timer_list *t)
return;
}
 
-   if (dpu_enc->cur_master &&
-   dpu_enc->cur_master->ops.is_autorefresh_enabled)
-   autorefresh_enabled =
-   dpu_enc->cur_master->ops.is_autorefresh_enabled(
-   dpu_enc->cur_master);
-
-   /*
-* Queue work to update the vsync event timer
-* if autorefresh is enabled.

[Freedreno] [DPU PATCH 0/6] Switch DPU to use upstream DSI driver for SDM845

[Jeykumar Sankaran]

SDM845 DPU driver was talking to dsi-staging driver for its dsi 
operations through the customized dpu_connector layer. The following 
series of patches removes DPU dependency from various dpu
connector API's before purging the dpu_connector altogether. It
also completes the switch to upstream DSI driver by removing
the dsi-staging driver and it's dependent sources.

The patch series is based on:
[1]https://www.spinics.net/lists/dri-devel/msg172315.html
[2]https://www.spinics.net/lists/dri-devel/msg172395.html

Jeykumar Sankaran (6):
  drm/msm: remove display stream compression(DSC) support for SM845
  drm/msm: remove support for ping pong split topology
  drm/msm: remove panel autorefresh support for SDM845
  drm/msm: strip down custom event ioctl's
  drm/msm: hook up DPU with upstream DSI
  drm/msm: remove dsi-staging driver

 .../config/arm64/chromiumos-arm64.flavour.config   |3 +-
 .../arm64/chromiumos-qualcomm.flavour.config   |3 +-
 drivers/gpu/drm/msm/Kconfig|   12 -
 drivers/gpu/drm/msm/Makefile   |   23 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  | 1195 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h  |  555 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  246 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |3 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  861 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   24 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   38 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |  409 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |   32 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   30 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   18 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c |  252 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h |  100 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|   17 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|   89 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|   40 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |   46 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |   18 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h   |4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  251 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  146 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   21 +-
 drivers/gpu/drm/msm/dpu_dbg.c  |3 -
 drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c  |  241 --
 drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h  |  201 -
 drivers/gpu/drm/msm/dsi-staging/dsi_clk.h  |  276 --
 drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c  | 1235 --
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c | 2846 -
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h |  623 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h  |  752 
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_1_4.c  |  480 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_0.c  |  234 --
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_2.c  |   42 -
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c  | 1312 --
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg.h |  196 -
 drivers/gpu/drm/msm/dsi-staging/dsi_defs.h |  579 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_display.c  | 4221 
 drivers/gpu/drm/msm/dsi-staging/dsi_display.h  |  556 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_display_test.c |  114 -
 drivers/gpu/drm/msm/dsi-staging/dsi_display_test.h |   31 -
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.c  |  688 
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.h  |  127 -
 drivers/gpu/drm/msm/dsi-staging/dsi_hw.h   |   48 -
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.c| 3321 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.h|  257 --
 drivers/gpu/drm/msm/dsi-staging/dsi_phy.c  |  937 -
 drivers/gpu/drm/msm/dsi-staging/dsi_phy.h  |  235 --
 drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h   |  260 --
 drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v2_0.c  |  252 --
 drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c  |  447 ---
 .../gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.c  |  676 
 .../gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.h  |  144 -
 .../gpu/drm/msm/dsi-staging/dsi_phy_timing_v2_0.c  |  126 -
 .../gpu/drm/msm/dsi-staging/dsi_phy_timing_v3_0.c  |  107 -
 drivers/gpu/drm/msm/dsi-staging/dsi_pwr.c  |  365 --
 drivers/gpu/drm/msm/dsi-staging/dsi_pwr.h  |   93 -
 drivers/gpu/drm/msm/msm_drv.c  |  242 +-
 drivers/gpu/drm/msm/msm_drv.h  |   55 -
 drivers/gpu/drm/msm/msm_kms.h  |2 -
 63 files changed, 185 insertions(+), 26575 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h
 delete mode

[Freedreno] [DPU PATCH 5/6] drm/msm: hook up DPU with upstream DSI

[Jeykumar Sankaran]

Switch DPU from dsi-staging to upstream dsi driver. To make
the switch atomic, this change includes:
- remove dpu connector layers
- clean up dpu connector dependencies in encoder/crtc
- compile out writeback and display port drivers
- compile out dsi-staging driver (separate patch submitted to
  remove the driver)
- adapt upstream device hierarchy

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 .../config/arm64/chromiumos-arm64.flavour.config   |4 +-
 .../arm64/chromiumos-qualcomm.flavour.config   |4 +-
 drivers/gpu/drm/msm/Makefile   |1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  | 1184 
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h  |  555 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |9 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c|  173 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|   10 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |8 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |6 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c|  220 +---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |   54 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   11 +
 drivers/gpu/drm/msm/dpu_dbg.c  |3 -
 drivers/gpu/drm/msm/msm_drv.c  |   41 +-
 drivers/gpu/drm/msm/msm_drv.h  |   39 -
 16 files changed, 158 insertions(+), 2164 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h

diff --git a/chromeos/config/arm64/chromiumos-arm64.flavour.config 
b/chromeos/config/arm64/chromiumos-arm64.flavour.config
index c676a69..7b20c8b 100644
--- a/chromeos/config/arm64/chromiumos-arm64.flavour.config
+++ b/chromeos/config/arm64/chromiumos-arm64.flavour.config
@@ -117,14 +117,14 @@ CONFIG_DRM_MIPI_DSI=y
 CONFIG_DRM_MSM=y
 CONFIG_DRM_MSM_DPU=y
 CONFIG_DRM_MSM_DSI=y
-CONFIG_DRM_MSM_DSI_STAGING=y
+# CONFIG_DRM_MSM_DSI_STAGING is not set
 # CONFIG_DRM_MSM_HDCP is not set
 # CONFIG_DRM_MSM_HDMI is not set
 # CONFIG_DRM_MSM_HDMI_HDCP is not set
 # CONFIG_DRM_MSM_MDP4 is not set
 # CONFIG_DRM_MSM_MDP5 is not set
 # CONFIG_DRM_MSM_REGISTER_LOGGING is not set
-CONFIG_DRM_MSM_WRITEBACK=y
+# CONFIG_DRM_MSM_WRITEBACK is not set
 # CONFIG_DRM_NOUVEAU is not set
 CONFIG_DRM_PANEL_INNOLUX_P079ZCA=y
 # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
diff --git a/chromeos/config/arm64/chromiumos-qualcomm.flavour.config 
b/chromeos/config/arm64/chromiumos-qualcomm.flavour.config
index e7f45f3..aad22a7 100644
--- a/chromeos/config/arm64/chromiumos-qualcomm.flavour.config
+++ b/chromeos/config/arm64/chromiumos-qualcomm.flavour.config
@@ -30,14 +30,14 @@ CONFIG_DRM_MIPI_DSI=y
 CONFIG_DRM_MSM=y
 CONFIG_DRM_MSM_DPU=y
 CONFIG_DRM_MSM_DSI=y
-CONFIG_DRM_MSM_DSI_STAGING=y
+# CONFIG_DRM_MSM_DSI_STAGING is not set
 # CONFIG_DRM_MSM_HDCP is not set
 # CONFIG_DRM_MSM_HDMI is not set
 # CONFIG_DRM_MSM_HDMI_HDCP is not set
 # CONFIG_DRM_MSM_MDP4 is not set
 # CONFIG_DRM_MSM_MDP5 is not set
 # CONFIG_DRM_MSM_REGISTER_LOGGING is not set
-CONFIG_DRM_MSM_WRITEBACK=y
+# CONFIG_DRM_MSM_WRITEBACK is not set
 CONFIG_DRM_PANEL_TRULY_WQXGA=y
 # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
 # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index b23a001..a8d8ad9 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -48,7 +48,6 @@ msm-y := \
disp/mdp5/mdp5_plane.o \
disp/mdp5/mdp5_smp.o \
disp/dpu1/dpu_color_processing.o \
-   disp/dpu1/dpu_connector.o \
disp/dpu1/dpu_core_irq.o \
disp/dpu1/dpu_core_perf.o \
disp/dpu1/dpu_crtc.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
deleted file mode 100644
index dc0978d..000
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ /dev/null
@@ -1,1184 +0,0 @@
-/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define pr_fmt(fmt)"[drm:%s:%d] " fmt, __func__, __LINE__
-#include "msm_drv.h"
-#include "dpu_dbg.h"
-
-#include "dpu_kms.h"
-#include "dpu_connector.h"
-#ifdef CONFIG_DRM_MSM_DSI_STAGING
-#include 
-#include "dsi_drm.h"
-#include "dsi_display.h"
-#endif
-
-#define BL_NODE_NAME_SIZE 32
-
-#define DPU_DEBUG_CONN(c, fmt,

[Freedreno] [DPU PATCH 2/6] drm/msm: remove support for ping pong split topology

[Jeykumar Sankaran]

Ping pong split topology was meant for low end soc's which
doesn't have enough layer mixers to support split panels.
Considering how uncommon the topology is for current chipset's and
also to simply the driver programming, striping off the support
for SDM845.

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   |  19 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 179 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   5 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   | 110 +
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |  21 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |   2 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |  33 
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |  11 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h   |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  37 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   2 -
 13 files changed, 15 insertions(+), 415 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index 1237efc..f7e9f76 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -41,8 +41,8 @@
{DPU_RM_TOPOLOGY_SINGLEPIPE,"dpu_singlepipe"},
{DPU_RM_TOPOLOGY_DUALPIPE,  "dpu_dualpipe"},
{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,  "dpu_dualpipemerge"},
-   {DPU_RM_TOPOLOGY_PPSPLIT,   "dpu_ppsplit"},
 };
+
 static const struct drm_prop_enum_list e_topology_control[] = {
{DPU_RM_TOPCTL_RESERVE_LOCK,"reserve_lock"},
{DPU_RM_TOPCTL_RESERVE_CLEAR,   "reserve_clear"},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 516458e..8e464fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1914,23 +1914,6 @@ static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
mutex_unlock(_crtc->crtc_lock);
 }
 
-static void _dpu_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
-{
-   int i;
-   struct dpu_crtc_state *cstate;
-
-   cstate = to_dpu_crtc_state(state);
-
-   cstate->is_ppsplit = false;
-   for (i = 0; i < cstate->num_connectors; i++) {
-   struct drm_connector *conn = cstate->connectors[i];
-
-   if (dpu_connector_get_topology_name(conn) ==
-   DPU_RM_TOPOLOGY_PPSPLIT)
-   cstate->is_ppsplit = true;
-   }
-}
-
 static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
struct drm_crtc_state *state)
 {
@@ -1993,7 +1976,6 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 
if (!dpu_crtc->num_mixers) {
_dpu_crtc_setup_mixers(crtc);
-   _dpu_crtc_setup_is_ppsplit(crtc->state);
_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
}
 
@@ -2901,7 +2883,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
 
-   _dpu_crtc_setup_is_ppsplit(state);
_dpu_crtc_setup_lm_bounds(crtc, state);
 
 /* get plane state for all drm planes associated with crtc state */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 6f12355..32375b1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -545,7 +545,6 @@ void dpu_encoder_helper_split_config(
struct dpu_encoder_virt *dpu_enc;
struct split_pipe_cfg cfg = { 0 };
struct dpu_hw_mdp *hw_mdptop;
-   enum dpu_rm_topology_name topology;
struct msm_display_info *disp_info;
 
if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
@@ -569,8 +568,6 @@ void dpu_encoder_helper_split_config(
if (phys_enc->split_role == ENC_ROLE_SOLO) {
if (hw_mdptop->ops.setup_split_pipe)
hw_mdptop->ops.setup_split_pipe(hw_mdptop, );
-   if (hw_mdptop->ops.setup_pp_split)
-   hw_mdptop->ops.setup_pp_split(hw_mdptop, );
return;
}
 
@@ -582,29 +579,11 @@ void dpu_encoder_helper_split_config(
phys_enc->ops.needs_single_flush(phys_enc))
cfg.split_flush_en = true;
 
-   topology = dpu_connector_get_topology_name(phys_enc->connector);
-   if (topology == DPU_RM_TOPOLOGY_PPSPLIT)
-   cfg.pp_split_slave = cfg.intf;
-   else
-   cfg.pp_split_slave = INTF_MA

[Freedreno] [DPU PATCH 4/6] drm/msm: strip down custom event ioctl's

[Jeykumar Sankaran]

Remove custom ioctl support in SDM845 which allows
user space to register/unregister for hw events.

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 218 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |  31 -
 drivers/gpu/drm/msm/msm_drv.c| 201 
 drivers/gpu/drm/msm/msm_kms.h|   2 -
 5 files changed, 1 insertion(+), 452 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 8e464fa..387919a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -39,31 +39,6 @@
 #include "dpu_core_perf.h"
 #include "dpu_trace.h"
 
-struct dpu_crtc_irq_info {
-   struct dpu_irq_callback irq;
-   u32 event;
-   int (*func)(struct drm_crtc *crtc, bool en,
-   struct dpu_irq_callback *irq);
-   struct list_head list;
-};
-
-struct dpu_crtc_custom_events {
-   u32 event;
-   int (*func)(struct drm_crtc *crtc, bool en,
-   struct dpu_irq_callback *irq);
-};
-
-static int dpu_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm,
-   bool en, struct dpu_irq_callback *ad_irq);
-static int dpu_crtc_idle_interrupt_handler(struct drm_crtc *crtc_drm,
-   bool en, struct dpu_irq_callback *idle_irq);
-
-static struct dpu_crtc_custom_events custom_events[] = {
-   {DRM_EVENT_AD_BACKLIGHT, dpu_cp_ad_interrupt},
-   {DRM_EVENT_CRTC_POWER, dpu_crtc_power_interrupt_handler},
-   {DRM_EVENT_IDLE_NOTIFY, dpu_crtc_idle_interrupt_handler}
-};
-
 /* layer mixer index on dpu_crtc */
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1
@@ -2455,9 +2430,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
struct drm_encoder *encoder;
struct dpu_crtc_mixer *m;
u32 i, misr_status;
-   unsigned long flags;
-   struct dpu_crtc_irq_info *node = NULL;
-   int ret = 0;
 
if (!crtc) {
DPU_ERROR("invalid crtc\n");
@@ -2479,17 +2451,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
dpu_encoder_virt_restore(encoder);
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, true, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to enable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrestore(_crtc->spin_lock, flags);
-
dpu_cp_crtc_post_ipc(crtc);
 
for (i = 0; i < dpu_crtc->num_mixers; ++i) {
@@ -2514,18 +2475,6 @@ static void dpu_crtc_handle_power_event(u32 event_type, 
void *arg)
dpu_crtc->misr_data[i];
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   node = NULL;
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, false, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to disable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrestore(_crtc->spin_lock, flags);
-
dpu_cp_crtc_pre_ipc(crtc);
break;
case DPU_POWER_EVENT_POST_DISABLE:
@@ -2553,8 +2502,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
struct drm_display_mode *mode;
struct drm_encoder *encoder;
struct msm_drm_private *priv;
-   unsigned long flags;
-   struct dpu_crtc_irq_info *node = NULL;
struct drm_event event;
u32 power_on;
int ret;
@@ -2614,17 +2561,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc)
atomic_set(_crtc->frame_pending, 0);
}
 
-   spin_lock_irqsave(_crtc->spin_lock, flags);
-   list_for_each_entry(node, _crtc->user_event_list, list) {
-   ret = 0;
-   if (node->func)
-   ret = node->func(crtc, false, >irq);
-   if (ret)
-   DPU_ERROR("%s failed to disable event %x\n",
-   dpu_crtc->name, node->event);
-   }
-   spin_unlock_irqrestore(_crtc->spin_lock, flags);
-
dpu_core_perf_crtc_update(crtc, 0, true);

[Freedreno] [DPU PATCH 1/6] drm/msm: remove display stream compression(DSC) support for SM845

[Jeykumar Sankaran]

Upstream DSI driver doesn't support DSC panels yet. Remove
the support for compression from DPU for now.

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/Makefile   |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  |   4 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 476 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h|  14 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h   |   7 +-
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c   |   1 -
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c   |   7 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  25 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h |  16 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 252 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 100 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h|  17 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c|  48 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h|  22 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c |  13 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h |   7 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c |  55 ---
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h |   8 -
 drivers/gpu/drm/msm/msm_drv.h  |  16 -
 20 files changed, 7 insertions(+), 1084 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 9c27991..b23a001 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -64,7 +64,6 @@ msm-y := \
disp/dpu1/dpu_hw_color_processing_v1_7.o \
disp/dpu1/dpu_hw_ctl.o \
disp/dpu1/dpu_hw_ds.o \
-   disp/dpu1/dpu_hw_dsc.o \
disp/dpu1/dpu_hw_dspp.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index 36607e3..1237efc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -39,12 +39,8 @@
 static const struct drm_prop_enum_list e_topology_name[] = {
{DPU_RM_TOPOLOGY_NONE,  "dpu_none"},
{DPU_RM_TOPOLOGY_SINGLEPIPE,"dpu_singlepipe"},
-   {DPU_RM_TOPOLOGY_SINGLEPIPE_DSC,"dpu_singlepipe_dsc"},
{DPU_RM_TOPOLOGY_DUALPIPE,  "dpu_dualpipe"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_DSC,  "dpu_dualpipe_dsc"},
{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,  "dpu_dualpipemerge"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC,  "dpu_dualpipemerge_dsc"},
-   {DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE, "dpu_dualpipe_dscmerge"},
{DPU_RM_TOPOLOGY_PPSPLIT,   "dpu_ppsplit"},
 };
 static const struct drm_prop_enum_list e_topology_control[] = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index 8756b2b..fade658 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -147,7 +147,7 @@ struct dpu_crtc_event {
  * @num_ctls  : Number of ctl paths in use
  * @num_mixers: Number of mixers in use
  * @mixers_swapped: Whether the mixers have been swapped for left/right update
- *  especially in the case of DSC Merge.
+   especially in the case of DSC Merge.
  * @mixers: List of active mixers
  * @event : Pointer to last received drm vblank event. If there is a
  *  pending vblank event, this will be non-null.
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 198c618..6f12355 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -32,7 +32,6 @@
 #include "dpu_formats.h"
 #include "dpu_encoder_phys.h"
 #include "dpu_power_handle.h"
-#include "dpu_hw_dsc.h"
 #include "dpu_crtc.h"
 #include "dpu_trace.h"
 #include "dpu_core_irq.h"
@@ -152,7 +151,6 @@ enum dpu_enc_rc_states {
  * Only valid after enable. Cleared as disable.
  * @hw_pp  Handle to the pingpong blocks used for the display. No.
  * pingpong blocks can be different than num_phys_encs.
- * @hw_dsc:Array of DSC block handles used for the display.
  * @intfs_swapped  Whether or not the phys_enc interfaces have been swapped
  * for partial update right-only cases, such as pingpong
  * split where virtual pingpong does not generate IRQs
@@ -199,7 +197,6 @@ struct dpu_encode

Re: [Freedreno] [DPU PATCH 06/11] drm/msm: Remove msm_commit/kthread, use atomic helper commit

[Jeykumar Sankaran]

On 2018-03-19 08:01, Sean Paul wrote:

On Mon, Mar 12, 2018 at 04:23:10PM -0400, Sean Paul wrote:

On Thu, Mar 08, 2018 at 05:08:03PM -0800, Jeykumar Sankaran wrote:
> On 2018-03-02 06:56, Sean Paul wrote:
> > On Thu, Mar 01, 2018 at 07:37:10PM -0500, Rob Clark wrote:
> > > On Thu, Mar 1, 2018 at 3:37 PM,  <jsa...@codeaurora.org> wrote:
> > > > On 2018-03-01 07:27, Sean Paul wrote:
> > > >>
> > > >> On Wed, Feb 28, 2018 at 08:07:00PM -0800, jsa...@codeaurora.org
> > wrote:
> > > >>>
> > > >>> On 2018-02-28 11:19, Sean Paul wrote:
> > > >>> > Moving further towards switching fully to the the atomic

helpers,

> > this
> > > >>> > patch removes the hand-rolled kthread nonblock commit code

and

> > uses
> > > >>
> > > >> the
> > > >>>
> > > >>> > atomic helpers commit_work model.
> > > >>> >
> > > >>> > There's still a lot of copypasta here, but it's still needed

to

> > > >>> > facilitate the swap_state and prepare_fence private

functions.

> > These
> > > >>> > will be sorted out in a follow-on patch.
> > > >>> >
> > > >>> > Change-Id: I9fcba27824ba63d3fab96cb2bc194bfa6f3475b7
> > > >>> > Signed-off-by: Sean Paul <seanp...@chromium.org>
> > > >>> > ---





> > > >>
> > > >>> > - /* only return zero if

work

> > is
> > > >>> > -  * queued

successfully.

> > > >>> > -  */
> > > >>> > - ret = 0;
> > > >>> > - } else {
> > > >>> > - DRM_ERROR(" Error for
> > crtc_id:
> > > >>> > %d\n",
> > > >>> > -
> > > >>> > priv->disp_thread[j].crtc_id);
> > > >>> > - }
> > > >>> > -     break;
> > > >>> > - }
> > > >>> > - }
>
> Care to remove priv->disp_thread and all its references as a part of

this

> change?

Definitely! Will revise.



Now that I look at it, disp_thread doesn't seem relevant to this 
change.

It
seems like it's used for deferred cleanup. So perhaps we could get rid 
of

it,
but IMO that would be a different patch.


Sean

hmm.. disp_threads are created per CRTC (per display) to allow 
concurrency of
hardware programming. So its not entirely irrelevant to this chnage. But 
since
it involves more than just priv->disp_thread cleanup, I am fine with 
cleaning

that in a separate patch.

Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>


>
> - Jeykumar S





--
Jeykumar S
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [Freedreno] [DPU PATCH v2] drm/msm: Use atomic private_obj instead of subclassing

[Jeykumar Sankaran]

On 2018-03-19 10:31, Sean Paul wrote:

Instead of subclassing atomic state, store driver private data in
private_obj/state. This allows us to remove the swap_state driver hook
for mdp5 and get closer to using the atomic helpers entirely.

Changes in v2:
 - Use state->state in disp duplicate_state callback (Jeykumar)

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>

With the below comment updated

Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>


---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 37 ++
 drivers/gpu/drm/msm/msm_atomic.c | 30 ---
 drivers/gpu/drm/msm/msm_drv.c| 65 ++--
 drivers/gpu/drm/msm/msm_drv.h|  4 +-
 drivers/gpu/drm/msm/msm_kms.h| 28 +-
 5 files changed, 95 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 6d8e3a9a6fc0..f1a248419655 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -74,36 +74,32 @@ struct mdp5_state *mdp5_get_state(struct
drm_atomic_state *s)
 {
struct msm_drm_private *priv = s->dev->dev_private;
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
-   struct msm_kms_state *state = to_kms_state(s);
-   struct mdp5_state *new_state;
+   struct msm_kms_state *kms_state;
int ret;

-   if (state->state)
-   return state->state;
-
ret = drm_modeset_lock(_kms->state_lock, s->acquire_ctx);
if (ret)
return ERR_PTR(ret);

-   new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
-   if (!new_state)
-   return ERR_PTR(-ENOMEM);
+   kms_state = msm_kms_get_state(s);
+   if (IS_ERR_OR_NULL(kms_state))
+   return (struct mdp5_state *)kms_state; /* casting ERR_PTR
*/

-   /* Copy state: */
-   new_state->hwpipe = mdp5_kms->state->hwpipe;
-   new_state->hwmixer = mdp5_kms->state->hwmixer;
-   if (mdp5_kms->smp)
-   new_state->smp = mdp5_kms->state->smp;
+   return kms_state->state;
+}

-   state->state = new_state;
+static void *mdp5_duplicate_state(void *state)
+{
+   if (!state)
+   return kzalloc(sizeof(struct mdp5_state), GFP_KERNEL);

-   return new_state;
+   return kmemdup(state, sizeof(struct mdp5_state), GFP_KERNEL);
 }

-static void mdp5_swap_state(struct msm_kms *kms, struct 
drm_atomic_state

*state)
+static void mdp5_destroy_state(void *state)
 {
-   struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
-   swap(to_kms_state(state)->state, mdp5_kms->state);
+   struct mdp5_state *mdp_state = state;
+   kfree(mdp_state);
 }

 static void mdp5_prepare_commit(struct msm_kms *kms, struct
drm_atomic_state *state)
@@ -229,7 +225,8 @@ static const struct mdp_kms_funcs kms_funcs = {
.irq = mdp5_irq,
.enable_vblank   = mdp5_enable_vblank,
.disable_vblank  = mdp5_disable_vblank,
-   .swap_state  = mdp5_swap_state,
+   .duplicate_state = mdp5_duplicate_state,
+   .destroy_state   = mdp5_destroy_state,
.prepare_commit  = mdp5_prepare_commit,
.complete_commit = mdp5_complete_commit,
.wait_for_crtc_commit_done =
mdp5_wait_for_crtc_commit_done,
@@ -726,8 +723,6 @@ static void mdp5_destroy(struct platform_device 
*pdev)


if (mdp5_kms->rpm_enabled)
pm_runtime_disable(>dev);
-
-   kfree(mdp5_kms->state);
 }

 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
diff --git a/drivers/gpu/drm/msm/msm_atomic.c
b/drivers/gpu/drm/msm/msm_atomic.c
index 7e54eb65d096..1f53262ea46b 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -169,9 +169,6 @@ int msm_atomic_commit(struct drm_device *dev,
 */
BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);

-   if (to_kms_state(state)->state)
-   priv->kms->funcs->swap_state(priv->kms, state);
-
/*
 * Provide the driver a chance to prepare for output fences. This
is
 * done after the point of no return, but before asynchronous
commits
@@ -210,30 +207,3 @@ int msm_atomic_commit(struct drm_device *dev,
drm_atomic_helper_cleanup_planes(dev, state);
return ret;
 }
-
-struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device 
*dev)

-{
-   struct msm_kms_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
-
-   if (!state || drm_atomic_state_init(dev, >base) < 0) {
-   kfree(state);
-   return NULL;
-   }
-
-   return >base;
-}
-
-void msm_atomic_state_clear(struct drm_atomic_state *s)
-{
-

Re: [Freedreno] [DPU PATCH v2] drm/msm: Don't duplicate modeset_enables atomic helper

[Jeykumar Sankaran]

On 2018-03-16 12:45, Sean Paul wrote:
Instead, shuffle things around so we kickoff crtc after enabling 
encoder

during modesets. Also moves the vblank wait to after the frame.

Changes in v2:
- Remove the encoder.commit hack, it's not required (Jeykumar)

Cc: Jeykumar Sankaran <jsa...@codeaurora.org>
Signed-off-by: Sean Paul <seanp...@chromium.org>


Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>


---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c |   9 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c  |   8 +-
 drivers/gpu/drm/msm/msm_atomic.c | 132 ++-
 3 files changed, 19 insertions(+), 130 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index a3ab6ed2bf1d..94fab2dcca5b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -3525,6 +3525,12 @@ static void dpu_crtc_enable(struct drm_crtc 
*crtc,

DPU_EVT32_VERBOSE(DRMID(crtc));
dpu_crtc = to_dpu_crtc(crtc);

+   if (msm_is_mode_seamless(>state->adjusted_mode) ||
+   msm_is_mode_seamless_vrr(>state->adjusted_mode)) {
+   DPU_DEBUG("Skipping crtc enable, seamless mode\n");
+   return;
+   }
+
pm_runtime_get_sync(crtc->dev->dev);

drm_for_each_encoder(encoder, crtc->dev) {
@@ -3572,6 +3578,9 @@ static void dpu_crtc_enable(struct drm_crtc 
*crtc,

DPU_POWER_EVENT_POST_ENABLE | DPU_POWER_EVENT_POST_DISABLE
|
DPU_POWER_EVENT_PRE_DISABLE,
dpu_crtc_handle_power_event, crtc, dpu_crtc->name);
+
+   if (msm_needs_vblank_pre_modeset(>state->adjusted_mode))
+   drm_crtc_wait_one_vblank(crtc);
 }

 struct plane_state {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 5ba345395b82..2c4c7fe1affe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -422,14 +422,14 @@ static void dpu_kms_prepare_commit(struct msm_kms
*kms,
dpu_encoder_prepare_commit(encoder);
 }

-static void dpu_kms_commit(struct msm_kms *kms,
-   struct drm_atomic_state *old_state)
+static void dpu_kms_commit(struct msm_kms *kms, struct 
drm_atomic_state

*state)
 {
struct drm_crtc *crtc;
-   struct drm_crtc_state *old_crtc_state;
+   struct drm_crtc_state *crtc_state;
+   struct dpu_crtc_state *cstate;
int i;

-   for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
+   for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
if (crtc->state->active) {
DPU_EVT32(DRMID(crtc));
dpu_crtc_commit_kickoff(crtc);
diff --git a/drivers/gpu/drm/msm/msm_atomic.c
b/drivers/gpu/drm/msm/msm_atomic.c
index 5cfb80345052..f5794dce25dd 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -84,131 +84,6 @@ static void msm_atomic_wait_for_commit_done(
}
 }

-/**
- * msm_atomic_helper_commit_modeset_enables - modeset commit to enable
outputs
- * @dev: DRM device
- * @old_state: atomic state object with old state structures
- *
- * This function enables all the outputs with the new configuration 
which

had to
- * be turned off for the update.
- *
- * For compatibility with legacy crtc helpers this should be called 
after

- * drm_atomic_helper_commit_planes(), which is what the default commit
function
- * does. But drivers with different needs can group the modeset 
commits

together
- * and do the plane commits at the end. This is useful for drivers 
doing

runtime
- * PM since planes updates then only happen when the CRTC is actually
enabled.
- */
-static void msm_atomic_helper_commit_modeset_enables(struct drm_device
*dev,
-   struct drm_atomic_state *old_state)
-{
-   struct drm_crtc *crtc;
-   struct drm_crtc_state *old_crtc_state;
-   struct drm_crtc_state *new_crtc_state;
-   struct drm_connector *connector;
-   struct drm_connector_state *new_conn_state;
-   struct msm_drm_private *priv = dev->dev_private;
-   struct msm_kms *kms = priv->kms;
-   int bridge_enable_count = 0;
-   int i;
-
-   for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state,
-   new_crtc_state, i) {
-   const struct drm_crtc_helper_funcs *funcs;
-
-   /* Need to filter out CRTCs where only planes change. */
-   if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
-   continue;
-
-   if (!new_crtc_state->active)
-   continue;
-
-   if (msm_is_mode_seamless(_crtc_state->mode) ||
-   msm_is_mode_seamless_vrr(
-   _crtc_state->adjusted_mode))
-   continue;
-

Re: [Freedreno] [DPU PATCH 02/11] drm/msm: Don't duplicate modeset_enables atomic helper

[Jeykumar Sankaran]

On 2018-03-14 08:14, Sean Paul wrote:

On Tue, Mar 13, 2018 at 04:57:35PM -0700, Jeykumar Sankaran wrote:

On 2018-03-12 13:21, Sean Paul wrote:
> On Thu, Mar 08, 2018 at 04:56:01PM -0800, Jeykumar Sankaran wrote:
> > On 2018-02-28 11:18, Sean Paul wrote:
> > > Instead, shuffle things around so we kickoff crtc after enabling
> encoder
> > > during modesets. Also moves the vblank wait to after the frame.
> > >
> > > Change-Id: I16c7b7f9390d04f6050aa20e17a5335fbf49eba3
> > > Signed-off-by: Sean Paul <seanp...@chromium.org>
> > > ---
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|   9 ++
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |   5 +-
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  31 -
> > >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h |   2 +
> > >  drivers/gpu/drm/msm/msm_atomic.c| 132
> +---
> > >  5 files changed, 48 insertions(+), 131 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > index a3ab6ed2bf1d..94fab2dcca5b 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> > > @@ -3525,6 +3525,12 @@ static void dpu_crtc_enable(struct drm_crtc
> > > *crtc,
> > >  DPU_EVT32_VERBOSE(DRMID(crtc));
> > >  dpu_crtc = to_dpu_crtc(crtc);
> > >
> > > +if (msm_is_mode_seamless(>state->adjusted_mode) ||
> > > +msm_is_mode_seamless_vrr(>state->adjusted_mode))

{

> > > +DPU_DEBUG("Skipping crtc enable, seamless

mode\n");

> > > +return;
> > > +}
> > > +
> > >  pm_runtime_get_sync(crtc->dev->dev);
> > >
> > >  drm_for_each_encoder(encoder, crtc->dev) {
> > > @@ -3572,6 +3578,9 @@ static void dpu_crtc_enable(struct drm_crtc
> *crtc,
> > >  DPU_POWER_EVENT_POST_ENABLE |

DPU_POWER_EVENT_POST_DISABLE

> > > |
> > >  DPU_POWER_EVENT_PRE_DISABLE,
> > >  dpu_crtc_handle_power_event, crtc,

dpu_crtc->name);

> > > +
> > > +if

(msm_needs_vblank_pre_modeset(>state->adjusted_mode))

> > > +drm_crtc_wait_one_vblank(crtc);
> > >  }
> > >
> > >  struct plane_state {
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > index 28ceb589ee40..4d1e3652dbf4 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > @@ -3693,8 +3693,11 @@ static void
> dpu_encoder_frame_done_timeout(struct
> > > timer_list *t)
> > >  static const struct drm_encoder_helper_funcs

dpu_encoder_helper_funcs

> =
> > > {
> > >  .mode_set = dpu_encoder_virt_mode_set,
> > >  .disable = dpu_encoder_virt_disable,
> > > -.enable = dpu_encoder_virt_enable,
> > > +.enable = dpu_kms_encoder_enable,
> > >  .atomic_check = dpu_encoder_virt_atomic_check,
> > > +
> > > +/* This is called by dpu_kms_encoder_enable */
> > > +.commit = dpu_encoder_virt_enable,
> > >  };
> > >
> > >  static const struct drm_encoder_funcs dpu_encoder_funcs = {
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > > index 81fd3a429e9f..3d83037e8305 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > > @@ -425,14 +425,37 @@ static void dpu_kms_prepare_commit(struct
> msm_kms
> > > *kms,
> > >  dpu_encoder_prepare_commit(encoder);
> > >  }
> > >
> > > -static void dpu_kms_commit(struct msm_kms *kms,
> > > -struct drm_atomic_state *old_state)
> > > +/*
> > > + * Override the encoder enable since we need to setup the inline
> > > rotator
> > > and do
> > > + * some crtc magic before enabling any bridge that might be

present.

> > > + */
> > > +void dpu_kms_encoder_enable(struct drm_encoder *encoder)
> > > +{
> > > +const struct drm_encoder_helper_funcs *funcs =
> > > encoder->helper_private;
> > > +struct drm_crtc *crtc = encoder->

Re: [Freedreno] [DPU PATCH 02/11] drm/msm: Don't duplicate modeset_enables atomic helper

[Jeykumar Sankaran]

On 2018-03-12 13:21, Sean Paul wrote:

On Thu, Mar 08, 2018 at 04:56:01PM -0800, Jeykumar Sankaran wrote:

On 2018-02-28 11:18, Sean Paul wrote:
> Instead, shuffle things around so we kickoff crtc after enabling

encoder

> during modesets. Also moves the vblank wait to after the frame.
>
> Change-Id: I16c7b7f9390d04f6050aa20e17a5335fbf49eba3
> Signed-off-by: Sean Paul <seanp...@chromium.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|   9 ++
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |   5 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  31 -
>  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h |   2 +
>  drivers/gpu/drm/msm/msm_atomic.c| 132

+---

>  5 files changed, 48 insertions(+), 131 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index a3ab6ed2bf1d..94fab2dcca5b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -3525,6 +3525,12 @@ static void dpu_crtc_enable(struct drm_crtc
> *crtc,
>DPU_EVT32_VERBOSE(DRMID(crtc));
>dpu_crtc = to_dpu_crtc(crtc);
>
> +  if (msm_is_mode_seamless(>state->adjusted_mode) ||
> +  msm_is_mode_seamless_vrr(>state->adjusted_mode)) {
> +  DPU_DEBUG("Skipping crtc enable, seamless mode\n");
> +  return;
> +  }
> +
>pm_runtime_get_sync(crtc->dev->dev);
>
>drm_for_each_encoder(encoder, crtc->dev) {
> @@ -3572,6 +3578,9 @@ static void dpu_crtc_enable(struct drm_crtc

*crtc,

>DPU_POWER_EVENT_POST_ENABLE | DPU_POWER_EVENT_POST_DISABLE
> |
>DPU_POWER_EVENT_PRE_DISABLE,
>dpu_crtc_handle_power_event, crtc, dpu_crtc->name);
> +
> +  if (msm_needs_vblank_pre_modeset(>state->adjusted_mode))
> +  drm_crtc_wait_one_vblank(crtc);
>  }
>
>  struct plane_state {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 28ceb589ee40..4d1e3652dbf4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -3693,8 +3693,11 @@ static void

dpu_encoder_frame_done_timeout(struct

> timer_list *t)
>  static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs

=

> {
>.mode_set = dpu_encoder_virt_mode_set,
>.disable = dpu_encoder_virt_disable,
> -  .enable = dpu_encoder_virt_enable,
> +  .enable = dpu_kms_encoder_enable,
>.atomic_check = dpu_encoder_virt_atomic_check,
> +
> +  /* This is called by dpu_kms_encoder_enable */
> +  .commit = dpu_encoder_virt_enable,
>  };
>
>  static const struct drm_encoder_funcs dpu_encoder_funcs = {
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 81fd3a429e9f..3d83037e8305 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -425,14 +425,37 @@ static void dpu_kms_prepare_commit(struct

msm_kms

> *kms,
>dpu_encoder_prepare_commit(encoder);
>  }
>
> -static void dpu_kms_commit(struct msm_kms *kms,
> -  struct drm_atomic_state *old_state)
> +/*
> + * Override the encoder enable since we need to setup the inline
> rotator
> and do
> + * some crtc magic before enabling any bridge that might be present.
> + */
> +void dpu_kms_encoder_enable(struct drm_encoder *encoder)
> +{
> +  const struct drm_encoder_helper_funcs *funcs =
> encoder->helper_private;
> +  struct drm_crtc *crtc = encoder->crtc;
> +
> +  /* Forward this enable call to the commit hook */
> +  if (funcs && funcs->commit)
> +  funcs->commit(encoder);

The purpose of this function is not clear. Where are we setting up the
inline rotator?
Why do we need a kickoff here?


The reason the code is shuffled is to avoid duplicating the entire 
atomic

helper
function. By moving calls into the ->enable hooks, we can avoid having 
to

hand
roll the helpers.

The kickoff is preserved from the helper copy when you call
kms->funcs->commit
in between the encoder enable and bridge enable. If this can be 
removed,

that'd
be even better. I was simply trying to preserve the call order of
everything.

Sean
I am with you on cleaning up the atomic helper copy. But using 
enc->commit helper

to call into encoder_enable doesn't look valid to me.

Also, I verified removing the kms->funcs->commit call between encoder 
enable and
bridge enable. It works fine with your newly placed kms->funcs->commit 
after
drm_atomic_helper_commit_modeset_enables. So can you revisit this 
function?


Jeykumar S



> +
> +  if (crtc &&a

Re: [Freedreno] [DPU PATCH 01/11] drm/msm: Skip seamless disables in crtc/encoder

[Jeykumar Sankaran]

On 2018-03-12 13:14, Sean Paul wrote:

On Fri, Mar 02, 2018 at 04:04:24PM -0800, jsa...@codeaurora.org wrote:

On 2018-02-28 11:18, Sean Paul wrote:
> Instead of duplicating whole swaths of atomic helper functions (which
> are already out-of-date), just skip the encoder/crtc disables in the
> .disable hooks.
>
> Change-Id: I7bd9183ae60624204fb1de9550656b776efc7202
> Signed-off-by: Sean Paul <seanp...@chromium.org>


Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>



Can you consider getting rid of these checks?


Do you mean the Change-Id? Yeah, I forgot to strip them out before
sending, I'll
make sure I clean it up before I apply.

Actually, I meant removing the seamless check flags that you are moving 
to

encode/crtc. But you can ignore that, I am planning to submit a seperate
change to remove the support from the whole pipeline.


> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|   8 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |   8 +
>  drivers/gpu/drm/msm/msm_atomic.c| 185

+---

>  3 files changed, 17 insertions(+), 184 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 3cdf1e3d9d96..a3ab6ed2bf1d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -3393,6 +3393,7 @@ static void dpu_crtc_disable(struct drm_crtc
> *crtc)
>  {
>struct dpu_crtc *dpu_crtc;
>struct dpu_crtc_state *cstate;
> +  struct drm_display_mode *mode;
>struct drm_encoder *encoder;
>struct msm_drm_private *priv;
>unsigned long flags;
> @@ -3407,8 +3408,15 @@ static void dpu_crtc_disable(struct drm_crtc
> *crtc)
>}
>dpu_crtc = to_dpu_crtc(crtc);
>cstate = to_dpu_crtc_state(crtc->state);
> +  mode = >base.adjusted_mode;
>priv = crtc->dev->dev_private;
>
> +  if (msm_is_mode_seamless(mode) || msm_is_mode_seamless_vrr(mode)
> ||
> +  msm_is_mode_seamless_dms(mode)) {
> +  DPU_DEBUG("Seamless mode is being applied, skip
> disable\n");
> +  return;
> +  }
> +
Another topic of discussion which should be brought up with dri-devel.

May not be common in PC world, but there are a handful of mobile OEM's
using panels which supports more than one resolution. Primary use 
cases

involve "seamless" switching to optimized display resolution when
streaming content changes resolutions or rendering lossless data.


Yeah, I think we can do this under the covers if the hardware supports 
it

such
as this patch. We could probably do a better job of making this useful 
for

other
drivers, but I was really just trying to get the seamless stuff out of 
the

way
so we don't need to roll our own atomic commit.

Sean



Jeykumar S.

>DPU_DEBUG("crtc%d\n", crtc->base.id);
>
>if (dpu_kms_is_suspend_state(crtc->dev))
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 3d168fa09f3f..28ceb589ee40 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -2183,6 +2183,7 @@ static void dpu_encoder_virt_disable(struct
> drm_encoder *drm_enc)
>struct dpu_encoder_virt *dpu_enc = NULL;
>struct msm_drm_private *priv;
>struct dpu_kms *dpu_kms;
> +  struct drm_display_mode *mode;
>int i = 0;
>
>if (!drm_enc) {
> @@ -2196,6 +2197,13 @@ static void dpu_encoder_virt_disable(struct
> drm_encoder *drm_enc)
>return;
>}
>
> +  mode = _enc->crtc->state->adjusted_mode;
> +  if (msm_is_mode_seamless(mode) || msm_is_mode_seamless_vrr(mode)
> ||
> +  msm_is_mode_seamless_dms(mode)) {
> +  DPU_DEBUG("Seamless mode is being applied, skip
> disable\n");
> +  return;
> +  }
> +
>dpu_enc = to_dpu_encoder_virt(drm_enc);
>DPU_DEBUG_ENC(dpu_enc, "\n");
>
> diff --git a/drivers/gpu/drm/msm/msm_atomic.c
> b/drivers/gpu/drm/msm/msm_atomic.c
> index 46536edb72ee..5cfb80345052 100644
> --- a/drivers/gpu/drm/msm/msm_atomic.c
> +++ b/drivers/gpu/drm/msm/msm_atomic.c
> @@ -84,189 +84,6 @@ static void msm_atomic_wait_for_commit_done(
>}
>  }
>
> -static void
> -msm_disable_outputs(struct drm_device *dev, struct drm_atomic_state
> *old_state)
> -{
> -  struct drm_connector *connector;
> -  struct drm_connector_state *old_conn_state, *new_conn_state;
> -  struct drm_crtc *crtc;
> -  struct drm_crtc_state *old_crtc_state, *new_crtc_state;
> -  int i;
> -
> -  for_each_oldnew_connector_in_state(old_state, connector,
> old_conn_state, new_conn_state, i) {
> -  const struct drm_encoder_helper_funcs *fu

Re: [Freedreno] [DPU PATCH 07/11] drm/msm: Use atomic private_obj instead of subclassing

[Jeykumar Sankaran]

On 2018-02-28 11:19, Sean Paul wrote:

Instead of subclassing atomic state, store driver private data in
private_obj/state. This allows us to remove the swap_state driver hook
for mdp5 and get closer to using the atomic helpers entirely.

Change-Id: I65a4a2887593ae257d584e00b352b5daf00e4e61
Signed-off-by: Sean Paul 
---
 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 37 ++
 drivers/gpu/drm/msm/msm_atomic.c | 30 ---
 drivers/gpu/drm/msm/msm_drv.c| 65 ++--
 drivers/gpu/drm/msm/msm_drv.h|  4 +-
 drivers/gpu/drm/msm/msm_kms.h| 28 +-
 5 files changed, 95 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 6d8e3a9a6fc0..f1a248419655 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -74,36 +74,32 @@ struct mdp5_state *mdp5_get_state(struct
drm_atomic_state *s)
 {
struct msm_drm_private *priv = s->dev->dev_private;
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
-   struct msm_kms_state *state = to_kms_state(s);
-   struct mdp5_state *new_state;
+   struct msm_kms_state *kms_state;
int ret;

-   if (state->state)
-   return state->state;
-
ret = drm_modeset_lock(_kms->state_lock, s->acquire_ctx);
if (ret)
return ERR_PTR(ret);

-   new_state = kmalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
-   if (!new_state)
-   return ERR_PTR(-ENOMEM);
+   kms_state = msm_kms_get_state(s);
+   if (IS_ERR_OR_NULL(kms_state))
+   return (struct mdp5_state *)kms_state; /* casting ERR_PTR
*/

-   /* Copy state: */
-   new_state->hwpipe = mdp5_kms->state->hwpipe;
-   new_state->hwmixer = mdp5_kms->state->hwmixer;
-   if (mdp5_kms->smp)
-   new_state->smp = mdp5_kms->state->smp;
+   return kms_state->state;
+}

-   state->state = new_state;
+static void *mdp5_duplicate_state(void *state)
+{
+   if (!state)
+   return kzalloc(sizeof(struct mdp5_state), GFP_KERNEL);

-   return new_state;
+   return kmemdup(state, sizeof(struct mdp5_state), GFP_KERNEL);
 }

-static void mdp5_swap_state(struct msm_kms *kms, struct 
drm_atomic_state

*state)
+static void mdp5_destroy_state(void *state)
 {
-   struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
-   swap(to_kms_state(state)->state, mdp5_kms->state);
+   struct mdp5_state *mdp_state = state;
+   kfree(mdp_state);
 }

 static void mdp5_prepare_commit(struct msm_kms *kms, struct
drm_atomic_state *state)
@@ -229,7 +225,8 @@ static const struct mdp_kms_funcs kms_funcs = {
.irq = mdp5_irq,
.enable_vblank   = mdp5_enable_vblank,
.disable_vblank  = mdp5_disable_vblank,
-   .swap_state  = mdp5_swap_state,
+   .duplicate_state = mdp5_duplicate_state,
+   .destroy_state   = mdp5_destroy_state,
.prepare_commit  = mdp5_prepare_commit,
.complete_commit = mdp5_complete_commit,
.wait_for_crtc_commit_done =
mdp5_wait_for_crtc_commit_done,
@@ -726,8 +723,6 @@ static void mdp5_destroy(struct platform_device 
*pdev)


if (mdp5_kms->rpm_enabled)
pm_runtime_disable(>dev);
-
-   kfree(mdp5_kms->state);
 }

 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt,
diff --git a/drivers/gpu/drm/msm/msm_atomic.c
b/drivers/gpu/drm/msm/msm_atomic.c
index 7e54eb65d096..1f53262ea46b 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -169,9 +169,6 @@ int msm_atomic_commit(struct drm_device *dev,
 */
BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);

-   if (to_kms_state(state)->state)
-   priv->kms->funcs->swap_state(priv->kms, state);
-
/*
 * Provide the driver a chance to prepare for output fences. This
is
 * done after the point of no return, but before asynchronous
commits
@@ -210,30 +207,3 @@ int msm_atomic_commit(struct drm_device *dev,
drm_atomic_helper_cleanup_planes(dev, state);
return ret;
 }
-
-struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device 
*dev)

-{
-   struct msm_kms_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
-
-   if (!state || drm_atomic_state_init(dev, >base) < 0) {
-   kfree(state);
-   return NULL;
-   }
-
-   return >base;
-}
-
-void msm_atomic_state_clear(struct drm_atomic_state *s)
-{
-   struct msm_kms_state *state = to_kms_state(s);
-   drm_atomic_state_default_clear(>base);
-   kfree(state->state);
-   state->state = NULL;
-}
-
-void msm_atomic_state_free(struct drm_atomic_state *state)
-{
-   kfree(to_kms_state(state)->state);
-   

Re: [Freedreno] [DPU PATCH 06/11] drm/msm: Remove msm_commit/kthread, use atomic helper commit

[Jeykumar Sankaran]

On 2018-03-02 06:56, Sean Paul wrote:

On Thu, Mar 01, 2018 at 07:37:10PM -0500, Rob Clark wrote:

On Thu, Mar 1, 2018 at 3:37 PM,   wrote:
> On 2018-03-01 07:27, Sean Paul wrote:
>>
>> On Wed, Feb 28, 2018 at 08:07:00PM -0800, jsa...@codeaurora.org

wrote:

>>>
>>> On 2018-02-28 11:19, Sean Paul wrote:
>>> > Moving further towards switching fully to the the atomic helpers,

this

>>> > patch removes the hand-rolled kthread nonblock commit code and

uses

>>
>> the
>>>
>>> > atomic helpers commit_work model.
>>> >
>>> > There's still a lot of copypasta here, but it's still needed to
>>> > facilitate the swap_state and prepare_fence private functions.

These

>>> > will be sorted out in a follow-on patch.
>>> >
>>> > Change-Id: I9fcba27824ba63d3fab96cb2bc194bfa6f3475b7
>>> > Signed-off-by: Sean Paul 
>>> > ---
>>> >  drivers/gpu/drm/msm/msm_atomic.c | 199
>>
>> ++-
>>>
>>> >  drivers/gpu/drm/msm/msm_drv.c|   1 -
>>> >  drivers/gpu/drm/msm/msm_drv.h|   4 -
>>> >  3 files changed, 35 insertions(+), 169 deletions(-)
>>> >
>>> > diff --git a/drivers/gpu/drm/msm/msm_atomic.c
>>> > b/drivers/gpu/drm/msm/msm_atomic.c
>>> > index 3a18bd3dc215..7e54eb65d096 100644
>>> > --- a/drivers/gpu/drm/msm/msm_atomic.c
>>> > +++ b/drivers/gpu/drm/msm/msm_atomic.c
>>> > @@ -21,51 +21,6 @@
>>> >  #include "msm_gem.h"
>>> >  #include "msm_fence.h"
>>> >
>>> > -struct msm_commit {
>>> > - struct drm_device *dev;
>>> > - struct drm_atomic_state *state;
>>> > - uint32_t crtc_mask;
>>> > - bool nonblock;
>>> > - struct kthread_work commit_work;
>>> > -};
>>> > -
>>> > -/* block until specified crtcs are no longer pending update, and
>>> > - * atomically mark them as pending update
>>> > - */
>>> > -static int start_atomic(struct msm_drm_private *priv, uint32_t
>>> > crtc_mask)
>>> > -{
>>> > - int ret;
>>> > -
>>> > - spin_lock(>pending_crtcs_event.lock);
>>> > - ret =

wait_event_interruptible_locked(priv->pending_crtcs_event,

>>> > - !(priv->pending_crtcs & crtc_mask));
>>> > - if (ret == 0) {
>>> > - DBG("start: %08x", crtc_mask);
>>> > - priv->pending_crtcs |= crtc_mask;
>>> > - }
>>> > - spin_unlock(>pending_crtcs_event.lock);
>>> > -
>>> > - return ret;
>>> > -}
>>> > -
>>> > -/* clear specified crtcs (no longer pending update)
>>> > - */
>>> > -static void end_atomic(struct msm_drm_private *priv, uint32_t
>>> > crtc_mask)
>>> > -{
>>> > - spin_lock(>pending_crtcs_event.lock);
>>> > - DBG("end: %08x", crtc_mask);
>>> > - priv->pending_crtcs &= ~crtc_mask;
>>> > - wake_up_all_locked(>pending_crtcs_event);
>>> > - spin_unlock(>pending_crtcs_event.lock);
>>> > -}
>>> > -
>>> > -static void commit_destroy(struct msm_commit *c)
>>> > -{
>>> > - end_atomic(c->dev->dev_private, c->crtc_mask);
>>> > - if (c->nonblock)
>>> > - kfree(c);
>>> > -}
>>> > -
>>> >  static void msm_atomic_wait_for_commit_done(
>>> >   struct drm_device *dev,
>>> >   struct drm_atomic_state *old_state)
>>> > @@ -118,6 +73,10 @@ static void msm_atomic_commit_tail(struct
>>> > drm_atomic_state *state)
>>> >
>>> >   msm_atomic_wait_for_commit_done(dev, state);
>>> >
>>> > + drm_atomic_helper_commit_hw_done(state);
>>> > +
>>> > + drm_atomic_helper_wait_for_vblanks(dev, state);
>>> > +
>>> >   drm_atomic_helper_cleanup_planes(dev, state);
>>> >
>>> >   kms->funcs->complete_commit(kms, state);
>>> > @@ -126,109 +85,25 @@ static void msm_atomic_commit_tail(struct
>>> > drm_atomic_state *state)
>>> >  /* The (potentially) asynchronous part of the commit.  At this

point

>>> >   * nothing can fail short of armageddon.
>>> >   */
>>> > -static void complete_commit(struct msm_commit *c)
>>> > +static void commit_tail(struct drm_atomic_state *state)
>>> >  {
>>> > - struct drm_atomic_state *state = c->state;
>>> > - struct drm_device *dev = state->dev;
>>> > + drm_atomic_helper_wait_for_fences(state->dev, state, false);
>>> >
>>> > - drm_atomic_helper_wait_for_fences(dev, state, false);
>>> > + drm_atomic_helper_wait_for_dependencies(state);
>>> >
>>> >   msm_atomic_commit_tail(state);
>>> >
>>> > - drm_atomic_state_put(state);
>>> > -}
>>> > -
>>> > -static void _msm_drm_commit_work_cb(struct kthread_work *work)
>>> > -{
>>> > - struct msm_commit *commit =  NULL;
>>> > -
>>> > - if (!work) {
>>> > - DRM_ERROR("%s: Invalid commit work data!\n",

__func__);

>>> > - return;
>>> > - }
>>> > -
>>> > - commit = container_of(work, struct msm_commit, commit_work);
>>> > -
>>> > - complete_commit(commit);
>>> > -
>>> > - commit_destroy(commit);
>>> > -}
>>> > -
>>> > -static struct msm_commit *commit_init(struct drm_atomic_state

*state,

>>> > - bool nonblock)
>>> > -{
>>> > - struct msm_commit *c = kzalloc(sizeof(*c), 

Re: [Freedreno] [DPU PATCH 03/11] drm/msm: Refactor complete_commit() to look more the helpers

[Jeykumar Sankaran]

On 2018-02-28 11:18, Sean Paul wrote:

Factor out the commit_tail() portions of complete_commit() into a
separate function to facilitate moving to the atomic helpers in future
patches.

Change-Id: I4b858ad9fe356b31ed0ed9eecdb394a61048e39c
Signed-off-by: Sean Paul <seanp...@chromium.org>


Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>


---
 drivers/gpu/drm/msm/msm_atomic.c | 25 -
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_atomic.c
b/drivers/gpu/drm/msm/msm_atomic.c
index f5794dce25dd..eb2ccda5da0f 100644
--- a/drivers/gpu/drm/msm/msm_atomic.c
+++ b/drivers/gpu/drm/msm/msm_atomic.c
@@ -84,18 +84,12 @@ static void msm_atomic_wait_for_commit_done(
}
 }

-/* The (potentially) asynchronous part of the commit.  At this point
- * nothing can fail short of armageddon.
- */
-static void complete_commit(struct msm_commit *c)
+static void msm_atomic_commit_tail(struct drm_atomic_state *state)
 {
-   struct drm_atomic_state *state = c->state;
struct drm_device *dev = state->dev;
struct msm_drm_private *priv = dev->dev_private;
struct msm_kms *kms = priv->kms;

-   drm_atomic_helper_wait_for_fences(dev, state, false);
-
kms->funcs->prepare_commit(kms, state);

drm_atomic_helper_commit_modeset_disables(dev, state);
@@ -127,10 +121,21 @@ static void complete_commit(struct msm_commit *c)
drm_atomic_helper_cleanup_planes(dev, state);

kms->funcs->complete_commit(kms, state);
+}

-   drm_atomic_state_put(state);
+/* The (potentially) asynchronous part of the commit.  At this point
+ * nothing can fail short of armageddon.
+ */
+static void complete_commit(struct msm_commit *c)
+{
+   struct drm_atomic_state *state = c->state;
+   struct drm_device *dev = state->dev;

-   commit_destroy(c);
+   drm_atomic_helper_wait_for_fences(dev, state, false);
+
+   msm_atomic_commit_tail(state);
+
+   drm_atomic_state_put(state);
 }

 static void _msm_drm_commit_work_cb(struct kthread_work *work)
@@ -145,6 +150,8 @@ static void _msm_drm_commit_work_cb(struct
kthread_work *work)
commit = container_of(work, struct msm_commit, commit_work);

complete_commit(commit);
+
+   commit_destroy(commit);
 }

 static struct msm_commit *commit_init(struct drm_atomic_state *state,


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Re: [Freedreno] [DPU PATCH 02/11] drm/msm: Don't duplicate modeset_enables atomic helper

[Jeykumar Sankaran]

On 2018-02-28 11:18, Sean Paul wrote:
Instead, shuffle things around so we kickoff crtc after enabling 
encoder

during modesets. Also moves the vblank wait to after the frame.

Change-Id: I16c7b7f9390d04f6050aa20e17a5335fbf49eba3
Signed-off-by: Sean Paul 
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c|   9 ++
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c |   5 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c |  31 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h |   2 +
 drivers/gpu/drm/msm/msm_atomic.c| 132 +---
 5 files changed, 48 insertions(+), 131 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index a3ab6ed2bf1d..94fab2dcca5b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -3525,6 +3525,12 @@ static void dpu_crtc_enable(struct drm_crtc 
*crtc,

DPU_EVT32_VERBOSE(DRMID(crtc));
dpu_crtc = to_dpu_crtc(crtc);

+   if (msm_is_mode_seamless(>state->adjusted_mode) ||
+   msm_is_mode_seamless_vrr(>state->adjusted_mode)) {
+   DPU_DEBUG("Skipping crtc enable, seamless mode\n");
+   return;
+   }
+
pm_runtime_get_sync(crtc->dev->dev);

drm_for_each_encoder(encoder, crtc->dev) {
@@ -3572,6 +3578,9 @@ static void dpu_crtc_enable(struct drm_crtc 
*crtc,

DPU_POWER_EVENT_POST_ENABLE | DPU_POWER_EVENT_POST_DISABLE
|
DPU_POWER_EVENT_PRE_DISABLE,
dpu_crtc_handle_power_event, crtc, dpu_crtc->name);
+
+   if (msm_needs_vblank_pre_modeset(>state->adjusted_mode))
+   drm_crtc_wait_one_vblank(crtc);
 }

 struct plane_state {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 28ceb589ee40..4d1e3652dbf4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -3693,8 +3693,11 @@ static void 
dpu_encoder_frame_done_timeout(struct

timer_list *t)
 static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs 
= {

.mode_set = dpu_encoder_virt_mode_set,
.disable = dpu_encoder_virt_disable,
-   .enable = dpu_encoder_virt_enable,
+   .enable = dpu_kms_encoder_enable,
.atomic_check = dpu_encoder_virt_atomic_check,
+
+   /* This is called by dpu_kms_encoder_enable */
+   .commit = dpu_encoder_virt_enable,
 };

 static const struct drm_encoder_funcs dpu_encoder_funcs = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 81fd3a429e9f..3d83037e8305 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -425,14 +425,37 @@ static void dpu_kms_prepare_commit(struct msm_kms
*kms,
dpu_encoder_prepare_commit(encoder);
 }

-static void dpu_kms_commit(struct msm_kms *kms,
-   struct drm_atomic_state *old_state)
+/*
+ * Override the encoder enable since we need to setup the inline 
rotator

and do
+ * some crtc magic before enabling any bridge that might be present.
+ */
+void dpu_kms_encoder_enable(struct drm_encoder *encoder)
+{
+   const struct drm_encoder_helper_funcs *funcs =
encoder->helper_private;
+   struct drm_crtc *crtc = encoder->crtc;
+
+   /* Forward this enable call to the commit hook */
+   if (funcs && funcs->commit)
+   funcs->commit(encoder);


The purpose of this function is not clear. Where are we setting up the 
inline rotator?

Why do we need a kickoff here?

+
+   if (crtc && crtc->state->active) {
+   DPU_EVT32(DRMID(crtc));
+   dpu_crtc_commit_kickoff(crtc);
+   }
+}
+
+static void dpu_kms_commit(struct msm_kms *kms, struct 
drm_atomic_state

*state)
 {
struct drm_crtc *crtc;
-   struct drm_crtc_state *old_crtc_state;
+   struct drm_crtc_state *crtc_state;
+   struct dpu_crtc_state *cstate;
int i;

-   for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
+   for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
+   /* If modeset is required, kickoff is run in
encoder_enable */
+   if (drm_atomic_crtc_needs_modeset(crtc_state))
+   continue;
+
if (crtc->state->active) {
DPU_EVT32(DRMID(crtc));
dpu_crtc_commit_kickoff(crtc);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index 8cadd29a48b1..42c809ed9467 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -529,4 +529,6 @@ int dpu_kms_fbo_reference(struct dpu_kms_fbo *fbo);
  */
 void dpu_kms_fbo_unreference(struct dpu_kms_fbo *fbo);

+void dpu_kms_encoder_enable(struct drm_encoder *encoder);
+
 #endif /* __dpu_kms_H__ */
diff --git a/drivers/gpu/drm/msm/msm_atomic.c

Re: [Freedreno] [PATCH RESEND 10/10] drm/msm: Restore msm_atomic_check hook

[Jeykumar Sankaran]

On 2018-02-21 07:18, Sean Paul wrote:
Somehow this got lost, put it back. We might want to re-evaluate 
whether

this is actually necessary, but for now let's actually use the thing.

Signed-off-by: Sean Paul <seanp...@chromium.org>


Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>


---
 drivers/gpu/drm/msm/msm_drv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c 
b/drivers/gpu/drm/msm/msm_drv.c

index 30c56b873fbe..eda4a2340f93 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -119,7 +119,7 @@ int msm_atomic_check(struct drm_device *dev,
 static const struct drm_mode_config_funcs mode_config_funcs = {
.fb_create = msm_framebuffer_create,
.output_poll_changed = msm_fb_output_poll_changed,
-   .atomic_check = drm_atomic_helper_check,
+   .atomic_check = msm_atomic_check,
.atomic_commit = msm_atomic_commit,
.atomic_state_alloc = msm_atomic_state_alloc,
.atomic_state_clear = msm_atomic_state_clear,


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Re: [Freedreno] [PATCH RESEND 05/10] drm/msm: Defer probe if display component not found

[Jeykumar Sankaran]

On 2018-02-21 07:18, Sean Paul wrote:

The downstream driver relies on Makefile ordering of files to ensure
components probe in the right order. This took me entirely too long to
sort out, so don't rely on that any longer.

Signed-off-by: Sean Paul <seanp...@chromium.org>


Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>


---
 drivers/gpu/drm/msm/msm_drv.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_drv.c 
b/drivers/gpu/drm/msm/msm_drv.c

index 9532321a0e4f..30c56b873fbe 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1784,6 +1784,7 @@ static int add_display_components(struct device 
*dev,

if (of_device_is_compatible(dev->of_node, "qcom,dpu-kms")) {
struct device_node *np = dev->of_node;
unsigned int i;
+   bool found = false;

 #ifdef CONFIG_DRM_MSM_DSI_STAGING
for (i = 0; i < MAX_DSI_ACTIVE_DISPLAY; i++) {
@@ -1794,8 +1795,11 @@ static int add_display_components(struct device 
*dev,

component_match_add(dev, matchptr, compare_of,
node);
pr_debug("Added component = %s\n", name);
+   found = true;
}
}
+   if (!found)
+   return -EPROBE_DEFER;
 #endif

for (i = 0; ; i++) {


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Re: [Freedreno] [PATCH RESEND 04/10] drm/msm: Remove smmu driver init/cleanup from msm_drv

[Jeykumar Sankaran]

On 2018-02-21 07:18, Sean Paul wrote:

Leftover bits from the initial removal of smmu.

Signed-off-by: Sean Paul <seanp...@chromium.org>


Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>


---
 drivers/gpu/drm/msm/msm_drv.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c 
b/drivers/gpu/drm/msm/msm_drv.c

index 106678a164c2..9532321a0e4f 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1966,9 +1966,6 @@ static int __init msm_drm_register(void)

DBG("init");
msm_mdp_register();
-#ifdef CONFIG_DRM_MSM_DPU
-   msm_smmu_driver_init();
-#endif
msm_dsi_register();
msm_edp_register();
msm_hdmi_register();
@@ -1985,9 +1982,6 @@ static void __exit msm_drm_unregister(void)
msm_edp_unregister();
msm_dsi_unregister();
msm_mdp_unregister();
-#ifdef CONFIG_DRM_MSM_DPU
-   msm_smmu_driver_cleanup();
-#endif
 }

 module_init(msm_drm_register);


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Re: [Freedreno] [PATCH RESEND 02/10] drm/msm: Include the dpu_dbg header in msm_drv.c

[Jeykumar Sankaran]

On 2018-02-21 07:18, Sean Paul wrote:

We'll need to clean up these conditionals further, but at least fix the
compilation error.

Signed-off-by: Sean Paul <seanp...@chromium.org>


Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>


---
 drivers/gpu/drm/msm/msm_drv.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_drv.c 
b/drivers/gpu/drm/msm/msm_drv.c

index e1b7e468c3dc..6f2affe5ccff 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -53,6 +53,9 @@
 #ifdef CONFIG_DRM_MSM_DSI_STAGING
 #include "dsi_display.h"
 #endif
+#ifdef CONFIG_DRM_MSM_DPU
+#include "dpu_dbg.h"
+#endif

 /*
  * MSM driver version:


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Re: [Freedreno] [PATCH RESEND 02/10] drm/msm: Include the dpu_dbg header in msm_drv.c

[Jeykumar Sankaran]

On 2018-02-21 07:18, Sean Paul wrote:

We'll need to clean up these conditionals further, but at least fix the
compilation error.

Signed-off-by: Sean Paul <seanp...@chromium.org>


Reviewed by Jeykumar Sankaran


---
 drivers/gpu/drm/msm/msm_drv.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_drv.c 
b/drivers/gpu/drm/msm/msm_drv.c

index e1b7e468c3dc..6f2affe5ccff 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -53,6 +53,9 @@
 #ifdef CONFIG_DRM_MSM_DSI_STAGING
 #include "dsi_display.h"
 #endif
+#ifdef CONFIG_DRM_MSM_DPU
+#include "dpu_dbg.h"
+#endif

 /*
  * MSM driver version:


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Re: [Freedreno] [PATCH RESEND 01/10] drm/msm: Add displayport files to Makefile

[Jeykumar Sankaran]

On 2018-02-21 07:18, Sean Paul wrote:

Still behind a config flag, and ymmv when trying to build them, but
they're present at least.

Signed-off-by: Sean Paul <seanp...@chromium.org>


Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>


---
 drivers/gpu/drm/msm/Makefile | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/msm/Makefile 
b/drivers/gpu/drm/msm/Makefile

index d9014441d022..fcd85ae28d66 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -108,6 +108,20 @@ msm-y := \
msm_ringbuffer.o \
msm_submitqueue.o

+msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_usbpd.o \
+   dp/dp_parser.o \
+   dp/dp_power.o \
+   dp/dp_catalog.o \
+   dp/dp_aux.o \
+   dp/dp_panel.o \
+   dp/dp_link.o \
+   dp/dp_ctrl.o \
+   dp/dp_audio.o \
+   dp/dp_debug.o \
+   dp/dp_display.o \
+   dp/dp_drm.o \
+   dp/dp_hdcp2p2.o
+
 msm_wb-$(CONFIG_DRM_MSM_WRITEBACK) += disp/dpu1/dpu_wb.o \
  disp/dpu1/dpu_encoder_phys_wb.o


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Re: [Freedreno] [DPU PATCH 05/11] drm/msm: Mark the crtc->state->event consumed

[Jeykumar Sankaran]

On 2018-02-28 11:19, Sean Paul wrote:

Don't leave the event != NULL once it's consumed, this is used a signal
to the atomic helpers that the event will be handled by the driver.

Change-Id: Ib934fb2e97bacbb4a1f9c780cc7369c2bb98ed50
Signed-off-by: Sean Paul <seanp...@chromium.org>


Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>


---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 2 ++
 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 1 +
 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 94fab2dcca5b..a261021e5deb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -2714,6 +2714,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc
*crtc,
} else {
spin_lock_irqsave(>event_lock, flags);
dpu_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);
}

@@ -2798,6 +2799,7 @@ static void dpu_crtc_atomic_flush(struct drm_crtc
*crtc,
} else {
spin_lock_irqsave(>event_lock, flags);
dpu_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);
}

diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
index 6e5e1aa54ce1..b001699297c4 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
@@ -351,6 +351,7 @@ static void mdp4_crtc_atomic_flush(struct drm_crtc
*crtc,

spin_lock_irqsave(>event_lock, flags);
mdp4_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);

blend_setup(crtc);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 8c5ed0b59e46..5cb490a58f20 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -704,6 +704,7 @@ static void mdp5_crtc_atomic_flush(struct drm_crtc
*crtc,

spin_lock_irqsave(>event_lock, flags);
mdp5_crtc->event = crtc->state->event;
+   crtc->state->event = NULL;
spin_unlock_irqrestore(>event_lock, flags);

/*


--
Jeykumar S
___
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno

Re: [Freedreno] [DPU PATCH 11/11] drm/msm: Remove dpu input fences

[Jeykumar Sankaran]

On 2018-02-28 11:19, Sean Paul wrote:

These are already provided by drm atomic core.

In conjunction with the output fences removed earlier, this obsoletes
dpu_fence, and it can be entirely removed as well.

Change-Id: Ida4924a09c455d7a84bfee569bd0d2fb436418de
Signed-off-by: Sean Paul <seanp...@chromium.org>


Reviewed-by: Jeykumar Sankaran <jsa...@codeaurora.org>


---
 drivers/gpu/drm/msm/Makefile  |   1 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  |  84 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_fence.c | 404 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_fence.h | 190 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 104 --
 drivers/gpu/drm/msm/msm_drv.h |   4 +-
 6 files changed, 1 insertion(+), 786 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_fence.c
 delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_fence.h

diff --git a/drivers/gpu/drm/msm/Makefile 
b/drivers/gpu/drm/msm/Makefile

index 2fb9ba11df19..b47ef5267e19 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -55,7 +55,6 @@ msm-y := \
disp/dpu1/dpu_encoder.o \
disp/dpu1/dpu_encoder_phys_cmd.o \
disp/dpu1/dpu_encoder_phys_vid.o \
-   disp/dpu1/dpu_fence.o \
disp/dpu1/dpu_formats.o \
disp/dpu1/dpu_hw_ad4.o \
disp/dpu1/dpu_hw_blk.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 2d44989ade7a..8dd986e476bd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -64,16 +64,6 @@ static struct dpu_crtc_custom_events custom_events[] 
=

{
{DRM_EVENT_IDLE_NOTIFY, dpu_crtc_idle_interrupt_handler}
 };

-/* default input fence timeout, in ms */
-#define DPU_CRTC_INPUT_FENCE_TIMEOUT1
-
-/*
- * The default input fence timeout is 2 seconds while max allowed
- * range is 10 seconds. Any value above 10 seconds adds glitches 
beyond

- * tolerance limit.
- */
-#define DPU_CRTC_MAX_INPUT_FENCE_TIMEOUT 1
-
 /* layer mixer index on dpu_crtc */
 #define LEFT_MIXER 0
 #define RIGHT_MIXER 1
@@ -1946,21 +1936,6 @@ static void _dpu_crtc_set_idle_timeout(struct
drm_crtc *crtc, u64 val)
}
 }

-/**
- * _dpu_crtc_set_input_fence_timeout - update ns version of in fence
timeout
- * @cstate: Pointer to dpu crtc state
- */
-static void _dpu_crtc_set_input_fence_timeout(struct dpu_crtc_state
*cstate)
-{
-   if (!cstate) {
-   DPU_ERROR("invalid cstate\n");
-   return;
-   }
-   cstate->input_fence_timeout_ns =
-   dpu_crtc_get_property(cstate,
CRTC_PROP_INPUT_FENCE_TIMEOUT);
-   cstate->input_fence_timeout_ns *= NSEC_PER_MSEC;
-}
-
 /**
  * _dpu_crtc_set_dim_layer_v1 - copy dim layer settings from userspace
  * @cstate:  Pointer to dpu crtc state
@@ -2385,53 +2360,6 @@ static int 
_dpu_crtc_check_dest_scaler_data(struct

drm_crtc *crtc,
return ret;
 }

-/**
- * _dpu_crtc_wait_for_fences - wait for incoming framebuffer sync 
fences

- * @crtc: Pointer to CRTC object
- */
-static void _dpu_crtc_wait_for_fences(struct drm_crtc *crtc)
-{
-   struct drm_plane *plane = NULL;
-   uint32_t wait_ms = 1;
-   ktime_t kt_end, kt_wait;
-   int rc = 0;
-
-   DPU_DEBUG("\n");
-
-   if (!crtc || !crtc->state) {
-   DPU_ERROR("invalid crtc/state %pK\n", crtc);
-   return;
-   }
-
-   /* use monotonic timer to limit total fence wait time */
-   kt_end = ktime_add_ns(ktime_get(),
-   to_dpu_crtc_state(crtc->state)->input_fence_timeout_ns);
-
-   /*
-* Wait for fences sequentially, as all of them need to be
signalled
-* before we can proceed.
-*
-* Limit total wait time to INPUT_FENCE_TIMEOUT, but still call
-* dpu_plane_wait_input_fence with wait_ms == 0 after the timeout
so
-* that each plane can check its fence status and react
appropriately
-* if its fence has timed out. Call input fence wait multiple
times if
-* fence wait is interrupted due to interrupt call.
-*/
-   DPU_ATRACE_BEGIN("plane_wait_input_fence");
-   drm_atomic_crtc_for_each_plane(plane, crtc) {
-   do {
-   kt_wait = ktime_sub(kt_end, ktime_get());
-   if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0)
-   wait_ms = ktime_to_ms(kt_wait);
-   else
-   wait_ms = 0;
-
-   rc = dpu_plane_wait_input_fence(plane, wait_ms);
-   } while (wait_ms && rc == -ERESTARTSYS);
-   }
-   DPU_ATRACE_END("plane_wait_input_fence");
-}
-
 static void _dpu_crtc_setup_mixer_for_encoder(
struct drm_crtc *crtc,
struct drm_encoder *enc)
@@ -2716,9 +2644,6 @@ static void d

[Freedreno] [DPU PATCH v3 1/2] drm/msm/dsi-staging: remove support for partial update

[Jeykumar Sankaran]

Remove support partial update and related changes from dsi-staging
since the DPU dependencies are getting cleaned up.

changes since v1:
- remove unused code changes instead of hiding under compilation flag
- remove all references to partial ROI.

changes since v2:
- cleanup partial update ROI in panel files

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c|  20 ---
 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h|  12 --
 drivers/gpu/drm/msm/dsi-staging/dsi_defs.h|   2 -
 drivers/gpu/drm/msm/dsi-staging/dsi_display.c | 104 +-
 drivers/gpu/drm/msm/dsi-staging/dsi_display.h |   5 +-
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.c |  26 +---
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.h |   4 +-
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.c   | 200 --
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.h   |   5 -
 9 files changed, 7 insertions(+), 371 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c 
b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
index 5aadbe5..1798f44 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
@@ -1809,26 +1809,6 @@ int dsi_ctrl_setup(struct dsi_ctrl *dsi_ctrl)
return rc;
 }
 
-int dsi_ctrl_set_roi(struct dsi_ctrl *dsi_ctrl, struct dsi_rect *roi,
-   bool *changed)
-{
-   int rc = 0;
-
-   if (!dsi_ctrl || !roi || !changed) {
-   pr_err("Invalid params\n");
-   return -EINVAL;
-   }
-
-   mutex_lock(_ctrl->ctrl_lock);
-   if (!dsi_rect_is_equal(_ctrl->roi, roi)) {
-   *changed = true;
-   memcpy(_ctrl->roi, roi, sizeof(dsi_ctrl->roi));
-   } else
-   *changed = false;
-   mutex_unlock(_ctrl->ctrl_lock);
-   return rc;
-}
-
 /**
  * dsi_ctrl_phy_reset_config() - Mask/unmask propagation of ahb reset signal
  * to DSI PHY hardware.
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h 
b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
index 30b4dab..1826372 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
@@ -436,18 +436,6 @@ int dsi_ctrl_async_timing_update(struct dsi_ctrl *dsi_ctrl,
 int dsi_ctrl_setup(struct dsi_ctrl *dsi_ctrl);
 
 /**
- * dsi_ctrl_set_roi() - Set DSI controller's region of interest
- * @dsi_ctrl:DSI controller handle.
- * @roi: Region of interest rectangle, must be less than mode 
bounds
- * @changed: Output parameter, set to true of the controller's ROI was
- *   dirtied by setting the new ROI, and DCS cmd update needed
- *
- * Return: error code.
- */
-int dsi_ctrl_set_roi(struct dsi_ctrl *dsi_ctrl, struct dsi_rect *roi,
-   bool *changed);
-
-/**
  * dsi_ctrl_set_tpg_state() - enable/disable test pattern on the controller
  * @dsi_ctrl:  DSI controller handle.
  * @on:enable/disable test pattern.
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h 
b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
index 9385cce..02c8d76 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
@@ -239,7 +239,6 @@ enum dsi_dfps_type {
  * @DSI_CMD_SET_LP2:   Low power mode 2
  * @DSI_CMD_SET_NOLP:  Low power mode disable
  * @DSI_CMD_SET_PPS:   DSC PPS command
- * @DSI_CMD_SET_ROI:  Panel ROI update
  * @DSI_CMD_SET_TIMING_SWITCH: Timing switch
  * @DSI_CMD_SET_POST_TIMING_SWITCH:Post timing switch
  * @DSI_CMD_SET_MAX
@@ -263,7 +262,6 @@ enum dsi_cmd_set_type {
DSI_CMD_SET_LP2,
DSI_CMD_SET_NOLP,
DSI_CMD_SET_PPS,
-   DSI_CMD_SET_ROI,
DSI_CMD_SET_TIMING_SWITCH,
DSI_CMD_SET_POST_TIMING_SWITCH,
DSI_CMD_SET_MAX
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c 
b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
index 72055dc..31b7d7e 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -3414,9 +3414,6 @@ int dsi_display_get_info(struct msm_display_info *info, 
void *disp)
break;
}
 
-   memcpy(>roi_caps, >panel->roi_caps,
-   sizeof(info->roi_caps));
-
 error:
mutex_unlock(>display_lock);
return rc;
@@ -3941,104 +3938,7 @@ int dsi_display_prepare(struct dsi_display *display)
return rc;
 }
 
-static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
-   const struct dsi_display_ctrl *ctrl,
-   const struct msm_roi_list *req_rois,
-   struct dsi_rect *out_roi)
-{
-   const struct dsi_rect *bounds = >ctrl->mode_bounds;
-   struct dsi_rect req_roi = { 0 };
-   int rc = 0;
-
-   if (req_rois->num_rects > 

[Freedreno] [DPU PATCH v3 2/2] drm/msm: remove partial update support

[Jeykumar Sankaran]

Implementation of partial update in DPU DRM is heavily
dependent on custom properties and dsi hooks. Removing the
support for now. We may need to revisit the support in the
future.

changes since v1:
- get away with unwanted parameter validation
- code style fixes
- remove header file definitions for partial update

changes since v2:
- remove compilation flag for DPU_AD4.

Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c | 139 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h |   7 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c  | 544 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h  |  18 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   | 277 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h   |   8 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms_utils.c |  42 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c |  13 -
 drivers/gpu/drm/msm/msm_drv.h |  56 ---
 9 files changed, 87 insertions(+), 1017 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index 57b8627..c5e6c53 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -424,8 +424,7 @@ int dpu_connector_pre_kickoff(struct drm_connector 
*connector)
 {
struct dpu_connector *c_conn;
struct dpu_connector_state *c_state;
-   struct msm_display_kickoff_params params;
-   int idx, rc;
+   int idx, rc = 0;
 
if (!connector) {
DPU_ERROR("invalid argument\n");
@@ -462,15 +461,8 @@ int dpu_connector_pre_kickoff(struct drm_connector 
*connector)
}
}
 
-   if (!c_conn->ops.pre_kickoff)
-   return 0;
-
-   params.rois = _state->rois;
-
DPU_EVT32_VERBOSE(connector->base.id);
 
-   rc = c_conn->ops.pre_kickoff(connector, c_conn->display, );
-
return rc;
 }
 
@@ -645,122 +637,6 @@ static void dpu_connector_atomic_reset(struct 
drm_connector *connector)
return _state->base;
 }
 
-static int _dpu_connector_roi_v1_check_roi(
-   struct dpu_connector *c_conn,
-   struct drm_clip_rect *roi_conn,
-   const struct msm_roi_caps *caps)
-{
-   const struct msm_roi_alignment *align = >align;
-   int w = roi_conn->x2 - roi_conn->x1;
-   int h = roi_conn->y2 - roi_conn->y1;
-
-   if (w <= 0 || h <= 0) {
-   DPU_ERROR_CONN(c_conn, "invalid conn roi w %d h %d\n", w, h);
-   return -EINVAL;
-   }
-
-   if (w < align->min_width || w % align->width_pix_align) {
-   DPU_ERROR_CONN(c_conn,
-   "invalid conn roi width %d min %d align %d\n",
-   w, align->min_width, align->width_pix_align);
-   return -EINVAL;
-   }
-
-   if (h < align->min_height || h % align->height_pix_align) {
-   DPU_ERROR_CONN(c_conn,
-   "invalid conn roi height %d min %d align %d\n",
-   h, align->min_height, align->height_pix_align);
-   return -EINVAL;
-   }
-
-   if (roi_conn->x1 % align->xstart_pix_align) {
-   DPU_ERROR_CONN(c_conn, "invalid conn roi x1 %d align %d\n",
-   roi_conn->x1, align->xstart_pix_align);
-   return -EINVAL;
-   }
-
-   if (roi_conn->y1 % align->ystart_pix_align) {
-   DPU_ERROR_CONN(c_conn, "invalid conn roi y1 %d align %d\n",
-   roi_conn->y1, align->ystart_pix_align);
-   return -EINVAL;
-   }
-
-   return 0;
-}
-
-static int _dpu_connector_set_roi_v1(
-   struct dpu_connector *c_conn,
-   struct dpu_connector_state *c_state,
-   void *usr_ptr)
-{
-   struct dpu_drm_roi_v1 roi_v1;
-   struct msm_display_info display_info;
-   struct msm_roi_caps *caps;
-   int i, rc;
-
-   if (!c_conn || !c_state) {
-   DPU_ERROR("invalid args\n");
-   return -EINVAL;
-   }
-
-   rc = dpu_connector_get_info(_conn->base, _info);
-   if (rc) {
-   DPU_ERROR_CONN(c_conn, "display get info error: %d\n", rc);
-   return rc;
-   }
-
-   caps = _info.roi_caps;
-   if (!caps->enabled) {
-   DPU_ERROR_CONN(c_conn, "display roi capability is disabled\n");
-   return -ENOTSUPP;
-   }
-
-   memset(_state->rois, 0, sizeof(c_state->rois));
-
-   if (!usr_ptr) {
-   DPU_DEBUG_CONN(c_conn, "rois cleared\n");
-   return 0;
-   }
-
-   if (copy_fro

[Freedreno] [DPU PATCH v2 2/2] drm/msm: remove partial update support

[Jeykumar Sankaran]

Implementation of partial update in DPU DRM is heavily
dependent on custom properties and dsi hooks. Removing the
support for now. We may need to revisit the support in the
future.

Change-Id: Idd87272fe4d4c0a26fcb405154c0605af1edf1ba
Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c  | 139 +--
 drivers/gpu/drm/msm/disp/dpu1/dpu_connector.h  |   7 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c   | 544 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h   |  18 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c| 277 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |   2 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h|   8 -
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms_utils.c  |  42 --
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c  |  13 -
 drivers/gpu/drm/msm/msm_drv.h  |  56 ---
 10 files changed, 89 insertions(+), 1017 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index 57b8627..c5e6c53 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -424,8 +424,7 @@ int dpu_connector_pre_kickoff(struct drm_connector 
*connector)
 {
struct dpu_connector *c_conn;
struct dpu_connector_state *c_state;
-   struct msm_display_kickoff_params params;
-   int idx, rc;
+   int idx, rc = 0;
 
if (!connector) {
DPU_ERROR("invalid argument\n");
@@ -462,15 +461,8 @@ int dpu_connector_pre_kickoff(struct drm_connector 
*connector)
}
}
 
-   if (!c_conn->ops.pre_kickoff)
-   return 0;
-
-   params.rois = _state->rois;
-
DPU_EVT32_VERBOSE(connector->base.id);
 
-   rc = c_conn->ops.pre_kickoff(connector, c_conn->display, );
-
return rc;
 }
 
@@ -645,122 +637,6 @@ static void dpu_connector_atomic_reset(struct 
drm_connector *connector)
return _state->base;
 }
 
-static int _dpu_connector_roi_v1_check_roi(
-   struct dpu_connector *c_conn,
-   struct drm_clip_rect *roi_conn,
-   const struct msm_roi_caps *caps)
-{
-   const struct msm_roi_alignment *align = >align;
-   int w = roi_conn->x2 - roi_conn->x1;
-   int h = roi_conn->y2 - roi_conn->y1;
-
-   if (w <= 0 || h <= 0) {
-   DPU_ERROR_CONN(c_conn, "invalid conn roi w %d h %d\n", w, h);
-   return -EINVAL;
-   }
-
-   if (w < align->min_width || w % align->width_pix_align) {
-   DPU_ERROR_CONN(c_conn,
-   "invalid conn roi width %d min %d align %d\n",
-   w, align->min_width, align->width_pix_align);
-   return -EINVAL;
-   }
-
-   if (h < align->min_height || h % align->height_pix_align) {
-   DPU_ERROR_CONN(c_conn,
-   "invalid conn roi height %d min %d align %d\n",
-   h, align->min_height, align->height_pix_align);
-   return -EINVAL;
-   }
-
-   if (roi_conn->x1 % align->xstart_pix_align) {
-   DPU_ERROR_CONN(c_conn, "invalid conn roi x1 %d align %d\n",
-   roi_conn->x1, align->xstart_pix_align);
-   return -EINVAL;
-   }
-
-   if (roi_conn->y1 % align->ystart_pix_align) {
-   DPU_ERROR_CONN(c_conn, "invalid conn roi y1 %d align %d\n",
-   roi_conn->y1, align->ystart_pix_align);
-   return -EINVAL;
-   }
-
-   return 0;
-}
-
-static int _dpu_connector_set_roi_v1(
-   struct dpu_connector *c_conn,
-   struct dpu_connector_state *c_state,
-   void *usr_ptr)
-{
-   struct dpu_drm_roi_v1 roi_v1;
-   struct msm_display_info display_info;
-   struct msm_roi_caps *caps;
-   int i, rc;
-
-   if (!c_conn || !c_state) {
-   DPU_ERROR("invalid args\n");
-   return -EINVAL;
-   }
-
-   rc = dpu_connector_get_info(_conn->base, _info);
-   if (rc) {
-   DPU_ERROR_CONN(c_conn, "display get info error: %d\n", rc);
-   return rc;
-   }
-
-   caps = _info.roi_caps;
-   if (!caps->enabled) {
-   DPU_ERROR_CONN(c_conn, "display roi capability is disabled\n");
-   return -ENOTSUPP;
-   }
-
-   memset(_state->rois, 0, sizeof(c_state->rois));
-
-   if (!usr_ptr) {
-   DPU_DEBUG_CONN(c_conn, "rois cleared\n");
-   return 0;
-   }
-
-   if (copy_from_user(_v1, usr_ptr, sizeof(roi_v1))) {
-   DPU_ERROR_CONN(c_conn, "failed to copy roi_v1

[Freedreno] [DPU PATCH 1/2] drm/msm/dsi-staging: compile out partial update path

[Jeykumar Sankaran]

compile out partial update related changes from dsi-staging
since the DPU dependencies are getting removed.

Change-Id: I02462f520cdf99c8445b18e60212ca46155f9710
Signed-off-by: Jeykumar Sankaran <jsa...@codeaurora.org>
---
 drivers/gpu/drm/msm/dsi-staging/dsi_display.c |  9 +++--
 drivers/gpu/drm/msm/dsi-staging/dsi_display.h |  5 ++---
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.c | 11 ++-
 drivers/gpu/drm/msm/dsi-staging/dsi_drm.h |  4 +---
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.c   |  4 
 drivers/gpu/drm/msm/dsi-staging/dsi_panel.h   |  2 --
 6 files changed, 20 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c 
b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
index 72055dc..3e32872 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -3414,8 +3414,10 @@ int dsi_display_get_info(struct msm_display_info *info, 
void *disp)
break;
}
 
+#ifdef DSI_PARTIAL_UPDATE
memcpy(>roi_caps, >panel->roi_caps,
sizeof(info->roi_caps));
+#endif
 
 error:
mutex_unlock(>display_lock);
@@ -3941,6 +3943,7 @@ int dsi_display_prepare(struct dsi_display *display)
return rc;
 }
 
+#ifdef DSI_PARTIAL_UPDATE
 static int dsi_display_calc_ctrl_roi(const struct dsi_display *display,
const struct dsi_display_ctrl *ctrl,
const struct msm_roi_list *req_rois,
@@ -4036,9 +4039,9 @@ static int dsi_display_set_roi(struct dsi_display 
*display,
 
return rc;
 }
+#endif
 
-int dsi_display_pre_kickoff(struct dsi_display *display,
-   struct msm_display_kickoff_params *params)
+int dsi_display_pre_kickoff(struct dsi_display *display)
 {
int rc = 0;
 
@@ -4046,7 +4049,9 @@ int dsi_display_pre_kickoff(struct dsi_display *display,
if (display->misr_enable)
_dsi_display_setup_misr(display);
 
+#ifdef DSI_PARTIAL_UPDATE
rc = dsi_display_set_roi(display, params->rois);
+#endif
 
return rc;
 }
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h 
b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
index b23a84d..a0f9ccf 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h
@@ -524,11 +524,10 @@ int dsi_display_set_power(struct drm_connector *connector,
 /*
  * dsi_display_pre_kickoff - program kickoff-time features
  * @display: Pointer to private display structure
- * @params: Parameters for kickoff-time programming
  * Returns: Zero on success
  */
-int dsi_display_pre_kickoff(struct dsi_display *display,
-   struct msm_display_kickoff_params *params);
+int dsi_display_pre_kickoff(struct dsi_display *display);
+
 /**
  * dsi_display_get_dst_format() - get dst_format from DSI display
  * @display: Handle to display
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c 
b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
index 6847c53..32a6e8f 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
@@ -443,6 +443,7 @@ int dsi_conn_post_init(struct drm_connector *connector,
break;
}
 
+#ifdef DSI_PARTIAL_UPDATE
if (panel->roi_caps.enabled) {
dpu_kms_info_add_keyint(info, "partial_update_num_roi",
panel->roi_caps.num_roi);
@@ -460,7 +461,8 @@ int dsi_conn_post_init(struct drm_connector *connector,
panel->roi_caps.align.min_height);
dpu_kms_info_add_keyint(info, "partial_update_roimerge",
panel->roi_caps.merge_rois);
-   }
+   }
+#endif
 
 end:
return 0;
@@ -598,15 +600,14 @@ enum drm_mode_status dsi_conn_mode_valid(struct 
drm_connector *connector,
 }
 
 int dsi_conn_pre_kickoff(struct drm_connector *connector,
-   void *display,
-   struct msm_display_kickoff_params *params)
+   void *display)
 {
-   if (!connector || !display || !params) {
+   if (!connector || !display) {
pr_err("Invalid params\n");
return -EINVAL;
}
 
-   return dsi_display_pre_kickoff(display, params);
+   return dsi_display_pre_kickoff(display);
 }
 
 void dsi_conn_enable_event(struct drm_connector *connector,
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h 
b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h
index f427340..38de33c 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h
@@ -112,12 +112,10 @@ struct dsi_bridge *dsi_drm_bridge_init(struct dsi_display 
*display,
  * dsi_display_pre_kickoff - program kickoff-time features
  * @connector: Pointer to drm connector structure
  * @display: Pointer to private display structure
- * @params: Parameters for kickoff-time programmi