Re: Re: [PATCH] RISC-V: Modify ABI-name length of vfloat16m8_t
Committed, thanks. From: juzhe.zh...@rivai.ai Date: 2024-01-12 09:38 To: wangfeng; gcc-patches CC: kito.cheng; jeffreyalaw; wangfeng Subject: Re: [PATCH] RISC-V: Modify ABI-name length of vfloat16m8_t Good catch. LGTM. juzhe.zh...@rivai.ai From: Feng Wang Date: 2024-01-12 09:35 To: gcc-patches CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang Subject: [PATCH] RISC-V: Modify ABI-name length of vfloat16m8_t The length of vfloat16m8_t ABI-name should be 17. gcc/ChangeLog: * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):Modify ABI-name length of vfloat16m8_t --- gcc/config/riscv/riscv-vector-builtins.def | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index 055ee8b2ca4..784b54c81a4 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -483,7 +483,7 @@ DEF_RVV_TYPE (vfloat16m4_t, 17, __rvv_float16m4_t, float16, RVVM4HF, _f16m4, /* Define tuple types for SEW = 16, LMUL = M4. */ DEF_RVV_TUPLE_TYPE (vfloat16m4x2_t, 19, __rvv_float16m4x2_t, vfloat16m4_t, float16, 2, _f16m4x2) /* LMUL = 8. */ -DEF_RVV_TYPE (vfloat16m8_t, 16, __rvv_float16m8_t, float16, RVVM8HF, _f16m8, +DEF_RVV_TYPE (vfloat16m8_t, 17, __rvv_float16m8_t, float16, RVVM8HF, _f16m8, _f16, _e16m8) /* Disable all when !TARGET_VECTOR_ELEN_FP_32. */ -- 2.17.1
[PATCH] RISC-V: Modify ABI-name length of vfloat16m8_t
The length of vfloat16m8_t ABI-name should be 17. gcc/ChangeLog: * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):Modify ABI-name length of vfloat16m8_t --- gcc/config/riscv/riscv-vector-builtins.def | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index 055ee8b2ca4..784b54c81a4 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -483,7 +483,7 @@ DEF_RVV_TYPE (vfloat16m4_t, 17, __rvv_float16m4_t, float16, RVVM4HF, _f16m4, /* Define tuple types for SEW = 16, LMUL = M4. */ DEF_RVV_TUPLE_TYPE (vfloat16m4x2_t, 19, __rvv_float16m4x2_t, vfloat16m4_t, float16, 2, _f16m4x2) /* LMUL = 8. */ -DEF_RVV_TYPE (vfloat16m8_t, 16, __rvv_float16m8_t, float16, RVVM8HF, _f16m8, +DEF_RVV_TYPE (vfloat16m8_t, 17, __rvv_float16m8_t, float16, RVVM8HF, _f16m8, _f16, _e16m8) /* Disable all when !TARGET_VECTOR_ELEN_FP_32. */ -- 2.17.1
回复: Re: [PATCH v7 1/2] RISC-V: Add crypto vector builtin function.
Committed, thanks Juzhe.
发件人： 钟居哲
发送时间： 2024-01-09 07:02
收件人： wangfeng; gcc-patches
抄送： kito.cheng; Jeff Law; wangfeng
主题： Re: [PATCH v7 1/2] RISC-V: Add crypto vector builtin function.
LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-08 17:12
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v7 1/2] RISC-V: Add crypto vector builtin function.
Patch v7:Resubmit after fix trl-checking issue. Passed all the riscv regression
test.
Patch v6:Remove unused code.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
Add new function_base for crypto vector.
(class bitmanip): Ditto.
(class b_reverse):Ditto.
(class vwsll): Ditto.
(class clmul): Ditto.
(class vg_nhab): Ditto.
(class crypto_vv):Ditto.
(class crypto_vi):Ditto.
(class vaeskf2_vsm3c):Ditto.
(class vsm3me): Ditto.
(BASE): Add BASE declaration for crypto vector.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
Add crypto vector intrinsic definition.
(vbrev): Ditto.
(vclz): Ditto.
(vctz): Ditto.
(vwsll): Ditto.
(vandn): Ditto.
(vbrev8): Ditto.
(vrev8): Ditto.
(vrol): Ditto.
(vror): Ditto.
(vclmul): Ditto.
(vclmulh): Ditto.
(vghsh): Ditto.
(vgmul): Ditto.
(vaesef): Ditto.
(vaesem): Ditto.
(vaesdf): Ditto.
(vaesdm): Ditto.
(vaesz): Ditto.
(vaeskf1): Ditto.
(vaeskf2): Ditto.
(vsha2ms): Ditto.
(vsha2ch): Ditto.
(vsha2cl): Ditto.
(vsm4k): Ditto.
(vsm4r): Ditto.
(vsm3me): Ditto.
(vsm3c): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add new function_shape for crypto vector.
(struct crypto_vi_def): Ditto.
(struct crypto_vv_no_op_type_def): Ditto.
(SHAPE): Add SHAPE declaration of crypto vector.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
Add new data type for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
Add new data struct for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(registered_function::overloaded_hash): Processing size_t uimm for C overloaded
func.
* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
---
.../riscv/riscv-vector-builtins-bases.cc | 264 +-
.../riscv/riscv-vector-builtins-bases.h | 28 ++
.../riscv/riscv-vector-builtins-functions.def | 94 +++
.../riscv/riscv-vector-builtins-shapes.cc | 87 +-
.../riscv/riscv-vector-builtins-shapes.h | 4 +
.../riscv/riscv-vector-builtins-types.def | 25 ++
gcc/config/riscv/riscv-vector-builtins.cc | 133 -
gcc/config/riscv/riscv-vector-builtins.def| 1 +
8 files changed, 633 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d70468542ee..d12bb89f91c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2127,6 +2127,212 @@ public:
}
};
+/* Below implements are vector crypto */
+/* Implements vandn.[vv,vx] */
+class vandn : public function_base
+{
+public:
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_vandn (e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_vandn_scalar (e.vector_mode
()));
+ default:
+gcc_unreachable ();
+ }
+ }
+};
+
+/* Implements vrol/vror/clz/ctz. */
+template
+class bitmanip : public function_base
+{
+public:
+ bool apply_tail_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool apply_mask_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool has_merge_operand_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+{
+ case OP_TYPE_v:
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_v (CODE, e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exac
回复: Re: [PATCH v8 2/2] RISC-V: Add crypto vector api-testing cases.
Committed, thanks Juzhe.
发件人： 钟居哲
发送时间： 2024-01-09 07:02
收件人： wangfeng; gcc-patches
抄送： kito.cheng; Jeff Law; wangfeng
主题： Re: [PATCH v8 2/2] RISC-V: Add crypto vector api-testing cases.
LGTM.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-01-08 17:12
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH v8 2/2] RISC-V: Add crypto vector api-testing cases.
Patch v8: Resubmit after fix the rtl-checking issue. Passed all the riscv
regression test.
Patch v7: Add newline at the end of file.
Patch v6: Move intrinsic tests into rvv/base.
Patch v5: Rebase
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvbb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c: New test.
* gcc.target/riscv/rvv/base/zvbc-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c: New test.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c: New test.
* gcc.target/riscv/rvv/base/zvkg-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvkned-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvknha-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvknhb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvksed-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvksh-intrinsic.c: New test.
* gcc.target/riscv/zvkb.c: New test.
---
.../riscv/rvv/base/zvbb-intrinsic.c | 179 ++
.../riscv/rvv/base/zvbb_vandn_vx_constraint.c | 15 ++
.../riscv/rvv/base/zvbc-intrinsic.c | 62 ++
.../riscv/rvv/base/zvbc_vx_constraint-1.c | 14 ++
.../riscv/rvv/base/zvbc_vx_constraint-2.c | 14 ++
.../riscv/rvv/base/zvkg-intrinsic.c | 24 +++
.../riscv/rvv/base/zvkned-intrinsic.c | 104 ++
.../riscv/rvv/base/zvknha-intrinsic.c | 33
.../riscv/rvv/base/zvknhb-intrinsic.c | 33
.../riscv/rvv/base/zvksed-intrinsic.c | 33
.../riscv/rvv/base/zvksh-intrinsic.c | 24 +++
gcc/testsuite/gcc.target/riscv/zvkb.c | 13 ++
12 files changed, 548 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvbc-intrinsic.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvkg-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvkned-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvknha-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvknhb-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvksed-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvksh-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkb.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
new file mode 100644
index 000..b7e25bfe819
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
@@ -0,0 +1,179 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvbb_zve64x -mabi=lp64d -Wno-psabi" } */
+#include "riscv_vector.h"
+
+vuint8mf8_t test_vandn_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u8mf8(vs2, vs1, vl);
+}
+
+vuint32m1_t test_vandn_vx_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u32m1(vs2, rs1, vl);
+}
+
+vuint32m2_t test_vandn_vv_u32m2_m(vbool16_t mask, vuint32m2_t vs2, vuint32m2_t
vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m2_m(mask, vs2, vs1, vl);
+}
+
+vuint16mf2_t test_vandn_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t vs2, uint16_t
rs1, size_t vl) {
+ return __riscv_vandn_vx_u16mf2_m(mask, vs2, rs1, vl);
+}
+
+vuint32m4_t test_vandn_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m4_tumu(mask, maskedoff, vs2, vs1, vl);
+}
+
+vuint64m4_t test_vandn_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff,
vuint64m4_t vs2, uint64_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u64m4_tumu(mask, maskedoff, vs2, rs1, vl);
+}
+
+vuint8m8_t test_vbrev_v_u8m8(vuint8m8_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u8m8(vs2, vl);
+}
+
+vuint16m1_t test_vbrev_v_u16m1_m(vbool16_t mask, vuint16m1_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u16m1_m(mask, vs2, vl);
+}
+
+vuint32m4_t test_vbrev_v_u32m4_tumu(vbool8_t mask, v
[PATCH v7 1/2] RISC-V: Add crypto vector builtin function.
Patch v7:Resubmit after fix trl-checking issue. Passed all the riscv regression
test.
Patch v6:Remove unused code.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
Add new function_base for crypto vector.
(class bitmanip): Ditto.
(class b_reverse):Ditto.
(class vwsll): Ditto.
(class clmul): Ditto.
(class vg_nhab): Ditto.
(class crypto_vv):Ditto.
(class crypto_vi):Ditto.
(class vaeskf2_vsm3c):Ditto.
(class vsm3me): Ditto.
(BASE): Add BASE declaration for crypto vector.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXTENSIONS):
Add crypto vector intrinsic definition.
(vbrev): Ditto.
(vclz): Ditto.
(vctz): Ditto.
(vwsll): Ditto.
(vandn): Ditto.
(vbrev8): Ditto.
(vrev8): Ditto.
(vrol): Ditto.
(vror): Ditto.
(vclmul): Ditto.
(vclmulh): Ditto.
(vghsh): Ditto.
(vgmul): Ditto.
(vaesef): Ditto.
(vaesem): Ditto.
(vaesdf): Ditto.
(vaesdm): Ditto.
(vaesz): Ditto.
(vaeskf1): Ditto.
(vaeskf2): Ditto.
(vsha2ms): Ditto.
(vsha2ch): Ditto.
(vsha2cl): Ditto.
(vsm4k): Ditto.
(vsm4r): Ditto.
(vsm3me): Ditto.
(vsm3c): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add new function_shape for crypto vector.
(struct crypto_vi_def): Ditto.
(struct crypto_vv_no_op_type_def): Ditto.
(SHAPE): Add SHAPE declaration of crypto vector.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_CRYPTO_SEW32_OPS):
Add new data type for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
Add new data struct for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(registered_function::overloaded_hash): Processing size_t uimm for C
overloaded func.
* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
---
.../riscv/riscv-vector-builtins-bases.cc | 264 +-
.../riscv/riscv-vector-builtins-bases.h | 28 ++
.../riscv/riscv-vector-builtins-functions.def | 94 +++
.../riscv/riscv-vector-builtins-shapes.cc | 87 +-
.../riscv/riscv-vector-builtins-shapes.h | 4 +
.../riscv/riscv-vector-builtins-types.def | 25 ++
gcc/config/riscv/riscv-vector-builtins.cc | 133 -
gcc/config/riscv/riscv-vector-builtins.def| 1 +
8 files changed, 633 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d70468542ee..d12bb89f91c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2127,6 +2127,212 @@ public:
}
};
+/* Below implements are vector crypto */
+/* Implements vandn.[vv,vx] */
+class vandn : public function_base
+{
+public:
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_vandn (e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_vandn_scalar (e.vector_mode
()));
+ default:
+gcc_unreachable ();
+ }
+ }
+};
+
+/* Implements vrol/vror/clz/ctz. */
+template
+class bitmanip : public function_base
+{
+public:
+ bool apply_tail_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool apply_mask_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool has_merge_operand_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+
+ rtx expand
[PATCH v8 2/2] RISC-V: Add crypto vector api-testing cases.
Patch v8: Resubmit after fix the rtl-checking issue. Passed all the riscv
regression test.
Patch v7: Add newline at the end of file.
Patch v6: Move intrinsic tests into rvv/base.
Patch v5: Rebase
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvbb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c: New test.
* gcc.target/riscv/rvv/base/zvbc-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c: New test.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c: New test.
* gcc.target/riscv/rvv/base/zvkg-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvkned-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvknha-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvknhb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvksed-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvksh-intrinsic.c: New test.
* gcc.target/riscv/zvkb.c: New test.
---
.../riscv/rvv/base/zvbb-intrinsic.c | 179 ++
.../riscv/rvv/base/zvbb_vandn_vx_constraint.c | 15 ++
.../riscv/rvv/base/zvbc-intrinsic.c | 62 ++
.../riscv/rvv/base/zvbc_vx_constraint-1.c | 14 ++
.../riscv/rvv/base/zvbc_vx_constraint-2.c | 14 ++
.../riscv/rvv/base/zvkg-intrinsic.c | 24 +++
.../riscv/rvv/base/zvkned-intrinsic.c | 104 ++
.../riscv/rvv/base/zvknha-intrinsic.c | 33
.../riscv/rvv/base/zvknhb-intrinsic.c | 33
.../riscv/rvv/base/zvksed-intrinsic.c | 33
.../riscv/rvv/base/zvksh-intrinsic.c | 24 +++
gcc/testsuite/gcc.target/riscv/zvkb.c | 13 ++
12 files changed, 548 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvbc-intrinsic.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvkg-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvkned-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvknha-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvknhb-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvksed-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvksh-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkb.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
new file mode 100644
index 000..b7e25bfe819
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
@@ -0,0 +1,179 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvbb_zve64x -mabi=lp64d -Wno-psabi" } */
+#include "riscv_vector.h"
+
+vuint8mf8_t test_vandn_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u8mf8(vs2, vs1, vl);
+}
+
+vuint32m1_t test_vandn_vx_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u32m1(vs2, rs1, vl);
+}
+
+vuint32m2_t test_vandn_vv_u32m2_m(vbool16_t mask, vuint32m2_t vs2, vuint32m2_t
vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m2_m(mask, vs2, vs1, vl);
+}
+
+vuint16mf2_t test_vandn_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t vs2, uint16_t
rs1, size_t vl) {
+ return __riscv_vandn_vx_u16mf2_m(mask, vs2, rs1, vl);
+}
+
+vuint32m4_t test_vandn_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m4_tumu(mask, maskedoff, vs2, vs1, vl);
+}
+
+vuint64m4_t test_vandn_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff,
vuint64m4_t vs2, uint64_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u64m4_tumu(mask, maskedoff, vs2, rs1, vl);
+}
+
+vuint8m8_t test_vbrev_v_u8m8(vuint8m8_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u8m8(vs2, vl);
+}
+
+vuint16m1_t test_vbrev_v_u16m1_m(vbool16_t mask, vuint16m1_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u16m1_m(mask, vs2, vl);
+}
+
+vuint32m4_t test_vbrev_v_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u32m4_tumu(mask, maskedoff, vs2, vl);
+}
+
+vuint16mf4_t test_vbrev8_v_u16mf4(vuint16mf4_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u16mf4(vs2, vl);
+}
+
+vuint32m1_t test_vbrev8_v_u32m1_m(vbool32_t mask, vuint32m1_t
[committed] RISC-V: Fix avl-type operand index error for ZVBC
This patch fix the rtl-checking error for crypto vector. The root cause is the avl-type index of zvbc ins is error,it should be operand[8] not operand[5]. gcc/ChangeLog: * config/riscv/vector.md: Modify avl_type operand index of zvbc ins. --- gcc/config/riscv/vector.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index be5beb5ab64..24b7b4394be 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -864,9 +864,9 @@ vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\ vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\ vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\ - vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll") + vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vclmul,vclmulh,vwsll") (const_int 8) -(eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vclmul,vclmulh") +(eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox") (const_int 5) (eq_attr "type" "vimuladd,vfmuladd") -- 2.17.1
[PATCH] RISC-V: Fix avl-type operand index error for ZVBC
This patch fix the rtl-checking error for crypto vector. The root cause is the avl-type index of zvbc ins is error,it should be operand[8] not operand[5]. gcc/ChangeLog: * config/riscv/vector.md: Modify avl_type operand index of zvbc ins. --- gcc/config/riscv/vector.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 3d2c1c3ce8f..e99a312b5b6 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -864,9 +864,9 @@ vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\ vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\ vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\ - vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll") + vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vclmul,vclmulh,vwsll") (const_int 8) -(eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vclmul,vclmulh") +(eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox") (const_int 5) (eq_attr "type" "vimuladd,vfmuladd") -- 2.17.1
Re: Re: [PATCH v7 1/2] RISC-V: Add crypto vector builtin function.
2024-01-05 16:55 juzhe.zhong wrote: >--- a/gcc/config/riscv/vector.md >+++ b/gcc/config/riscv/vector.md >@@ -864,9 +864,9 @@ > vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\ > vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\ > vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\ >- vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll") >+ vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vclmul,vclmulh,vwsll") > (const_int 8) >- (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vclmul,vclmulh") >+ (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox") > (const_int 5) > > >Ah, I knew something go wrong in case of attribute bugs. > >I think it should be a separate patch which is "Fix vlmax type attribute bugs >of vclmul and vclmulh instructions". > > > >juzhe.zh...@rivai.ai > OK. Will separate it. >From: Feng Wang >Date: 2024-01-05 16:51 >To: gcc-patches >CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang >Subject: [PATCH v7 1/2] RISC-V: Add crypto vector builtin function. >Patch v7:Fix avl_type operand index of zvbc ins. >Patch v6:Remove unused code. >Patch v5:Rebase. >Patch v4:Merge crypto vector function.def into vector. >Patch v3:Define a shape for vaesz and merge vector-crypto-types.def > into riscv-vector-builtins-types.def. >Patch v2:Optimize function_shape class for crypto_vector. > >This patch add the intrinsic funtions of crypto vector based on the >intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob >/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md). > >Co-Authored by: Songhe Zhu >Co-Authored by: Ciyan Pan >gcc/ChangeLog: > >* config/riscv/riscv-vector-builtins-bases.cc (class vandn): >Add new function_base for crypto vector. >(class bitmanip): Ditto. >(class b_reverse):Ditto. >(class vwsll): Ditto. >(class clmul): Ditto. >(class vg_nhab): Ditto. >(class crypto_vv):Ditto. >(class crypto_vi):Ditto. >(class vaeskf2_vsm3c):Ditto. >(class vsm3me): Ditto. >(BASE): Add BASE declaration for crypto vector. >* config/riscv/riscv-vector-builtins-bases.h: Ditto. >* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS): >Add crypto vector intrinsic definition. >(vbrev): Ditto. >(vclz): Ditto. >(vctz): Ditto. >(vwsll): Ditto. >(vandn): Ditto. >(vbrev8): Ditto. >(vrev8): Ditto. >(vrol): Ditto. >(vror): Ditto. >(vclmul): Ditto. >(vclmulh): Ditto. >(vghsh): Ditto. >(vgmul): Ditto. >(vaesef): Ditto. >(vaesem): Ditto. >(vaesdf): Ditto. >(vaesdm): Ditto. >(vaesz): Ditto. >(vaeskf1): Ditto. >(vaeskf2): Ditto. >(vsha2ms): Ditto. >(vsha2ch): Ditto. >(vsha2cl): Ditto. >(vsm4k): Ditto. >(vsm4r): Ditto. >(vsm3me): Ditto. >(vsm3c): Ditto. >* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def): >Add new function_shape for crypto vector. >(struct crypto_vi_def): Ditto. >(struct crypto_vv_no_op_type_def): Ditto. >(SHAPE): Add SHAPE declaration of crypto vector. >* config/riscv/riscv-vector-builtins-shapes.h: Ditto. >* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS): >Add new data type for crypto vector. >(DEF_RVV_CRYPTO_SEW64_OPS): Ditto. >(vuint32mf2_t): Ditto. >(vuint32m1_t): Ditto. >(vuint32m2_t): Ditto. >(vuint32m4_t): Ditto. >(vuint32m8_t): Ditto. >(vuint64m1_t): Ditto. >(vuint64m2_t): Ditto. >(vuint64m4_t): Ditto. >(vuint64m8_t): Ditto. >* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS): >Add new data struct for crypto vector. >(DEF_RVV_CRYPTO_SEW64_OPS): Ditto. >(registered_function::overloaded_hash): Processing size_t uimm for C >overloaded func. >* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE. >* config/riscv/vector.md: Modify avl_type operand index of zvbc ins. >--- >.../riscv/riscv-vector-builtins-bases.cc | 264 +- >.../riscv/riscv-vector-builtins-bases.h | 28 ++ >.../riscv/riscv-vector-builtins-functions.def | 94 +++ >.../riscv/riscv-vector-builtins-shapes.cc | 87 +- >.../riscv/riscv-vector-builtins-shapes.h | 4 + >.../riscv/riscv-vector-builtins-types.def | 25 ++ >gcc/config/riscv/riscv-vector-builtins.cc | 133 - >gcc/config/riscv/riscv-vector-builtins.def | 1 + >gcc/config/riscv/vector.md | 4 +-
[PATCH v7 1/2] RISC-V: Add crypto vector builtin function.
Patch v7:Fix avl_type operand index of zvbc ins.
Patch v6:Remove unused code.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
Add new function_base for crypto vector.
(class bitmanip): Ditto.
(class b_reverse):Ditto.
(class vwsll): Ditto.
(class clmul): Ditto.
(class vg_nhab): Ditto.
(class crypto_vv):Ditto.
(class crypto_vi):Ditto.
(class vaeskf2_vsm3c):Ditto.
(class vsm3me): Ditto.
(BASE): Add BASE declaration for crypto vector.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXTENSIONS):
Add crypto vector intrinsic definition.
(vbrev): Ditto.
(vclz): Ditto.
(vctz): Ditto.
(vwsll): Ditto.
(vandn): Ditto.
(vbrev8): Ditto.
(vrev8): Ditto.
(vrol): Ditto.
(vror): Ditto.
(vclmul): Ditto.
(vclmulh): Ditto.
(vghsh): Ditto.
(vgmul): Ditto.
(vaesef): Ditto.
(vaesem): Ditto.
(vaesdf): Ditto.
(vaesdm): Ditto.
(vaesz): Ditto.
(vaeskf1): Ditto.
(vaeskf2): Ditto.
(vsha2ms): Ditto.
(vsha2ch): Ditto.
(vsha2cl): Ditto.
(vsm4k): Ditto.
(vsm4r): Ditto.
(vsm3me): Ditto.
(vsm3c): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add new function_shape for crypto vector.
(struct crypto_vi_def): Ditto.
(struct crypto_vv_no_op_type_def): Ditto.
(SHAPE): Add SHAPE declaration of crypto vector.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_CRYPTO_SEW32_OPS):
Add new data type for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
Add new data struct for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(registered_function::overloaded_hash): Processing size_t uimm for C
overloaded func.
* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
* config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
---
.../riscv/riscv-vector-builtins-bases.cc | 264 +-
.../riscv/riscv-vector-builtins-bases.h | 28 ++
.../riscv/riscv-vector-builtins-functions.def | 94 +++
.../riscv/riscv-vector-builtins-shapes.cc | 87 +-
.../riscv/riscv-vector-builtins-shapes.h | 4 +
.../riscv/riscv-vector-builtins-types.def | 25 ++
gcc/config/riscv/riscv-vector-builtins.cc | 133 -
gcc/config/riscv/riscv-vector-builtins.def| 1 +
gcc/config/riscv/vector.md| 4 +-
9 files changed, 635 insertions(+), 5 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 810783bff4c..fba98124473 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2127,6 +2127,212 @@ public:
}
};
+/* Below implements are vector crypto */
+/* Implements vandn.[vv,vx] */
+class vandn : public function_base
+{
+public:
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_vandn (e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_vandn_scalar (e.vector_mode
()));
+ default:
+gcc_unreachable ();
+ }
+ }
+};
+
+/* Implements vrol/vror/clz/ctz. */
+template
+class bitmanip : public function_base
+{
+public:
+ bool apply_tail_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool apply_mask_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool has_merge_operand_p () const override
+ {
+
Re: Re: [committed] RISC-V: Add crypto vector builtin function.
Yes, as Juzhe said I had run all the riscv regression, but without RTL check. I will fix it. Sorry for forgetting to enable RTL checking for testing. Thanks Juzhe for helping me reverse this commit. From: juzhe.zh...@rivai.ai Date: 2024-01-05 11:28 To: palmer CC: gcc-patches; kito.cheng; Kito.cheng Subject: Re: Re: [committed] RISC-V: Add crypto vector builtin function. We (me and kito) has reviewed vector-crypto. I believe Wang Feng has done && passed the regression (with no RTL check), but he just didn't enable RTL check I guessed. (By default, RTL check is disabled in riscv-gnu-toolchain, developers need to enable it manually). It's ok to revert the patch, then commit it after he fixes the ICE with enabling RTL check. juzhe.zh...@rivai.ai From: Palmer Dabbelt Date: 2024-01-05 11:24 To: juzhe.zhong CC: gcc-patches; Kito Cheng; Kito.cheng Subject: Re: [committed] RISC-V: Add crypto vector builtin function. On Thu, 04 Jan 2024 19:17:21 PST (-0800), juzhe.zh...@rivai.ai wrote: > Hi, Wang Feng. > > Your patch has some ICEs: > FAIL: gcc.target/riscv/rvv/base/zvbc-intrinsic.c (internal compiler error: > RTL check: expected code 'const_int', have 'reg' in vlmax_avl_type_p, at > config/riscv/riscv-v.cc:4930) > FAIL: gcc.target/riscv/rvv/base/zvbc-intrinsic.c (test for excess errors) > FAIL: gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c (internal compiler > error: RTL check: expected code 'const_int', have 'reg' in vlmax_avl_type_p, > at config/riscv/riscv-v.cc:4930) > FAIL: gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c (test for excess > errors) > FAIL: gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c (internal compiler > error: RTL check: expected code 'const_int', have 'reg' in vlmax_avl_type_p, > at config/riscv/riscv-v.cc:4930) > FAIL: gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c (test for excess > errors) So let's just revert it, it doesn't even look like it was reviewed. We've set a really bad precedent here where we're just merging a bunch of unreviewed code and sorting out the regressions in trunk, that's not the right way to do things. > > I suspect you didn't enable rtl check in the regression: > > ../../configure --enable-gcc-checking=rtl. > Plz enable rtl check in the regression tests. > > > > juzhe.zh...@rivai.ai
[committed] RISC-V: Add crypto vector api-testing cases.
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvbb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c: New test.
* gcc.target/riscv/rvv/base/zvbc-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c: New test.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c: New test.
* gcc.target/riscv/rvv/base/zvkg-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvkned-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvknha-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvknhb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvksed-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvksh-intrinsic.c: New test.
* gcc.target/riscv/zvkb.c: New test.
---
.../riscv/rvv/base/zvbb-intrinsic.c | 179 ++
.../riscv/rvv/base/zvbb_vandn_vx_constraint.c | 15 ++
.../riscv/rvv/base/zvbc-intrinsic.c | 62 ++
.../riscv/rvv/base/zvbc_vx_constraint-1.c | 14 ++
.../riscv/rvv/base/zvbc_vx_constraint-2.c | 14 ++
.../riscv/rvv/base/zvkg-intrinsic.c | 24 +++
.../riscv/rvv/base/zvkned-intrinsic.c | 104 ++
.../riscv/rvv/base/zvknha-intrinsic.c | 33
.../riscv/rvv/base/zvknhb-intrinsic.c | 33
.../riscv/rvv/base/zvksed-intrinsic.c | 33
.../riscv/rvv/base/zvksh-intrinsic.c | 24 +++
gcc/testsuite/gcc.target/riscv/zvkb.c | 13 ++
12 files changed, 548 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvbc-intrinsic.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvkg-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvkned-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvknha-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvknhb-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvksed-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvksh-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkb.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
new file mode 100644
index 000..b7e25bfe819
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
@@ -0,0 +1,179 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvbb_zve64x -mabi=lp64d -Wno-psabi" } */
+#include "riscv_vector.h"
+
+vuint8mf8_t test_vandn_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u8mf8(vs2, vs1, vl);
+}
+
+vuint32m1_t test_vandn_vx_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u32m1(vs2, rs1, vl);
+}
+
+vuint32m2_t test_vandn_vv_u32m2_m(vbool16_t mask, vuint32m2_t vs2, vuint32m2_t
vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m2_m(mask, vs2, vs1, vl);
+}
+
+vuint16mf2_t test_vandn_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t vs2, uint16_t
rs1, size_t vl) {
+ return __riscv_vandn_vx_u16mf2_m(mask, vs2, rs1, vl);
+}
+
+vuint32m4_t test_vandn_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m4_tumu(mask, maskedoff, vs2, vs1, vl);
+}
+
+vuint64m4_t test_vandn_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff,
vuint64m4_t vs2, uint64_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u64m4_tumu(mask, maskedoff, vs2, rs1, vl);
+}
+
+vuint8m8_t test_vbrev_v_u8m8(vuint8m8_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u8m8(vs2, vl);
+}
+
+vuint16m1_t test_vbrev_v_u16m1_m(vbool16_t mask, vuint16m1_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u16m1_m(mask, vs2, vl);
+}
+
+vuint32m4_t test_vbrev_v_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u32m4_tumu(mask, maskedoff, vs2, vl);
+}
+
+vuint16mf4_t test_vbrev8_v_u16mf4(vuint16mf4_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u16mf4(vs2, vl);
+}
+
+vuint32m1_t test_vbrev8_v_u32m1_m(vbool32_t mask, vuint32m1_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u32m1_m(mask, vs2, vl);
+}
+
+vuint64m1_t test_vbrev8_v_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff,
vuint64m1_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u64m1_tumu(mask, maskedoff, vs2, vl);
+}
+
+vuint16m4_t test_vrev8_v_u16m4(vuint16m4_t vs2, size_t vl) {
+ return __riscv_vrev8_v_u16m4(vs2, vl);
+}
+
[committed] RISC-V: Add crypto vector builtin function.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
Add new function_base for crypto vector.
(class bitmanip): Ditto.
(class b_reverse):Ditto.
(class vwsll): Ditto.
(class clmul): Ditto.
(class vg_nhab): Ditto.
(class crypto_vv):Ditto.
(class crypto_vi):Ditto.
(class vaeskf2_vsm3c):Ditto.
(class vsm3me): Ditto.
(BASE): Add BASE declaration for crypto vector.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXTENSIONS):
Add crypto vector intrinsic definition.
(vbrev): Ditto.
(vclz): Ditto.
(vctz): Ditto.
(vwsll): Ditto.
(vandn): Ditto.
(vbrev8): Ditto.
(vrev8): Ditto.
(vrol): Ditto.
(vror): Ditto.
(vclmul): Ditto.
(vclmulh): Ditto.
(vghsh): Ditto.
(vgmul): Ditto.
(vaesef): Ditto.
(vaesem): Ditto.
(vaesdf): Ditto.
(vaesdm): Ditto.
(vaesz): Ditto.
(vaeskf1): Ditto.
(vaeskf2): Ditto.
(vsha2ms): Ditto.
(vsha2ch): Ditto.
(vsha2cl): Ditto.
(vsm4k): Ditto.
(vsm4r): Ditto.
(vsm3me): Ditto.
(vsm3c): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add new function_shape for crypto vector.
(struct crypto_vi_def): Ditto.
(struct crypto_vv_no_op_type_def): Ditto.
(SHAPE): Add SHAPE declaration of crypto vector.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_CRYPTO_SEW32_OPS):
Add new data type for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
Add new data struct for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(registered_function::overloaded_hash): Processing size_t uimm for C
overloaded func.
* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
---
.../riscv/riscv-vector-builtins-bases.cc | 264 +-
.../riscv/riscv-vector-builtins-bases.h | 28 ++
.../riscv/riscv-vector-builtins-functions.def | 94 +++
.../riscv/riscv-vector-builtins-shapes.cc | 87 +-
.../riscv/riscv-vector-builtins-shapes.h | 4 +
.../riscv/riscv-vector-builtins-types.def | 25 ++
gcc/config/riscv/riscv-vector-builtins.cc | 133 -
gcc/config/riscv/riscv-vector-builtins.def| 1 +
8 files changed, 633 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 810783bff4c..fba98124473 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2127,6 +2127,212 @@ public:
}
};
+/* Below implements are vector crypto */
+/* Implements vandn.[vv,vx] */
+class vandn : public function_base
+{
+public:
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_vandn (e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_vandn_scalar (e.vector_mode
()));
+ default:
+gcc_unreachable ();
+ }
+ }
+};
+
+/* Implements vrol/vror/clz/ctz. */
+template
+class bitmanip : public function_base
+{
+public:
+ bool apply_tail_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool apply_mask_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool has_merge_operand_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+{
+ case OP_TYPE_v:
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_v (CODE, e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_v_scalar (CODE, e.vector_mode
()));
+ default:
+gcc_unreachable ();
+}
+ }
+};
+
+/*
[PATCH v7 2/2] RISC-V: Add crypto vector api-testing cases.
Patch v7: Add newline at the end of file.
Patch v6: Move intrinsic tests into rvv/base.
Patch v5: Rebase
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvbb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c: New test.
* gcc.target/riscv/rvv/base/zvbc-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c: New test.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c: New test.
* gcc.target/riscv/rvv/base/zvkg-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvkned-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvknha-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvknhb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvksed-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvksh-intrinsic.c: New test.
* gcc.target/riscv/zvkb.c: New test.
---
.../riscv/rvv/base/zvbb-intrinsic.c | 179 ++
.../riscv/rvv/base/zvbb_vandn_vx_constraint.c | 15 ++
.../riscv/rvv/base/zvbc-intrinsic.c | 62 ++
.../riscv/rvv/base/zvbc_vx_constraint-1.c | 14 ++
.../riscv/rvv/base/zvbc_vx_constraint-2.c | 14 ++
.../riscv/rvv/base/zvkg-intrinsic.c | 24 +++
.../riscv/rvv/base/zvkned-intrinsic.c | 104 ++
.../riscv/rvv/base/zvknha-intrinsic.c | 33
.../riscv/rvv/base/zvknhb-intrinsic.c | 33
.../riscv/rvv/base/zvksed-intrinsic.c | 33
.../riscv/rvv/base/zvksh-intrinsic.c | 24 +++
gcc/testsuite/gcc.target/riscv/zvkb.c | 13 ++
12 files changed, 548 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvbc-intrinsic.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvkg-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvkned-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvknha-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvknhb-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvksed-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvksh-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkb.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
new file mode 100644
index 000..b7e25bfe819
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
@@ -0,0 +1,179 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvbb_zve64x -mabi=lp64d -Wno-psabi" } */
+#include "riscv_vector.h"
+
+vuint8mf8_t test_vandn_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u8mf8(vs2, vs1, vl);
+}
+
+vuint32m1_t test_vandn_vx_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u32m1(vs2, rs1, vl);
+}
+
+vuint32m2_t test_vandn_vv_u32m2_m(vbool16_t mask, vuint32m2_t vs2, vuint32m2_t
vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m2_m(mask, vs2, vs1, vl);
+}
+
+vuint16mf2_t test_vandn_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t vs2, uint16_t
rs1, size_t vl) {
+ return __riscv_vandn_vx_u16mf2_m(mask, vs2, rs1, vl);
+}
+
+vuint32m4_t test_vandn_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m4_tumu(mask, maskedoff, vs2, vs1, vl);
+}
+
+vuint64m4_t test_vandn_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff,
vuint64m4_t vs2, uint64_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u64m4_tumu(mask, maskedoff, vs2, rs1, vl);
+}
+
+vuint8m8_t test_vbrev_v_u8m8(vuint8m8_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u8m8(vs2, vl);
+}
+
+vuint16m1_t test_vbrev_v_u16m1_m(vbool16_t mask, vuint16m1_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u16m1_m(mask, vs2, vl);
+}
+
+vuint32m4_t test_vbrev_v_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u32m4_tumu(mask, maskedoff, vs2, vl);
+}
+
+vuint16mf4_t test_vbrev8_v_u16mf4(vuint16mf4_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u16mf4(vs2, vl);
+}
+
+vuint32m1_t test_vbrev8_v_u32m1_m(vbool32_t mask, vuint32m1_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u32m1_m(mask, vs2, vl);
+}
+
+vuint64m1_t
[PATCH v6 2/2] RISC-V: Add crypto vector api-testing cases.
Patch v6: Move intrinsic tests into rvv/base.
Patch v5: Rebase
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvbb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c: New test.
* gcc.target/riscv/rvv/base/zvbc-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c: New test.
* gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c: New test.
* gcc.target/riscv/rvv/base/zvkg-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvkned-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvknha-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvknhb-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvksed-intrinsic.c: New test.
* gcc.target/riscv/rvv/base/zvksh-intrinsic.c: New test.
* gcc.target/riscv/zvkb.c: New test.
---
.../riscv/rvv/base/zvbb-intrinsic.c | 179 ++
.../riscv/rvv/base/zvbb_vandn_vx_constraint.c | 15 ++
.../riscv/rvv/base/zvbc-intrinsic.c | 62 ++
.../riscv/rvv/base/zvbc_vx_constraint-1.c | 14 ++
.../riscv/rvv/base/zvbc_vx_constraint-2.c | 14 ++
.../riscv/rvv/base/zvkg-intrinsic.c | 24 +++
.../riscv/rvv/base/zvkned-intrinsic.c | 105 ++
.../riscv/rvv/base/zvknha-intrinsic.c | 33
.../riscv/rvv/base/zvknhb-intrinsic.c | 33
.../riscv/rvv/base/zvksed-intrinsic.c | 33
.../riscv/rvv/base/zvksh-intrinsic.c | 24 +++
gcc/testsuite/gcc.target/riscv/zvkb.c | 13 ++
12 files changed, 549 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbb_vandn_vx_constraint.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvbc-intrinsic.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-1.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/zvbc_vx_constraint-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvkg-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvkned-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvknha-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvknhb-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvksed-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvksh-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkb.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
new file mode 100644
index 000..b7e25bfe819
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvbb-intrinsic.c
@@ -0,0 +1,179 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvbb_zve64x -mabi=lp64d -Wno-psabi" } */
+#include "riscv_vector.h"
+
+vuint8mf8_t test_vandn_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u8mf8(vs2, vs1, vl);
+}
+
+vuint32m1_t test_vandn_vx_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u32m1(vs2, rs1, vl);
+}
+
+vuint32m2_t test_vandn_vv_u32m2_m(vbool16_t mask, vuint32m2_t vs2, vuint32m2_t
vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m2_m(mask, vs2, vs1, vl);
+}
+
+vuint16mf2_t test_vandn_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t vs2, uint16_t
rs1, size_t vl) {
+ return __riscv_vandn_vx_u16mf2_m(mask, vs2, rs1, vl);
+}
+
+vuint32m4_t test_vandn_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m4_tumu(mask, maskedoff, vs2, vs1, vl);
+}
+
+vuint64m4_t test_vandn_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff,
vuint64m4_t vs2, uint64_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u64m4_tumu(mask, maskedoff, vs2, rs1, vl);
+}
+
+vuint8m8_t test_vbrev_v_u8m8(vuint8m8_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u8m8(vs2, vl);
+}
+
+vuint16m1_t test_vbrev_v_u16m1_m(vbool16_t mask, vuint16m1_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u16m1_m(mask, vs2, vl);
+}
+
+vuint32m4_t test_vbrev_v_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u32m4_tumu(mask, maskedoff, vs2, vl);
+}
+
+vuint16mf4_t test_vbrev8_v_u16mf4(vuint16mf4_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u16mf4(vs2, vl);
+}
+
+vuint32m1_t test_vbrev8_v_u32m1_m(vbool32_t mask, vuint32m1_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u32m1_m(mask, vs2, vl);
+}
+
+vuint64m1_t test_vbrev8_v_u64m1_tumu(vbool64_t mask,
Re: Re: [committed] RISC-V: Modify copyright year of vector-crypto.md
2024-01-03 00:32 Jeff Law wrote: > > >On 1/1/24 19:25, Feng Wang wrote: >> gcc/ChangeLog: >> * config/riscv/vector-crypto.md: Modify copyright year. >> --- >> gcc/config/riscv/vector-crypto.md | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/gcc/config/riscv/vector-crypto.md >> b/gcc/config/riscv/vector-crypto.md >> index e40b1543954..9625014e45e 100755 >> --- a/gcc/config/riscv/vector-crypto.md >> +++ b/gcc/config/riscv/vector-crypto.md >> @@ -1,5 +1,5 @@ >> ;; Machine description for the RISC-V Vector Crypto extensions. >> -;; Copyright (C) 2023 Free Software Foundation, Inc. >> +;; Copyright (C) 2024 Free Software Foundation, Inc.Please don't change >> Copyright notices in the future. There's very >specific rules around those and we do them en-masse at the start of the >year using existing scripts and such. > >jeff OK, got it. Thanks.
[PATCH v6 1/2] RISC-V: Add crypto vector builtin function.
Patch v6:Remove unused code.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
Add new function_base for crypto vector.
(class bitmanip): Ditto.
(class b_reverse):Ditto.
(class vwsll): Ditto.
(class clmul): Ditto.
(class vg_nhab): Ditto.
(class crypto_vv):Ditto.
(class crypto_vi):Ditto.
(class vaeskf2_vsm3c):Ditto.
(class vsm3me): Ditto.
(BASE): Add BASE declaration for crypto vector.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXTENSIONS):
Add crypto vector intrinsic definition.
(vbrev): Ditto.
(vclz): Ditto.
(vctz): Ditto.
(vwsll): Ditto.
(vandn): Ditto.
(vbrev8): Ditto.
(vrev8): Ditto.
(vrol): Ditto.
(vror): Ditto.
(vclmul): Ditto.
(vclmulh): Ditto.
(vghsh): Ditto.
(vgmul): Ditto.
(vaesef): Ditto.
(vaesem): Ditto.
(vaesdf): Ditto.
(vaesdm): Ditto.
(vaesz): Ditto.
(vaeskf1): Ditto.
(vaeskf2): Ditto.
(vsha2ms): Ditto.
(vsha2ch): Ditto.
(vsha2cl): Ditto.
(vsm4k): Ditto.
(vsm4r): Ditto.
(vsm3me): Ditto.
(vsm3c): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add new function_shape for crypto vector.
(struct crypto_vi_def): Ditto.
(struct crypto_vv_no_op_type_def): Ditto.
(SHAPE): Add SHAPE declaration of crypto vector.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_CRYPTO_SEW32_OPS):
Add new data type for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
Add new data struct for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(registered_function::overloaded_hash): Processing size_t uimm for C
overloaded func.
* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
---
.../riscv/riscv-vector-builtins-bases.cc | 264 +-
.../riscv/riscv-vector-builtins-bases.h | 28 ++
.../riscv/riscv-vector-builtins-functions.def | 94 +++
.../riscv/riscv-vector-builtins-shapes.cc | 87 +-
.../riscv/riscv-vector-builtins-shapes.h | 4 +
.../riscv/riscv-vector-builtins-types.def | 25 ++
gcc/config/riscv/riscv-vector-builtins.cc | 133 -
gcc/config/riscv/riscv-vector-builtins.def| 1 +
8 files changed, 633 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d70468542ee..d12bb89f91c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2127,6 +2127,212 @@ public:
}
};
+/* Below implements are vector crypto */
+/* Implements vandn.[vv,vx] */
+class vandn : public function_base
+{
+public:
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_vandn (e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_vandn_scalar (e.vector_mode
()));
+ default:
+gcc_unreachable ();
+ }
+ }
+};
+
+/* Implements vrol/vror/clz/ctz. */
+template
+class bitmanip : public function_base
+{
+public:
+ bool apply_tail_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool apply_mask_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool has_merge_operand_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+{
+ case OP_TYPE_v:
+
Re: Re: [PATCH v5 1/2] RISC-V: Add crypto vector builtin function.
2024-01-02 15:55 juzhe.zhong wrote:
>+/* Static information about a set of crypto vector functions. */
>+struct crypto_function_group_info
>+{
>+ struct function_group_info rvv_function_group_info;
>+ /* Whether the function is available. */
>+ unsigned int (*avail) (void);
>+};
>
>What is this used for ?
Will delete it.
>
>
>juzhe.zh...@rivai.ai
>
>From: Feng Wang
>Date: 2024-01-02 15:47
>To: gcc-patches
>CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
>Subject: [PATCH v5 1/2] RISC-V: Add crypto vector builtin function.
>Patch v5:Rebase.
>Patch v4:Merge crypto vector function.def into vector.
>Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
> into riscv-vector-builtins-types.def.
>Patch v2:Optimize function_shape class for crypto_vector.
>
>This patch add the intrinsic funtions of crypto vector based on the
>intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
>/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
>
>Co-Authored by: Songhe Zhu
>Co-Authored by: Ciyan Pan
>gcc/ChangeLog:
>
>* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
>Add new function_base for crypto vector.
>(class bitmanip): Ditto.
>(class b_reverse):Ditto.
>(class vwsll): Ditto.
>(class clmul): Ditto.
>(class vg_nhab): Ditto.
>(class crypto_vv):Ditto.
>(class crypto_vi):Ditto.
>(class vaeskf2_vsm3c):Ditto.
>(class vsm3me): Ditto.
>(BASE): Add BASE declaration for crypto vector.
>* config/riscv/riscv-vector-builtins-bases.h: Ditto.
>* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
>Add crypto vector intrinsic definition.
>(vbrev): Ditto.
>(vclz): Ditto.
>(vctz): Ditto.
>(vwsll): Ditto.
>(vandn): Ditto.
>(vbrev8): Ditto.
>(vrev8): Ditto.
>(vrol): Ditto.
>(vror): Ditto.
>(vclmul): Ditto.
>(vclmulh): Ditto.
>(vghsh): Ditto.
>(vgmul): Ditto.
>(vaesef): Ditto.
>(vaesem): Ditto.
>(vaesdf): Ditto.
>(vaesdm): Ditto.
>(vaesz): Ditto.
>(vaeskf1): Ditto.
>(vaeskf2): Ditto.
>(vsha2ms): Ditto.
>(vsha2ch): Ditto.
>(vsha2cl): Ditto.
>(vsm4k): Ditto.
>(vsm4r): Ditto.
>(vsm3me): Ditto.
>(vsm3c): Ditto.
>* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
>Add new function_shape for crypto vector.
>(struct crypto_vi_def): Ditto.
>(struct crypto_vv_no_op_type_def): Ditto.
>(SHAPE): Add SHAPE declaration of crypto vector.
>* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
>* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
>Add new data type for crypto vector.
>(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
>(vuint32mf2_t): Ditto.
>(vuint32m1_t): Ditto.
>(vuint32m2_t): Ditto.
>(vuint32m4_t): Ditto.
>(vuint32m8_t): Ditto.
>(vuint64m1_t): Ditto.
>(vuint64m2_t): Ditto.
>(vuint64m4_t): Ditto.
>(vuint64m8_t): Ditto.
>* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
>Add new data struct for crypto vector.
>(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
>(registered_function::overloaded_hash): Processing size_t uimm for C
>overloaded func.
>* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
>---
>.../riscv/riscv-vector-builtins-bases.cc | 264 +-
>.../riscv/riscv-vector-builtins-bases.h | 28 ++
>.../riscv/riscv-vector-builtins-functions.def | 94 +++
>.../riscv/riscv-vector-builtins-shapes.cc | 87 +-
>.../riscv/riscv-vector-builtins-shapes.h | 4 +
>.../riscv/riscv-vector-builtins-types.def | 25 ++
>gcc/config/riscv/riscv-vector-builtins.cc | 133 -
>gcc/config/riscv/riscv-vector-builtins.def | 1 +
>gcc/config/riscv/riscv-vector-builtins.h | 8 +
>9 files changed, 641 insertions(+), 3 deletions(-)
>
>diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
>b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>index d70468542ee..d12bb89f91c 100644
>--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
>+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>@@ -2127,6 +2127,212 @@ public:
> }
>};
>+/* Below implements are vector crypto */
>+/* Implements vandn.[vv,vx] */
>+class vandn : public function_base
>+{
>+public:
>+ rtx expand (function_expander ) const override
>+ {
>+ switch (e.op_info->op)
>+ {
>+ case OP_TYPE_vv:
>+ return e.use_exact_insn (code_for_pred_vandn (e.vector_mode ()));
>+ case OP
[PATCH v5 2/2] RISC-V: Add crypto vector api-testing cases.
Patch v5: Rebase.
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing case s.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zvbb-intrinsic.c: New test.
* gcc.target/riscv/zvbb_vandn_vx_constraint.c: New test.
* gcc.target/riscv/zvbc-intrinsic.c: New test.
* gcc.target/riscv/zvbc_vx_constraint-2.c: New test.
* gcc.target/riscv/zvbc_vx_constraint-1.c: New test.
* gcc.target/riscv/zvkb.c: New test.
* gcc.target/riscv/zvkg-intrinsic.c: New test.
* gcc.target/riscv/zvkned-intrinsic.c: New test.
* gcc.target/riscv/zvknha-intrinsic.c: New test.
* gcc.target/riscv/zvknhb-intrinsic.c: New test.
* gcc.target/riscv/zvksed-intrinsic.c: New test.
* gcc.target/riscv/zvksh-intrinsic.c: New test.
---
.../gcc.target/riscv/zvbb-intrinsic.c | 179 ++
.../riscv/zvbb_vandn_vx_constraint.c | 15 ++
.../gcc.target/riscv/zvbc-intrinsic.c | 62 ++
.../gcc.target/riscv/zvbc_vx_constraint-2.c | 14 ++
.../gcc.target/riscv/zvbc_vx_constraint.c | 14 ++
gcc/testsuite/gcc.target/riscv/zvkb.c | 13 ++
.../gcc.target/riscv/zvkg-intrinsic.c | 24 +++
.../gcc.target/riscv/zvkned-intrinsic.c | 105 ++
.../gcc.target/riscv/zvknha-intrinsic.c | 33
.../gcc.target/riscv/zvknhb-intrinsic.c | 33
.../gcc.target/riscv/zvksed-intrinsic.c | 33
.../gcc.target/riscv/zvksh-intrinsic.c| 24 +++
12 files changed, 549 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zvbb-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvbb_vandn_vx_constraint.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvbc-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvbc_vx_constraint-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvbc_vx_constraint.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkg-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkned-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvknha-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvknhb-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvksed-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvksh-intrinsic.c
diff --git a/gcc/testsuite/gcc.target/riscv/zvbb-intrinsic.c
b/gcc/testsuite/gcc.target/riscv/zvbb-intrinsic.c
new file mode 100644
index 000..7d436d2a43c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zvbb-intrinsic.c
@@ -0,0 +1,179 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvbb_zve64x -mabi=lp64d -Wno-psabi" } */
+#include
+
+vuint8mf8_t test_vandn_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u8mf8(vs2, vs1, vl);
+}
+
+vuint32m1_t test_vandn_vx_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u32m1(vs2, rs1, vl);
+}
+
+vuint32m2_t test_vandn_vv_u32m2_m(vbool16_t mask, vuint32m2_t vs2, vuint32m2_t
vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m2_m(mask, vs2, vs1, vl);
+}
+
+vuint16mf2_t test_vandn_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t vs2, uint16_t
rs1, size_t vl) {
+ return __riscv_vandn_vx_u16mf2_m(mask, vs2, rs1, vl);
+}
+
+vuint32m4_t test_vandn_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m4_tumu(mask, maskedoff, vs2, vs1, vl);
+}
+
+vuint64m4_t test_vandn_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff,
vuint64m4_t vs2, uint64_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u64m4_tumu(mask, maskedoff, vs2, rs1, vl);
+}
+
+vuint8m8_t test_vbrev_v_u8m8(vuint8m8_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u8m8(vs2, vl);
+}
+
+vuint16m1_t test_vbrev_v_u16m1_m(vbool16_t mask, vuint16m1_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u16m1_m(mask, vs2, vl);
+}
+
+vuint32m4_t test_vbrev_v_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u32m4_tumu(mask, maskedoff, vs2, vl);
+}
+
+vuint16mf4_t test_vbrev8_v_u16mf4(vuint16mf4_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u16mf4(vs2, vl);
+}
+
+vuint32m1_t test_vbrev8_v_u32m1_m(vbool32_t mask, vuint32m1_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u32m1_m(mask, vs2, vl);
+}
+
+vuint64m1_t test_vbrev8_v_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff,
vuint64m1_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u64m1_tumu(mask, maskedoff, vs2, vl);
+}
+
+vuint16m4_t test_vrev8_v_u16m4(vuint16m4_t vs2, size_t vl) {
+ return __riscv_vrev8_v_u16m4(vs2, vl);
+}
+
+vuint8m4_t test_vrev8_v_u8m4_m(vbool2_t mask, vuint8m4_t vs2,
[PATCH v5 1/2] RISC-V: Add crypto vector builtin function.
Patch v5:Rebase.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
Add new function_base for crypto vector.
(class bitmanip): Ditto.
(class b_reverse):Ditto.
(class vwsll): Ditto.
(class clmul): Ditto.
(class vg_nhab): Ditto.
(class crypto_vv):Ditto.
(class crypto_vi):Ditto.
(class vaeskf2_vsm3c):Ditto.
(class vsm3me): Ditto.
(BASE): Add BASE declaration for crypto vector.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXTENSIONS):
Add crypto vector intrinsic definition.
(vbrev): Ditto.
(vclz): Ditto.
(vctz): Ditto.
(vwsll): Ditto.
(vandn): Ditto.
(vbrev8): Ditto.
(vrev8): Ditto.
(vrol): Ditto.
(vror): Ditto.
(vclmul): Ditto.
(vclmulh): Ditto.
(vghsh): Ditto.
(vgmul): Ditto.
(vaesef): Ditto.
(vaesem): Ditto.
(vaesdf): Ditto.
(vaesdm): Ditto.
(vaesz): Ditto.
(vaeskf1): Ditto.
(vaeskf2): Ditto.
(vsha2ms): Ditto.
(vsha2ch): Ditto.
(vsha2cl): Ditto.
(vsm4k): Ditto.
(vsm4r): Ditto.
(vsm3me): Ditto.
(vsm3c): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add new function_shape for crypto vector.
(struct crypto_vi_def): Ditto.
(struct crypto_vv_no_op_type_def): Ditto.
(SHAPE): Add SHAPE declaration of crypto vector.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_CRYPTO_SEW32_OPS):
Add new data type for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
Add new data struct for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(registered_function::overloaded_hash): Processing size_t uimm for C
overloaded func.
* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
---
.../riscv/riscv-vector-builtins-bases.cc | 264 +-
.../riscv/riscv-vector-builtins-bases.h | 28 ++
.../riscv/riscv-vector-builtins-functions.def | 94 +++
.../riscv/riscv-vector-builtins-shapes.cc | 87 +-
.../riscv/riscv-vector-builtins-shapes.h | 4 +
.../riscv/riscv-vector-builtins-types.def | 25 ++
gcc/config/riscv/riscv-vector-builtins.cc | 133 -
gcc/config/riscv/riscv-vector-builtins.def| 1 +
gcc/config/riscv/riscv-vector-builtins.h | 8 +
9 files changed, 641 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d70468542ee..d12bb89f91c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2127,6 +2127,212 @@ public:
}
};
+/* Below implements are vector crypto */
+/* Implements vandn.[vv,vx] */
+class vandn : public function_base
+{
+public:
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_vandn (e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_vandn_scalar (e.vector_mode
()));
+ default:
+gcc_unreachable ();
+ }
+ }
+};
+
+/* Implements vrol/vror/clz/ctz. */
+template
+class bitmanip : public function_base
+{
+public:
+ bool apply_tail_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool apply_mask_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool has_merge_operand_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+{
[committed] RISC-V: Modify copyright year of vector-crypto.md
gcc/ChangeLog: * config/riscv/vector-crypto.md: Modify copyright year. --- gcc/config/riscv/vector-crypto.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md index e40b1543954..9625014e45e 100755 --- a/gcc/config/riscv/vector-crypto.md +++ b/gcc/config/riscv/vector-crypto.md @@ -1,5 +1,5 @@ ;; Machine description for the RISC-V Vector Crypto extensions. -;; Copyright (C) 2023 Free Software Foundation, Inc. +;; Copyright (C) 2024 Free Software Foundation, Inc. ;; This file is part of GCC. -- 2.17.1
[committed] RISC-V: Add crypto machine descriptions
Co-Authored by: Songhe Zhu Co-Authored by: Ciyan Pan gcc/ChangeLog: * config/riscv/iterators.md: Add rotate insn name. * config/riscv/riscv.md: Add new insns name for crypto vector. * config/riscv/vector-iterators.md: Add new iterators for crypto vector. * config/riscv/vector.md: Add the corresponding attr for crypto vector. * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector. --- gcc/config/riscv/iterators.md| 4 +- gcc/config/riscv/riscv.md| 33 +- gcc/config/riscv/vector-crypto.md| 654 +++ gcc/config/riscv/vector-iterators.md | 36 ++ gcc/config/riscv/vector.md | 55 ++- 5 files changed, 761 insertions(+), 21 deletions(-) create mode 100755 gcc/config/riscv/vector-crypto.md diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index ecf033f2fa7..f332fba7031 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -304,7 +304,9 @@ (umax "maxu") (clz "clz") (ctz "ctz") -(popcount "cpop")]) +(popcount "cpop") +(rotate "rol") +(rotatert "ror")]) ;; --- ;; Int Iterators. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 68f7203b676..52c5ce30115 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -428,6 +428,34 @@ ;; vcompressvector compress instruction ;; vmov whole vector register move ;; vector unknown vector instruction +;; 17. Crypto Vector instructions +;; vandncrypto vector bitwise and-not instructions +;; vbrevcrypto vector reverse bits in elements instructions +;; vbrev8 crypto vector reverse bits in bytes instructions +;; vrev8crypto vector reverse bytes instructions +;; vclz crypto vector count leading Zeros instructions +;; vctz crypto vector count lrailing Zeros instructions +;; vrol crypto vector rotate left instructions +;; vror crypto vector rotate right instructions +;; vwsllcrypto vector widening shift left logical instructions +;; vclmul crypto vector carry-less multiply - return low half instructions +;; vclmulh crypto vector carry-less multiply - return high half instructions +;; vghshcrypto vector add-multiply over GHASH Galois-Field instructions +;; vgmulcrypto vector multiply over GHASH Galois-Field instrumctions +;; vaesef crypto vector AES final-round encryption instructions +;; vaesem crypto vector AES middle-round encryption instructions +;; vaesdf crypto vector AES final-round decryption instructions +;; vaesdm crypto vector AES middle-round decryption instructions +;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation instructions +;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation instructions +;; vaeszcrypto vector AES round zero encryption/decryption instructions +;; vsha2ms crypto vector SHA-2 message schedule instructions +;; vsha2ch crypto vector SHA-2 two rounds of compression instructions +;; vsha2cl crypto vector SHA-2 two rounds of compression instructions +;; vsm4kcrypto vector SM4 KeyExpansion instructions +;; vsm4rcrypto vector SM4 Rounds instructions +;; vsm3me crypto vector SM3 Message Expansion instructions +;; vsm3ccrypto vector SM3 Compression instructions (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -447,7 +475,9 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov,vector" + vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, @@ -3786,6 +3816,7 @@ (include "thead.md") (include "generic-ooo.md") (include "vector.md") +(include "vector-crypto.md") (include "zicond.md") (include "sfb.md") (include "zc.md") diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md new file mode 100755 index 000..e40b1543954 --- /dev/null +++ b/gcc/config/riscv/vector-crypto.md @@ -0,0 +1,654 @@ +;; Machine description for the RISC-V Vector Crypto extensions. +;; Copyright (C) 2023 Free Software Foundation, Inc. +
Re: [PATCH] RISC-V: Add crypto machine descriptions
2023-12-22 09:59 Feng Wang wrote: Sorry for forgetting to add the patch version number. It should be [PATCH v8 2/3] >Patch v8: Remove unused iterator and add newline at the end. >Patch v7: Remove mode of const_int_operand and typo. Add > newline at the end and comment at the beginning. >Patch v6: Swap the operator order of vandn.vv >Patch v5: Add vec_duplicate operator. >Patch v4: Add process of SEW=64 in RV32 system. >Patch v3: Moidfy constrains for crypto vector. >Patch v2: Add crypto vector ins into RATIO attr and use vr as >destination register. > >This patch add the crypto machine descriptions(vector-crypto.md) and >some new iterators which are used by crypto vector ext. > >Co-Authored by: Songhe Zhu >Co-Authored by: Ciyan Pan >gcc/ChangeLog: > > * config/riscv/iterators.md: Add rotate insn name. > * config/riscv/riscv.md: Add new insns name for crypto vector. > * config/riscv/vector-iterators.md: Add new iterators for crypto vector. > * config/riscv/vector.md: Add the corresponding attr for crypto vector. > * config/riscv/vector-crypto.md: New file.The machine descriptions for > crypto vector. >--- > gcc/config/riscv/iterators.md | 4 +- > gcc/config/riscv/riscv.md | 33 +- > gcc/config/riscv/vector-crypto.md | 654 +++ > gcc/config/riscv/vector-iterators.md | 36 ++ > gcc/config/riscv/vector.md | 55 ++- > 5 files changed, 761 insertions(+), 21 deletions(-) > create mode 100755 gcc/config/riscv/vector-crypto.md > >diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md >index ecf033f2fa7..f332fba7031 100644 >--- a/gcc/config/riscv/iterators.md >+++ b/gcc/config/riscv/iterators.md >@@ -304,7 +304,9 @@ >(umax "maxu") >(clz "clz") >(ctz "ctz") >- (popcount "cpop")]) >+ (popcount "cpop") >+ (rotate "rol") >+ (rotatert "ror")]) > > ;; --- > ;; Int Iterators. >diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md >index ee8b71c22aa..88019a46a53 100644 >--- a/gcc/config/riscv/riscv.md >+++ b/gcc/config/riscv/riscv.md >@@ -427,6 +427,34 @@ > ;; vcompress vector compress instruction > ;; vmov whole vector register move > ;; vector unknown vector instruction >+;; 17. Crypto Vector instructions >+;; vandn crypto vector bitwise and-not instructions >+;; vbrev crypto vector reverse bits in elements instructions >+;; vbrev8 crypto vector reverse bits in bytes instructions >+;; vrev8 crypto vector reverse bytes instructions >+;; vclz crypto vector count leading Zeros instructions >+;; vctz crypto vector count lrailing Zeros instructions >+;; vrol crypto vector rotate left instructions >+;; vror crypto vector rotate right instructions >+;; vwsll crypto vector widening shift left logical instructions >+;; vclmul crypto vector carry-less multiply - return low half >instructions >+;; vclmulh crypto vector carry-less multiply - return high half >instructions >+;; vghsh crypto vector add-multiply over GHASH Galois-Field >instructions >+;; vgmul crypto vector multiply over GHASH Galois-Field instrumctions >+;; vaesef crypto vector AES final-round encryption instructions >+;; vaesem crypto vector AES middle-round encryption instructions >+;; vaesdf crypto vector AES final-round decryption instructions >+;; vaesdm crypto vector AES middle-round decryption instructions >+;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation >instructions >+;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation >instructions >+;; vaesz crypto vector AES round zero encryption/decryption >instructions >+;; vsha2ms crypto vector SHA-2 message schedule instructions >+;; vsha2ch crypto vector SHA-2 two rounds of compression instructions >+;; vsha2cl crypto vector SHA-2 two rounds of compression instructions >+;; vsm4k crypto vector SM4 KeyExpansion instructions >+;; vsm4r crypto vector SM4 Rounds instructions >+;; vsm3me crypto vector SM3 Message Expansion instructio
[PATCH] RISC-V: Add crypto machine descriptions
Patch v8: Remove unused iterator and add newline at the end. Patch v7: Remove mode of const_int_operand and typo. Add newline at the end and comment at the beginning. Patch v6: Swap the operator order of vandn.vv Patch v5: Add vec_duplicate operator. Patch v4: Add process of SEW=64 in RV32 system. Patch v3: Moidfy constrains for crypto vector. Patch v2: Add crypto vector ins into RATIO attr and use vr as destination register. This patch add the crypto machine descriptions(vector-crypto.md) and some new iterators which are used by crypto vector ext. Co-Authored by: Songhe Zhu Co-Authored by: Ciyan Pan gcc/ChangeLog: * config/riscv/iterators.md: Add rotate insn name. * config/riscv/riscv.md: Add new insns name for crypto vector. * config/riscv/vector-iterators.md: Add new iterators for crypto vector. * config/riscv/vector.md: Add the corresponding attr for crypto vector. * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector. --- gcc/config/riscv/iterators.md| 4 +- gcc/config/riscv/riscv.md| 33 +- gcc/config/riscv/vector-crypto.md| 654 +++ gcc/config/riscv/vector-iterators.md | 36 ++ gcc/config/riscv/vector.md | 55 ++- 5 files changed, 761 insertions(+), 21 deletions(-) create mode 100755 gcc/config/riscv/vector-crypto.md diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index ecf033f2fa7..f332fba7031 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -304,7 +304,9 @@ (umax "maxu") (clz "clz") (ctz "ctz") -(popcount "cpop")]) +(popcount "cpop") +(rotate "rol") +(rotatert "ror")]) ;; --- ;; Int Iterators. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ee8b71c22aa..88019a46a53 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -427,6 +427,34 @@ ;; vcompressvector compress instruction ;; vmov whole vector register move ;; vector unknown vector instruction +;; 17. Crypto Vector instructions +;; vandncrypto vector bitwise and-not instructions +;; vbrevcrypto vector reverse bits in elements instructions +;; vbrev8 crypto vector reverse bits in bytes instructions +;; vrev8crypto vector reverse bytes instructions +;; vclz crypto vector count leading Zeros instructions +;; vctz crypto vector count lrailing Zeros instructions +;; vrol crypto vector rotate left instructions +;; vror crypto vector rotate right instructions +;; vwsllcrypto vector widening shift left logical instructions +;; vclmul crypto vector carry-less multiply - return low half instructions +;; vclmulh crypto vector carry-less multiply - return high half instructions +;; vghshcrypto vector add-multiply over GHASH Galois-Field instructions +;; vgmulcrypto vector multiply over GHASH Galois-Field instrumctions +;; vaesef crypto vector AES final-round encryption instructions +;; vaesem crypto vector AES middle-round encryption instructions +;; vaesdf crypto vector AES final-round decryption instructions +;; vaesdm crypto vector AES middle-round decryption instructions +;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation instructions +;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation instructions +;; vaeszcrypto vector AES round zero encryption/decryption instructions +;; vsha2ms crypto vector SHA-2 message schedule instructions +;; vsha2ch crypto vector SHA-2 two rounds of compression instructions +;; vsha2cl crypto vector SHA-2 two rounds of compression instructions +;; vsm4kcrypto vector SM4 KeyExpansion instructions +;; vsm4rcrypto vector SM4 Rounds instructions +;; vsm3me crypto vector SM3 Message Expansion instructions +;; vsm3ccrypto vector SM3 Compression instructions (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -446,7 +474,9 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov,vector" + vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" (cond [(eq_attr "got" "load") (const_string "load") ;; If a
[PATCH v7 2/3] RISC-V: Add crypto machine descriptions
Patch v7: Remove mode of const_int_operand and typo. Add newline at the end and comment at the beginning. Patch v6: Swap the operator order of vandn.vv Patch v5: Add vec_duplicate operator. Patch v4: Add process of SEW=64 in RV32 system. Patch v3: Moidfy constrains for crypto vector. Patch v2: Add crypto vector ins into RATIO attr and use vr as destination register. This patch add the crypto machine descriptions(vector-crypto.md) and some new iterators which are used by crypto vector ext. Co-Authored by: Songhe Zhu Co-Authored by: Ciyan Pan gcc/ChangeLog: * config/riscv/iterators.md: Add rotate insn name. * config/riscv/riscv.md: Add new insns name for crypto vector. * config/riscv/vector-iterators.md: Add new iterators for crypto vector. * config/riscv/vector.md: Add the corresponding attr for crypto vector. * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector. --- gcc/config/riscv/iterators.md| 4 +- gcc/config/riscv/riscv.md| 33 +- gcc/config/riscv/vector-crypto.md| 654 +++ gcc/config/riscv/vector-iterators.md | 41 ++ gcc/config/riscv/vector.md | 55 ++- 5 files changed, 766 insertions(+), 21 deletions(-) create mode 100755 gcc/config/riscv/vector-crypto.md diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index ecf033f2fa7..f332fba7031 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -304,7 +304,9 @@ (umax "maxu") (clz "clz") (ctz "ctz") -(popcount "cpop")]) +(popcount "cpop") +(rotate "rol") +(rotatert "ror")]) ;; --- ;; Int Iterators. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ee8b71c22aa..88019a46a53 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -427,6 +427,34 @@ ;; vcompressvector compress instruction ;; vmov whole vector register move ;; vector unknown vector instruction +;; 17. Crypto Vector instructions +;; vandncrypto vector bitwise and-not instructions +;; vbrevcrypto vector reverse bits in elements instructions +;; vbrev8 crypto vector reverse bits in bytes instructions +;; vrev8crypto vector reverse bytes instructions +;; vclz crypto vector count leading Zeros instructions +;; vctz crypto vector count lrailing Zeros instructions +;; vrol crypto vector rotate left instructions +;; vror crypto vector rotate right instructions +;; vwsllcrypto vector widening shift left logical instructions +;; vclmul crypto vector carry-less multiply - return low half instructions +;; vclmulh crypto vector carry-less multiply - return high half instructions +;; vghshcrypto vector add-multiply over GHASH Galois-Field instructions +;; vgmulcrypto vector multiply over GHASH Galois-Field instrumctions +;; vaesef crypto vector AES final-round encryption instructions +;; vaesem crypto vector AES middle-round encryption instructions +;; vaesdf crypto vector AES final-round decryption instructions +;; vaesdm crypto vector AES middle-round decryption instructions +;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation instructions +;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation instructions +;; vaeszcrypto vector AES round zero encryption/decryption instructions +;; vsha2ms crypto vector SHA-2 message schedule instructions +;; vsha2ch crypto vector SHA-2 two rounds of compression instructions +;; vsha2cl crypto vector SHA-2 two rounds of compression instructions +;; vsm4kcrypto vector SM4 KeyExpansion instructions +;; vsm4rcrypto vector SM4 Rounds instructions +;; vsm3me crypto vector SM3 Message Expansion instructions +;; vsm3ccrypto vector SM3 Compression instructions (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -446,7 +474,9 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov,vector" + vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, @@ -3777,6
[PATCH v6 2/3] RISC-V: Add crypto machine descriptions
Patch v6: Swap the operator order of vandn.vv.Make report riscv.exp with "riscv-sim/-march=rv64gc/-mabi=lp64d/-mcmodel=medlow" is passed. Patch v5: Add vec_duplicate operator. Patch v4: Add process of SEW=64 in RV32 system. Patch v3: Moidfy constrains for crypto vector. Patch v2: Add crypto vector ins into RATIO attr and use vr as destination register. This patch add the crypto machine descriptions(vector-crypto.md) and some new iterators which are used by crypto vector ext. Co-Authored by: Songhe Zhu Co-Authored by: Ciyan Pan gcc/ChangeLog: * config/riscv/iterators.md: Add rotate insn name. * config/riscv/riscv.md: Add new insns name for crypto vector. * config/riscv/vector-iterators.md: Add new iterators for crypto vector. * config/riscv/vector.md: Add the corresponding attr for crypto vector. * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector. --- gcc/config/riscv/iterators.md| 4 +- gcc/config/riscv/riscv.md| 33 +- gcc/config/riscv/vector-crypto.md| 635 +++ gcc/config/riscv/vector-iterators.md | 41 ++ gcc/config/riscv/vector.md | 55 ++- 5 files changed, 747 insertions(+), 21 deletions(-) create mode 100755 gcc/config/riscv/vector-crypto.md diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index ecf033f2fa7..f332fba7031 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -304,7 +304,9 @@ (umax "maxu") (clz "clz") (ctz "ctz") -(popcount "cpop")]) +(popcount "cpop") +(rotate "rol") +(rotatert "ror")]) ;; --- ;; Int Iterators. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ee8b71c22aa..88019a46a53 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -427,6 +427,34 @@ ;; vcompressvector compress instruction ;; vmov whole vector register move ;; vector unknown vector instruction +;; 17. Crypto Vector instructions +;; vandncrypto vector bitwise and-not instructions +;; vbrevcrypto vector reverse bits in elements instructions +;; vbrev8 crypto vector reverse bits in bytes instructions +;; vrev8crypto vector reverse bytes instructions +;; vclz crypto vector count leading Zeros instructions +;; vctz crypto vector count lrailing Zeros instructions +;; vrol crypto vector rotate left instructions +;; vror crypto vector rotate right instructions +;; vwsllcrypto vector widening shift left logical instructions +;; vclmul crypto vector carry-less multiply - return low half instructions +;; vclmulh crypto vector carry-less multiply - return high half instructions +;; vghshcrypto vector add-multiply over GHASH Galois-Field instructions +;; vgmulcrypto vector multiply over GHASH Galois-Field instrumctions +;; vaesef crypto vector AES final-round encryption instructions +;; vaesem crypto vector AES middle-round encryption instructions +;; vaesdf crypto vector AES final-round decryption instructions +;; vaesdm crypto vector AES middle-round decryption instructions +;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation instructions +;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation instructions +;; vaeszcrypto vector AES round zero encryption/decryption instructions +;; vsha2ms crypto vector SHA-2 message schedule instructions +;; vsha2ch crypto vector SHA-2 two rounds of compression instructions +;; vsha2cl crypto vector SHA-2 two rounds of compression instructions +;; vsm4kcrypto vector SM4 KeyExpansion instructions +;; vsm4rcrypto vector SM4 Rounds instructions +;; vsm3me crypto vector SM3 Message Expansion instructions +;; vsm3ccrypto vector SM3 Compression instructions (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -446,7 +474,9 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov,vector" + vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, @@ -3777,6 +3807,7 @@ (include
[PATCH v5 2/3] RISC-V: Add crypto machine descriptions
Patch v5: Add vec_duplicate operator. Make report riscv.exp with "riscv-sim/-march=rv64gc/-mabi=lp64d/-mcmodel=medlow" is passed. Patch v4: Add process of SEW=64 in RV32 system. Patch v3: Moidfy constrains for crypto vector. Patch v2: Add crypto vector ins into RATIO attr and use vr as destination register. This patch add the crypto machine descriptions(vector-crypto.md) and some new iterators which are used by crypto vector ext. Co-Authored by: Songhe Zhu Co-Authored by: Ciyan Pan gcc/ChangeLog: * config/riscv/iterators.md: Add rotate insn name. * config/riscv/riscv.md: Add new insns name for crypto vector. * config/riscv/vector-iterators.md: Add new iterators for crypto vector. * config/riscv/vector.md: Add the corresponding attr for crypto vector. * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector. --- gcc/config/riscv/iterators.md| 4 +- gcc/config/riscv/riscv.md| 33 +- gcc/config/riscv/vector-crypto.md| 635 +++ gcc/config/riscv/vector-iterators.md | 41 ++ gcc/config/riscv/vector.md | 55 ++- 5 files changed, 747 insertions(+), 21 deletions(-) create mode 100755 gcc/config/riscv/vector-crypto.md diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index ecf033f2fa7..f332fba7031 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -304,7 +304,9 @@ (umax "maxu") (clz "clz") (ctz "ctz") -(popcount "cpop")]) +(popcount "cpop") +(rotate "rol") +(rotatert "ror")]) ;; --- ;; Int Iterators. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ee8b71c22aa..88019a46a53 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -427,6 +427,34 @@ ;; vcompressvector compress instruction ;; vmov whole vector register move ;; vector unknown vector instruction +;; 17. Crypto Vector instructions +;; vandncrypto vector bitwise and-not instructions +;; vbrevcrypto vector reverse bits in elements instructions +;; vbrev8 crypto vector reverse bits in bytes instructions +;; vrev8crypto vector reverse bytes instructions +;; vclz crypto vector count leading Zeros instructions +;; vctz crypto vector count lrailing Zeros instructions +;; vrol crypto vector rotate left instructions +;; vror crypto vector rotate right instructions +;; vwsllcrypto vector widening shift left logical instructions +;; vclmul crypto vector carry-less multiply - return low half instructions +;; vclmulh crypto vector carry-less multiply - return high half instructions +;; vghshcrypto vector add-multiply over GHASH Galois-Field instructions +;; vgmulcrypto vector multiply over GHASH Galois-Field instrumctions +;; vaesef crypto vector AES final-round encryption instructions +;; vaesem crypto vector AES middle-round encryption instructions +;; vaesdf crypto vector AES final-round decryption instructions +;; vaesdm crypto vector AES middle-round decryption instructions +;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation instructions +;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation instructions +;; vaeszcrypto vector AES round zero encryption/decryption instructions +;; vsha2ms crypto vector SHA-2 message schedule instructions +;; vsha2ch crypto vector SHA-2 two rounds of compression instructions +;; vsha2cl crypto vector SHA-2 two rounds of compression instructions +;; vsm4kcrypto vector SM4 KeyExpansion instructions +;; vsm4rcrypto vector SM4 Rounds instructions +;; vsm3me crypto vector SM3 Message Expansion instructions +;; vsm3ccrypto vector SM3 Compression instructions (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -446,7 +474,9 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov,vector" + vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, @@ -3777,6 +3807,7 @@ (include "thead.md") (include "generic-ooo.md")
Re: Re: [PATCH v4 2/3] RISC-V: Add crypto machine descriptions
2023-12-20 15:12 juzhe.zhong wrote: >+ (and:VI >+ (match_operand:VI 3 "register_operand" "vr, vr, vr, vr") >+ (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr"))) >Swap the order: > >(not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr") > (and:VI > (match_operand:VI 3 "register_operand" "vr, vr, vr, vr") The description in the spec is"Each bit of Op1 is inverted and logically ANDed with the corresponding bits in vs2", so I think the "and" should be placed outside. > >+ (and:VI_QHS >+ (match_operand:VI_QHS 3 "register_operand" "vr, vr,vr, vr") >+ (not: >+ (match_operand: 4 "register_operand" " r, r, r, r"))) > >-> > >+ (and:VI_QHS+ (not:VI_QHS+ (vec_duplicate:VI_QHS > >+ (match_operand: 4 "register_operand" " r, r, r, r"))) >+ (match_operand:VI_QHS 3 "register_operand" "vr, vr,vr, vr")) OK. Will add vec_duplicate. > >Can you add EEW64 vx test on RV32 ? > > > > >juzhe.zh...@rivai.ai > The test cases are added at [PATCH v4 3/3] RISC-V: Add crypto vector api-testing cases. gcc.target/riscv/zvbb_vandn_vx_constraint.c gcc.target/riscv/zvbc_vx_constraint-2.c: New test. gcc.target/riscv/zvbc_vx_constraint-1.c: New test. Thanks.
[PATCH v4 3/3] RISC-V: Add crypto vector api-testing cases.
Patch v4: Add some RV32 vx constraint testcase.
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zvbb-intrinsic.c: New test.
* gcc.target/riscv/zvbb_vandn_vx_constraint.c: New test.
* gcc.target/riscv/zvbc-intrinsic.c: New test.
* gcc.target/riscv/zvbc_vx_constraint-2.c: New test.
* gcc.target/riscv/zvbc_vx_constraint-1.c: New test.
* gcc.target/riscv/zvkb.c: New test.
* gcc.target/riscv/zvkg-intrinsic.c: New test.
* gcc.target/riscv/zvkned-intrinsic.c: New test.
* gcc.target/riscv/zvknha-intrinsic.c: New test.
* gcc.target/riscv/zvknhb-intrinsic.c: New test.
* gcc.target/riscv/zvksed-intrinsic.c: New test.
* gcc.target/riscv/zvksh-intrinsic.c: New test.
---
.../gcc.target/riscv/zvbb-intrinsic.c | 179 ++
.../riscv/zvbb_vandn_vx_constraint.c | 15 ++
.../gcc.target/riscv/zvbc-intrinsic.c | 62 ++
.../gcc.target/riscv/zvbc_vx_constraint-2.c | 14 ++
.../gcc.target/riscv/zvbc_vx_constraint-1.c | 14 ++
gcc/testsuite/gcc.target/riscv/zvkb.c | 13 ++
.../gcc.target/riscv/zvkg-intrinsic.c | 24 +++
.../gcc.target/riscv/zvkned-intrinsic.c | 105 ++
.../gcc.target/riscv/zvknha-intrinsic.c | 33
.../gcc.target/riscv/zvknhb-intrinsic.c | 33
.../gcc.target/riscv/zvksed-intrinsic.c | 33
.../gcc.target/riscv/zvksh-intrinsic.c| 24 +++
12 files changed, 549 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zvbb-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvbb_vandn_vx_constraint.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvbc-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvbc_vx_constraint-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvbc_vx_constraint-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkg-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkned-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvknha-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvknhb-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvksed-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvksh-intrinsic.c
diff --git a/gcc/testsuite/gcc.target/riscv/zvbb-intrinsic.c
b/gcc/testsuite/gcc.target/riscv/zvbb-intrinsic.c
new file mode 100644
index 000..7d436d2a43c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zvbb-intrinsic.c
@@ -0,0 +1,179 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvbb_zve64x -mabi=lp64d -Wno-psabi" } */
+#include
+
+vuint8mf8_t test_vandn_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u8mf8(vs2, vs1, vl);
+}
+
+vuint32m1_t test_vandn_vx_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u32m1(vs2, rs1, vl);
+}
+
+vuint32m2_t test_vandn_vv_u32m2_m(vbool16_t mask, vuint32m2_t vs2, vuint32m2_t
vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m2_m(mask, vs2, vs1, vl);
+}
+
+vuint16mf2_t test_vandn_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t vs2, uint16_t
rs1, size_t vl) {
+ return __riscv_vandn_vx_u16mf2_m(mask, vs2, rs1, vl);
+}
+
+vuint32m4_t test_vandn_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m4_tumu(mask, maskedoff, vs2, vs1, vl);
+}
+
+vuint64m4_t test_vandn_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff,
vuint64m4_t vs2, uint64_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u64m4_tumu(mask, maskedoff, vs2, rs1, vl);
+}
+
+vuint8m8_t test_vbrev_v_u8m8(vuint8m8_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u8m8(vs2, vl);
+}
+
+vuint16m1_t test_vbrev_v_u16m1_m(vbool16_t mask, vuint16m1_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u16m1_m(mask, vs2, vl);
+}
+
+vuint32m4_t test_vbrev_v_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u32m4_tumu(mask, maskedoff, vs2, vl);
+}
+
+vuint16mf4_t test_vbrev8_v_u16mf4(vuint16mf4_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u16mf4(vs2, vl);
+}
+
+vuint32m1_t test_vbrev8_v_u32m1_m(vbool32_t mask, vuint32m1_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u32m1_m(mask, vs2, vl);
+}
+
+vuint64m1_t test_vbrev8_v_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff,
vuint64m1_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u64m1_tumu(mask, maskedoff, vs2, vl);
+}
+
+vuint16m4_t test_vrev8_v_u16m4(vuint16m4_t vs2, size_t vl) {
+ return __riscv_vrev8_v_u16m4(vs2, vl);
+}
+
+vuint8m4_t test_vrev8_v_u8m4_m(vbool2_t mask, vuint8m4_t vs2, size_t vl) {
+
[PATCH v4 2/3] RISC-V: Add crypto machine descriptions
Patch v4: Add process of SEW=64 in RV32 system. Patch v3: Moidfy constrains for crypto vector. Patch v2: Add crypto vector ins into RATIO attr and use vr as destination register. This patch add the crypto machine descriptions(vector-crypto.md) and some new iterators which are used by crypto vector ext. Co-Authored by: Songhe Zhu Co-Authored by: Ciyan Pan gcc/ChangeLog: * config/riscv/iterators.md: Add rotate insn name. * config/riscv/riscv.md: Add new insns name for crypto vector. * config/riscv/vector-iterators.md: Add new iterators for crypto vector. * config/riscv/vector.md: Add the corresponding attr for crypto vector. * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector. --- gcc/config/riscv/iterators.md| 4 +- gcc/config/riscv/riscv.md| 33 +- gcc/config/riscv/vector-crypto.md| 628 +++ gcc/config/riscv/vector-iterators.md | 41 ++ gcc/config/riscv/vector.md | 55 ++- 5 files changed, 740 insertions(+), 21 deletions(-) create mode 100755 gcc/config/riscv/vector-crypto.md diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index ecf033f2fa7..f332fba7031 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -304,7 +304,9 @@ (umax "maxu") (clz "clz") (ctz "ctz") -(popcount "cpop")]) +(popcount "cpop") +(rotate "rol") +(rotatert "ror")]) ;; --- ;; Int Iterators. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ee8b71c22aa..88019a46a53 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -427,6 +427,34 @@ ;; vcompressvector compress instruction ;; vmov whole vector register move ;; vector unknown vector instruction +;; 17. Crypto Vector instructions +;; vandncrypto vector bitwise and-not instructions +;; vbrevcrypto vector reverse bits in elements instructions +;; vbrev8 crypto vector reverse bits in bytes instructions +;; vrev8crypto vector reverse bytes instructions +;; vclz crypto vector count leading Zeros instructions +;; vctz crypto vector count lrailing Zeros instructions +;; vrol crypto vector rotate left instructions +;; vror crypto vector rotate right instructions +;; vwsllcrypto vector widening shift left logical instructions +;; vclmul crypto vector carry-less multiply - return low half instructions +;; vclmulh crypto vector carry-less multiply - return high half instructions +;; vghshcrypto vector add-multiply over GHASH Galois-Field instructions +;; vgmulcrypto vector multiply over GHASH Galois-Field instrumctions +;; vaesef crypto vector AES final-round encryption instructions +;; vaesem crypto vector AES middle-round encryption instructions +;; vaesdf crypto vector AES final-round decryption instructions +;; vaesdm crypto vector AES middle-round decryption instructions +;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation instructions +;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation instructions +;; vaeszcrypto vector AES round zero encryption/decryption instructions +;; vsha2ms crypto vector SHA-2 message schedule instructions +;; vsha2ch crypto vector SHA-2 two rounds of compression instructions +;; vsha2cl crypto vector SHA-2 two rounds of compression instructions +;; vsm4kcrypto vector SM4 KeyExpansion instructions +;; vsm4rcrypto vector SM4 Rounds instructions +;; vsm3me crypto vector SM3 Message Expansion instructions +;; vsm3ccrypto vector SM3 Compression instructions (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -446,7 +474,9 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov,vector" + vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, @@ -3777,6 +3807,7 @@ (include "thead.md") (include "generic-ooo.md") (include "vector.md") +(include "vector-crypto.md") (include "zicond.md") (include "sfb.md") (include "zc.md") diff --git
[PATCH v4 1/3] RISC-V: Add crypto vector builtin function.
Patch v4:Merge crypto vector function.def into vector.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
Add new function_base for crypto vector.
(class bitmanip): Ditto.
(class b_reverse):Ditto.
(class vwsll): Ditto.
(class clmul): Ditto.
(class vg_nhab): Ditto.
(class crypto_vv):Ditto.
(class crypto_vi):Ditto.
(class vaeskf2_vsm3c):Ditto.
(class vsm3me): Ditto.
(BASE): Add BASE declaration for crypto vector.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXTENSIONS):
Add crypto vector intrinsic definition.
(vbrev): Ditto.
(vclz): Ditto.
(vctz): Ditto.
(vwsll): Ditto.
(vandn): Ditto.
(vbrev8): Ditto.
(vrev8): Ditto.
(vrol): Ditto.
(vror): Ditto.
(vclmul): Ditto.
(vclmulh): Ditto.
(vghsh): Ditto.
(vgmul): Ditto.
(vaesef): Ditto.
(vaesem): Ditto.
(vaesdf): Ditto.
(vaesdm): Ditto.
(vaesz): Ditto.
(vaeskf1): Ditto.
(vaeskf2): Ditto.
(vsha2ms): Ditto.
(vsha2ch): Ditto.
(vsha2cl): Ditto.
(vsm4k): Ditto.
(vsm4r): Ditto.
(vsm3me): Ditto.
(vsm3c): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add new function_shape for crypto vector.
(struct crypto_vi_def): Ditto.
(struct crypto_vv_no_op_type_def): Ditto.
(SHAPE): Add SHAPE declaration of crypto vector.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_CRYPTO_SEW32_OPS):
Add new data type for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
Add new data struct for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(registered_function::overloaded_hash): Processing size_t uimm for C
overloaded func.
* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
---
.../riscv/riscv-vector-builtins-bases.cc | 264 +-
.../riscv/riscv-vector-builtins-bases.h | 28 ++
.../riscv/riscv-vector-builtins-functions.def | 94 +++
.../riscv/riscv-vector-builtins-shapes.cc | 87 +-
.../riscv/riscv-vector-builtins-shapes.h | 4 +
.../riscv/riscv-vector-builtins-types.def | 25 ++
gcc/config/riscv/riscv-vector-builtins.cc | 133 -
gcc/config/riscv/riscv-vector-builtins.def| 1 +
8 files changed, 633 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d70468542ee..d12bb89f91c 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2127,6 +2127,212 @@ public:
}
};
+/* Below implements are vector crypto */
+/* Implements vandn.[vv,vx] */
+class vandn : public function_base
+{
+public:
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_vandn (e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_vandn_scalar (e.vector_mode
()));
+ default:
+gcc_unreachable ();
+ }
+ }
+};
+
+/* Implements vrol/vror/clz/ctz. */
+template
+class bitmanip : public function_base
+{
+public:
+ bool apply_tail_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool apply_mask_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool has_merge_operand_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+{
+ case OP_TYPE_v:
+ case OP_TYPE_vv:
+return
[committed] RISC-V: Add required_extensions in function_group
In order to add other vector related extensions in the future, this
patch add one more parameter in the function_group_info, it will be
used to determine whether intrinsic registration processing is required.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXTENSIONS):
Add new macro for match function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
Add one more parameter for macro
expanding.
(handle_pragma_vector): Add match function calls.
* config/riscv/riscv-vector-builtins.h (enum required_ext):
Add enum defination for required extension.
(struct function_group_info): Add one more parameter for checking
required-ext.
---
.../riscv/riscv-vector-builtins-functions.def | 2 +
gcc/config/riscv/riscv-vector-builtins.cc | 7 ++-
gcc/config/riscv/riscv-vector-builtins.h | 46 +++
3 files changed, 53 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 1c37fd5fffe..03421d5bc10 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -36,6 +36,7 @@ along with GCC; see the file COPYING3. If not see
#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)
#endif
+#define REQUIRED_EXTENSIONS VECTOR_EXT
/* Internal helper functions for gimple fold use. */
DEF_RVV_FUNCTION (read_vl, read_vl, none_preds, p_none_void_ops)
DEF_RVV_FUNCTION (vlenb, vlenb, none_preds, ul_none_void_ops)
@@ -650,5 +651,6 @@ DEF_RVV_FUNCTION (vsoxseg, seg_indexed_loadstore,
none_m_preds, tuple_v_scalar_p
DEF_RVV_FUNCTION (vsoxseg, seg_indexed_loadstore, none_m_preds,
tuple_v_scalar_ptr_eew32_index_ops)
DEF_RVV_FUNCTION (vsoxseg, seg_indexed_loadstore, none_m_preds,
tuple_v_scalar_ptr_eew64_index_ops)
DEF_RVV_FUNCTION (vlsegff, seg_fault_load, full_preds,
tuple_v_scalar_const_ptr_size_ptr_ops)
+#undef REQUIRED_EXTENSIONS
#undef DEF_RVV_FUNCTION
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 6330a3a41c3..4e2c66c2de7 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2685,7 +2685,7 @@ static CONSTEXPR const function_type_info
function_types[] = {
/* A list of all RVV intrinsic functions. */
static function_group_info function_groups[] = {
#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)
\
- {#NAME, ::NAME, ::SHAPE, PREDS, OPS_INFO},
+ {#NAME, ::NAME, ::SHAPE, PREDS, OPS_INFO, REQUIRED_EXTENSIONS},
#include "riscv-vector-builtins-functions.def"
};
@@ -4413,7 +4413,10 @@ handle_pragma_vector ()
= new hash_table (1023);
function_builder builder;
for (unsigned int i = 0; i < ARRAY_SIZE (function_groups); ++i)
-builder.register_function_group (function_groups[i]);
+ {
+if (function_groups[i].match (function_groups[i].required_extensions))
+ builder.register_function_group (function_groups[i]);
+ }
}
/* Return the function decl with RVV function subcode CODE, or error_mark_node
diff --git a/gcc/config/riscv/riscv-vector-builtins.h
b/gcc/config/riscv/riscv-vector-builtins.h
index cd8ccab1724..4f38c09d73d 100644
--- a/gcc/config/riscv/riscv-vector-builtins.h
+++ b/gcc/config/riscv/riscv-vector-builtins.h
@@ -110,6 +110,21 @@ static const unsigned int CP_WRITE_CSR = 1U << 5;
#define RVV_REQUIRE_MIN_VLEN_64 (1 << 5) /* Require TARGET_MIN_VLEN >=
64. */
#define RVV_REQUIRE_ELEN_FP_16 (1 << 6) /* Require FP ELEN >= 32. */
+/* Enumerates the required extensions. */
+enum required_ext
+{
+ VECTOR_EXT, /* Vector extension */
+ ZVBB_EXT,/* Cryto vector Zvbb sub-ext */
+ ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */
+ ZVBC_EXT,/* Crypto vector Zvbc sub-ext */
+ ZVKG_EXT,/* Crypto vector Zvkg sub-ext */
+ ZVKNED_EXT, /* Crypto vector Zvkned sub-ext */
+ ZVKNHA_OR_ZVKNHB_EXT, /* Crypto vector Zvknh[ab] sub-ext */
+ ZVKNHB_EXT, /* Crypto vector Zvknhb sub-ext */
+ ZVKSED_EXT, /* Crypto vector Zvksed sub-ext */
+ ZVKSH_EXT, /* Crypto vector Zvksh sub-ext */
+};
+
/* Enumerates the RVV operand types. */
enum operand_type_index
{
@@ -212,6 +227,35 @@ class function_shape;
/* Static information about a set of functions. */
struct function_group_info
{
+ /* Return true if required extension is enabled */
+ bool match (required_ext ext_value) const
+ {
+switch (ext_value)
+{
+ case VECTOR_EXT:
+return TARGET_VECTOR;
+ case ZVBB_EXT:
+return TARGET_ZVBB;
+ case ZVBB_OR_ZVKB_EXT:
+return (TARGET_ZVBB || TARGET_ZVKB);
+ case ZVBC_EXT:
+return TARGET_ZVBC;
+ case ZVKG_EXT:
+return TARGET_ZVKG;
+ case ZVKNED_EXT:
+return
[PATCH] RISC-V: Add required_extensions in function_group
In order to add other vector related extensions in the future, this
patch add one more parameter in the function_group_info, it will be
used to determine whether intrinsic registration processing is required.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-functions.def
(REQUIRED_EXTENSIONS):
Add new macro for match function.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
Add one more parameter for macro
expanding.
(handle_pragma_vector): Add match function calls.
* config/riscv/riscv-vector-builtins.h (enum required_ext):
Add enum defination for required extension.
(struct function_group_info): Add one more parameter for checking
required-ext.
---
.../riscv/riscv-vector-builtins-functions.def | 2 +
gcc/config/riscv/riscv-vector-builtins.cc | 7 ++-
gcc/config/riscv/riscv-vector-builtins.h | 46 +++
3 files changed, 53 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 1c37fd5fffe..03421d5bc10 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -36,6 +36,7 @@ along with GCC; see the file COPYING3. If not see
#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)
#endif
+#define REQUIRED_EXTENSIONS VECTOR_EXT
/* Internal helper functions for gimple fold use. */
DEF_RVV_FUNCTION (read_vl, read_vl, none_preds, p_none_void_ops)
DEF_RVV_FUNCTION (vlenb, vlenb, none_preds, ul_none_void_ops)
@@ -650,5 +651,6 @@ DEF_RVV_FUNCTION (vsoxseg, seg_indexed_loadstore,
none_m_preds, tuple_v_scalar_p
DEF_RVV_FUNCTION (vsoxseg, seg_indexed_loadstore, none_m_preds,
tuple_v_scalar_ptr_eew32_index_ops)
DEF_RVV_FUNCTION (vsoxseg, seg_indexed_loadstore, none_m_preds,
tuple_v_scalar_ptr_eew64_index_ops)
DEF_RVV_FUNCTION (vlsegff, seg_fault_load, full_preds,
tuple_v_scalar_const_ptr_size_ptr_ops)
+#undef REQUIRED_EXTENSIONS
#undef DEF_RVV_FUNCTION
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
b/gcc/config/riscv/riscv-vector-builtins.cc
index 6330a3a41c3..4e2c66c2de7 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2685,7 +2685,7 @@ static CONSTEXPR const function_type_info
function_types[] = {
/* A list of all RVV intrinsic functions. */
static function_group_info function_groups[] = {
#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO)
\
- {#NAME, ::NAME, ::SHAPE, PREDS, OPS_INFO},
+ {#NAME, ::NAME, ::SHAPE, PREDS, OPS_INFO, REQUIRED_EXTENSIONS},
#include "riscv-vector-builtins-functions.def"
};
@@ -4413,7 +4413,10 @@ handle_pragma_vector ()
= new hash_table (1023);
function_builder builder;
for (unsigned int i = 0; i < ARRAY_SIZE (function_groups); ++i)
-builder.register_function_group (function_groups[i]);
+ {
+if (function_groups[i].match (function_groups[i].required_extensions))
+ builder.register_function_group (function_groups[i]);
+ }
}
/* Return the function decl with RVV function subcode CODE, or error_mark_node
diff --git a/gcc/config/riscv/riscv-vector-builtins.h
b/gcc/config/riscv/riscv-vector-builtins.h
index cd8ccab1724..4f38c09d73d 100644
--- a/gcc/config/riscv/riscv-vector-builtins.h
+++ b/gcc/config/riscv/riscv-vector-builtins.h
@@ -110,6 +110,21 @@ static const unsigned int CP_WRITE_CSR = 1U << 5;
#define RVV_REQUIRE_MIN_VLEN_64 (1 << 5) /* Require TARGET_MIN_VLEN >=
64. */
#define RVV_REQUIRE_ELEN_FP_16 (1 << 6) /* Require FP ELEN >= 32. */
+/* Enumerates the required extensions. */
+enum required_ext
+{
+ VECTOR_EXT, /* Vector extension */
+ ZVBB_EXT,/* Cryto vector Zvbb sub-ext */
+ ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */
+ ZVBC_EXT,/* Crypto vector Zvbc sub-ext */
+ ZVKG_EXT,/* Crypto vector Zvkg sub-ext */
+ ZVKNED_EXT, /* Crypto vector Zvkned sub-ext */
+ ZVKNHA_OR_ZVKNHB_EXT, /* Crypto vector Zvknh[ab] sub-ext */
+ ZVKNHB_EXT, /* Crypto vector Zvknhb sub-ext */
+ ZVKSED_EXT, /* Crypto vector Zvksed sub-ext */
+ ZVKSH_EXT, /* Crypto vector Zvksh sub-ext */
+};
+
/* Enumerates the RVV operand types. */
enum operand_type_index
{
@@ -212,6 +227,35 @@ class function_shape;
/* Static information about a set of functions. */
struct function_group_info
{
+ /* Return true if required extension is enabled */
+ bool match (required_ext ext_value) const
+ {
+switch (ext_value)
+{
+ case VECTOR_EXT:
+return TARGET_VECTOR;
+ case ZVBB_EXT:
+return TARGET_ZVBB;
+ case ZVBB_OR_ZVKB_EXT:
+return (TARGET_ZVBB || TARGET_ZVKB);
+ case ZVBC_EXT:
+return TARGET_ZVBC;
+ case ZVKG_EXT:
+return TARGET_ZVKG;
+ case ZVKNED_EXT:
+return
[committed] Revert "RISC-V: Add avail interface into function_group_info"
This reverts commit ce7e66787b5b4ad385b21756da5a89171d233ddc. Will refactor this part in the same way as aarch64 sve. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Revert changes. (read_vl): Ditto. (vlenb): Ditto. (vsetvl): Ditto. (vsetvlmax): Ditto. (vle): Ditto. (vse): Ditto. (vlm): Ditto. (vsm): Ditto. (vlse): Ditto. (vsse): Ditto. (vluxei8): Ditto. (vluxei16): Ditto. (vluxei32): Ditto. (vluxei64): Ditto. (vloxei8): Ditto. (vloxei16): Ditto. (vloxei32): Ditto. (vloxei64): Ditto. (vsuxei8): Ditto. (vsuxei16): Ditto. (vsuxei32): Ditto. (vsuxei64): Ditto. (vsoxei8): Ditto. (vsoxei16): Ditto. (vsoxei32): Ditto. (vsoxei64): Ditto. (vleff): Ditto. (vadd): Ditto. (vsub): Ditto. (vrsub): Ditto. (vneg): Ditto. (vwaddu): Ditto. (vwsubu): Ditto. (vwadd): Ditto. (vwsub): Ditto. (vwcvt_x): Ditto. (vwcvtu_x): Ditto. (vzext): Ditto. (vsext): Ditto. (vadc): Ditto. (vmadc): Ditto. (vsbc): Ditto. (vmsbc): Ditto. (vand): Ditto. (vor): Ditto. (vxor): Ditto. (vnot): Ditto. (vsll): Ditto. (vsra): Ditto. (vsrl): Ditto. (vnsrl): Ditto. (vnsra): Ditto. (vncvt_x): Ditto. (vmseq): Ditto. (vmsne): Ditto. (vmsltu): Ditto. (vmslt): Ditto. (vmsleu): Ditto. (vmsle): Ditto. (vmsgtu): Ditto. (vmsgt): Ditto. (vmsgeu): Ditto. (vmsge): Ditto. (vminu): Ditto. (vmin): Ditto. (vmaxu): Ditto. (vmax): Ditto. (vmul): Ditto. (vmulh): Ditto. (vmulhu): Ditto. (vmulhsu): Ditto. (vdivu): Ditto. (vdiv): Ditto. (vremu): Ditto. (vrem): Ditto. (vwmul): Ditto. (vwmulu): Ditto. (vwmulsu): Ditto. (vmacc): Ditto. (vnmsac): Ditto. (vmadd): Ditto. (vnmsub): Ditto. (vwmaccu): Ditto. (vwmacc): Ditto. (vwmaccsu): Ditto. (vwmaccus): Ditto. (vmerge): Ditto. (vmv_v): Ditto. (vsaddu): Ditto. (vsadd): Ditto. (vssubu): Ditto. (vssub): Ditto. (vaaddu): Ditto. (vaadd): Ditto. (vasubu): Ditto. (vasub): Ditto. (vsmul): Ditto. (vssrl): Ditto. (vssra): Ditto. (vnclipu): Ditto. (vnclip): Ditto. (vfadd): Ditto. (vfsub): Ditto. (vfrsub): Ditto. (vfadd_frm): Ditto. (vfsub_frm): Ditto. (vfrsub_frm): Ditto. (vfwadd): Ditto. (vfwsub): Ditto. (vfwadd_frm): Ditto. (vfwsub_frm): Ditto. (vfmul): Ditto. (vfdiv): Ditto. (vfrdiv): Ditto. (vfmul_frm): Ditto. (vfdiv_frm): Ditto. (vfrdiv_frm): Ditto. (vfwmul): Ditto. (vfwmul_frm): Ditto. (vfmacc): Ditto. (vfnmsac): Ditto. (vfmadd): Ditto. (vfnmsub): Ditto. (vfnmacc): Ditto. (vfmsac): Ditto. (vfnmadd): Ditto. (vfmsub): Ditto. (vfmacc_frm): Ditto. (vfnmacc_frm): Ditto. (vfmsac_frm): Ditto. (vfnmsac_frm): Ditto. (vfmadd_frm): Ditto. (vfnmadd_frm): Ditto. (vfmsub_frm): Ditto. (vfnmsub_frm): Ditto. (vfwmacc): Ditto. (vfwnmacc): Ditto. (vfwmsac): Ditto. (vfwnmsac): Ditto. (vfwmacc_frm): Ditto. (vfwnmacc_frm): Ditto. (vfwmsac_frm): Ditto. (vfwnmsac_frm): Ditto. (vfsqrt): Ditto. (vfsqrt_frm): Ditto. (vfrsqrt7): Ditto. (vfrec7): Ditto. (vfrec7_frm): Ditto. (vfmin): Ditto. (vfmax): Ditto. (vfsgnj): Ditto. (vfsgnjn): Ditto. (vfsgnjx): Ditto. (vfneg): Ditto. (vfabs): Ditto. (vmfeq): Ditto. (vmfne): Ditto. (vmflt): Ditto. (vmfle): Ditto. (vmfgt): Ditto. (vmfge): Ditto. (vfclass): Ditto. (vfmerge): Ditto. (vfmv_v): Ditto. (vfcvt_x): Ditto. (vfcvt_xu): Ditto. (vfcvt_rtz_x): Ditto. (vfcvt_rtz_xu): Ditto. (vfcvt_f): Ditto. (vfcvt_x_frm): Ditto. (vfcvt_xu_frm): Ditto. (vfcvt_f_frm): Ditto. (vfwcvt_x): Ditto. (vfwcvt_xu): Ditto. (vfwcvt_rtz_x): Ditto. (vfwcvt_rtz_xu): Ditto. (vfwcvt_f): Ditto. (vfwcvt_x_frm): Ditto. (vfwcvt_xu_frm): Ditto. (vfncvt_x): Ditto. (vfncvt_xu): Ditto. (vfncvt_rtz_x): Ditto.
[PATCH] Revert "RISC-V: Add avail interface into function_group_info"
This reverts commit ce7e66787b5b4ad385b21756da5a89171d233ddc. Will refactor this part in the same way as aarch64 sve. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Revert changes. (read_vl): Ditto. (vlenb): Ditto. (vsetvl): Ditto. (vsetvlmax): Ditto. (vle): Ditto. (vse): Ditto. (vlm): Ditto. (vsm): Ditto. (vlse): Ditto. (vsse): Ditto. (vluxei8): Ditto. (vluxei16): Ditto. (vluxei32): Ditto. (vluxei64): Ditto. (vloxei8): Ditto. (vloxei16): Ditto. (vloxei32): Ditto. (vloxei64): Ditto. (vsuxei8): Ditto. (vsuxei16): Ditto. (vsuxei32): Ditto. (vsuxei64): Ditto. (vsoxei8): Ditto. (vsoxei16): Ditto. (vsoxei32): Ditto. (vsoxei64): Ditto. (vleff): Ditto. (vadd): Ditto. (vsub): Ditto. (vrsub): Ditto. (vneg): Ditto. (vwaddu): Ditto. (vwsubu): Ditto. (vwadd): Ditto. (vwsub): Ditto. (vwcvt_x): Ditto. (vwcvtu_x): Ditto. (vzext): Ditto. (vsext): Ditto. (vadc): Ditto. (vmadc): Ditto. (vsbc): Ditto. (vmsbc): Ditto. (vand): Ditto. (vor): Ditto. (vxor): Ditto. (vnot): Ditto. (vsll): Ditto. (vsra): Ditto. (vsrl): Ditto. (vnsrl): Ditto. (vnsra): Ditto. (vncvt_x): Ditto. (vmseq): Ditto. (vmsne): Ditto. (vmsltu): Ditto. (vmslt): Ditto. (vmsleu): Ditto. (vmsle): Ditto. (vmsgtu): Ditto. (vmsgt): Ditto. (vmsgeu): Ditto. (vmsge): Ditto. (vminu): Ditto. (vmin): Ditto. (vmaxu): Ditto. (vmax): Ditto. (vmul): Ditto. (vmulh): Ditto. (vmulhu): Ditto. (vmulhsu): Ditto. (vdivu): Ditto. (vdiv): Ditto. (vremu): Ditto. (vrem): Ditto. (vwmul): Ditto. (vwmulu): Ditto. (vwmulsu): Ditto. (vmacc): Ditto. (vnmsac): Ditto. (vmadd): Ditto. (vnmsub): Ditto. (vwmaccu): Ditto. (vwmacc): Ditto. (vwmaccsu): Ditto. (vwmaccus): Ditto. (vmerge): Ditto. (vmv_v): Ditto. (vsaddu): Ditto. (vsadd): Ditto. (vssubu): Ditto. (vssub): Ditto. (vaaddu): Ditto. (vaadd): Ditto. (vasubu): Ditto. (vasub): Ditto. (vsmul): Ditto. (vssrl): Ditto. (vssra): Ditto. (vnclipu): Ditto. (vnclip): Ditto. (vfadd): Ditto. (vfsub): Ditto. (vfrsub): Ditto. (vfadd_frm): Ditto. (vfsub_frm): Ditto. (vfrsub_frm): Ditto. (vfwadd): Ditto. (vfwsub): Ditto. (vfwadd_frm): Ditto. (vfwsub_frm): Ditto. (vfmul): Ditto. (vfdiv): Ditto. (vfrdiv): Ditto. (vfmul_frm): Ditto. (vfdiv_frm): Ditto. (vfrdiv_frm): Ditto. (vfwmul): Ditto. (vfwmul_frm): Ditto. (vfmacc): Ditto. (vfnmsac): Ditto. (vfmadd): Ditto. (vfnmsub): Ditto. (vfnmacc): Ditto. (vfmsac): Ditto. (vfnmadd): Ditto. (vfmsub): Ditto. (vfmacc_frm): Ditto. (vfnmacc_frm): Ditto. (vfmsac_frm): Ditto. (vfnmsac_frm): Ditto. (vfmadd_frm): Ditto. (vfnmadd_frm): Ditto. (vfmsub_frm): Ditto. (vfnmsub_frm): Ditto. (vfwmacc): Ditto. (vfwnmacc): Ditto. (vfwmsac): Ditto. (vfwnmsac): Ditto. (vfwmacc_frm): Ditto. (vfwnmacc_frm): Ditto. (vfwmsac_frm): Ditto. (vfwnmsac_frm): Ditto. (vfsqrt): Ditto. (vfsqrt_frm): Ditto. (vfrsqrt7): Ditto. (vfrec7): Ditto. (vfrec7_frm): Ditto. (vfmin): Ditto. (vfmax): Ditto. (vfsgnj): Ditto. (vfsgnjn): Ditto. (vfsgnjx): Ditto. (vfneg): Ditto. (vfabs): Ditto. (vmfeq): Ditto. (vmfne): Ditto. (vmflt): Ditto. (vmfle): Ditto. (vmfgt): Ditto. (vmfge): Ditto. (vfclass): Ditto. (vfmerge): Ditto. (vfmv_v): Ditto. (vfcvt_x): Ditto. (vfcvt_xu): Ditto. (vfcvt_rtz_x): Ditto. (vfcvt_rtz_xu): Ditto. (vfcvt_f): Ditto. (vfcvt_x_frm): Ditto. (vfcvt_xu_frm): Ditto. (vfcvt_f_frm): Ditto. (vfwcvt_x): Ditto. (vfwcvt_xu): Ditto. (vfwcvt_rtz_x): Ditto. (vfwcvt_rtz_xu): Ditto. (vfwcvt_f): Ditto. (vfwcvt_x_frm): Ditto. (vfwcvt_xu_frm): Ditto. (vfncvt_x): Ditto. (vfncvt_xu): Ditto. (vfncvt_rtz_x): Ditto.
[committed] RISC-V:Add crypto vector implied ISA info.
Due to the crypto vector entension is depend on the Vector extension,
so add the implied ISA info with the corresponding crypto vector extension.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Modify implied ISA info.
* config/riscv/arch-canonicalize: Add crypto vector implied info.
---
gcc/common/config/riscv/riscv-common.cc | 9 +
gcc/config/riscv/arch-canonicalize | 21 +++--
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 4d5a2f874a2..76987598143 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -145,6 +145,15 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvksc", "zvbc"},
{"zvksg", "zvks"},
{"zvksg", "zvkg"},
+ {"zvbb", "zvkb"},
+ {"zvbc", "zve64x"},
+ {"zvkb", "zve32x"},
+ {"zvkg", "zve32x"},
+ {"zvkned", "zve32x"},
+ {"zvknha", "zve32x"},
+ {"zvknhb", "zve64x"},
+ {"zvksed", "zve32x"},
+ {"zvksh", "zve32x"},
{"zfh", "zfhmin"},
{"zfhmin", "f"},
diff --git a/gcc/config/riscv/arch-canonicalize
b/gcc/config/riscv/arch-canonicalize
index ea2f67a0944..a8f47a1752b 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -69,12 +69,21 @@ IMPLIED_EXT = {
"zvl32768b" : ["zvl16384b"],
"zvl65536b" : ["zvl32768b"],
- "zvkn" : ["zvkned", "zvknhb", "zvbb", "zvkt"],
- "zvknc" : ["zvkn", "zvbc"],
- "zvkng" : ["zvkn", "zvkg"],
- "zvks" : ["zvksed", "zvksh", "zvbb", "zvkt"],
- "zvksc" : ["zvks", "zvbc"],
- "zvksg" : ["zvks", "zvkg"],
+ "zvkn" : ["zvkned", "zvknhb", "zvkb", "zvkt"],
+ "zvknc" : ["zvkn", "zvbc"],
+ "zvkng" : ["zvkn", "zvkg"],
+ "zvks" : ["zvksed", "zvksh", "zvkb", "zvkt"],
+ "zvksc" : ["zvks", "zvbc"],
+ "zvksg" : ["zvks", "zvkg"],
+ "zvbb" : ["zvkb"],
+ "zvbc" : ["zve64x"],
+ "zvkb" : ["zve32x"],
+ "zvkg" : ["zve32x"],
+ "zvkned" : ["zve32x"],
+ "zvknha" : ["zve32x"],
+ "zvknhb" : ["zve64x"],
+ "zvksed" : ["zve32x"],
+ "zvksh" : ["zve32x"],
}
def arch_canonicalize(arch, isa_spec):
--
2.17.1
Re: Re: [PATCH v3 2/4] RISC-V: Add crypto vector builtin function.
2023-12-13 18:18 juzhe.zhong wrote:
>
>
>+ multiple_p (GET_MODE_BITSIZE (e.arg_mode (0)),
>+ GET_MODE_BITSIZE (e.arg_mode (1)), );
>
>Change it into gcc_assert (multiple_p (...))
>
>+/* A list of all Vector Crypto intrinsic functions. */
>+static function_group_info cryoto_function_groups[] = {
>+#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO, AVAIL) \
>+ {#NAME, ::NAME, ::SHAPE, PREDS, OPS_INFO,\
>+ riscv_vector_avail_ ## AVAIL},
>+#include "riscv-vector-crypto-builtins-functions.def"
>+};
>Why do you add this ? I think it should belong to function_groups.
The original intention of this modification was to make the processing flow of
the crypto vector more clearer.
If you think it should merge into V extension, I will do it.
Thanks.
Feng Wang
>
>+ /* Dfine the crypto vector builtin functions. */
>+ for (unsigned int i = 0; i < ARRAY_SIZE (cryoto_function_groups); ++i)
>+ {
>+ function_group_info *f = _function_groups[i];
>+ if (f->avail && f->avail ())
>+ builder.register_function_group (cryoto_function_groups[i]);
>+ }
>
>
>I think it should be:
>
>for (unsigned int i = 0; i < ARRAY_SIZE (function_groups); ++i)
> if (avail)
> builder.register_function_group (function_groups[i]);
>
>
>
>
>juzhe.zh...@rivai.ai
>
[PATCH v3 4/4] RISC-V: Add crypto vector api-testing cases.
Patch v3: Refine crypto vector api-testing cases.
Patch v2: Update march info according to the change of riscv-common.c
This patch add crypto vector api-testing cases based on
https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/vector-crypto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zvbb-intrinsic.c: New test.
* gcc.target/riscv/zvbc-intrinsic.c: New test.
* gcc.target/riscv/zvkb.c: New test.
* gcc.target/riscv/zvkg-intrinsic.c: New test.
* gcc.target/riscv/zvkned-intrinsic.c: New test.
* gcc.target/riscv/zvknha-intrinsic.c: New test.
* gcc.target/riscv/zvknhb-intrinsic.c: New test.
* gcc.target/riscv/zvksed-intrinsic.c: New test.
* gcc.target/riscv/zvksh-intrinsic.c: New test.
---
.../gcc.target/riscv/zvbb-intrinsic.c | 179 ++
.../gcc.target/riscv/zvbc-intrinsic.c | 62 ++
gcc/testsuite/gcc.target/riscv/zvkb.c | 13 ++
.../gcc.target/riscv/zvkg-intrinsic.c | 24 +++
.../gcc.target/riscv/zvkned-intrinsic.c | 105 ++
.../gcc.target/riscv/zvknha-intrinsic.c | 33
.../gcc.target/riscv/zvknhb-intrinsic.c | 33
.../gcc.target/riscv/zvksed-intrinsic.c | 33
.../gcc.target/riscv/zvksh-intrinsic.c| 24 +++
9 files changed, 506 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zvbb-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvbc-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkb.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkg-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvkned-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvknha-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvknhb-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvksed-intrinsic.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvksh-intrinsic.c
diff --git a/gcc/testsuite/gcc.target/riscv/zvbb-intrinsic.c
b/gcc/testsuite/gcc.target/riscv/zvbb-intrinsic.c
new file mode 100644
index 000..7d436d2a43c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zvbb-intrinsic.c
@@ -0,0 +1,179 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvbb_zve64x -mabi=lp64d -Wno-psabi" } */
+#include
+
+vuint8mf8_t test_vandn_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u8mf8(vs2, vs1, vl);
+}
+
+vuint32m1_t test_vandn_vx_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u32m1(vs2, rs1, vl);
+}
+
+vuint32m2_t test_vandn_vv_u32m2_m(vbool16_t mask, vuint32m2_t vs2, vuint32m2_t
vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m2_m(mask, vs2, vs1, vl);
+}
+
+vuint16mf2_t test_vandn_vx_u16mf2_m(vbool32_t mask, vuint16mf2_t vs2, uint16_t
rs1, size_t vl) {
+ return __riscv_vandn_vx_u16mf2_m(mask, vs2, rs1, vl);
+}
+
+vuint32m4_t test_vandn_vv_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) {
+ return __riscv_vandn_vv_u32m4_tumu(mask, maskedoff, vs2, vs1, vl);
+}
+
+vuint64m4_t test_vandn_vx_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff,
vuint64m4_t vs2, uint64_t rs1, size_t vl) {
+ return __riscv_vandn_vx_u64m4_tumu(mask, maskedoff, vs2, rs1, vl);
+}
+
+vuint8m8_t test_vbrev_v_u8m8(vuint8m8_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u8m8(vs2, vl);
+}
+
+vuint16m1_t test_vbrev_v_u16m1_m(vbool16_t mask, vuint16m1_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u16m1_m(mask, vs2, vl);
+}
+
+vuint32m4_t test_vbrev_v_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff,
vuint32m4_t vs2, size_t vl) {
+ return __riscv_vbrev_v_u32m4_tumu(mask, maskedoff, vs2, vl);
+}
+
+vuint16mf4_t test_vbrev8_v_u16mf4(vuint16mf4_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u16mf4(vs2, vl);
+}
+
+vuint32m1_t test_vbrev8_v_u32m1_m(vbool32_t mask, vuint32m1_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u32m1_m(mask, vs2, vl);
+}
+
+vuint64m1_t test_vbrev8_v_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff,
vuint64m1_t vs2, size_t vl) {
+ return __riscv_vbrev8_v_u64m1_tumu(mask, maskedoff, vs2, vl);
+}
+
+vuint16m4_t test_vrev8_v_u16m4(vuint16m4_t vs2, size_t vl) {
+ return __riscv_vrev8_v_u16m4(vs2, vl);
+}
+
+vuint8m4_t test_vrev8_v_u8m4_m(vbool2_t mask, vuint8m4_t vs2, size_t vl) {
+ return __riscv_vrev8_v_u8m4_m(mask, vs2, vl);
+}
+
+vuint32m1_t test_vrev8_v_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff,
vuint32m1_t vs2, size_t vl) {
+ return __riscv_vrev8_v_u32m1_tumu(mask, maskedoff, vs2, vl);
+}
+
+vuint8m8_t test_vrol_vv_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) {
+ return __riscv_vrol_vv_u8m8(vs2, vs1, vl);
+}
+
+vuint16m4_t test_vrol_vx_u16m4(vuint16m4_t vs2, size_t rs1, size_t vl) {
+ return __riscv_vrol_vx_u16m4(vs2, rs1, vl);
+}
+
+vuint16mf2_t test_vrol_vv_u16mf2_m(vbool32_t mask, vuint16mf2_t vs2,
vuint16mf2_t vs1, size_t vl) {
+ return __riscv_vrol_vv_u16mf2_m(mask, vs2,
[PATCH v3 3/4] RISC-V: Add crypto machine descriptions
Patch v3: Moidfy constrains for crypto vector. Patch v2: Add crypto vector ins into RATIO attr and use vr as destination register. This patch add the crypto machine descriptions(vector-crypto.md) and some new iterators which are used by crypto vector ext. Co-Authored by: Songhe Zhu Co-Authored by: Ciyan Pan gcc/ChangeLog: * config/riscv/iterators.md: Add rotate insn name. * config/riscv/riscv.md: Add new insns name for crypto vector. * config/riscv/vector-iterators.md: Add new iterators for crypto vector. * config/riscv/vector.md: Add the corresponding attr for crypto vector. * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector. --- gcc/config/riscv/iterators.md| 4 +- gcc/config/riscv/riscv.md| 33 +- gcc/config/riscv/vector-crypto.md| 502 +++ gcc/config/riscv/vector-iterators.md | 41 +++ gcc/config/riscv/vector.md | 55 ++- 5 files changed, 614 insertions(+), 21 deletions(-) create mode 100755 gcc/config/riscv/vector-crypto.md diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index ecf033f2fa7..f332fba7031 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -304,7 +304,9 @@ (umax "maxu") (clz "clz") (ctz "ctz") -(popcount "cpop")]) +(popcount "cpop") +(rotate "rol") +(rotatert "ror")]) ;; --- ;; Int Iterators. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index eed997116b0..572ad381d65 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -427,6 +427,34 @@ ;; vcompressvector compress instruction ;; vmov whole vector register move ;; vector unknown vector instruction +;; 17. Crypto Vector instructions +;; vandncrypto vector bitwise and-not instructions +;; vbrevcrypto vector reverse bits in elements instructions +;; vbrev8 crypto vector reverse bits in bytes instructions +;; vrev8crypto vector reverse bytes instructions +;; vclz crypto vector count leading Zeros instructions +;; vctz crypto vector count lrailing Zeros instructions +;; vrol crypto vector rotate left instructions +;; vror crypto vector rotate right instructions +;; vwsllcrypto vector widening shift left logical instructions +;; vclmul crypto vector carry-less multiply - return low half instructions +;; vclmulh crypto vector carry-less multiply - return high half instructions +;; vghshcrypto vector add-multiply over GHASH Galois-Field instructions +;; vgmulcrypto vector multiply over GHASH Galois-Field instrumctions +;; vaesef crypto vector AES final-round encryption instructions +;; vaesem crypto vector AES middle-round encryption instructions +;; vaesdf crypto vector AES final-round decryption instructions +;; vaesdm crypto vector AES middle-round decryption instructions +;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation instructions +;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation instructions +;; vaeszcrypto vector AES round zero encryption/decryption instructions +;; vsha2ms crypto vector SHA-2 message schedule instructions +;; vsha2ch crypto vector SHA-2 two rounds of compression instructions +;; vsha2cl crypto vector SHA-2 two rounds of compression instructions +;; vsm4kcrypto vector SM4 KeyExpansion instructions +;; vsm4rcrypto vector SM4 Rounds instructions +;; vsm3me crypto vector SM3 Message Expansion instructions +;; vsm3ccrypto vector SM3 Compression instructions (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -446,7 +474,9 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov,vector" + vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, @@ -3771,6 +3801,7 @@ (include "thead.md") (include "generic-ooo.md") (include "vector.md") +(include "vector-crypto.md") (include "zicond.md") (include "sfb.md") (include "zc.md") diff --git a/gcc/config/riscv/vector-crypto.md
[PATCH v3 2/4] RISC-V: Add crypto vector builtin function.
Patch v3:Define a shape for vaesz and merge vector-crypto-types.def
into riscv-vector-builtins-types.def.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-avail.h (AVAIL): Add AVAIL macro
definition.
* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
Add new function_base for crypto vector.
(class bitmanip): Ditto.
(class b_reverse):Ditto.
(class vwsll): Ditto.
(class clmul): Ditto.
(class vg_nhab): Ditto.
(class crypto_vv):Ditto.
(class crypto_vi):Ditto.
(class vaeskf2_vsm3c):Ditto.
(class vsm3me): Ditto.
(BASE): Add BASE declaration for crypto vector.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add new function_shape for crypto vector.
(struct crypto_vi_def): Ditto.
(struct crypto_vv_no_op_type_def): Ditto.
(SHAPE): Add SHAPE declaration of crypto vector.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_CRYPTO_SEW32_OPS):
Add new data type for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
Add new data struct for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(DEF_RVV_FUNCTION): Redefine DEF_RVV_FUNCTION macro for crypto vector.
(registered_function::overloaded_hash): Processing size_t uimm for C
overloaded func.
(handle_pragma_vector): Add registration for crypto vector.
* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
* config/riscv/t-riscv: Add building dependency files.
* config/riscv/riscv-vector-crypto-builtins-functions.def: New file.
---
.../riscv/riscv-vector-builtins-avail.h | 10 +
.../riscv/riscv-vector-builtins-bases.cc | 259 +-
.../riscv/riscv-vector-builtins-bases.h | 28 ++
.../riscv/riscv-vector-builtins-shapes.cc | 87 +-
.../riscv/riscv-vector-builtins-shapes.h | 4 +
.../riscv/riscv-vector-builtins-types.def | 25 ++
gcc/config/riscv/riscv-vector-builtins.cc | 149 +-
gcc/config/riscv/riscv-vector-builtins.def| 1 +
gcc/config/riscv/riscv-vector-builtins.h | 8 +
...riscv-vector-crypto-builtins-functions.def | 78 ++
gcc/config/riscv/t-riscv | 1 +
11 files changed, 647 insertions(+), 3 deletions(-)
create mode 100755 gcc/config/riscv/riscv-vector-crypto-builtins-functions.def
diff --git a/gcc/config/riscv/riscv-vector-builtins-avail.h
b/gcc/config/riscv/riscv-vector-builtins-avail.h
index b11a8bcbc7f..4079fa1423a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-avail.h
+++ b/gcc/config/riscv/riscv-vector-builtins-avail.h
@@ -8,5 +8,15 @@ namespace riscv_vector {
#define AVAIL(NAME, COND)
\
static unsigned int riscv_vector_avail_##NAME(void) { return (COND); }
+AVAIL (zvbb, TARGET_ZVBB)
+AVAIL (zvbc, TARGET_ZVBC)
+AVAIL (zvkb_or_zvbb, TARGET_ZVKB || TARGET_ZVBB)
+AVAIL (zvkg, TARGET_ZVKG)
+AVAIL (zvkned, TARGET_ZVKNED)
+AVAIL (zvknha_or_zvknhb, TARGET_ZVKNHA || TARGET_ZVKNHB)
+AVAIL (zvknhb, TARGET_ZVKNHB)
+AVAIL (zvksed, TARGET_ZVKSED)
+AVAIL (zvksh, TARGET_ZVKSH)
+
} // namespace riscv_vector
#endif
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d70468542ee..6d52230e9ba 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2127,6 +2127,207 @@ public:
}
};
+/* Below implements are vector crypto */
+/* Implements vandn.[vv,vx] */
+class vandn : public function_base
+{
+public:
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_vandn (e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_vandn_scalar (e.vector_mode
()));
+ default:
+gcc_unreachable ();
+ }
+ }
+};
+
+/* Implements vrol/vror/clz/ctz. */
[PATCH v2 1/4] RISC-V:Add crypto vector implied ISA info.
Patch v2: Change the implied ISA info using the minimum set and add
dependencies info into the python script.
Due to the crypto vector entension is depend on the Vector extension,
so the "v" info is added into implied ISA info with the corresponding
crypto vector extension.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Modify implied ISA info.
* config/riscv/arch-canonicalize: Add crypto vector implied info.
---
gcc/common/config/riscv/riscv-common.cc | 9 +
gcc/config/riscv/arch-canonicalize | 21 +++--
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 4d5a2f874a2..76987598143 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -145,6 +145,15 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvksc", "zvbc"},
{"zvksg", "zvks"},
{"zvksg", "zvkg"},
+ {"zvbb", "zvkb"},
+ {"zvbc", "zve64x"},
+ {"zvkb", "zve32x"},
+ {"zvkg", "zve32x"},
+ {"zvkned", "zve32x"},
+ {"zvknha", "zve32x"},
+ {"zvknhb", "zve64x"},
+ {"zvksed", "zve32x"},
+ {"zvksh", "zve32x"},
{"zfh", "zfhmin"},
{"zfhmin", "f"},
diff --git a/gcc/config/riscv/arch-canonicalize
b/gcc/config/riscv/arch-canonicalize
index ea2f67a0944..a8f47a1752b 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -69,12 +69,21 @@ IMPLIED_EXT = {
"zvl32768b" : ["zvl16384b"],
"zvl65536b" : ["zvl32768b"],
- "zvkn" : ["zvkned", "zvknhb", "zvbb", "zvkt"],
- "zvknc" : ["zvkn", "zvbc"],
- "zvkng" : ["zvkn", "zvkg"],
- "zvks" : ["zvksed", "zvksh", "zvbb", "zvkt"],
- "zvksc" : ["zvks", "zvbc"],
- "zvksg" : ["zvks", "zvkg"],
+ "zvkn" : ["zvkned", "zvknhb", "zvkb", "zvkt"],
+ "zvknc" : ["zvkn", "zvbc"],
+ "zvkng" : ["zvkn", "zvkg"],
+ "zvks" : ["zvksed", "zvksh", "zvkb", "zvkt"],
+ "zvksc" : ["zvks", "zvbc"],
+ "zvksg" : ["zvks", "zvkg"],
+ "zvbb" : ["zvkb"],
+ "zvbc" : ["zve64x"],
+ "zvkb" : ["zve32x"],
+ "zvkg" : ["zve32x"],
+ "zvkned" : ["zve32x"],
+ "zvknha" : ["zve32x"],
+ "zvknhb" : ["zve64x"],
+ "zvksed" : ["zve32x"],
+ "zvksh" : ["zve32x"],
}
def arch_canonicalize(arch, isa_spec):
--
2.17.1
[committed] MAINTAINERS: Update my email address
ChangeLog: * MAINTAINERS: Update my email address --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index f3683ff03ec..bc47e30325b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -705,7 +705,7 @@ Marcel Vollweiler Ville Voutilainen Nenad Vukicevic Feng Wang -Feng Wang s +Feng Wang Hongyu Wang Jiong Wang Stephen M. Webb -- 2.17.1
[committed] RISC-V: Add avail interface into function_group_info
Patch v3: Fix typo and remove the modification of rvv.exp. Patch v2: Using variadic macro and add the dependency into t-riscv. In order to add other extension about vector,this patch add unsigned int (*avail) (void) into function_group_info to determine whether to register the intrinsic based on ISA info. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Add AVAIL argument. (read_vl): Using AVAIL argument default value. (vlenb): Ditto. (vsetvl): Ditto. (vsetvlmax): Ditto. (vle): Ditto. (vse): Ditto. (vlm): Ditto. (vsm): Ditto. (vlse): Ditto. (vsse): Ditto. (vluxei8): Ditto. (vluxei16): Ditto. (vluxei32): Ditto. (vluxei64): Ditto. (vloxei8): Ditto. (vloxei16): Ditto. (vloxei32): Ditto. (vloxei64): Ditto. (vsuxei8): Ditto. (vsuxei16): Ditto. (vsuxei32): Ditto. (vsuxei64): Ditto. (vsoxei8): Ditto. (vsoxei16): Ditto. (vsoxei32): Ditto. (vsoxei64): Ditto. (vleff): Ditto. (vadd): Ditto. (vsub): Ditto. (vrsub): Ditto. (vneg): Ditto. (vwaddu): Ditto. (vwsubu): Ditto. (vwadd): Ditto. (vwsub): Ditto. (vwcvt_x): Ditto. (vwcvtu_x): Ditto. (vzext): Ditto. (vsext): Ditto. (vadc): Ditto. (vmadc): Ditto. (vsbc): Ditto. (vmsbc): Ditto. (vand): Ditto. (vor): Ditto. (vxor): Ditto. (vnot): Ditto. (vsll): Ditto. (vsra): Ditto. (vsrl): Ditto. (vnsrl): Ditto. (vnsra): Ditto. (vncvt_x): Ditto. (vmseq): Ditto. (vmsne): Ditto. (vmsltu): Ditto. (vmslt): Ditto. (vmsleu): Ditto. (vmsle): Ditto. (vmsgtu): Ditto. (vmsgt): Ditto. (vmsgeu): Ditto. (vmsge): Ditto. (vminu): Ditto. (vmin): Ditto. (vmaxu): Ditto. (vmax): Ditto. (vmul): Ditto. (vmulh): Ditto. (vmulhu): Ditto. (vmulhsu): Ditto. (vdivu): Ditto. (vdiv): Ditto. (vremu): Ditto. (vrem): Ditto. (vwmul): Ditto. (vwmulu): Ditto. (vwmulsu): Ditto. (vmacc): Ditto. (vnmsac): Ditto. (vmadd): Ditto. (vnmsub): Ditto. (vwmaccu): Ditto. (vwmacc): Ditto. (vwmaccsu): Ditto. (vwmaccus): Ditto. (vmerge): Ditto. (vmv_v): Ditto. (vsaddu): Ditto. (vsadd): Ditto. (vssubu): Ditto. (vssub): Ditto. (vaaddu): Ditto. (vaadd): Ditto. (vasubu): Ditto. (vasub): Ditto. (vsmul): Ditto. (vssrl): Ditto. (vssra): Ditto. (vnclipu): Ditto. (vnclip): Ditto. (vfadd): Ditto. (vfsub): Ditto. (vfrsub): Ditto. (vfadd_frm): Ditto. (vfsub_frm): Ditto. (vfrsub_frm): Ditto. (vfwadd): Ditto. (vfwsub): Ditto. (vfwadd_frm): Ditto. (vfwsub_frm): Ditto. (vfmul): Ditto. (vfdiv): Ditto. (vfrdiv): Ditto. (vfmul_frm): Ditto. (vfdiv_frm): Ditto. (vfrdiv_frm): Ditto. (vfwmul): Ditto. (vfwmul_frm): Ditto. (vfmacc): Ditto. (vfnmsac): Ditto. (vfmadd): Ditto. (vfnmsub): Ditto. (vfnmacc): Ditto. (vfmsac): Ditto. (vfnmadd): Ditto. (vfmsub): Ditto. (vfmacc_frm): Ditto. (vfnmacc_frm): Ditto. (vfmsac_frm): Ditto. (vfnmsac_frm): Ditto. (vfmadd_frm): Ditto. (vfnmadd_frm): Ditto. (vfmsub_frm): Ditto. (vfnmsub_frm): Ditto. (vfwmacc): Ditto. (vfwnmacc): Ditto. (vfwmsac): Ditto. (vfwnmsac): Ditto. (vfwmacc_frm): Ditto. (vfwnmacc_frm): Ditto. (vfwmsac_frm): Ditto. (vfwnmsac_frm): Ditto. (vfsqrt): Ditto. (vfsqrt_frm): Ditto. (vfrsqrt7): Ditto. (vfrec7): Ditto. (vfrec7_frm): Ditto. (vfmin): Ditto. (vfmax): Ditto. (vfsgnj): Ditto. (vfsgnjn): Ditto. (vfsgnjx): Ditto. (vfneg): Ditto. (vfabs): Ditto. (vmfeq): Ditto. (vmfne): Ditto. (vmflt): Ditto. (vmfle): Ditto. (vmfgt): Ditto. (vmfge): Ditto. (vfclass): Ditto. (vfmerge): Ditto. (vfmv_v): Ditto. (vfcvt_x): Ditto. (vfcvt_xu): Ditto. (vfcvt_rtz_x): Ditto. (vfcvt_rtz_xu): Ditto. (vfcvt_f): Ditto. (vfcvt_x_frm): Ditto. (vfcvt_xu_frm): Ditto. (vfcvt_f_frm): Ditto. (vfwcvt_x): Ditto. (vfwcvt_xu): Ditto. (vfwcvt_rtz_x): Ditto.
[committed] MAINTAINERS: Add myself to write after approval and DCO
ChangeLog: * MAINTAINERS: Add myself to write after approval --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0dbcbadcfd7..f3683ff03ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -705,6 +705,7 @@ Marcel Vollweiler Ville Voutilainen Nenad Vukicevic Feng Wang +Feng Wang s Hongyu Wang Jiong Wang Stephen M. Webb -- 2.17.1
Re: Re: [PATCH][v3] RISC-V: Add avail interface into function_group_info
2023-12-11 13:05 Kito Cheng wrote: >I am happy with this change now, however I didn't see any place call avail >function yet? Do I miss something? Are you planning to send follow up >patches to add that? >If so, LGTM. Yes, the crypto vector will determine whether to register the corresponding sub extension's intrinsic function by calling the AVAIL macro.
[PATCH][v3] RISC-V: Add avail interface into function_group_info
Patch v3: Fix typo and remove the modification of rvv.exp. Patch v2: Using variadic macro and add the dependency into t-riscv. In order to add other extension about vector,this patch add unsigned int (*avail) (void) into function_group_info to determine whether to register the intrinsic based on ISA info. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Add AVAIL argument. (read_vl): Using AVAIL argument default value. (vlenb): Ditto. (vsetvl): Ditto. (vsetvlmax): Ditto. (vle): Ditto. (vse): Ditto. (vlm): Ditto. (vsm): Ditto. (vlse): Ditto. (vsse): Ditto. (vluxei8): Ditto. (vluxei16): Ditto. (vluxei32): Ditto. (vluxei64): Ditto. (vloxei8): Ditto. (vloxei16): Ditto. (vloxei32): Ditto. (vloxei64): Ditto. (vsuxei8): Ditto. (vsuxei16): Ditto. (vsuxei32): Ditto. (vsuxei64): Ditto. (vsoxei8): Ditto. (vsoxei16): Ditto. (vsoxei32): Ditto. (vsoxei64): Ditto. (vleff): Ditto. (vadd): Ditto. (vsub): Ditto. (vrsub): Ditto. (vneg): Ditto. (vwaddu): Ditto. (vwsubu): Ditto. (vwadd): Ditto. (vwsub): Ditto. (vwcvt_x): Ditto. (vwcvtu_x): Ditto. (vzext): Ditto. (vsext): Ditto. (vadc): Ditto. (vmadc): Ditto. (vsbc): Ditto. (vmsbc): Ditto. (vand): Ditto. (vor): Ditto. (vxor): Ditto. (vnot): Ditto. (vsll): Ditto. (vsra): Ditto. (vsrl): Ditto. (vnsrl): Ditto. (vnsra): Ditto. (vncvt_x): Ditto. (vmseq): Ditto. (vmsne): Ditto. (vmsltu): Ditto. (vmslt): Ditto. (vmsleu): Ditto. (vmsle): Ditto. (vmsgtu): Ditto. (vmsgt): Ditto. (vmsgeu): Ditto. (vmsge): Ditto. (vminu): Ditto. (vmin): Ditto. (vmaxu): Ditto. (vmax): Ditto. (vmul): Ditto. (vmulh): Ditto. (vmulhu): Ditto. (vmulhsu): Ditto. (vdivu): Ditto. (vdiv): Ditto. (vremu): Ditto. (vrem): Ditto. (vwmul): Ditto. (vwmulu): Ditto. (vwmulsu): Ditto. (vmacc): Ditto. (vnmsac): Ditto. (vmadd): Ditto. (vnmsub): Ditto. (vwmaccu): Ditto. (vwmacc): Ditto. (vwmaccsu): Ditto. (vwmaccus): Ditto. (vmerge): Ditto. (vmv_v): Ditto. (vsaddu): Ditto. (vsadd): Ditto. (vssubu): Ditto. (vssub): Ditto. (vaaddu): Ditto. (vaadd): Ditto. (vasubu): Ditto. (vasub): Ditto. (vsmul): Ditto. (vssrl): Ditto. (vssra): Ditto. (vnclipu): Ditto. (vnclip): Ditto. (vfadd): Ditto. (vfsub): Ditto. (vfrsub): Ditto. (vfadd_frm): Ditto. (vfsub_frm): Ditto. (vfrsub_frm): Ditto. (vfwadd): Ditto. (vfwsub): Ditto. (vfwadd_frm): Ditto. (vfwsub_frm): Ditto. (vfmul): Ditto. (vfdiv): Ditto. (vfrdiv): Ditto. (vfmul_frm): Ditto. (vfdiv_frm): Ditto. (vfrdiv_frm): Ditto. (vfwmul): Ditto. (vfwmul_frm): Ditto. (vfmacc): Ditto. (vfnmsac): Ditto. (vfmadd): Ditto. (vfnmsub): Ditto. (vfnmacc): Ditto. (vfmsac): Ditto. (vfnmadd): Ditto. (vfmsub): Ditto. (vfmacc_frm): Ditto. (vfnmacc_frm): Ditto. (vfmsac_frm): Ditto. (vfnmsac_frm): Ditto. (vfmadd_frm): Ditto. (vfnmadd_frm): Ditto. (vfmsub_frm): Ditto. (vfnmsub_frm): Ditto. (vfwmacc): Ditto. (vfwnmacc): Ditto. (vfwmsac): Ditto. (vfwnmsac): Ditto. (vfwmacc_frm): Ditto. (vfwnmacc_frm): Ditto. (vfwmsac_frm): Ditto. (vfwnmsac_frm): Ditto. (vfsqrt): Ditto. (vfsqrt_frm): Ditto. (vfrsqrt7): Ditto. (vfrec7): Ditto. (vfrec7_frm): Ditto. (vfmin): Ditto. (vfmax): Ditto. (vfsgnj): Ditto. (vfsgnjn): Ditto. (vfsgnjx): Ditto. (vfneg): Ditto. (vfabs): Ditto. (vmfeq): Ditto. (vmfne): Ditto. (vmflt): Ditto. (vmfle): Ditto. (vmfgt): Ditto. (vmfge): Ditto. (vfclass): Ditto. (vfmerge): Ditto. (vfmv_v): Ditto. (vfcvt_x): Ditto. (vfcvt_xu): Ditto. (vfcvt_rtz_x): Ditto. (vfcvt_rtz_xu): Ditto. (vfcvt_f): Ditto. (vfcvt_x_frm): Ditto. (vfcvt_xu_frm): Ditto. (vfcvt_f_frm): Ditto. (vfwcvt_x): Ditto. (vfwcvt_xu): Ditto. (vfwcvt_rtz_x): Ditto.
Re: Re: [PATCH][v2] RISC-V: Add avail interface into function_group_info
2023-12-08 11:35 Kito Cheng wrote: >> Without comma, there is a warning "warning: ISO C++11 requires at least one >> argument for the "..." in a variadic macro". >> So I add the comma. > >Oh, thanks, I wasn't aware that, maybe take one more argument to '...' > >#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, ...) > >Anyway my intention is to reduce unnecessary diff as possible. Hi Kito, I understand. So I tried to many ways want to minimize this modification, I have also tried the method you mentioned,there is still a warning. But just a warning won't affect the functionality.If you think it's okay, then there's no need to modify the original definition.
Re: Re: [PATCH][v2] RISC-V: Add avail interface into function_group_info
2023-12-08 11:18 Kito Cheng wrote: >> @@ -31,624 +31,627 @@ along with GCC; see the file COPYING3. If not see >> - OPS_INFO describes all information of return type and each >> argument type. >> >> + - AVAIL this argument is the optional for AVAIL.Determin the enable >> + of the intrinsic function. >> + >> */ >> #ifndef DEF_RVV_FUNCTION >> -#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO) >> +#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO, AVAIL) > > >#define DEF_RVV_FUNCTION(NAME, SHAPE, PREDS, OPS_INFO, ...) > >> #endif >> >> /* Internal helper functions for gimple fold use. */ >> -DEF_RVV_FUNCTION (read_vl, read_vl, none_preds, p_none_void_ops) >> -DEF_RVV_FUNCTION (vlenb, vlenb, none_preds, ul_none_void_ops) >> +DEF_RVV_FUNCTION (read_vl, read_vl, none_preds, p_none_void_ops, ) >> +DEF_RVV_FUNCTION (vlenb, vlenb, none_preds, ul_none_void_ops, ) > >And keep this unchanged, you don't need extra comma. > Without comma, there is a warning "warning: ISO C++11 requires at least one argument for the "..." in a variadic macro". So I add the comma. >DEF_RVV_FUNCTION (read_vl, read_vl, none_preds, p_none_void_ops) >DEF_RVV_FUNCTION (vlenb, vlenb, none_preds, ul_none_void_ops) > >> >> /* 6. Configuration-Setting Instructions. */ >> >> -DEF_RVV_FUNCTION (vsetvl, vsetvl, none_preds, i_none_size_size_ops) >> -DEF_RVV_FUNCTION (vsetvlmax, vsetvlmax, none_preds, i_none_size_void_ops) >> +DEF_RVV_FUNCTION (vsetvl, vsetvl, none_preds, i_none_size_size_ops, ) >> +DEF_RVV_FUNCTION (vsetvlmax, vsetvlmax, none_preds, i_none_size_void_ops, ) >> >> /* 7. Vector Loads and Stores. */ >> >> // 7.4. Vector Unit-Stride Instructions >> -DEF_RVV_FUNCTION (vle, loadstore, full_preds, all_v_scalar_const_ptr_ops) >> -DEF_RVV_FUNCTION (vse, loadstore, none_m_preds, all_v_scalar_ptr_ops) >> -DEF_RVV_FUNCTION (vlm, loadstore, none_preds, b_v_scalar_const_ptr_ops) >> -DEF_RVV_FUNCTION (vsm, loadstore, none_preds, b_v_scalar_ptr_ops) >> +DEF_RVV_FUNCTION (vle, loadstore, full_preds, all_v_scalar_const_ptr_ops, ) >> +DEF_RVV_FUNCTION (vse, loadstore, none_m_preds, all_v_scalar_ptr_ops, ) >> +DEF_RVV_FUNCTION (vlm, loadstore, none_preds, b_v_scalar_const_ptr_ops, ) >> +DEF_RVV_FUNCTION (vsm, loadstore, none_preds, b_v_scalar_ptr_ops, ) >> >> // 7.5. Vector Strided Instructions >> -DEF_RVV_FUNCTION (vlse, loadstore, full_preds, >> all_v_scalar_const_ptr_ptrdiff_ops) >> -DEF_RVV_FUNCTION (vsse, loadstore, none_m_preds, >> all_v_scalar_ptr_ptrdiff_ops) >> +DEF_RVV_FUNCTION (vlse, loadstore, full_preds, >> all_v_scalar_const_ptr_ptrdiff_ops, ) >> +DEF_RVV_FUNCTION (vsse, loadstore, none_m_preds, >> all_v_scalar_ptr_ptrdiff_ops, ) >> >> // 7.6. Vector Indexed Instructions >> -DEF_RVV_FUNCTION (vluxei8, indexed_loadstore, full_preds, >> all_v_scalar_const_ptr_eew8_index_ops) >> -DEF_RVV_FUNCTION (vluxei16, indexed_loadstore, full_preds, >> all_v_scalar_const_ptr_eew16_index_ops) >> -DEF_RVV_FUNCTION (vluxei32, indexed_loadstore, full_preds, >> all_v_scalar_const_ptr_eew32_index_ops) >> -DEF_RVV_FUNCTION (vluxei64, indexed_loadstore, full_preds, >> all_v_scalar_const_ptr_eew64_index_ops) >> -DEF_RVV_FUNCTION (vloxei8, indexed_loadstore, full_preds, >> all_v_scalar_const_ptr_eew8_index_ops) >> -DEF_RVV_FUNCTION (vloxei16, indexed_loadstore, full_preds, >> all_v_scalar_const_ptr_eew16_index_ops) >> -DEF_RVV_FUNCTION (vloxei32, indexed_loadstore, full_preds, >> all_v_scalar_const_ptr_eew32_index_ops) >> -DEF_RVV_FUNCTION (vloxei64, indexed_loadstore, full_preds, >> all_v_scalar_const_ptr_eew64_index_ops) >> -DEF_RVV_FUNCTION (vsuxei8, indexed_loadstore, none_m_preds, >> all_v_scalar_ptr_eew8_index_ops) >> -DEF_RVV_FUNCTION (vsuxei16, indexed_loadstore, none_m_preds, >> all_v_scalar_ptr_eew16_index_ops) >> -DEF_RVV_FUNCTION (vsuxei32, indexed_loadstore, none_m_preds, >> all_v_scalar_ptr_eew32_index_ops) >> -DEF_RVV_FUNCTION (vsuxei64, indexed_loadstore, none_m_preds, >> all_v_scalar_ptr_eew64_index_ops) >> -DEF_RVV_FUNCTION (vsoxei8, indexed_loadstore, none_m_preds, >> all_v_scalar_ptr_eew8_index_ops) >> -DEF_RVV_FUNCTION (vsoxei16, indexed_loadstore, none_m_preds, >> all_v_scalar_ptr_eew16_index_ops) >> -DEF_RVV_FUNCTION (vsoxei32, indexed_loadstore, none_m_preds, >> all_v_scalar_ptr_eew32_index_ops) >> -DEF_RVV_FUNCTION (vsoxei64, indexed_loadstore, none_m_preds, >> all_v_scalar_ptr_eew64_index_ops) >> +DEF_RVV_FUNCTION (vluxei8, indexed_loadstore, full_preds, >> all_v_scalar_const_ptr_eew8_index_ops, ) >> +DEF_RVV_FUNCTION (vluxei16, indexed_loadstore, full_preds, >> all_v_scalar_const_ptr_eew16_index_ops, ) >> +DEF_RVV_FUNCTION (vluxei32, indexed_loadstore, full_preds, >> all_v_scalar_const_ptr_eew32_index_ops, ) >> +DEF_RVV_FUNCTION (vluxei64,
Re: [PATCH][v2] RISC-V: Add avail interface into function_group_info
2023-12-08 10:44 Feng Wang wrote: Have run all the vector api-testing. >Patch v2: Using variadic macro and add the dependency into t-riscv > >In order to add other extension about vector,this patch add >unsigned int (*avail) (void) into function_group_info to determine >whether to register the intrinsic based on ISA info. > >gcc/ChangeLog: > > * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): > Add AVAIL argument. > (read_vl): Using AVAIL argument default value. > (vlenb): Ditto. > (vsetvl): Ditto. > (vsetvlmax): Ditto. > (vle): Ditto. > (vse): Ditto. > (vlm): Ditto. > (vsm): Ditto. > (vlse): Ditto. > (vsse): Ditto. > (vluxei8): Ditto. > (vluxei16): Ditto. > (vluxei32): Ditto. > (vluxei64): Ditto. > (vloxei8): Ditto. > (vloxei16): Ditto. > (vloxei32): Ditto. > (vloxei64): Ditto. > (vsuxei8): Ditto. > (vsuxei16): Ditto. > (vsuxei32): Ditto. > (vsuxei64): Ditto. > (vsoxei8): Ditto. > (vsoxei16): Ditto. > (vsoxei32): Ditto. > (vsoxei64): Ditto. > (vleff): Ditto. > (vadd): Ditto. > (vsub): Ditto. > (vrsub): Ditto. > (vneg): Ditto. > (vwaddu): Ditto. > (vwsubu): Ditto. > (vwadd): Ditto. > (vwsub): Ditto. > (vwcvt_x): Ditto. > (vwcvtu_x): Ditto. > (vzext): Ditto. > (vsext): Ditto. > (vadc): Ditto. > (vmadc): Ditto. > (vsbc): Ditto. > (vmsbc): Ditto. > (vand): Ditto. > (vor): Ditto. > (vxor): Ditto. > (vnot): Ditto. > (vsll): Ditto. > (vsra): Ditto. > (vsrl): Ditto. > (vnsrl): Ditto. > (vnsra): Ditto. > (vncvt_x): Ditto. > (vmseq): Ditto. > (vmsne): Ditto. > (vmsltu): Ditto. > (vmslt): Ditto. > (vmsleu): Ditto. > (vmsle): Ditto. > (vmsgtu): Ditto. > (vmsgt): Ditto. > (vmsgeu): Ditto. > (vmsge): Ditto. > (vminu): Ditto. > (vmin): Ditto. > (vmaxu): Ditto. > (vmax): Ditto. > (vmul): Ditto. > (vmulh): Ditto. > (vmulhu): Ditto. > (vmulhsu): Ditto. > (vdivu): Ditto. > (vdiv): Ditto. > (vremu): Ditto. > (vrem): Ditto. > (vwmul): Ditto. > (vwmulu): Ditto. > (vwmulsu): Ditto. > (vmacc): Ditto. > (vnmsac): Ditto. > (vmadd): Ditto. > (vnmsub): Ditto. > (vwmaccu): Ditto. > (vwmacc): Ditto. > (vwmaccsu): Ditto. > (vwmaccus): Ditto. > (vmerge): Ditto. > (vmv_v): Ditto. > (vsaddu): Ditto. > (vsadd): Ditto. > (vssubu): Ditto. > (vssub): Ditto. > (vaaddu): Ditto. > (vaadd): Ditto. > (vasubu): Ditto. > (vasub): Ditto. > (vsmul): Ditto. > (vssrl): Ditto. > (vssra): Ditto. > (vnclipu): Ditto. > (vnclip): Ditto. > (vfadd): Ditto. > (vfsub): Ditto. > (vfrsub): Ditto. > (vfadd_frm): Ditto. > (vfsub_frm): Ditto. > (vfrsub_frm): Ditto. > (vfwadd): Ditto. > (vfwsub): Ditto. > (vfwadd_frm): Ditto. > (vfwsub_frm): Ditto. > (vfmul): Ditto. > (vfdiv): Ditto. > (vfrdiv): Ditto. > (vfmul_frm): Ditto. > (vfdiv_frm): Ditto. > (vfrdiv_frm): Ditto. > (vfwmul): Ditto. > (vfwmul_frm): Ditto. > (vfmacc): Ditto. > (vfnmsac): Ditto. > (vfmadd): Ditto. > (vfnmsub): Ditto. > (vfnmacc): Ditto. > (vfmsac): Ditto. > (vfnmadd): Ditto. > (vfmsub): Ditto. > (vfmacc_frm): Ditto. > (vfnmacc_frm): Ditto. > (vfmsac_frm): Ditto. > (vfnmsac_frm): Ditto. > (vfmadd_frm): Ditto. > (vfnmadd_frm): Ditto. > (vfmsub_frm): Ditto. > (vfnmsub_frm): Ditto. > (vfwmacc): Ditto. > (vfwnmacc): Ditto. > (vfwmsac): Ditto. > (vfwnmsac): Ditto. > (vfwmacc_frm): Ditto. > (vfwnmacc_frm): Ditto. >
[PATCH][v2] RISC-V: Add avail interface into function_group_info
Patch v2: Using variadic macro and add the dependency into t-riscv In order to add other extension about vector,this patch add unsigned int (*avail) (void) into function_group_info to determine whether to register the intrinsic based on ISA info. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Add AVAIL argument. (read_vl): Using AVAIL argument default value. (vlenb): Ditto. (vsetvl): Ditto. (vsetvlmax): Ditto. (vle): Ditto. (vse): Ditto. (vlm): Ditto. (vsm): Ditto. (vlse): Ditto. (vsse): Ditto. (vluxei8): Ditto. (vluxei16): Ditto. (vluxei32): Ditto. (vluxei64): Ditto. (vloxei8): Ditto. (vloxei16): Ditto. (vloxei32): Ditto. (vloxei64): Ditto. (vsuxei8): Ditto. (vsuxei16): Ditto. (vsuxei32): Ditto. (vsuxei64): Ditto. (vsoxei8): Ditto. (vsoxei16): Ditto. (vsoxei32): Ditto. (vsoxei64): Ditto. (vleff): Ditto. (vadd): Ditto. (vsub): Ditto. (vrsub): Ditto. (vneg): Ditto. (vwaddu): Ditto. (vwsubu): Ditto. (vwadd): Ditto. (vwsub): Ditto. (vwcvt_x): Ditto. (vwcvtu_x): Ditto. (vzext): Ditto. (vsext): Ditto. (vadc): Ditto. (vmadc): Ditto. (vsbc): Ditto. (vmsbc): Ditto. (vand): Ditto. (vor): Ditto. (vxor): Ditto. (vnot): Ditto. (vsll): Ditto. (vsra): Ditto. (vsrl): Ditto. (vnsrl): Ditto. (vnsra): Ditto. (vncvt_x): Ditto. (vmseq): Ditto. (vmsne): Ditto. (vmsltu): Ditto. (vmslt): Ditto. (vmsleu): Ditto. (vmsle): Ditto. (vmsgtu): Ditto. (vmsgt): Ditto. (vmsgeu): Ditto. (vmsge): Ditto. (vminu): Ditto. (vmin): Ditto. (vmaxu): Ditto. (vmax): Ditto. (vmul): Ditto. (vmulh): Ditto. (vmulhu): Ditto. (vmulhsu): Ditto. (vdivu): Ditto. (vdiv): Ditto. (vremu): Ditto. (vrem): Ditto. (vwmul): Ditto. (vwmulu): Ditto. (vwmulsu): Ditto. (vmacc): Ditto. (vnmsac): Ditto. (vmadd): Ditto. (vnmsub): Ditto. (vwmaccu): Ditto. (vwmacc): Ditto. (vwmaccsu): Ditto. (vwmaccus): Ditto. (vmerge): Ditto. (vmv_v): Ditto. (vsaddu): Ditto. (vsadd): Ditto. (vssubu): Ditto. (vssub): Ditto. (vaaddu): Ditto. (vaadd): Ditto. (vasubu): Ditto. (vasub): Ditto. (vsmul): Ditto. (vssrl): Ditto. (vssra): Ditto. (vnclipu): Ditto. (vnclip): Ditto. (vfadd): Ditto. (vfsub): Ditto. (vfrsub): Ditto. (vfadd_frm): Ditto. (vfsub_frm): Ditto. (vfrsub_frm): Ditto. (vfwadd): Ditto. (vfwsub): Ditto. (vfwadd_frm): Ditto. (vfwsub_frm): Ditto. (vfmul): Ditto. (vfdiv): Ditto. (vfrdiv): Ditto. (vfmul_frm): Ditto. (vfdiv_frm): Ditto. (vfrdiv_frm): Ditto. (vfwmul): Ditto. (vfwmul_frm): Ditto. (vfmacc): Ditto. (vfnmsac): Ditto. (vfmadd): Ditto. (vfnmsub): Ditto. (vfnmacc): Ditto. (vfmsac): Ditto. (vfnmadd): Ditto. (vfmsub): Ditto. (vfmacc_frm): Ditto. (vfnmacc_frm): Ditto. (vfmsac_frm): Ditto. (vfnmsac_frm): Ditto. (vfmadd_frm): Ditto. (vfnmadd_frm): Ditto. (vfmsub_frm): Ditto. (vfnmsub_frm): Ditto. (vfwmacc): Ditto. (vfwnmacc): Ditto. (vfwmsac): Ditto. (vfwnmsac): Ditto. (vfwmacc_frm): Ditto. (vfwnmacc_frm): Ditto. (vfwmsac_frm): Ditto. (vfwnmsac_frm): Ditto. (vfsqrt): Ditto. (vfsqrt_frm): Ditto. (vfrsqrt7): Ditto. (vfrec7): Ditto. (vfrec7_frm): Ditto. (vfmin): Ditto. (vfmax): Ditto. (vfsgnj): Ditto. (vfsgnjn): Ditto. (vfsgnjx): Ditto. (vfneg): Ditto. (vfabs): Ditto. (vmfeq): Ditto. (vmfne): Ditto. (vmflt): Ditto. (vmfle): Ditto. (vmfgt): Ditto. (vmfge): Ditto. (vfclass): Ditto. (vfmerge): Ditto. (vfmv_v): Ditto. (vfcvt_x): Ditto. (vfcvt_xu): Ditto. (vfcvt_rtz_x): Ditto. (vfcvt_rtz_xu): Ditto. (vfcvt_f): Ditto. (vfcvt_x_frm): Ditto. (vfcvt_xu_frm): Ditto. (vfcvt_f_frm): Ditto. (vfwcvt_x): Ditto. (vfwcvt_xu): Ditto. (vfwcvt_rtz_x): Ditto. (vfwcvt_rtz_xu) Ditto.: (vfwcvt_f): Ditto. (vfwcvt_x_frm):
Re: Re: [PATCH] RISC-V: Add avail interface into function_group_info
2023-12-07 20:23 juzhe.zhong wrote: >Thanks for doing this! > >+AVAIL (always, true) >-> AVAIL (true, true) > >+DEF_RVV_FUNCTION (vmul, alu, full_preds, iu_vvv_ops, always) >-> DEF_RVV_FUNCTION (vmul, alu, full_preds, iu_vvv_ops, true) > >Btw, we have full coverage rvv -intrinsic API testing generator for GNU . >https://github.com/riscv-non-isa/rvv-intrinsic-doc/ >Could you run it ? Your colleague Lixu knows it. > OK. got it, I will run it. Thanks. > > > >juzhe.zh...@rivai.ai > >From: Feng Wang >Date: 2023-12-07 20:17 >To: gcc-patches >CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang >Subject: [PATCH] RISC-V: Add avail interface into function_group_info >In order to add other extension about vector,this patch add >unsigned int (*avail) (void) into function_group_info to determine >whether to register the intrinsic based on ISA info. > >gcc/ChangeLog: > >* config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Add >AVAIL def. >(read_vl): Add avail_always interface. >(vlenb): Ditto. >(vsetvl): Ditto. >(vsetvlmax): Ditto. >(vle): Ditto. >(vse): Ditto. >(vlm): Ditto. >(vsm): Ditto. >(vlse): Ditto. >(vsse): Ditto. >(vluxei8): Ditto. >(vluxei16): Ditto. >(vluxei32): Ditto. >(vluxei64): Ditto. >(vloxei8): Ditto. >(vloxei16): Ditto. >(vloxei32): Ditto. >(vloxei64): Ditto. >(vsuxei8): Ditto. >(vsuxei16): Ditto. >(vsuxei32): Ditto. >(vsuxei64): Ditto. >(vsoxei8): Ditto. >(vsoxei16): Ditto. >(vsoxei32): Ditto. >(vsoxei64):Ditto. >(vleff): Ditto. >(vadd): Ditto. >(vsub): Ditto. >(vrsub): Ditto. >(vneg): Ditto. >(vwaddu): Ditto. >(vwsubu): Ditto. >(vwadd): Ditto. >(vwsub): Ditto. >(vwcvt_x): Ditto. >(vwcvtu_x):Ditto. >(vzext): Ditto. >(vsext): Ditto. >(vadc): Ditto. >(vmadc): Ditto. >(vsbc): Ditto. >(vmsbc): Ditto. >(vand): Ditto. >(vor): Ditto. >(vxor): Ditto. >(vnot): Ditto. >(vsll): Ditto. >(vsra): Ditto. >(vsrl): Ditto. >(vnsrl): Ditto. >(vnsra): Ditto. >(vncvt_x): Ditto. >(vmseq): Ditto. >(vmsne): Ditto. >(vmsltu): Ditto. >(vmslt): Ditto. >(vmsleu): Ditto. >(vmsle): Ditto. >(vmsgtu): Ditto. >(vmsgt): Ditto. >(vmsgeu): Ditto. >(vmsge): Ditto. >(vminu): Ditto. >(vmin): Ditto. >(vmaxu): Ditto. >(vmax): Ditto. >(vmul): Ditto. >(vmulh): Ditto. >(vmulhu): Ditto. >(vmulhsu): Ditto. >(vdivu): Ditto. >(vdiv): Ditto. >(vremu): Ditto. >(vrem): Ditto. >(vwmul): Ditto. >(vwmulu): Ditto. >(vwmulsu): Ditto. >(vmacc): Ditto. >(vnmsac): Ditto. >(vmadd): Ditto. >(vnmsub): Ditto. >(vwmaccu): Ditto. >(vwmacc): Ditto. >(vwmaccsu): Ditto. >(vwmaccus): Ditto. >(vmerge): Ditto. >(vmv_v): Ditto. >(vsaddu): Ditto. >(vsadd): Ditto. >(vssubu): Ditto. >(vssub): Ditto. >(vaaddu): Ditto. >(vaadd): Ditto. >(vasubu): Ditto. >(vasub): Ditto. >(vsmul): Ditto. >(vssrl): Ditto. >(vssra): Ditto. >(vnclipu): Ditto. >(vnclip): Ditto. >(vfadd): Ditto. >(vfsub): Ditto. >(vfrsub): Ditto. >(vfadd_frm): Ditto. >(vfsub_frm): Ditto. >(vfrsub_frm): Ditto. >(vfwadd): Ditto. >(vfwsub): Ditto. >(vfwadd_frm): Ditto. >(vfwsub_frm): Ditto. >(vfmul): Ditto. >(vfdiv): Ditto. >(vfrdiv): Ditto. >(vfmul_frm): Ditto. >(vfdiv_frm): Ditto. >(vfrdiv_frm): Ditto. >(vfwmul): Ditto. >(vfwmul_frm): Ditto. >(vfmacc): Ditto. >(vfnmsac): Ditto. >(vfmadd): Ditto. >(vfnmsub): Ditto. >(vfnmacc): Ditto. >(vfmsac): Ditto. >(vfnmadd): Ditto. >(vfmsub): Ditto. >(vfmacc_frm): Ditto. >(vfnmacc_frm): Ditto. >(vfmsac_frm): Ditto. >(vfnmsac_frm): Ditto. >(vfmadd_frm): Ditto. >(vfnmadd_frm): Ditto. >(vfmsub_frm): Ditto. >(vfnmsub_frm): Ditto. >(vfwmacc): Ditto. >(vfwnmacc): Ditto. >(vfwmsac): Ditto. >(vfwnmsac): Ditto. >(vfwmacc_frm): Ditto. >(vfwnmacc_frm): Ditto. >(vfwmsac_frm): Ditto. >(vfwnmsac_frm): Ditto. >(vfsqrt): Ditto. >(vfsqrt_frm): Ditto. >(vfrsqrt7): Ditto. >(vfrec7): Ditto. >(vfrec7_frm): Ditto. >(vfmin): Ditto. >(vfmax): Ditto. >(vfsgnj): Ditto. >(vfsgnjn): Ditto. >(vfsgnjx): Ditto. >(vfneg): Ditto. >(vfabs): Ditto. >(vmfeq):
[PATCH] RISC-V: Add avail interface into function_group_info
In order to add other extension about vector,this patch add unsigned int (*avail) (void) into function_group_info to determine whether to register the intrinsic based on ISA info. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (DEF_RVV_FUNCTION): Add AVAIL def. (read_vl): Add avail_always interface. (vlenb): Ditto. (vsetvl): Ditto. (vsetvlmax): Ditto. (vle): Ditto. (vse): Ditto. (vlm): Ditto. (vsm): Ditto. (vlse): Ditto. (vsse): Ditto. (vluxei8): Ditto. (vluxei16): Ditto. (vluxei32): Ditto. (vluxei64): Ditto. (vloxei8): Ditto. (vloxei16): Ditto. (vloxei32): Ditto. (vloxei64): Ditto. (vsuxei8): Ditto. (vsuxei16): Ditto. (vsuxei32): Ditto. (vsuxei64): Ditto. (vsoxei8): Ditto. (vsoxei16): Ditto. (vsoxei32): Ditto. (vsoxei64):Ditto. (vleff): Ditto. (vadd):Ditto. (vsub):Ditto. (vrsub): Ditto. (vneg):Ditto. (vwaddu): Ditto. (vwsubu): Ditto. (vwadd): Ditto. (vwsub): Ditto. (vwcvt_x): Ditto. (vwcvtu_x):Ditto. (vzext): Ditto. (vsext): Ditto. (vadc):Ditto. (vmadc): Ditto. (vsbc): Ditto. (vmsbc): Ditto. (vand): Ditto. (vor): Ditto. (vxor): Ditto. (vnot): Ditto. (vsll): Ditto. (vsra): Ditto. (vsrl): Ditto. (vnsrl): Ditto. (vnsra): Ditto. (vncvt_x): Ditto. (vmseq): Ditto. (vmsne): Ditto. (vmsltu): Ditto. (vmslt): Ditto. (vmsleu): Ditto. (vmsle): Ditto. (vmsgtu): Ditto. (vmsgt): Ditto. (vmsgeu): Ditto. (vmsge): Ditto. (vminu): Ditto. (vmin): Ditto. (vmaxu): Ditto. (vmax): Ditto. (vmul): Ditto. (vmulh): Ditto. (vmulhu): Ditto. (vmulhsu): Ditto. (vdivu): Ditto. (vdiv): Ditto. (vremu): Ditto. (vrem): Ditto. (vwmul): Ditto. (vwmulu): Ditto. (vwmulsu): Ditto. (vmacc): Ditto. (vnmsac): Ditto. (vmadd): Ditto. (vnmsub): Ditto. (vwmaccu): Ditto. (vwmacc): Ditto. (vwmaccsu): Ditto. (vwmaccus): Ditto. (vmerge): Ditto. (vmv_v): Ditto. (vsaddu): Ditto. (vsadd): Ditto. (vssubu): Ditto. (vssub): Ditto. (vaaddu): Ditto. (vaadd): Ditto. (vasubu): Ditto. (vasub): Ditto. (vsmul): Ditto. (vssrl): Ditto. (vssra): Ditto. (vnclipu): Ditto. (vnclip): Ditto. (vfadd): Ditto. (vfsub): Ditto. (vfrsub): Ditto. (vfadd_frm): Ditto. (vfsub_frm): Ditto. (vfrsub_frm): Ditto. (vfwadd): Ditto. (vfwsub): Ditto. (vfwadd_frm): Ditto. (vfwsub_frm): Ditto. (vfmul): Ditto. (vfdiv): Ditto. (vfrdiv): Ditto. (vfmul_frm): Ditto. (vfdiv_frm): Ditto. (vfrdiv_frm): Ditto. (vfwmul): Ditto. (vfwmul_frm): Ditto. (vfmacc): Ditto. (vfnmsac): Ditto. (vfmadd): Ditto. (vfnmsub): Ditto. (vfnmacc): Ditto. (vfmsac): Ditto. (vfnmadd): Ditto. (vfmsub): Ditto. (vfmacc_frm): Ditto. (vfnmacc_frm): Ditto. (vfmsac_frm): Ditto. (vfnmsac_frm): Ditto. (vfmadd_frm): Ditto. (vfnmadd_frm): Ditto. (vfmsub_frm): Ditto. (vfnmsub_frm): Ditto. (vfwmacc): Ditto. (vfwnmacc): Ditto. (vfwmsac): Ditto. (vfwnmsac): Ditto. (vfwmacc_frm): Ditto. (vfwnmacc_frm): Ditto. (vfwmsac_frm): Ditto. (vfwnmsac_frm): Ditto. (vfsqrt): Ditto. (vfsqrt_frm): Ditto. (vfrsqrt7): Ditto. (vfrec7): Ditto. (vfrec7_frm): Ditto. (vfmin): Ditto. (vfmax): Ditto. (vfsgnj): Ditto. (vfsgnjn): Ditto. (vfsgnjx): Ditto. (vfneg): Ditto. (vfabs): Ditto. (vmfeq): Ditto. (vmfne): Ditto. (vmflt): Ditto. (vmfle): Ditto. (vmfgt): Ditto. (vmfge): Ditto. (vfclass): Ditto. (vfmerge): Ditto. (vfmv_v): Ditto. (vfcvt_x): Ditto. (vfcvt_xu): Ditto. (vfcvt_rtz_x): Ditto. (vfcvt_rtz_xu): Ditto. (vfcvt_f): Ditto. (vfcvt_x_frm): Ditto. (vfcvt_xu_frm): Ditto. (vfcvt_f_frm): Ditto. (vfwcvt_x): Ditto. (vfwcvt_xu): Ditto. (vfwcvt_rtz_x): Ditto. (vfwcvt_rtz_xu): Ditto. (vfwcvt_f): Ditto. (vfwcvt_x_frm): Ditto. (vfwcvt_xu_frm): Ditto. (vfncvt_x): Ditto. (vfncvt_xu): Ditto.
Re: Re: [PATCH 2/4][v2] RISC-V: Add crypto vector builtin function.
OK. Will do it firstly.
Thanks.
ESWIN
海宁奕斯伟集成电路设计有限公司
王峰
From: juzhe.zh...@rivai.ai
Date: 2023-12-07 10:39
To: wangfeng; gcc-patches
CC: kito.cheng; jeffreyalaw; zhusonghe; panciyan; wangfeng
Subject: Re: Re: [PATCH 2/4][v2] RISC-V: Add crypto vector builtin function.
I think you can send a single separate patch with adding unsigned int (*avail)
(void)
into current function_group_info first.
And test full coverage current rvv intrinsics.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-12-07 10:28
To: wangfeng; gcc-patches
CC: kito.cheng; jeffreyalaw; zhusonghe; panciyan; wangfeng
Subject: Re: [PATCH 2/4][v2] RISC-V: Add crypto vector builtin function.
+/* There is no op_type name in vaesz overloaded intrinsic */
+if (!((strcmp (instance.base_name, "vaesz") == 0) && overloaded_p))
+ b.append_name (operand_suffixes[instance.op_info->op]);
You can dedicate a shape for vaesz to avoid use strcmp.
diff --git a/gcc/config/riscv/riscv-vector-crypto-builtins-avail.h
b/gcc/config/riscv/riscv-vector-crypto-builtins-avail.h
new file mode 100755
index 000..c360c1d794f
--- /dev/null
+++ b/gcc/config/riscv/riscv-vector-crypto-builtins-avail.h
@@ -0,0 +1,25 @@
+#ifndef GCC_RISCV_VECTOR_CRYPTO_BUILTINS_AVAIL_H
+#define GCC_RISCV_VECTOR_CRYPTO_BUILTINS_AVAIL_H
+
+#include "insn-codes.h"
+namespace riscv_vector {
+
+/* Declare an availability predicate for built-in functions. */
+#define AVAIL(NAME, COND) \
+ static unsigned int \
+ riscv_vector_crypto_avail_##NAME (void) \
+ { \
+ return (COND); \
+ }
+
+AVAIL (zvbb, TARGET_ZVBB)
+AVAIL (zvbc, TARGET_ZVBC)
+AVAIL (zvkb_or_zvbb, TARGET_ZVKB || TARGET_ZVBB)
+AVAIL (zvkg, TARGET_ZVKG)
+AVAIL (zvkned, TARGET_ZVKNED)
+AVAIL (zvknha_or_zvknhb, TARGET_ZVKNHA || TARGET_ZVKNHB)
+AVAIL (zvknhb, TARGET_ZVKNHB)
+AVAIL (zvksed, TARGET_ZVKSED)
+AVAIL (zvksh, TARGET_ZVKSH)
+}
+#endif
Can you rename riscv-vector-crypto-builtins-avail.h into
riscv-vector-crypto-builtins-avail.h
make it into riscv-vector-builtins-avail.h
make AVAIL not the crypto specific.
make it general, so that we can use them for future BF16 vector support.
So, I think instead of create crypto_function_group_info, I prefer add unsigned
int (*avail) (void); into current function_group_info.
For current vector intrinsics:
DEF_RVV_FUNCTION (vlsegff, seg_fault_load, full_preds,
tuple_v_scalar_const_ptr_size_ptr_ops)
change it into:
DEF_RVV_FUNCTION (vlsegff, seg_fault_load, full_preds,
tuple_v_scalar_const_ptr_size_ptr_ops, true)
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-07 10:15
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; zhusonghe; panciyan; Feng Wang
Subject: [PATCH 2/4][v2] RISC-V: Add crypto vector builtin function.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
Add new function_base for crypto vector.
(class bitmanip): Ditto.
(class b_reverse):Ditto.
(class vwsll):Ditto.
(class clmul):Ditto.
(class vg_nhab): Ditto.
(class crypto_vv):Ditto.
(class crypto_vi):Ditto.
(class vaeskf2_vsm3c):Ditto.
(class vsm3me):Ditto.
(BASE): Add BASE declaration for crypto vector.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add new function_shape for crypto vector.
(struct crypto_vi_def): Ditto.
(SHAPE): Add SHAPE declaration of crypto vector.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
Add new data struct for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(DEF_VECTOR_CRYPTO_FUNCTION): New MACRO define of crypto vector.
(registered_function::overloaded_hash): Processing size_t uimm for C overloaded
func.
(handle_pragma_vector): Add registration for crypto vector.
* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
* config/riscv/riscv-vector-builtins.h (struct crypto_function_group_info):
Add new struct definition for crypto vector.
* config/riscv/t-riscv: Add building dependency files.
* config/riscv/riscv-vector-crypto-builtins-avail.h:
New file to control enable.
* config/riscv/riscv-vector-crypto-builtins-functions.def:
New file. Definition of crypto vector.
* config/riscv/riscv-vector-crypto-builtins-types.def:
New file. New type definition for crypto vector.
---
.../riscv/riscv-vector-builtins-bases.cc | 259 +-
.../riscv/riscv-vector-builtins-bases.h | 28 ++
.../riscv/riscv-vector-builtins-shapes.cc | 58 +++-
.../riscv/riscv-vector-builtins-shapes.h | 3
[PATCH 2/4][v2] RISC-V: Add crypto vector builtin function.
Patch v2:Optimize function_shape class for crypto_vector.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
Add new function_base for crypto vector.
(class bitmanip): Ditto.
(class b_reverse):Ditto.
(class vwsll):Ditto.
(class clmul):Ditto.
(class vg_nhab): Ditto.
(class crypto_vv):Ditto.
(class crypto_vi):Ditto.
(class vaeskf2_vsm3c):Ditto.
(class vsm3me):Ditto.
(BASE): Add BASE declaration for crypto vector.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add new function_shape for crypto vector.
(struct crypto_vi_def): Ditto.
(SHAPE): Add SHAPE declaration of crypto vector.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
Add new data struct for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(DEF_VECTOR_CRYPTO_FUNCTION): New MACRO define of crypto vector.
(registered_function::overloaded_hash): Processing size_t uimm for C
overloaded func.
(handle_pragma_vector): Add registration for crypto vector.
* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
* config/riscv/riscv-vector-builtins.h (struct
crypto_function_group_info):
Add new struct definition for crypto vector.
* config/riscv/t-riscv: Add building dependency files.
* config/riscv/riscv-vector-crypto-builtins-avail.h:
New file to control enable.
* config/riscv/riscv-vector-crypto-builtins-functions.def:
New file. Definition of crypto vector.
* config/riscv/riscv-vector-crypto-builtins-types.def:
New file. New type definition for crypto vector.
---
.../riscv/riscv-vector-builtins-bases.cc | 259 +-
.../riscv/riscv-vector-builtins-bases.h | 28 ++
.../riscv/riscv-vector-builtins-shapes.cc | 58 +++-
.../riscv/riscv-vector-builtins-shapes.h | 3 +
gcc/config/riscv/riscv-vector-builtins.cc | 152 +-
gcc/config/riscv/riscv-vector-builtins.def| 1 +
gcc/config/riscv/riscv-vector-builtins.h | 8 +
.../riscv-vector-crypto-builtins-avail.h | 25 ++
...riscv-vector-crypto-builtins-functions.def | 78 ++
.../riscv-vector-crypto-builtins-types.def| 21 ++
gcc/config/riscv/t-riscv | 2 +
11 files changed, 632 insertions(+), 3 deletions(-)
create mode 100755 gcc/config/riscv/riscv-vector-crypto-builtins-avail.h
create mode 100755 gcc/config/riscv/riscv-vector-crypto-builtins-functions.def
create mode 100755 gcc/config/riscv/riscv-vector-crypto-builtins-types.def
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d70468542ee..6d52230e9ba 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2127,6 +2127,207 @@ public:
}
};
+/* Below implements are vector crypto */
+/* Implements vandn.[vv,vx] */
+class vandn : public function_base
+{
+public:
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_vandn (e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_vandn_scalar (e.vector_mode
()));
+ default:
+gcc_unreachable ();
+ }
+ }
+};
+
+/* Implements vrol/vror/clz/ctz. */
+template
+class bitmanip : public function_base
+{
+public:
+ bool apply_tail_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool apply_mask_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool has_merge_operand_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+{
+ case OP_TYPE_v:
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_v (CODE, e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_v_scalar (CODE, e.vector_mode
()));
+ default:
+gcc_unreachable ();
+}
+ }
+};
+
+/* Implements vbrev/vbrev8/vrev8. */
+template
+class b_reverse : public function_base
+{
+public:
+ rtx expand
[PATCH 3/4][v2] RISC-V: Add crypto machine descriptions
Patch v2: Add crypto vector ins into RATIO attr and use vr as destination register. This patch add the crypto machine descriptions(vector-crypto.md) and some new iterators which are used by crypto vector ext. Co-Authored by: Songhe Zhu Co-Authored by: Ciyan Pan gcc/ChangeLog: * config/riscv/iterators.md: Add rotate insn name. * config/riscv/riscv.md: Add new insns name for crypto vector. * config/riscv/vector-iterators.md: Add new iterators for crypto vector. * config/riscv/vector.md: Add the corresponding attr for crypto vector. * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector. --- gcc/config/riscv/iterators.md| 4 +- gcc/config/riscv/riscv.md| 33 +- gcc/config/riscv/vector-crypto.md| 500 +++ gcc/config/riscv/vector-iterators.md | 41 +++ gcc/config/riscv/vector.md | 55 ++- 5 files changed, 612 insertions(+), 21 deletions(-) create mode 100755 gcc/config/riscv/vector-crypto.md diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index ecf033f2fa7..f332fba7031 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -304,7 +304,9 @@ (umax "maxu") (clz "clz") (ctz "ctz") -(popcount "cpop")]) +(popcount "cpop") +(rotate "rol") +(rotatert "ror")]) ;; --- ;; Int Iterators. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 935eeb7fd8e..a887f3cd412 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -428,6 +428,34 @@ ;; vcompressvector compress instruction ;; vmov whole vector register move ;; vector unknown vector instruction +;; 17. Crypto Vector instructions +;; vandncrypto vector bitwise and-not instructions +;; vbrevcrypto vector reverse bits in elements instructions +;; vbrev8 crypto vector reverse bits in bytes instructions +;; vrev8crypto vector reverse bytes instructions +;; vclz crypto vector count leading Zeros instructions +;; vctz crypto vector count lrailing Zeros instructions +;; vrol crypto vector rotate left instructions +;; vror crypto vector rotate right instructions +;; vwsllcrypto vector widening shift left logical instructions +;; vclmul crypto vector carry-less multiply - return low half instructions +;; vclmulh crypto vector carry-less multiply - return high half instructions +;; vghshcrypto vector add-multiply over GHASH Galois-Field instructions +;; vgmulcrypto vector multiply over GHASH Galois-Field instrumctions +;; vaesef crypto vector AES final-round encryption instructions +;; vaesem crypto vector AES middle-round encryption instructions +;; vaesdf crypto vector AES final-round decryption instructions +;; vaesdm crypto vector AES middle-round decryption instructions +;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation instructions +;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation instructions +;; vaeszcrypto vector AES round zero encryption/decryption instructions +;; vsha2ms crypto vector SHA-2 message schedule instructions +;; vsha2ch crypto vector SHA-2 two rounds of compression instructions +;; vsha2cl crypto vector SHA-2 two rounds of compression instructions +;; vsm4kcrypto vector SM4 KeyExpansion instructions +;; vsm4rcrypto vector SM4 Rounds instructions +;; vsm3me crypto vector SM3 Message Expansion instructions +;; vsm3ccrypto vector SM3 Compression instructions (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -447,7 +475,9 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov,vector" + vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, @@ -3747,6 +3777,7 @@ (include "thead.md") (include "generic-ooo.md") (include "vector.md") +(include "vector-crypto.md") (include "zicond.md") (include "zc.md") (include "corev.md") diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md new file mode 100755 index
[PATCH 1/4][v2] RISC-V:Add crypto vector implied ISA info.
Patch v2: Change the implied ISA info using the minimum set and add
dependencies info into the python script.
Due to the crypto vector entension is depend on the Vector extension,
so the "v" info is added into implied ISA info with the corresponding
crypto vector extension.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Modify implied ISA info.
* config/riscv/arch-canonicalize: Add crypto vector implied info.
---
gcc/common/config/riscv/riscv-common.cc | 9 +
gcc/config/riscv/arch-canonicalize | 21 +++--
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 6c210412515..a7aa3435a8a 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -120,6 +120,15 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvksc", "zvbc"},
{"zvksg", "zvks"},
{"zvksg", "zvkg"},
+ {"zvbb", "zvkb"},
+ {"zvbc", "zve64x"},
+ {"zvkb", "zve32x"},
+ {"zvkg", "zve32x"},
+ {"zvkned", "zve32x"},
+ {"zvknha", "zve32x"},
+ {"zvknhb", "zve64x"},
+ {"zvksed", "zve32x"},
+ {"zvksh", "zve32x"},
{"zfh", "zfhmin"},
{"zfhmin", "f"},
diff --git a/gcc/config/riscv/arch-canonicalize
b/gcc/config/riscv/arch-canonicalize
index ea2f67a0944..a8f47a1752b 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -69,12 +69,21 @@ IMPLIED_EXT = {
"zvl32768b" : ["zvl16384b"],
"zvl65536b" : ["zvl32768b"],
- "zvkn" : ["zvkned", "zvknhb", "zvbb", "zvkt"],
- "zvknc" : ["zvkn", "zvbc"],
- "zvkng" : ["zvkn", "zvkg"],
- "zvks" : ["zvksed", "zvksh", "zvbb", "zvkt"],
- "zvksc" : ["zvks", "zvbc"],
- "zvksg" : ["zvks", "zvkg"],
+ "zvkn" : ["zvkned", "zvknhb", "zvkb", "zvkt"],
+ "zvknc" : ["zvkn", "zvbc"],
+ "zvkng" : ["zvkn", "zvkg"],
+ "zvks" : ["zvksed", "zvksh", "zvkb", "zvkt"],
+ "zvksc" : ["zvks", "zvbc"],
+ "zvksg" : ["zvks", "zvkg"],
+ "zvbb" : ["zvkb"],
+ "zvbc" : ["zve64x"],
+ "zvkb" : ["zve32x"],
+ "zvkg" : ["zve32x"],
+ "zvkned" : ["zve32x"],
+ "zvknha" : ["zve32x"],
+ "zvknhb" : ["zve64x"],
+ "zvksed" : ["zve32x"],
+ "zvksh" : ["zve32x"],
}
def arch_canonicalize(arch, isa_spec):
--
2.17.1
Re: Re: [PATCH 1/4] RISC-V: Add crypto vector implied ISA info.
2023-12-06 11:33 Tsukasa OI wrote:
>On 2023/12/06 11:45, Feng Wang wrote:
>> Due to the crypto vector entension is depend on the Vector extension,
>> so the "v" info is added into implied ISA info with the corresponding
>> crypto vector extension.
>
>Hi Feng,
>
>It's true that vector crypto extensions are based on the vector
>extension but it *does not* mean that it requires full the 'V'
>extension. Vector crypto extensions also consider about embedded
>processors where VLEN < 128.
>
>Quoting the documentation:
>
>> The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the composite
>> extensions Zvkn
>> and Zvks-- require a Zve64x base, or application ("V") base Vector Extension.
>>
>> All of the other Vector Crypto Extensions can be built on any embedded
>> (Zve*) or application ("V")
>> base Vector Extension.
>
>So, correct dependencies to add are like follows:
>
>> + {"zvbb", "zvkb"},
>> + {"zvbc", "zve64x"},
>> + {"zvkb", "zve32x"},
>> + {"zvkg", "zve32x"},
>> + {"zvkned", "zve32x"},
>> + {"zvknha", "zve32x"},
>> + {"zvknhb", "zve64x"},
>> + {"zvksed", "zve32x"},
>> + {"zvksh", "zve32x"},
>
>Note that 'V' indirectly depends on both 'Zve32x' and 'Zve64x' so this
>would be fine to represent "or application ('V')" part quoted above.
>
>Also, consider adding those dependencies to the Python script
>gcc/config/riscv/arch-canonicalize.
>
>Thanks,
>Tsukasa
>
I modified this part. Thank you for your correction.
>
>
>
>>
>> gcc/ChangeLog:
>>
>> * common/config/riscv/riscv-common.cc: Add "v" into implied ISA info.
>> ---
>> gcc/common/config/riscv/riscv-common.cc | 9 +
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/gcc/common/config/riscv/riscv-common.cc
>> b/gcc/common/config/riscv/riscv-common.cc
>> index 6c210412515..dbb42ca2f1e 100644
>> --- a/gcc/common/config/riscv/riscv-common.cc
>> +++ b/gcc/common/config/riscv/riscv-common.cc
>> @@ -120,6 +120,15 @@ static const riscv_implied_info_t riscv_implied_info[] =
>> {"zvksc", "zvbc"},
>> {"zvksg", "zvks"},
>> {"zvksg", "zvkg"},
>> + {"zvbb", "zvkb"},
>> + {"zvbc", "v"},
>> + {"zvkb", "v"},
>> + {"zvkg", "v"},
>> + {"zvkned", "v"},
>> + {"zvknha", "v"},
>> + {"zvknhb", "v"},
>> + {"zvksed", "v"},
>> + {"zvksh", "v"},
>>
>> {"zfh", "zfhmin"},
>> {"zfhmin", "f"},
Re: Re: [PATCH 3/4] RISC-V: Add crypto vector machine descriptions
2023-12-06 14:53 juzhe.zhong wrote: >Do vector crypto instruction demand RATIO ? > >If no, add them into: > >;; It is valid for instruction that require sew/lmul ratio. >(define_attr "ratio" "" > (cond [(eq_attr "type" "vimov,vfmov,vldux,vldox,vstux,vstox,\ > vialu,vshift,vicmp,vimul,vidiv,vsalu,\ > vext,viwalu,viwmul,vicalu,vnshift,\ > vimuladd,vimerge,vaalu,vsmul,vsshift,\ > vnclip,viminmax,viwmuladd,vmffs,vmsfs,\ > vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,\ > vfwalu,vfwmul,vfsqrt,vfrecp,vfsgnj,vfcmp,\ > vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\ > vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\ > vfncvtftof,vfmuladd,vfwmuladd,vfclass,vired,\ > viwred,vfredu,vfredo,vfwredu,vfwredo,vimovvx,\ > vimovxv,vfmovvf,vfmovfv,vslideup,vslidedown,\ > vislide1up,vislide1down,vfslide1up,vfslide1down,\ > vgather,vcompress,vlsegdux,vlsegdox,vssegtux,vssegtox") > (const_int INVALID_ATTRIBUTE) > Modified, thanks! > >+(define_insn "@pred_vandn" >+ [(set (match_operand:VI 0 "register_operand" "=vd,vd") > >Seems all vector crypto instructions are not allowed to use v0 ? Why not use >vr? > >+ (set_attr "mode" "")]) >use is enough. Done. > >+(define_insn "@pred_vwsll_scalar" >+ [(set (match_operand:VWEXTI 0 "register_operand" "=") >+ (if_then_else:VWEXTI >+ (unspec: >+ [(match_operand: 1 "vector_mask_operand" "vmWc1") >+ (match_operand 5 "vector_length_operand" " rK") >+ (match_operand 6 "const_int_operand" " i") >+ (match_operand 7 "const_int_operand" " i") >+ (match_operand 8 "const_int_operand" " i") >+ (reg:SI VL_REGNUM) >+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) >+ (ashift:VWEXTI >+ (zero_extend:VWEXTI >+ (match_operand: 3 "register_operand" "vr")) >+ (match_operand: 4 "pmode_reg_or_uimm5_operand" "rK")) >+ (match_operand:VWEXTI 2 "vector_merge_operand" "0vu")))] >+ "TARGET_ZVBB" >+ "vwsll.v%o4\t%0,%3,%4%p1" >+ [(set_attr "type" "vwsll") >+ (set_attr "mode" "")]) > >Seems that we can leverage EEW widen overlap ? > >See RVV ISA: > > ;; According to RVV ISA: > ;; The destination EEW is greater than the source EEW, the source >EMUL is at least 1, > ;; and the overlap is in the highest-numbered part of the destination >register group > ;; (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, >v2, or v4 is not). > ;; So the source operand should have LMUL >= 1. > >Reference patch: >https://gcc.gnu.org/pipermail/gcc-patches/2023-December/638869.html > >Currently, I don't have a solution to support highest-number overlap for vv >instruction. >Keep them early clobber for now it ok. > > > >juzhe.zh...@rivai.ai Will update this part after your patch merged. > >From: Feng Wang >Date: 2023-12-06 10:45 >To: gcc-patches >CC: kito.cheng; jeffreyalaw; juzhe.zhong; zhusonghe; panciyan; Feng Wang >Subject: [PATCH 3/4] RISC-V: Add crypto vector machine descriptions >This patch add the crypto machine descriptions(vector-crypto.md) and >some new iterators which are used by crypto vector ext. > >Co-Authored by: Songhe Zhu >Co-Authored by: Ciyan Pan > >gcc/ChangeLog: > >* config/riscv/iterators.md: Add rotate insn name. >* config/riscv/riscv.md: Add new insns name for crypto vector. >* config/riscv/vector-iterators.md: Add new iterators for crypto vector. >* config/riscv/vector.md: Add the corresponding attr for crypto vector. >* config/riscv/vector-crypto.md: New file.The machine descriptions for crypto >vector. >--- >gcc/config/riscv/iterators.md | 4 +- >gcc/config/riscv/riscv.md | 33 +- >gcc/config/riscv/vector-crypto.md | 500 +++ >gcc/config/riscv/vector-iterators.md | 41 +++ >gcc/config/riscv/vector.md | 49 ++- >5 files changed, 607 insertions(+), 20 deletions(-) >create mode 100755 g
[PATCH 3/4] RISC-V: Add crypto vector machine descriptions
This patch add the crypto machine descriptions(vector-crypto.md) and some new iterators which are used by crypto vector ext. Co-Authored by: Songhe Zhu Co-Authored by: Ciyan Pan gcc/ChangeLog: * config/riscv/iterators.md: Add rotate insn name. * config/riscv/riscv.md: Add new insns name for crypto vector. * config/riscv/vector-iterators.md: Add new iterators for crypto vector. * config/riscv/vector.md: Add the corresponding attr for crypto vector. * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector. --- gcc/config/riscv/iterators.md| 4 +- gcc/config/riscv/riscv.md| 33 +- gcc/config/riscv/vector-crypto.md| 500 +++ gcc/config/riscv/vector-iterators.md | 41 +++ gcc/config/riscv/vector.md | 49 ++- 5 files changed, 607 insertions(+), 20 deletions(-) create mode 100755 gcc/config/riscv/vector-crypto.md diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index ecf033f2fa7..f332fba7031 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -304,7 +304,9 @@ (umax "maxu") (clz "clz") (ctz "ctz") -(popcount "cpop")]) +(popcount "cpop") +(rotate "rol") +(rotatert "ror")]) ;; --- ;; Int Iterators. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 935eeb7fd8e..a887f3cd412 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -428,6 +428,34 @@ ;; vcompressvector compress instruction ;; vmov whole vector register move ;; vector unknown vector instruction +;; 17. Crypto Vector instructions +;; vandncrypto vector bitwise and-not instructions +;; vbrevcrypto vector reverse bits in elements instructions +;; vbrev8 crypto vector reverse bits in bytes instructions +;; vrev8crypto vector reverse bytes instructions +;; vclz crypto vector count leading Zeros instructions +;; vctz crypto vector count lrailing Zeros instructions +;; vrol crypto vector rotate left instructions +;; vror crypto vector rotate right instructions +;; vwsllcrypto vector widening shift left logical instructions +;; vclmul crypto vector carry-less multiply - return low half instructions +;; vclmulh crypto vector carry-less multiply - return high half instructions +;; vghshcrypto vector add-multiply over GHASH Galois-Field instructions +;; vgmulcrypto vector multiply over GHASH Galois-Field instrumctions +;; vaesef crypto vector AES final-round encryption instructions +;; vaesem crypto vector AES middle-round encryption instructions +;; vaesdf crypto vector AES final-round decryption instructions +;; vaesdm crypto vector AES middle-round decryption instructions +;; vaeskf1 crypto vector AES-128 Forward KeySchedule generation instructions +;; vaeskf2 crypto vector AES-256 Forward KeySchedule generation instructions +;; vaeszcrypto vector AES round zero encryption/decryption instructions +;; vsha2ms crypto vector SHA-2 message schedule instructions +;; vsha2ch crypto vector SHA-2 two rounds of compression instructions +;; vsha2cl crypto vector SHA-2 two rounds of compression instructions +;; vsm4kcrypto vector SM4 KeyExpansion instructions +;; vsm4rcrypto vector SM4 Rounds instructions +;; vsm3me crypto vector SM3 Message Expansion instructions +;; vsm3ccrypto vector SM3 Compression instructions (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -447,7 +475,9 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo, vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv, vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, - vgather,vcompress,vmov,vector" + vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, + vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, @@ -3747,6 +3777,7 @@ (include "thead.md") (include "generic-ooo.md") (include "vector.md") +(include "vector-crypto.md") (include "zicond.md") (include "zc.md") (include "corev.md") diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md new file mode 100755 index 000..a40ecef4342 --- /dev/null +++ b/gcc/config/riscv/vector-crypto.md @@ -0,0
[PATCH 2/4] RISC-V: Add crypto vector builtin function.
This patch add the intrinsic funtions of crypto vector based on the
intrinsic doc(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob
/eopc/vector-crypto/auto-generated/vector-crypto/intrinsic_funcs.md).
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class vandn):
Add new function_base for crypto vector.
(class bitmanip): Ditto.
(class b_reverse):Ditto.
(class vwsll):Ditto.
(class clmul):Ditto.
(class vg_nhab): Ditto.
(class crypto_vv):Ditto.
(class crypto_vi):Ditto.
(class vaeskf2_vsm3c):Ditto.
(class vsm3me):Ditto.
(BASE): Add BASE declaration for crypto vector.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add new function_shape for crypto vector.
(struct crypto_vi_def): Ditto.
(SHAPE): Add SHAPE declaration of crypto vector.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
Add new data struct for crypto vector.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
(DEF_VECTOR_CRYPTO_FUNCTION): New MACRO define of crypto vector.
(registered_function::overloaded_hash): Processing size_t uimm for C
overloaded func.
(handle_pragma_vector): Add registration for crypto vector.
* config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
* config/riscv/riscv-vector-builtins.h (struct
crypto_function_group_info):
Add new struct definition for crypto vector.
* config/riscv/t-riscv: Add building dependency files.
* config/riscv/riscv-vector-crypto-builtins-avail.h:
New file to control enable.
* config/riscv/riscv-vector-crypto-builtins-functions.def:
New file. Definition of crypto vector.
* config/riscv/riscv-vector-crypto-builtins-types.def:
New file. New type definition for crypto vector.
---
.../riscv/riscv-vector-builtins-bases.cc | 259 +-
.../riscv/riscv-vector-builtins-bases.h | 28 ++
.../riscv/riscv-vector-builtins-shapes.cc | 66 -
.../riscv/riscv-vector-builtins-shapes.h | 4 +
gcc/config/riscv/riscv-vector-builtins.cc | 152 +-
gcc/config/riscv/riscv-vector-builtins.def| 1 +
gcc/config/riscv/riscv-vector-builtins.h | 8 +
.../riscv-vector-crypto-builtins-avail.h | 25 ++
...riscv-vector-crypto-builtins-functions.def | 78 ++
.../riscv-vector-crypto-builtins-types.def| 21 ++
gcc/config/riscv/t-riscv | 2 +
11 files changed, 641 insertions(+), 3 deletions(-)
create mode 100755 gcc/config/riscv/riscv-vector-crypto-builtins-avail.h
create mode 100755 gcc/config/riscv/riscv-vector-crypto-builtins-functions.def
create mode 100755 gcc/config/riscv/riscv-vector-crypto-builtins-types.def
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d70468542ee..6d52230e9ba 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2127,6 +2127,207 @@ public:
}
};
+/* Below implements are vector crypto */
+/* Implements vandn.[vv,vx] */
+class vandn : public function_base
+{
+public:
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_vandn (e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_vandn_scalar (e.vector_mode
()));
+ default:
+gcc_unreachable ();
+ }
+ }
+};
+
+/* Implements vrol/vror/clz/ctz. */
+template
+class bitmanip : public function_base
+{
+public:
+ bool apply_tail_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool apply_mask_policy_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+ bool has_merge_operand_p () const override
+ {
+return (CODE == CLZ || CODE == CTZ) ? false : true;
+ }
+
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+{
+ case OP_TYPE_v:
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_v (CODE, e.vector_mode ()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_v_scalar (CODE, e.vector_mode
()));
+ default:
+gcc_unreachable ();
+}
+ }
+};
+
+/* Implements vbrev/vbrev8/vrev8. */
+template
+class b_reverse : public function_base
+{
+public:
+ rtx expand (function_expander ) const override
+ {
+ return
[PATCH 1/4] RISC-V: Add crypto vector implied ISA info.
Due to the crypto vector entension is depend on the Vector extension,
so the "v" info is added into implied ISA info with the corresponding
crypto vector extension.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add "v" into implied ISA info.
---
gcc/common/config/riscv/riscv-common.cc | 9 +
1 file changed, 9 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 6c210412515..dbb42ca2f1e 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -120,6 +120,15 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvksc", "zvbc"},
{"zvksg", "zvks"},
{"zvksg", "zvkg"},
+ {"zvbb", "zvkb"},
+ {"zvbc", "v"},
+ {"zvkb", "v"},
+ {"zvkg", "v"},
+ {"zvkned", "v"},
+ {"zvknha", "v"},
+ {"zvknhb", "v"},
+ {"zvksed", "v"},
+ {"zvksh","v"},
{"zfh", "zfhmin"},
{"zfhmin", "f"},
--
2.17.1
Re: Re: [PATCH 1/7] RISC-V: Add intrinsic functions for crypto vector Zvbb extension
2023-12-04 16:01 Kito Cheng wrote: >Hi Feng: > >Thanks for the patch! a few inline comments below, also don't include >all test files from doc generator, only include a few within the patch >is fine, e.g. pick one for each group, so that it won't make GCC >source tree bloat too much. > OK. All the test cases are indeed too large, will be reduced. >> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md >> index 935eeb7fd8e..2a3777e168c 100644 >> --- a/gcc/config/riscv/riscv.md >> +++ b/gcc/config/riscv/riscv.md >> @@ -428,6 +428,15 @@ >> ;; vcompress vector compress instruction >> ;; vmov whole vector register move >> ;; vector unknown vector instruction >> +;; vandn crypto vector bitwise and-not instructions >> +;; vbrev crypto vector reverse bits in elements instructions >> +;; vbrev8 crypto vector reverse bits in bytes instructions >> +;; vrev8 crypto vector reverse bytes instructions >> +;; vclz crypto vector count leading Zeros instructions >> +;; vctz crypto vector count lrailing Zeros instructions >> +;; vrol crypto vector rotate left instructions >> +;; vror crypto vector rotate right instructions > >Use vialu for above operations, no new type for those instructions. > >> +;; vwsll crypto vector widening shift left logical instructions > >Rename to vwshift to make it consistent with vnshift. > >> diff --git a/gcc/config/riscv/vector-crypto.md >> b/gcc/config/riscv/vector-crypto.md >> new file mode 100755 >> index 000..0373cf6f48a >> --- /dev/null >> +++ b/gcc/config/riscv/vector-crypto.md >> @@ -0,0 +1,207 @@ >> +(define_c_enum "unspec" [ >> + ;; Zvbb unspecs >> + UNSPEC_VANDN >> + UNSPEC_VBREV >> + UNSPEC_VBREV8 >> + UNSPEC_VREV8 >> + UNSPEC_VCLZ >> + UNSPEC_VCTZ >> + UNSPEC_VROL >> + UNSPEC_VROR >> + UNSPEC_VWSLL >> +]) > >Could you use generic RTL code for andn, clz, ctl, rol, ror and wsll >rather than unspec? Got it! will optimize it., thanks! Feng Wang
[PATCH v2] RISC-V: Update crypto vector ISA info with latest spec
Rebase and resend this patch due to it was not added into patchwork
before. Kito had already reviewed it. Please refer to
https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg327499.html
This patch add the Zvkb subset of crypto vector extension. The
corresponding test cases have aslo been modified.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add zvkb ISA info.
* config/riscv/riscv.opt: Add Mask(ZVKB)
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zvkn-1.c: Replace zvbb with zvkb.
* gcc.target/riscv/zvkn.c: Ditto.
* gcc.target/riscv/zvknc-1.c:Ditto.
* gcc.target/riscv/zvknc-2.c:Ditto.
* gcc.target/riscv/zvknc.c: Ditto.
* gcc.target/riscv/zvkng-1.c:Ditto.
* gcc.target/riscv/zvkng-2.c:Ditto.
* gcc.target/riscv/zvkng.c: Ditto.
* gcc.target/riscv/zvks-1.c: Ditto.
* gcc.target/riscv/zvks.c: Ditto.
* gcc.target/riscv/zvksc-1.c:Ditto.
* gcc.target/riscv/zvksc-2.c:Ditto.
* gcc.target/riscv/zvksc.c: Ditto.
* gcc.target/riscv/zvksg-1.c:Ditto.
* gcc.target/riscv/zvksg-2.c:Ditto.
* gcc.target/riscv/zvksg.c: Ditto.
---
gcc/common/config/riscv/riscv-common.cc | 6 --
gcc/config/riscv/riscv.opt | 2 ++
gcc/testsuite/gcc.target/riscv/zvkn-1.c | 8
gcc/testsuite/gcc.target/riscv/zvkn.c| 4 ++--
gcc/testsuite/gcc.target/riscv/zvknc-1.c | 8
gcc/testsuite/gcc.target/riscv/zvknc-2.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvknc.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvkng-1.c | 8
gcc/testsuite/gcc.target/riscv/zvkng-2.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvkng.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvks-1.c | 8
gcc/testsuite/gcc.target/riscv/zvks.c| 4 ++--
gcc/testsuite/gcc.target/riscv/zvksc-1.c | 8
gcc/testsuite/gcc.target/riscv/zvksc-2.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvksc.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvksg-1.c | 8
gcc/testsuite/gcc.target/riscv/zvksg-2.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvksg.c | 4 ++--
18 files changed, 50 insertions(+), 46 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index ded85b4c578..6c210412515 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -106,7 +106,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvkn", "zvkned"},
{"zvkn", "zvknhb"},
- {"zvkn", "zvbb"},
+ {"zvkn", "zvkb"},
{"zvkn", "zvkt"},
{"zvknc", "zvkn"},
{"zvknc", "zvbc"},
@@ -114,7 +114,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvkng", "zvkg"},
{"zvks", "zvksed"},
{"zvks", "zvksh"},
- {"zvks", "zvbb"},
+ {"zvks", "zvkb"},
{"zvks", "zvkt"},
{"zvksc", "zvks"},
{"zvksc", "zvbc"},
@@ -253,6 +253,7 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zvbb", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvbc", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zvkb", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvkg", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvkned", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvknha", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1624,6 +1625,7 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zvbb", _options::x_riscv_zvb_subext, MASK_ZVBB},
{"zvbc", _options::x_riscv_zvb_subext, MASK_ZVBC},
+ {"zvkb", _options::x_riscv_zvb_subext, MASK_ZVKB},
{"zvkg", _options::x_riscv_zvk_subext, MASK_ZVKG},
{"zvkned", _options::x_riscv_zvk_subext, MASK_ZVKNED},
{"zvknha", _options::x_riscv_zvk_subext, MASK_ZVKNHA},
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 0c6517bdc8b..78186fff6c5 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -319,6 +319,8 @@ Mask(ZVBB) Var(riscv_zvb_subext)
Mask(ZVBC) Var(riscv_zvb_subext)
+Mask(ZVKB) Var(riscv_zvb_subext)
+
TargetVariable
int riscv_zvk_subext
diff --git a/gcc/testsuite/gcc.target/riscv/zvkn-1.c
b/gcc/testsuite/gcc.target/riscv/zvkn-1.c
index 23b255b4779..069a8f66c92 100644
--- a/gcc/testsuite/gcc.target/riscv/zvkn-1.c
+++ b/gcc/testsuite/gcc.target/riscv/zvkn-1.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvkned_zvknhb_zvbb_zvkt" { target { rv64 } } }
*/
-/* { dg-options "-march=rv32gc_zvkned_zvknhb_zvbb_zvkt" { target { rv32 } } }
*/
+/* { dg-options "-march=rv64gc_zvkned_zvknhb_zvkb_zvkt" { target { rv64 } } }
*/
+/* { dg-options "-march=rv32gc_zvkned_zvknhb_zvkb_zvkt" { target { rv32 } } }
*/
#ifndef __riscv_zvkn
#error "Feature macro for `Zvkn' not defined"
@@ -14,8 +14,8 @@
#error "Feature macro for `Zvknhb' not defined"
#endif
-#ifndef __riscv_zvbb
-#error "Feature macro for `Zvbb' not defined"
+#ifndef __riscv_zvkb
+#error "Feature macro for `Zvkb' not defined"
#endif
#ifndef __riscv_zvkt
diff --git a/gcc/testsuite/gcc.target/riscv/zvkn.c
回复: [PATCH 2/7] RISC-V: Add intrinsic functions for crypto vector Zvbc extension
2023-12-04 11:37 juzhe.zhong wrote: Will split again as you mentioned. Thanks. Feng Wang >Hi, eswin. > >Thanks for contributing vector crypto support. > >It seems patches mess up. Could you rebase your patch to the trunk GCC cleanly >and send it again. > >The patches look odd to me, for example: > > // ZVBB >-DEF_VECTOR_CRYPTO_FUNCTION (vandn, zvbb, full_preds, u_vvv_ops, zvkb_or_zvbb) >-DEF_VECTOR_CRYPTO_FUNCTION (vandn, zvbb, full_preds, u_vvx_ops, zvkb_or_zvbb) >-DEF_VECTOR_CRYPTO_FUNCTION (vbrev, zvbb, full_preds, u_vv_ops, zvbb) >-DEF_VECTOR_CRYPTO_FUNCTION (vbrev8, zvbb, full_preds, u_vv_ops, zvkb_or_zvbb) >-DEF_VECTOR_CRYPTO_FUNCTION (vrev8, zvbb, full_preds, u_vv_ops, zvkb_or_zvbb) >-DEF_VECTOR_CRYPTO_FUNCTION (vclz, zvbb, none_m_preds, u_vv_ops, zvbb) >-DEF_VECTOR_CRYPTO_FUNCTION (vctz, zvbb, none_m_preds, u_vv_ops, zvbb) >-DEF_VECTOR_CRYPTO_FUNCTION (vrol, zvbb, full_preds, u_vvv_ops, zvkb_or_zvbb) >-DEF_VECTOR_CRYPTO_FUNCTION (vrol, zvbb, full_preds, u_shift_vvx_ops, >zvkb_or_zvbb) >-DEF_VECTOR_CRYPTO_FUNCTION (vror, zvbb, full_preds, u_vvv_ops, zvkb_or_zvbb) >-DEF_VECTOR_CRYPTO_FUNCTION (vror, zvbb, full_preds, u_shift_vvx_ops, >zvkb_or_zvbb) >-DEF_VECTOR_CRYPTO_FUNCTION (vwsll, zvbb, full_preds, u_wvv_ops, zvbb) >-DEF_VECTOR_CRYPTO_FUNCTION (vwsll, zvbb, full_preds, u_shift_wvx_ops, zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vandn, zvbb_zvbc, full_preds, u_vvv_ops, >zvkb_or_zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vandn, zvbb_zvbc, full_preds, u_vvx_ops, >zvkb_or_zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vbrev, zvbb_zvbc, full_preds, u_vv_ops, zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vbrev8, zvbb_zvbc, full_preds, u_vv_ops, >zvkb_or_zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vrev8, zvbb_zvbc, full_preds, u_vv_ops, >zvkb_or_zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vclz, zvbb_zvbc, none_m_preds, u_vv_ops, zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vctz, zvbb_zvbc, none_m_preds, u_vv_ops, zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vrol, zvbb_zvbc, full_preds, u_vvv_ops, >zvkb_or_zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vrol, zvbb_zvbc, full_preds, u_shift_vvx_ops, >zvkb_or_zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vror, zvbb_zvbc, full_preds, u_vvv_ops, >zvkb_or_zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vror, zvbb_zvbc, full_preds, u_shift_vvx_ops, >zvkb_or_zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vwsll, zvbb_zvbc, full_preds, u_wvv_ops, zvbb) >+DEF_VECTOR_CRYPTO_FUNCTION (vwsll, zvbb_zvbc, full_preds, u_shift_wvx_ops, >zvbb) > >Seems you mess up your local development which is not easy to review. > >I would expecting patches as follows: > >1. Add crypto march support (riscv-common.cc） >2. Add crypto machine descriptions (vector-cryptio.md) >3. Add crypto builtin. >4. Add testcases. > >Thanks. > > > >juzhe.zh...@rivai.ai
[PATCH 7/7] RISC-V: Add intrinsic functions for crypto vector Zvksh extension
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvksh extension. And all
the test cases are added for api-testing.
Co-Authored by: Songhe Zhu
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zvksh in riscv_implied_info.
* config/riscv/riscv-vector-builtins-bases.cc (class vaeskf2): Add new
function_base for Zvksh.
(class vaeskf2_vsm3c): Ditto.
(class vsm3me): Ditto.
(BASE): Add Zvksh BASE declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct zvbb_zvbc_def):
Add function_builder for Zvksh.
(struct crypto_vv_def): Ditto.
* config/riscv/riscv-vector-crypto-builtins-avail.h (AVAIL): Add enable
condition.
* config/riscv/riscv-vector-crypto-builtins-functions.def (vsm4r): Add
intrinsc def.
(vsm3me): Ditto.
(vsm3c): Ditto.
* config/riscv/riscv.md: Add Zvksh ins name.
* config/riscv/vector-crypto.md (sm3c): Add Zvksh md patterns.
(@pred_vaeskf2_scalar): Ditto.
(@pred_vi_nomaskedoff_scalar): Ditto.
(@pred_vsm3me): Ditto.
* config/riscv/vector.md: Add the corresponding attribute for Zvksh.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zvk/zvk.exp:
* gcc.target/riscv/zvk/zvksh/vsm3c.c: New test.
* gcc.target/riscv/zvk/zvksh/vsm3c_overloaded.c: New test.
* gcc.target/riscv/zvk/zvksh/vsm3me.c: New test.
* gcc.target/riscv/zvk/zvksh/vsm3me_overloaded.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 1 +
.../riscv/riscv-vector-builtins-bases.cc | 26 --
.../riscv/riscv-vector-builtins-bases.h | 2 +
.../riscv/riscv-vector-builtins-shapes.cc | 10 ++--
.../riscv-vector-crypto-builtins-avail.h | 1 +
...riscv-vector-crypto-builtins-functions.def | 5 +-
gcc/config/riscv/riscv.md | 4 +-
gcc/config/riscv/vector-crypto.md | 43 +---
gcc/config/riscv/vector.md| 12 ++---
gcc/testsuite/gcc.target/riscv/zvk/zvk.exp| 2 +
.../gcc.target/riscv/zvk/zvksh/vsm3c.c| 51 +++
.../riscv/zvk/zvksh/vsm3c_overloaded.c| 51 +++
.../gcc.target/riscv/zvk/zvksh/vsm3me.c | 51 +++
.../riscv/zvk/zvksh/vsm3me_overloaded.c | 51 +++
14 files changed, 286 insertions(+), 24 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3c.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3c_overloaded.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3me.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvksh/vsm3me_overloaded.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 87595b135ef..dbb42ca2f1e 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -128,6 +128,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvknha", "v"},
{"zvknhb", "v"},
{"zvksed", "v"},
+ {"zvksh","v"},
{"zfh", "zfhmin"},
{"zfhmin", "f"},
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 83309f07661..07a9dc49104 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2302,8 +2302,9 @@ public:
}
};
-/* Implements vaeskf2. */
-class vaeskf2 : public function_base
+/* Implements vaeskf2/vsm3c. */
+template
+class vaeskf2_vsm3c : public function_base
{
public:
bool apply_mask_policy_p () const override { return false; }
@@ -2312,7 +2313,20 @@ public:
rtx expand (function_expander ) const override
{
-return e.use_exact_insn (code_for_pred_vaeskf2_scalar (e.vector_mode ()));
+return e.use_exact_insn (code_for_pred_vi_nomaskedoff_scalar (UNSPEC,
e.vector_mode ()));
+ }
+};
+
+/* Implements vsm3me. */
+class vsm3me : public function_base
+{
+public:
+ bool apply_mask_policy_p () const override { return false; }
+ bool use_mask_predication_p () const override { return false; }
+
+ rtx expand (function_expander ) const override
+ {
+return e.use_exact_insn (code_for_pred_vsm3me (e.vector_mode ()));
}
};
@@ -2593,12 +2607,14 @@ static CONSTEXPR const crypto_vv
vaesdf_obj;
static CONSTEXPR const crypto_vv vaesdm_obj;
static CONSTEXPR const crypto_vv vaesz_obj;
static CONSTEXPR const crypto_vi vaeskf1_obj;
-static CONSTEXPR const vaeskf2 vaeskf2_obj;
+static CONSTEXPR const vaeskf2_vsm3c vaeskf2_obj;
static CONSTEXPR const vg_nhab vsha2ms_obj;
static CONSTEXPR const vg_nhab vsha2ch_obj;
static CONSTEXPR const vg_nhab vsha2cl_obj;
static CONSTEXPR const crypto_vi vsm4k_obj;
static
[PATCH 5/7] RISC-V: Add intrinsic functions for crypto vector Zvknh[ab] extension
This patch add the intrinsic functions(according to https://github.com/ riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/ vector-crypto/intrinsic_funcs.md) for crypto vector Zvknh[ab] extension. And all the test cases are added for api-testing. Co-Authored by: Songhe Zhu gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Zvknh[ab] in riscv_implied_info. * config/riscv/riscv-vector-builtins-bases.cc (class vghsh): Add new function_base for Zvknh[ab]. (class vg_nhab): Ditto. (BASE): Add Zvknh[ab] BASE declaration. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def): Add function_builder for Zvknh[ab]. * config/riscv/riscv-vector-builtins.cc: Define new data struct for Zvknh[ab]. * config/riscv/riscv-vector-crypto-builtins-avail.h (AVAIL): Add enable condition. * config/riscv/riscv-vector-crypto-builtins-functions.def (vaeskf2): Add intrinsc def. (vsha2ms): Ditto. (vsha2ch): Ditto. (vsha2cl): Ditto. * config/riscv/riscv.md: Add Zvknh[ab] ins name. * config/riscv/vector-crypto.md (sha2ms): Add Zvknh[ab] md patterns. (@pred_vghsh): Ditto. (@pred_v): Dito. (@pred_vgmul): Ditto * config/riscv/vector.md: Add the corresponding attribute for Zvknh[ab]. gcc/testsuite/ChangeLog: * gcc.target/riscv/zvk/zvk.exp: * gcc.target/riscv/zvk/zvknha/vsha2ch.c: New test. * gcc.target/riscv/zvk/zvknha/vsha2ch_overloaded.c: New test. * gcc.target/riscv/zvk/zvknha/vsha2cl.c: New test. * gcc.target/riscv/zvk/zvknha/vsha2cl_overloaded.c: New test. * gcc.target/riscv/zvk/zvknha/vsha2ms.c: New test. * gcc.target/riscv/zvk/zvknha/vsha2ms_overloaded.c: New test. * gcc.target/riscv/zvk/zvknhb/vsha2ch.c: New test. * gcc.target/riscv/zvk/zvknhb/vsha2ch_overloaded.c: New test. * gcc.target/riscv/zvk/zvknhb/vsha2cl.c: New test. * gcc.target/riscv/zvk/zvknhb/vsha2cl_overloaded.c: New test. * gcc.target/riscv/zvk/zvknhb/vsha2ms.c: New test. * gcc.target/riscv/zvk/zvknhb/vsha2ms_overloaded.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 2 + .../riscv/riscv-vector-builtins-bases.cc | 15 +++- .../riscv/riscv-vector-builtins-bases.h | 3 + .../riscv/riscv-vector-builtins-shapes.cc | 7 +- gcc/config/riscv/riscv-vector-builtins.cc | 6 ++ .../riscv-vector-crypto-builtins-avail.h | 2 + ...riscv-vector-crypto-builtins-functions.def | 10 ++- gcc/config/riscv/riscv.md | 27 +++--- gcc/config/riscv/vector-crypto.md | 55 +--- gcc/config/riscv/vector.md| 12 +-- gcc/testsuite/gcc.target/riscv/zvk/zvk.exp| 4 + .../gcc.target/riscv/zvk/zvknha/vsha2ch.c | 51 .../riscv/zvk/zvknha/vsha2ch_overloaded.c | 51 .../gcc.target/riscv/zvk/zvknha/vsha2cl.c | 51 .../riscv/zvk/zvknha/vsha2cl_overloaded.c | 51 .../gcc.target/riscv/zvk/zvknha/vsha2ms.c | 51 .../riscv/zvk/zvknha/vsha2ms_overloaded.c | 51 .../gcc.target/riscv/zvk/zvknhb/vsha2ch.c | 83 +++ .../riscv/zvk/zvknhb/vsha2ch_overloaded.c | 83 +++ .../gcc.target/riscv/zvk/zvknhb/vsha2cl.c | 83 +++ .../riscv/zvk/zvknhb/vsha2cl_overloaded.c | 83 +++ .../gcc.target/riscv/zvk/zvknhb/vsha2ms.c | 83 +++ .../riscv/zvk/zvknhb/vsha2ms_overloaded.c | 83 +++ 23 files changed, 892 insertions(+), 55 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvknha/vsha2ch.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvknha/vsha2ch_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvknha/vsha2cl.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvknha/vsha2cl_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvknha/vsha2ms.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvknha/vsha2ms_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvknhb/vsha2ch.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvknhb/vsha2ch_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvknhb/vsha2cl.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvknhb/vsha2cl_overloaded.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvknhb/vsha2ms.c create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvknhb/vsha2ms_overloaded.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 60a174d4801..7201ac3866c 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -125,6 +125,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
[PATCH 6/7] RISC-V: Add intrinsic functions for crypto vector Zvksed extension.
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvksed extension. And all
the test cases are added for api-testing.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zvksed in riscv_implied_info.
* config/riscv/riscv-vector-builtins-bases.cc (class vaeskf1): Add new
function_base for Zvksed.
(class crypto_vi): Ditto.
(BASE): Add Zvksed BASE declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add function_builder for Zvksed.
* config/riscv/riscv-vector-crypto-builtins-avail.h (AVAIL): Add enable
condition.
* config/riscv/riscv-vector-crypto-builtins-functions.def (vsha2cl):
Add intrinsc def.
(vsm4k): Ditto.
(vsm4r): Ditto.
* config/riscv/riscv.md: Add Zvksed ins name.
* config/riscv/vector-crypto.md (sm4k): Add Zvksed md patterns.
(@pred_vaeskf1_scalar):Ditto.
(@pred_crypto_vi_scalar): Ditto.
* config/riscv/vector.md: Add the corresponding attribute for Zvksed.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zvk/zvk.exp:
* gcc.target/riscv/zvk/zvksed/vsm4k.c: New test.
* gcc.target/riscv/zvk/zvksed/vsm4k_overloaded.c: New test.
* gcc.target/riscv/zvk/zvksed/vsm4r.c: New test.
* gcc.target/riscv/zvk/zvksed/vsm4r_overloaded.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 1 +
.../riscv/riscv-vector-builtins-bases.cc | 13 +-
.../riscv/riscv-vector-builtins-bases.h | 2 +
.../riscv/riscv-vector-builtins-shapes.cc | 2 +-
.../riscv-vector-crypto-builtins-avail.h | 1 +
...riscv-vector-crypto-builtins-functions.def | 10 +-
gcc/config/riscv/riscv.md | 5 +-
gcc/config/riscv/vector-crypto.md | 40 +++--
gcc/config/riscv/vector.md| 20 ++-
gcc/testsuite/gcc.target/riscv/zvk/zvk.exp| 3 +-
.../gcc.target/riscv/zvk/zvksed/vsm4k.c | 50 ++
.../riscv/zvk/zvksed/vsm4k_overloaded.c | 50 ++
.../gcc.target/riscv/zvk/zvksed/vsm4r.c | 170 ++
.../riscv/zvk/zvksed/vsm4r_overloaded.c | 170 ++
14 files changed, 505 insertions(+), 32 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvksed/vsm4k.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvksed/vsm4k_overloaded.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvksed/vsm4r.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvksed/vsm4r_overloaded.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 7201ac3866c..87595b135ef 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -127,6 +127,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvkned", "v"},
{"zvknha", "v"},
{"zvknhb", "v"},
+ {"zvksed", "v"},
{"zfh", "zfhmin"},
{"zfhmin", "f"},
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index a3670ec5b38..83309f07661 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2288,8 +2288,9 @@ public:
}
};
-/* Implements vaeskf1. */
-class vaeskf1 : public function_base
+/* Implements vaeskf1/vsm4k. */
+template
+class crypto_vi : public function_base
{
public:
bool apply_mask_policy_p () const override { return false; }
@@ -2297,7 +2298,7 @@ public:
rtx expand (function_expander ) const override
{
-return e.use_exact_insn (code_for_pred_vaeskf1_scalar (e.vector_mode ()));
+return e.use_exact_insn (code_for_pred_crypto_vi_scalar (UNSPEC,
e.vector_mode ()));
}
};
@@ -2591,11 +2592,13 @@ static CONSTEXPR const crypto_vv
vaesem_obj;
static CONSTEXPR const crypto_vv vaesdf_obj;
static CONSTEXPR const crypto_vv vaesdm_obj;
static CONSTEXPR const crypto_vv vaesz_obj;
-static CONSTEXPR const vaeskf1 vaeskf1_obj;
+static CONSTEXPR const crypto_vi vaeskf1_obj;
static CONSTEXPR const vaeskf2 vaeskf2_obj;
static CONSTEXPR const vg_nhab vsha2ms_obj;
static CONSTEXPR const vg_nhab vsha2ch_obj;
static CONSTEXPR const vg_nhab vsha2cl_obj;
+static CONSTEXPR const crypto_vi vsm4k_obj;
+static CONSTEXPR const crypto_vv vsm4r_obj;
/* Declare the function base NAME, pointing it to an instance
of class _obj. */
@@ -2882,4 +2885,6 @@ BASE (vaeskf2)
BASE (vsha2ms)
BASE (vsha2ch)
BASE (vsha2cl)
+BASE (vsm4k)
+BASE (vsm4r)
} // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 0560b0008f0..e9e6d7bfe7f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++
[PATCH 4/7] RISC-V: Add intrinsic functions for crypto vector Zvkned extension
This patch add the intrinsic functions(according to https://github.com/ riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/ vector-crypto/intrinsic_funcs.md) for crypto vector Zvkned extension. And all the test cases are added for api-testing. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Zvkned in riscv_implied_info. * config/riscv/riscv-vector-builtins-bases.cc (class crypto_vv): Add new function_base for Zvkned. (class vaeskf1): Ditto. (class vgmul): Ditto. (class vaeskf2): Ditto. (BASE): Add Zvkned BASE declaration. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (struct zvbb_zvbc_def): Add new function_builder for Zvkned. (struct crypto_vi_def): Ditto. (SHAPE): Add Zvkned SHAPE declaration. * config/riscv/riscv-vector-builtins-shapes.h: Ditto. * config/riscv/riscv-vector-builtins.cc (registered_function::overloaded_hash): Process the overloaded of size_t. * config/riscv/riscv-vector-builtins.def (vi): Add new operator type. * config/riscv/riscv-vector-crypto-builtins-avail.h (AVAIL): Add enable condition. * config/riscv/riscv-vector-crypto-builtins-functions.def (vgmul): Optimize vgmul. (vaesef): Add intrinsc def. (vaesem): Ditto. (vaesdf): Ditto. (vaesdm): Ditto. (vaesz): Ditto. (vaeskf1) Ditto. (vaeskf2) Ditto. * config/riscv/riscv.md: Add Zvkned ins name. * config/riscv/vector-crypto.md (aesef): Add Zvkned md patterns. (vv): Ditto. (@pred_crypto_vv): Ditto. (@pred_crypto_vvx1_scalar): Ditto. (@pred_crypto_vvx2_scalar): Ditto. (@pred_crypto_vvx4_scalar): Ditto. (@pred_crypto_vvx8_scalar): Ditto. (@pred_crypto_vvx16_scalar): Ditto. (@pred_vaeskf1_scalar): Ditto. (@pred_vaeskf2_scalar): Ditto. * config/riscv/vector-iterators.md: Add new iterators for Zvkned. * config/riscv/vector.md: Add the corresponding attribute for Zvkned. gcc/testsuite/ChangeLog: * gcc.target/riscv/zvk/zvk.exp: * gcc.target/riscv/zvk/zvkned/vaesdf.c: New test. * gcc.target/riscv/zvk/zvkned/vaesdf_overloaded.c: New test. * gcc.target/riscv/zvk/zvkned/vaesdm.c: New test. * gcc.target/riscv/zvk/zvkned/vaesdm_overloaded.c: New test. * gcc.target/riscv/zvk/zvkned/vaesef.c: New test. * gcc.target/riscv/zvk/zvkned/vaesef_overloaded.c: New test. * gcc.target/riscv/zvk/zvkned/vaesem.c: New test. * gcc.target/riscv/zvk/zvkned/vaesem_overloaded.c: New test. * gcc.target/riscv/zvk/zvkned/vaeskf1.c: New test. * gcc.target/riscv/zvk/zvkned/vaeskf1_overloaded.c: New test. * gcc.target/riscv/zvk/zvkned/vaeskf2.c: New test. * gcc.target/riscv/zvk/zvkned/vaeskf2_overloaded.c: New test. * gcc.target/riscv/zvk/zvkned/vaesz.c: New test. * gcc.target/riscv/zvk/zvkned/vaesz_overloaded.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 1 + .../riscv/riscv-vector-builtins-bases.cc | 80 +++- .../riscv/riscv-vector-builtins-bases.h | 7 + .../riscv/riscv-vector-builtins-shapes.cc | 41 +++- .../riscv/riscv-vector-builtins-shapes.h | 1 + gcc/config/riscv/riscv-vector-builtins.cc | 62 +- gcc/config/riscv/riscv-vector-builtins.def| 1 + .../riscv-vector-crypto-builtins-avail.h | 1 + ...riscv-vector-crypto-builtins-functions.def | 34 +++- gcc/config/riscv/riscv.md | 8 +- gcc/config/riscv/vector-crypto.md | 184 ++ gcc/config/riscv/vector-iterators.md | 32 +++ gcc/config/riscv/vector.md| 23 ++- gcc/testsuite/gcc.target/riscv/zvk/zvk.exp| 2 + .../gcc.target/riscv/zvk/zvkned/vaesdf.c | 169 .../riscv/zvk/zvkned/vaesdf_overloaded.c | 169 .../gcc.target/riscv/zvk/zvkned/vaesdm.c | 170 .../riscv/zvk/zvkned/vaesdm_overloaded.c | 170 .../gcc.target/riscv/zvk/zvkned/vaesef.c | 170 .../riscv/zvk/zvkned/vaesef_overloaded.c | 170 .../gcc.target/riscv/zvk/zvkned/vaesem.c | 170 .../riscv/zvk/zvkned/vaesem_overloaded.c | 170 .../gcc.target/riscv/zvk/zvkned/vaeskf1.c | 50 + .../riscv/zvk/zvkned/vaeskf1_overloaded.c | 50 + .../gcc.target/riscv/zvk/zvkned/vaeskf2.c | 50 + .../riscv/zvk/zvkned/vaeskf2_overloaded.c | 50 + .../gcc.target/riscv/zvk/zvkned/vaesz.c | 130 + .../riscv/zvk/zvkned/vaesz_overloaded.c | 130 + 28 files changed, 2278 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvkned/vaesdf.c create mode 100644
[PATCH 3/7] RISC-V: Add intrinsic functions for crypto vector Zvkg extension
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvkg extension. And all
the test cases are added for api-testing.
Co-Authored by: Songhe Zhu
Co-Authored by: Ciyan Pan
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zvkg in riscv_implied_info.
* config/riscv/riscv-vector-builtins-bases.cc (class vghsh):Add new
function_base for Zvkg.
(class vgmul): Ditto.
(BASE): Add Zvkg BASE declaration.
* config/riscv/riscv-vector-builtins-bases.h:Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
Add function_builder for Zvkg.
(SHAPE): Add Zvkg SHAPE declaration.
* config/riscv/riscv-vector-builtins-shapes.h:Dito.
* config/riscv/riscv-vector-builtins.cc: Define new data struct for
Zvkg.
* config/riscv/riscv-vector-crypto-builtins-avail.h (AVAIL): Add enable
condition.
* config/riscv/riscv-vector-crypto-builtins-functions.def (vghsh): Add
intrinsc def.
(vgmul): Ditto.
* config/riscv/riscv.md: Add Zvkg ins name.
* config/riscv/vector-crypto.md (@pred_vghsh): Add Zvkg md
patterns.
(@pred_vgmul): Ditto.
* config/riscv/vector-iterators.md: Add new iterators for Zvkg.
* config/riscv/vector.md: Add the corresponding attribute for Zvkg.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zvk/zvk.exp:
* gcc.target/riscv/zvk/zvkg/vghsh.c: New test.
* gcc.target/riscv/zvk/zvkg/vghsh_overloaded.c: New test.
* gcc.target/riscv/zvk/zvkg/vgmul.c: New test.
* gcc.target/riscv/zvk/zvkg/vgmul_overloaded.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 1 +
.../riscv/riscv-vector-builtins-bases.cc | 29 +++
.../riscv/riscv-vector-builtins-bases.h | 2 +
.../riscv/riscv-vector-builtins-shapes.cc | 23 +
.../riscv/riscv-vector-builtins-shapes.h | 1 +
gcc/config/riscv/riscv-vector-builtins.cc | 15 ++
.../riscv-vector-crypto-builtins-avail.h | 1 +
...riscv-vector-crypto-builtins-functions.def | 3 ++
gcc/config/riscv/riscv.md | 4 +-
gcc/config/riscv/vector-crypto.md | 43 +++-
gcc/config/riscv/vector-iterators.md | 4 ++
gcc/config/riscv/vector.md| 19 +++
gcc/testsuite/gcc.target/riscv/zvk/zvk.exp| 2 +
.../gcc.target/riscv/zvk/zvkg/vghsh.c | 51 +++
.../riscv/zvk/zvkg/vghsh_overloaded.c | 51 +++
.../gcc.target/riscv/zvk/zvkg/vgmul.c | 51 +++
.../riscv/zvk/zvkg/vgmul_overloaded.c | 51 +++
17 files changed, 340 insertions(+), 11 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvkg/vghsh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvkg/vghsh_overloaded.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvkg/vgmul.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvkg/vgmul_overloaded.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 296500e15df..3eefd0263f9 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -123,6 +123,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvbb", "zvkb"},
{"zvbc", "v"},
{"zvkb", "v"},
+ {"zvkg", "v"},
{"zfh", "zfhmin"},
{"zfhmin", "f"},
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 45b1e563ff4..0cb9b2925af 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2227,6 +2227,31 @@ public:
}
};
+class vghsh : public function_base
+{
+public:
+ bool apply_mask_policy_p () const override { return false; }
+ bool use_mask_predication_p () const override { return false; }
+ bool has_merge_operand_p () const override { return false; }
+ rtx expand (function_expander ) const override
+ {
+ return e.use_exact_insn (code_for_pred_vghsh (e.vector_mode ()));
+ }
+};
+
+
+class vgmul : public function_base
+{
+public:
+ bool apply_mask_policy_p () const override { return false; }
+ bool use_mask_predication_p () const override { return false; }
+ bool has_merge_operand_p () const override { return false; }
+ rtx expand (function_expander ) const override
+ {
+ return e.use_exact_insn (code_for_pred_vgmul (e.vector_mode ()));
+ }
+};
+
static CONSTEXPR const vsetvl vsetvl_obj;
static CONSTEXPR const vsetvl vsetvlmax_obj;
static CONSTEXPR const loadstore vle_obj;
@@ -2496,6 +2521,8 @@ static CONSTEXPR const vcltzvctz_obj;
static CONSTEXPR const vwsll vwsll_obj;
static CONSTEXPR const clmul vclmul_obj;
static CONSTEXPR const clmul
[PATCH 2/7] RISC-V: Add intrinsic functions for crypto vector Zvbc extension
This patch add the intrinsic functions(according to https://github.com/
riscv-non-isa/rvv-intrinsic-doc/blob/eopc/vector-crypto/auto-generated/
vector-crypto/intrinsic_funcs.md) for crypto vector Zvbc extension. And all
the test cases are added for api-testing.
Co-Authored by: Songhe Zhu
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zvbc in riscv_implied_info.
* config/riscv/riscv-vector-builtins-bases.cc (class clmul):Add new
function_base for Zvbc.
(BASE): Add Zvbc BASE declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct zvbb_def): Add
new function_builder for Zvbc.
(struct zvbb_zvbc_def): Combine function_base of Zvbb and Zvbc.
(SHAPE): Add Zvbc SHAPE declaration.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc
(DEF_RVV_CRYPTO_SEW32_OPS):Define new data struct for Zvbc.
(DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
* config/riscv/riscv-vector-crypto-builtins-avail.h (AVAIL): Add enable
condition.
* config/riscv/riscv-vector-crypto-builtins-functions.def (vandn): Add
intrinsc def.
(vbrev): Ditto.
(vbrev8): Ditto.
(vrev8): Ditto.
(vclz): Ditto.
(vctz): Ditto.
(vrol): Ditto.
(vror): Ditto.
(vwsll): Ditto.
(vclmul): Ditto.
(vclmulh):Ditto.
* config/riscv/riscv.md: Add Zvbc ins name.
* config/riscv/vector-crypto.md (h): Add Zvbc md patterns.
(@pred_vclmul): Ditto.
(@pred_vclmul_scalar): Ditto.
* config/riscv/vector-iterators.md: Add new iterators for Zvbc.
* config/riscv/vector.md: Add the corresponding attribute for Zvbc.
* config/riscv/riscv-vector-crypto-builtins-types.def: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zvk/zvk.exp:
* gcc.target/riscv/zvk/zvbc/vclmul.c: New test.
* gcc.target/riscv/zvk/zvbc/vclmul_overloaded.c: New test.
* gcc.target/riscv/zvk/zvbc/vclmulh.c: New test.
* gcc.target/riscv/zvk/zvbc/vclmulh_overloaded.c: New test.
---
gcc/common/config/riscv/riscv-common.cc | 1 +
.../riscv/riscv-vector-builtins-bases.cc | 22 ++
.../riscv/riscv-vector-builtins-bases.h | 2 +
.../riscv/riscv-vector-builtins-shapes.cc | 6 +-
.../riscv/riscv-vector-builtins-shapes.h | 2 +-
gcc/config/riscv/riscv-vector-builtins.cc | 29 +++
.../riscv-vector-crypto-builtins-avail.h | 1 +
...riscv-vector-crypto-builtins-functions.def | 31 +--
.../riscv-vector-crypto-builtins-types.def| 21 ++
gcc/config/riscv/riscv.md | 5 +-
gcc/config/riscv/vector-crypto.md | 50 +
gcc/config/riscv/vector-iterators.md | 5 +
gcc/config/riscv/vector.md| 14 +-
.../gcc.target/riscv/zvk/zvbc/vclmul.c| 208 ++
.../riscv/zvk/zvbc/vclmul_overloaded.c| 208 ++
.../gcc.target/riscv/zvk/zvbc/vclmulh.c | 208 ++
.../riscv/zvk/zvbc/vclmulh_overloaded.c | 208 ++
gcc/testsuite/gcc.target/riscv/zvk/zvk.exp| 2 +
18 files changed, 998 insertions(+), 25 deletions(-)
create mode 100755 gcc/config/riscv/riscv-vector-crypto-builtins-types.def
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvbc/vclmul.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvbc/vclmul_overloaded.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvbc/vclmulh.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zvk/zvbc/vclmulh_overloaded.c
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index a5fb492c690..296500e15df 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -121,6 +121,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvksg", "zvks"},
{"zvksg", "zvkg"},
{"zvbb", "zvkb"},
+ {"zvbc", "v"},
{"zvkb", "v"},
{"zfh", "zfhmin"},
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index e41343b4a1a..45b1e563ff4 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2209,6 +2209,24 @@ public:
}
};
+template
+class clmul : public function_base
+{
+public:
+ rtx expand (function_expander ) const override
+ {
+switch (e.op_info->op)
+ {
+ case OP_TYPE_vv:
+return e.use_exact_insn (code_for_pred_vclmul (UNSPEC, e.vector_mode
()));
+ case OP_TYPE_vx:
+return e.use_exact_insn (code_for_pred_vclmul_scalar (UNSPEC,
e.vector_mode ()));
+ default:
+gcc_unreachable ();
+ }
+ }
+};
+
static CONSTEXPR const vsetvl vsetvl_obj;
static CONSTEXPR const vsetvl vsetvlmax_obj;
static CONSTEXPR const
[PATCH] RISC-V: Update crypto vector ISA info with latest spec
This patch add the Zvkb subset of crypto vector extension. The
corresponding test cases have aslo been modified.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add zvkb ISA info.
* config/riscv/riscv.opt: Add Mask(ZVKB)
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zvkn-1.c: Replace zvbb with zvkb.
* gcc.target/riscv/zvkn.c: Ditto.
* gcc.target/riscv/zvknc-1.c: Ditto.
* gcc.target/riscv/zvknc-2.c: Ditto.
* gcc.target/riscv/zvknc.c: Ditto.
* gcc.target/riscv/zvkng-1.c: Ditto.
* gcc.target/riscv/zvkng-2.c: Ditto.
* gcc.target/riscv/zvkng.c: Ditto.
* gcc.target/riscv/zvks-1.c: Ditto.
* gcc.target/riscv/zvks.c: Ditto.
* gcc.target/riscv/zvksc-1.c: Ditto.
* gcc.target/riscv/zvksc-2.c: Ditto.
* gcc.target/riscv/zvksc.c: Ditto.
* gcc.target/riscv/zvksg-1.c: Ditto.
* gcc.target/riscv/zvksg-2.c: Ditto.
* gcc.target/riscv/zvksg.c: Ditto.
---
gcc/common/config/riscv/riscv-common.cc | 6 --
gcc/config/riscv/riscv.opt | 2 ++
gcc/testsuite/gcc.target/riscv/zvkn-1.c | 8
gcc/testsuite/gcc.target/riscv/zvkn.c| 4 ++--
gcc/testsuite/gcc.target/riscv/zvknc-1.c | 8
gcc/testsuite/gcc.target/riscv/zvknc-2.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvknc.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvkng-1.c | 8
gcc/testsuite/gcc.target/riscv/zvkng-2.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvkng.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvks-1.c | 8
gcc/testsuite/gcc.target/riscv/zvks.c| 4 ++--
gcc/testsuite/gcc.target/riscv/zvksc-1.c | 8
gcc/testsuite/gcc.target/riscv/zvksc-2.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvksc.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvksg-1.c | 8
gcc/testsuite/gcc.target/riscv/zvksg-2.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zvksg.c | 4 ++--
18 files changed, 50 insertions(+), 46 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index ded85b4c578..6c210412515 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -106,7 +106,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvkn", "zvkned"},
{"zvkn", "zvknhb"},
- {"zvkn", "zvbb"},
+ {"zvkn", "zvkb"},
{"zvkn", "zvkt"},
{"zvknc", "zvkn"},
{"zvknc", "zvbc"},
@@ -114,7 +114,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zvkng", "zvkg"},
{"zvks", "zvksed"},
{"zvks", "zvksh"},
- {"zvks", "zvbb"},
+ {"zvks", "zvkb"},
{"zvks", "zvkt"},
{"zvksc", "zvks"},
{"zvksc", "zvbc"},
@@ -253,6 +253,7 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zvbb", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvbc", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zvkb", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvkg", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvkned", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvknha", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1624,6 +1625,7 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zvbb", _options::x_riscv_zvb_subext, MASK_ZVBB},
{"zvbc", _options::x_riscv_zvb_subext, MASK_ZVBC},
+ {"zvkb", _options::x_riscv_zvb_subext, MASK_ZVKB},
{"zvkg", _options::x_riscv_zvk_subext, MASK_ZVKG},
{"zvkned", _options::x_riscv_zvk_subext, MASK_ZVKNED},
{"zvknha", _options::x_riscv_zvk_subext, MASK_ZVKNHA},
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 0c6517bdc8b..78186fff6c5 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -319,6 +319,8 @@ Mask(ZVBB) Var(riscv_zvb_subext)
Mask(ZVBC) Var(riscv_zvb_subext)
+Mask(ZVKB) Var(riscv_zvb_subext)
+
TargetVariable
int riscv_zvk_subext
diff --git a/gcc/testsuite/gcc.target/riscv/zvkn-1.c
b/gcc/testsuite/gcc.target/riscv/zvkn-1.c
index 23b255b4779..069a8f66c92 100644
--- a/gcc/testsuite/gcc.target/riscv/zvkn-1.c
+++ b/gcc/testsuite/gcc.target/riscv/zvkn-1.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zvkned_zvknhb_zvbb_zvkt" { target { rv64 } } }
*/
-/* { dg-options "-march=rv32gc_zvkned_zvknhb_zvbb_zvkt" { target { rv32 } } }
*/
+/* { dg-options "-march=rv64gc_zvkned_zvknhb_zvkb_zvkt" { target { rv64 } } }
*/
+/* { dg-options "-march=rv32gc_zvkned_zvknhb_zvkb_zvkt" { target { rv32 } } }
*/
#ifndef __riscv_zvkn
#error "Feature macro for `Zvkn' not defined"
@@ -14,8 +14,8 @@
#error "Feature macro for `Zvknhb' not defined"
#endif
-#ifndef __riscv_zvbb
-#error "Feature macro for `Zvbb' not defined"
+#ifndef __riscv_zvkb
+#error "Feature macro for `Zvkb' not defined"
#endif
#ifndef __riscv_zvkt
diff --git a/gcc/testsuite/gcc.target/riscv/zvkn.c
b/gcc/testsuite/gcc.target/riscv/zvkn.c
index 0047ebdede6..bcecbcc7e77 100644
--- a/gcc/testsuite/gcc.target/riscv/zvkn.c
+++ b/gcc/testsuite/gcc.target/riscv/zvkn.c
@@ -14,8 +14,8 @@
#error "Feature macro for
Re: Re: [PATCH v2] gimple-match.pd Add more optimization for gimple_cond
On 2023-11-28 11:06 Andrew Pinski wrote:
>On Mon, Nov 27, 2023 at 6:56 PM Feng Wang wrote:
>>
>> The link of PATCH v1:
>> https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg326661.html
>> This patch add another condition for gimple-cond optimization. Refer to
>> the following test case.
>> int foo1 (int data, int res)
>> {
>> res = data & 0xf;
>> res |= res << 4;
>> if (res < 0x22)
>> return 0x22;
>> return res;
>> }
>> with the compilation flag "-O2",
>> before this patch the log info of phiopt2 pass is
>> [local count: 1073741824]:
>> res_5 = data_1(D) & 15;
>> _6 = (unsigned int) res_5;
>> _7 = _6 * 17;
>> res_8 = (int) _7;
>> if (_7 <= 33)
>> goto ; [21.72%]
>> else
>> goto ; [78.28%]
>>
>> [local count: 233216728]:
>>
>> [local count: 1073741824]:
>> # _9 = PHI
>> return _9;
>> after this patch the the log info of phiopt2 pass is
>> [local count: 1073741824]:
>> res_5 = data_1(D) & 15;
>> _6 = (unsigned int) res_5;
>> _7 = _6 * 17;
>> res_8 = (int) _7;
>> _10 = MAX_EXPR <_7, 34>;
>> _3 = (int) _10;
>> return _3;
>> This patch optimizes the phi node to generate "MAX_EXPR".
>> The root cause of minmax replacement failure is the type of "_7"
>> is unsigned, but the type of const_int "34" is signed. It makes
>> types_match (c2_type, from_type) return false. So I add another
>> condition to process this scenario.
>>
>> gcc/ChangeLog:
>>
>> * match.pd: Add another condition to process type mismatch.
>
>This should most likely be:
> ((cond (cmp (convert1? x) c1) (convert2? x) c2) pattern): Also allow
>conversions that only change the sign.
>
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.dg/tree-ssa/phi-opt-41.c: New test.
>> ---
>> gcc/match.pd | 5 -
>> gcc/testsuite/gcc.dg/tree-ssa/phi-opt-41.c | 24 ++
>> 2 files changed, 28 insertions(+), 1 deletion(-)
>> create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/phi-opt-41.c
>>
>> diff --git a/gcc/match.pd b/gcc/match.pd
>> index 95225e4ca5f..e864845bfa9 100644
>> --- a/gcc/match.pd
>> +++ b/gcc/match.pd
>> @@ -5419,7 +5419,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
>> && (types_match (c2_type, from_type)
>> || (TYPE_PRECISION (c2_type) > TYPE_PRECISION (from_type)
>> && (TYPE_UNSIGNED (from_type)
>> - || TYPE_SIGN (c2_type) == TYPE_SIGN (from_type)
>> + || TYPE_SIGN (c2_type) == TYPE_SIGN (from_type)))
>> + || (TYPE_UNSIGNED (from_type) != TYPE_UNSIGNED (c2_type)
>> + && TYPE_PRECISION (c2_type) == TYPE_PRECISION (from_type)
>> + && !TYPE_OVERFLOW_WRAPS (c2_type
>
>What is the need for TYPE_OVERFLOW_WRAPS here? Also I think you just
>need the check for TYPE_PRECISION instead of the rest.
>Maybe instead of types_match here, tree_nop_conversion_p could be used
>instead. I am not 100% sure though.
>
>I also suspect you should add a few other testcases that don't depend
>on VRP changing things. Maybe a runtime test too.
>
>Thanks,
>Andrew
>
I want to make sure the cont_int "c2" won't be overflow,so I use the
TYPE_OVERFLOW_WRAPS.
I checked the code , tree_nop_conversion_p judge the TYPE_PRECISION or
TYPE_MODE and doesn't
care the unsigned_flag, it should be fine for this scenario, I'm not sure if
there's a problem with this
modification, I will run the regression to check whether it causes other
issues.
Thanks,
Feng Wang
>> {
>> if (cmp != EQ_EXPR)
>> code = minmax_from_comparison (cmp, @1, @3, @1, @2);
>> diff --git a/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-41.c
>> b/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-41.c
>> new file mode 100644
>> index 000..d1101c2f9f7
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-41.c
>> @@ -0,0 +1,24 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-O2 -fdump-tree-phiopt2" } */
>> +
>> +int foo1 (int data, int res)
>> +{
>> + res = data & 0xf;
>> + res |= res << 4;
>> + if (res < 0x22)
>> + return 0x22;
>> + return res;
>> +}
>> +
>> +int foo2 (int data, int res)
>> +{
>> + res = data & 0xf;
>> + unsigned int r = res;
>> + r*=17;
>> + res = r;
>> + if (r < 0x22)
>> + return 0x22;
>> + return res;
>> +}
>> +
>> +/* { dg-final { scan-tree-dump-times "MAX_EXPR" 2 "phiopt2" } } */
>> \ No newline at end of file
>> --
>> 2.17.1
>>
[PATCH v2] gimple-match.pd Add more optimization for gimple_cond
The link of PATCH v1:
https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg326661.html
This patch add another condition for gimple-cond optimization. Refer to
the following test case.
int foo1 (int data, int res)
{
res = data & 0xf;
res |= res << 4;
if (res < 0x22)
return 0x22;
return res;
}
with the compilation flag "-O2",
before this patch the log info of phiopt2 pass is
[local count: 1073741824]:
res_5 = data_1(D) & 15;
_6 = (unsigned int) res_5;
_7 = _6 * 17;
res_8 = (int) _7;
if (_7 <= 33)
goto ; [21.72%]
else
goto ; [78.28%]
[local count: 233216728]:
[local count: 1073741824]:
# _9 = PHI
return _9;
after this patch the the log info of phiopt2 pass is
[local count: 1073741824]:
res_5 = data_1(D) & 15;
_6 = (unsigned int) res_5;
_7 = _6 * 17;
res_8 = (int) _7;
_10 = MAX_EXPR <_7, 34>;
_3 = (int) _10;
return _3;
This patch optimizes the phi node to generate "MAX_EXPR".
The root cause of minmax replacement failure is the type of "_7"
is unsigned, but the type of const_int "34" is signed. It makes
types_match (c2_type, from_type) return false. So I add another
condition to process this scenario.
gcc/ChangeLog:
* match.pd: Add another condition to process type mismatch.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/phi-opt-41.c: New test.
---
gcc/match.pd | 5 -
gcc/testsuite/gcc.dg/tree-ssa/phi-opt-41.c | 24 ++
2 files changed, 28 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/phi-opt-41.c
diff --git a/gcc/match.pd b/gcc/match.pd
index 95225e4ca5f..e864845bfa9 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -5419,7 +5419,10 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
&& (types_match (c2_type, from_type)
|| (TYPE_PRECISION (c2_type) > TYPE_PRECISION (from_type)
&& (TYPE_UNSIGNED (from_type)
-|| TYPE_SIGN (c2_type) == TYPE_SIGN (from_type)
+|| TYPE_SIGN (c2_type) == TYPE_SIGN (from_type)))
+ || (TYPE_UNSIGNED (from_type) != TYPE_UNSIGNED (c2_type)
+ && TYPE_PRECISION (c2_type) == TYPE_PRECISION (from_type)
+ && !TYPE_OVERFLOW_WRAPS (c2_type
{
if (cmp != EQ_EXPR)
code = minmax_from_comparison (cmp, @1, @3, @1, @2);
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-41.c
b/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-41.c
new file mode 100644
index 000..d1101c2f9f7
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/phi-opt-41.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-phiopt2" } */
+
+int foo1 (int data, int res)
+{
+ res = data & 0xf;
+ res |= res << 4;
+ if (res < 0x22)
+return 0x22;
+ return res;
+}
+
+int foo2 (int data, int res)
+{
+ res = data & 0xf;
+ unsigned int r = res;
+ r*=17;
+ res = r;
+ if (r < 0x22)
+return 0x22;
+ return res;
+}
+
+/* { dg-final { scan-tree-dump-times "MAX_EXPR" 2 "phiopt2" } } */
\ No newline at end of file
--
2.17.1
Re: Re: [PATCH] gimple-vr-values:Add constraint for gimple-cond optimization
On 2023-11-23 14:34 Andrew Pinski wrote:
>
>On Wed, Nov 22, 2023 at 10:07 PM Feng Wang wrote:
>>
>> This patch add another condition for gimple-cond optimization. Refer to
>> the following test case.
>> int foo1 (int data, int res)
>> {
>> res = data & 0xf;
>> res |= res << 4;
>> if (res < 0x22)
>> return 0x22;
>> return res;
>> }
>> with the compilation flag "-march=rv64gc_zba_zbb -mabi=lp64d -O2",
>> before this patch the compilation result is
>> foo1:
>> andi a0,a0,15
>> slliw a5,a0,4
>> addw a3,a5,a0
>> li a4,33
>> add a0,a5,a0
>> bleu a3,a4,.L5
>> ret
>> .L5:
>> li a0,34
>> ret
>> after this patch the compilation result is
>> foo1:
>> andi a0,a0,15
>> slliw a5,a0,4
>> add a5,a5,a0
>> li a0,34
>> max a0,a5,a0
>> ret
>> The reason is in the pass_early_vrp, the arg0 of gimple_cond
>> is replaced,but the PHI node still use the arg0.
>> The some of evrp pass logs are as follows
>> gimple_assign
>> gimple_assign
>> gimple_cond
>> goto ; [INV]
>> else
>> goto ; [INV]
>>
>> :
>> // predicted unlikely by early return (on trees) predictor.
>>
>> :
>> # gimple_phi <_2, 34(3), res_5(2)>
>> The arg0 of gimple_cond is replaced by _9,but the gimple_phi still
>> uses res_5,it will cause optimization fail of PHI node to MAX_EXPR.
>> So the next_use_is_phi is added to control the replacement.
>
>I don't think this is the correct appoarch here.
>We end up with the same original issue if we had wrote it like:
>```
>int foo1 (int data, int res)
>{
> res = data & 0xf;
> unsigned int r = res;
> r*=17;
> res = r;
> if (r < 0x22)
> return 0x22;
> return res;
>}
>```
>I suspect instead we should extend the match.pd patterns to match this max.
>We should be able to extend:
>```
>(for cmp (lt le gt ge eq ne)
> (simplify
> (cond (cmp (convert1? @1) INTEGER_CST@3) (convert2? @1) INTEGER_CST@2)
> (with
>```
>To match instead by changing the second @1 with @4 and then using
>bitwise_equal_p . If @1 != @4 but bitwise_equal_p is true, you need to
>make sure the outer convert1/convert2 are nop conversions so that you
>get the same extension I think ...
>
>Note you could instead improve minmax_replacement but I have been in
>the process of moving those changes to match.pd.
>
>Thanks,
>Andrew Pinski
Thanks for your feedback. The minmax replacement happens in phiopt pass, there
is one condition
that requires the "arg_false"(from PHI node) should be same with "smaller"(from
gimple_cond).
So I made this change. But as you said, this modification is not very suitable,
and I have not considered
it comprehensively. I'm not very familiar with match.pd, can it solve this
judgment problem?
Thanks,
Feng Wang
>
>>
>> gcc/ChangeLog:
>>
>> * vr-values.cc (next_use_is_phi):
>> (simplify_using_ranges::simplify_casted_compare):
>> add new function next_use_is_phi to control the replacement.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/zbb-min-max-04.c: New test.
>> ---
>> gcc/testsuite/gcc.target/riscv/zbb-min-max-04.c | 14 ++
>> gcc/vr-values.cc | 15 ++-
>> 2 files changed, 28 insertions(+), 1 deletion(-)
>> create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-min-max-04.c
>>
>> diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-04.c
>> b/gcc/testsuite/gcc.target/riscv/zbb-min-max-04.c
>> new file mode 100644
>> index 000..8c3e87a35e0
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-04.c
>> @@ -0,0 +1,14 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=rv64gc_zba_zbb -mabi=lp64d" } */
>> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
>> +
>> +int foo1 (int data, int res)
>> +{
>> + res = data & 0xf;
>> + res |= res << 4;
>> + if (res < 0x22
[PATCH] gimple-vr-values:Add constraint for gimple-cond optimization
This patch add another condition for gimple-cond optimization. Refer to
the following test case.
int foo1 (int data, int res)
{
res = data & 0xf;
res |= res << 4;
if (res < 0x22)
return 0x22;
return res;
}
with the compilation flag "-march=rv64gc_zba_zbb -mabi=lp64d -O2",
before this patch the compilation result is
foo1:
andia0,a0,15
slliw a5,a0,4
addwa3,a5,a0
li a4,33
add a0,a5,a0
bleua3,a4,.L5
ret
.L5:
li a0,34
ret
after this patch the compilation result is
foo1:
andia0,a0,15
slliw a5,a0,4
add a5,a5,a0
li a0,34
max a0,a5,a0
ret
The reason is in the pass_early_vrp, the arg0 of gimple_cond
is replaced,but the PHI node still use the arg0.
The some of evrp pass logs are as follows
gimple_assign
gimple_assign
gimple_cond
goto ; [INV]
else
goto ; [INV]
:
// predicted unlikely by early return (on trees) predictor.
:
# gimple_phi <_2, 34(3), res_5(2)>
The arg0 of gimple_cond is replaced by _9,but the gimple_phi still
uses res_5,it will cause optimization fail of PHI node to MAX_EXPR.
So the next_use_is_phi is added to control the replacement.
gcc/ChangeLog:
* vr-values.cc (next_use_is_phi):
(simplify_using_ranges::simplify_casted_compare):
add new function next_use_is_phi to control the replacement.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-min-max-04.c: New test.
---
gcc/testsuite/gcc.target/riscv/zbb-min-max-04.c | 14 ++
gcc/vr-values.cc| 15 ++-
2 files changed, 28 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-min-max-04.c
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-min-max-04.c
b/gcc/testsuite/gcc.target/riscv/zbb-min-max-04.c
new file mode 100644
index 000..8c3e87a35e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-min-max-04.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba_zbb -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+int foo1 (int data, int res)
+{
+ res = data & 0xf;
+ res |= res << 4;
+ if (res < 0x22)
+return 0x22;
+ return res;
+}
+
+/* { dg-final { scan-assembler-times "max\t" 1 } } */
\ No newline at end of file
diff --git a/gcc/vr-values.cc b/gcc/vr-values.cc
index ecb294131b0..1f7a727c638 100644
--- a/gcc/vr-values.cc
+++ b/gcc/vr-values.cc
@@ -1263,6 +1263,18 @@ simplify_using_ranges::simplify_compare_using_ranges_1
(tree_code _code, tr
return happened;
}
+/* Return true if the next use of SSA_NAME is PHI node */
+bool
+next_use_is_phi (tree arg)
+{
+ use_operand_p imm = &(SSA_NAME_IMM_USE_NODE (arg));
+ use_operand_p next = imm->next;
+ if (next && next->loc.stmt
+ && (gimple_code (next->loc.stmt) == GIMPLE_PHI))
+return true;
+ return false;
+}
+
/* Simplify OP0 code OP1 when OP1 is a constant and OP0 was a SSA_NAME
defined by a type conversion. Replacing OP0 with RHS of the type conversion.
Doing so makes the conversion dead which helps subsequent passes. */
@@ -1305,7 +1317,8 @@ simplify_using_ranges::simplify_casted_compare (tree_code
&, tree , tree
if (TREE_CODE (innerop) == SSA_NAME
&& !POINTER_TYPE_P (TREE_TYPE (innerop))
&& !SSA_NAME_OCCURS_IN_ABNORMAL_PHI (innerop)
- && desired_pro_or_demotion_p (TREE_TYPE (innerop), TREE_TYPE (op0)))
+ && desired_pro_or_demotion_p (TREE_TYPE (innerop), TREE_TYPE (op0))
+ && !next_use_is_phi (op0))
{
value_range vr;
--
2.17.1
Re: Re: [PATCH v3] RISC-V:Optimize the MASK opt generation
Hi, Kito & Jeff Due to National Day reasons, I was unable to reply to the email in a timely manner. Thank you for making the necessary changes to this patch. For the introduction of this bug, I will also carefully summarize my experience and lessons to avoid the recurrence of such problems. Thank you again! ------ Feng Wang >Proposed fix, and verified with "mawk" and "gawk -P" (gawk with posix >mode) on my linux also some other report it work on freebsd, just wait >review :) > >https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631785.html > >On Tue, Oct 3, 2023 at 2:07 AM Jeff Law wrote: >> >> >> >> On 10/2/23 12:03, David Edelsohn wrote: >> > On Mon, Oct 2, 2023 at 1:59 PM Jeff Law > > <mailto:jeffreya...@gmail.com>> wrote: >> > >> > >> > >> > On 10/2/23 11:20, David Edelsohn wrote: >> > > Wang, >> > > >> > > The AWK portions of this patch broke bootstrap on AIX. >> > > >> > > Also, the AWK portions are common code, not RISC-V specific. I >> > don't >> > > see anywhere that the common portions of the patch were reviewed or >> > > approved by anyone with authority to approve the changes to the >> > AWK files. >> > > >> > > This patch should not have been committed without approval by a >> > reviewer >> > > with authority for that portion of the compiler and should have been >> > > tested on targets other than RISC-V if common parts of the >> > compiler were >> > > changed. >> > I acked the generic bits. So the lack of testing on another target is >> > on me. >> > >> > >> > Hi, Jeff >> > >> > Sorry. I didn't see a comment from a global reviewer in the V3 thread. >> NP. >> >> > >> > I am using Gawk on AIX. After the change, I see a parse error from >> > gawk. I'm rebuilding with a checkout just before the change to confirm >> > that it was the source of the error, and it seems to be past that >> > failure location. I didn't keep the exact error. Once I get past this >> > build cycle, I'll reproduce it. >> I think there's already a patch circulating which fixes this. It broke >> at least one other platform. Hopefully it'll all be sorted out today. >> >> >> jeff
[PATCH v6] RISC-V:Optimize the MASK opt generation
New patch add some comments and update docs for this new usage. --- Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)" to generate MASK and TARGET MACRO automatically. This patch improve the MACRO generation of MASK_* and TARGET_*. Due to the more and more riscv extensions are added, the default target_flag is full. Before this patch,if you want to add new MACRO,you should define the MACRO in the riscv-opts.h manually. After this patch, you just need two steps: 1.Define the new TargetVariable. 2.Define "MASK(name) Var(new_target_flag). gcc/ChangeLog: * config/riscv/riscv-opts.h (MASK_ZICSR): (MASK_ZIFENCEI): Delete; (MASK_ZIHINTNTL):Ditto; (MASK_ZIHINTPAUSE): Ditto; (TARGET_ZICSR): Ditto; (TARGET_ZIFENCEI): Ditto; (TARGET_ZIHINTNTL): Ditto; (TARGET_ZIHINTPAUSE):Ditto; (MASK_ZAWRS):Ditto; (TARGET_ZAWRS): Ditto; (MASK_ZBA): Ditto; (MASK_ZBB): Ditto; (MASK_ZBC): Ditto; (MASK_ZBS): Ditto; (TARGET_ZBA):Ditto; (TARGET_ZBB):Ditto; (TARGET_ZBC):Ditto; (TARGET_ZBS):Ditto; (MASK_ZFINX):Ditto; (MASK_ZDINX):Ditto; (MASK_ZHINX):Ditto; (MASK_ZHINXMIN): Ditto; (TARGET_ZFINX): Ditto; (TARGET_ZDINX): Ditto; (TARGET_ZHINX): Ditto; (TARGET_ZHINXMIN): Ditto; (MASK_ZBKB): Ditto; (MASK_ZBKC): Ditto; (MASK_ZBKX): Ditto; (MASK_ZKNE): Ditto; (MASK_ZKND): Ditto; (MASK_ZKNH): Ditto; (MASK_ZKR): Ditto; (MASK_ZKSED):Ditto; (MASK_ZKSH): Ditto; (MASK_ZKT): Ditto; (TARGET_ZBKB): Ditto; (TARGET_ZBKC): Ditto; (TARGET_ZBKX): Ditto; (TARGET_ZKNE): Ditto; (TARGET_ZKND): Ditto; (TARGET_ZKNH): Ditto; (TARGET_ZKR):Ditto; (TARGET_ZKSED): Ditto; (TARGET_ZKSH): Ditto; (TARGET_ZKT):Ditto; (MASK_ZTSO): Ditto; (TARGET_ZTSO): Ditto; (MASK_VECTOR_ELEN_32): Ditto; (MASK_VECTOR_ELEN_64): Ditto; (MASK_VECTOR_ELEN_FP_32):Ditto; (MASK_VECTOR_ELEN_FP_64):Ditto; (MASK_VECTOR_ELEN_FP_16):Ditto; (TARGET_VECTOR_ELEN_32): Ditto; (TARGET_VECTOR_ELEN_64): Ditto; (TARGET_VECTOR_ELEN_FP_32):Ditto; (TARGET_VECTOR_ELEN_FP_64):Ditto; (TARGET_VECTOR_ELEN_FP_16):Ditto; (MASK_ZVBB): Ditto; (MASK_ZVBC): Ditto; (TARGET_ZVBB): Ditto; (TARGET_ZVBC): Ditto; (MASK_ZVKG): Ditto; (MASK_ZVKNED): Ditto; (MASK_ZVKNHA): Ditto; (MASK_ZVKNHB): Ditto; (MASK_ZVKSED): Ditto; (MASK_ZVKSH): Ditto; (MASK_ZVKN): Ditto; (MASK_ZVKNC): Ditto; (MASK_ZVKNG): Ditto; (MASK_ZVKS): Ditto; (MASK_ZVKSC): Ditto; (MASK_ZVKSG): Ditto; (MASK_ZVKT): Ditto; (TARGET_ZVKG): Ditto; (TARGET_ZVKNED): Ditto; (TARGET_ZVKNHA): Ditto; (TARGET_ZVKNHB): Ditto; (TARGET_ZVKSED): Ditto; (TARGET_ZVKSH):Ditto; (TARGET_ZVKN): Ditto; (TARGET_ZVKNC):Ditto; (TARGET_ZVKNG):Ditto; (TARGET_ZVKS): Ditto; (TARGET_ZVKSC):Ditto; (TARGET_ZVKSG):Ditto; (TARGET_ZVKT): Ditto; (MASK_ZVL32B): Ditto; (MASK_ZVL64B): Ditto; (MASK_ZVL128B):Ditto; (MASK_ZVL256B):Ditto; (MASK_ZVL512B):Ditto; (MASK_ZVL1024B): Ditto; (MASK_ZVL2048B): Ditto; (MASK_ZVL4096B): Ditto; (MASK_ZVL8192B): Ditto; (MASK_ZVL16384B): Ditto; (MASK_ZVL32768B): Ditto; (MASK_ZVL65536B): Ditto; (TARGET_ZVL32B): Ditto; (TARGET_ZVL64B): Ditto; (TARGET_ZVL128B): Ditto; (TARGET_ZVL256B): Ditto; (TARGET_ZVL512B): Ditto; (TARGET_ZVL1024B): Ditto; (TARGET_ZVL2048B): Ditto; (TARGET_ZVL4096B): Ditto; (TARGET_ZVL8192B): Ditto; (TARGET_ZVL16384B):Ditto; (TARGET_ZVL32768B):Ditto; (TARGET_ZVL65536B):Ditto; (MASK_ZICBOZ): Ditto; (MASK_ZICBOM): Ditto; (MASK_ZICBOP): Ditto; (TARGET_ZICBOZ): Ditto; (TARGET_ZICBOM): Ditto; (TARGET_ZICBOP):
[PATCH v5] RISC-V:Optimize the MASK opt generation
Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)" to generate MASK and TARGET MACRO automatically. This patch improve the MACRO generation of MASK_* and TARGET_*. Due to the more and more riscv extensions are added, the default target_flag is full. Before this patch,if you want to add new MACRO,you should define the MACRO in the riscv-opts.h manually. After this patch, you just need two steps: 1.Define the new TargetVariable. 2.Define "MASK(name) Var(new_target_flag). gcc/ChangeLog: * config/riscv/riscv-opts.h (MASK_ZICSR): (MASK_ZIFENCEI): Delete; (MASK_ZIHINTNTL):Ditto; (MASK_ZIHINTPAUSE): Ditto; (TARGET_ZICSR): Ditto; (TARGET_ZIFENCEI): Ditto; (TARGET_ZIHINTNTL): Ditto; (TARGET_ZIHINTPAUSE):Ditto; (MASK_ZAWRS):Ditto; (TARGET_ZAWRS): Ditto; (MASK_ZBA): Ditto; (MASK_ZBB): Ditto; (MASK_ZBC): Ditto; (MASK_ZBS): Ditto; (TARGET_ZBA):Ditto; (TARGET_ZBB):Ditto; (TARGET_ZBC):Ditto; (TARGET_ZBS):Ditto; (MASK_ZFINX):Ditto; (MASK_ZDINX):Ditto; (MASK_ZHINX):Ditto; (MASK_ZHINXMIN): Ditto; (TARGET_ZFINX): Ditto; (TARGET_ZDINX): Ditto; (TARGET_ZHINX): Ditto; (TARGET_ZHINXMIN): Ditto; (MASK_ZBKB): Ditto; (MASK_ZBKC): Ditto; (MASK_ZBKX): Ditto; (MASK_ZKNE): Ditto; (MASK_ZKND): Ditto; (MASK_ZKNH): Ditto; (MASK_ZKR): Ditto; (MASK_ZKSED):Ditto; (MASK_ZKSH): Ditto; (MASK_ZKT): Ditto; (TARGET_ZBKB): Ditto; (TARGET_ZBKC): Ditto; (TARGET_ZBKX): Ditto; (TARGET_ZKNE): Ditto; (TARGET_ZKND): Ditto; (TARGET_ZKNH): Ditto; (TARGET_ZKR):Ditto; (TARGET_ZKSED): Ditto; (TARGET_ZKSH): Ditto; (TARGET_ZKT):Ditto; (MASK_ZTSO): Ditto; (TARGET_ZTSO): Ditto; (MASK_VECTOR_ELEN_32): Ditto; (MASK_VECTOR_ELEN_64): Ditto; (MASK_VECTOR_ELEN_FP_32):Ditto; (MASK_VECTOR_ELEN_FP_64):Ditto; (MASK_VECTOR_ELEN_FP_16):Ditto; (TARGET_VECTOR_ELEN_32): Ditto; (TARGET_VECTOR_ELEN_64): Ditto; (TARGET_VECTOR_ELEN_FP_32):Ditto; (TARGET_VECTOR_ELEN_FP_64):Ditto; (TARGET_VECTOR_ELEN_FP_16):Ditto; (MASK_ZVBB): Ditto; (MASK_ZVBC): Ditto; (TARGET_ZVBB): Ditto; (TARGET_ZVBC): Ditto; (MASK_ZVKG): Ditto; (MASK_ZVKNED): Ditto; (MASK_ZVKNHA): Ditto; (MASK_ZVKNHB): Ditto; (MASK_ZVKSED): Ditto; (MASK_ZVKSH): Ditto; (MASK_ZVKN): Ditto; (MASK_ZVKNC): Ditto; (MASK_ZVKNG): Ditto; (MASK_ZVKS): Ditto; (MASK_ZVKSC): Ditto; (MASK_ZVKSG): Ditto; (MASK_ZVKT): Ditto; (TARGET_ZVKG): Ditto; (TARGET_ZVKNED): Ditto; (TARGET_ZVKNHA): Ditto; (TARGET_ZVKNHB): Ditto; (TARGET_ZVKSED): Ditto; (TARGET_ZVKSH):Ditto; (TARGET_ZVKN): Ditto; (TARGET_ZVKNC):Ditto; (TARGET_ZVKNG):Ditto; (TARGET_ZVKS): Ditto; (TARGET_ZVKSC):Ditto; (TARGET_ZVKSG):Ditto; (TARGET_ZVKT): Ditto; (MASK_ZVL32B): Ditto; (MASK_ZVL64B): Ditto; (MASK_ZVL128B):Ditto; (MASK_ZVL256B):Ditto; (MASK_ZVL512B):Ditto; (MASK_ZVL1024B): Ditto; (MASK_ZVL2048B): Ditto; (MASK_ZVL4096B): Ditto; (MASK_ZVL8192B): Ditto; (MASK_ZVL16384B): Ditto; (MASK_ZVL32768B): Ditto; (MASK_ZVL65536B): Ditto; (TARGET_ZVL32B): Ditto; (TARGET_ZVL64B): Ditto; (TARGET_ZVL128B): Ditto; (TARGET_ZVL256B): Ditto; (TARGET_ZVL512B): Ditto; (TARGET_ZVL1024B): Ditto; (TARGET_ZVL2048B): Ditto; (TARGET_ZVL4096B): Ditto; (TARGET_ZVL8192B): Ditto; (TARGET_ZVL16384B):Ditto; (TARGET_ZVL32768B):Ditto; (TARGET_ZVL65536B):Ditto; (MASK_ZICBOZ): Ditto; (MASK_ZICBOM): Ditto; (MASK_ZICBOP): Ditto; (TARGET_ZICBOZ): Ditto; (TARGET_ZICBOM): Ditto; (TARGET_ZICBOP): Ditto; (MASK_ZICOND): Ditto;
[PATCH v4] RISC-V:Optimize the MASK opt generation
This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt generation" and add the new explanation in the options.texi. gcc/ChangeLog: * config/riscv/riscv-opts.h (MASK_ZICSR): (MASK_ZIFENCEI): Delete; (MASK_ZIHINTNTL):Ditto; (MASK_ZIHINTPAUSE): Ditto; (TARGET_ZICSR): Ditto; (TARGET_ZIFENCEI): Ditto; (TARGET_ZIHINTNTL): Ditto; (TARGET_ZIHINTPAUSE):Ditto; (MASK_ZAWRS):Ditto; (TARGET_ZAWRS): Ditto; (MASK_ZBA): Ditto; (MASK_ZBB): Ditto; (MASK_ZBC): Ditto; (MASK_ZBS): Ditto; (TARGET_ZBA):Ditto; (TARGET_ZBB):Ditto; (TARGET_ZBC):Ditto; (TARGET_ZBS):Ditto; (MASK_ZFINX):Ditto; (MASK_ZDINX):Ditto; (MASK_ZHINX):Ditto; (MASK_ZHINXMIN): Ditto; (TARGET_ZFINX): Ditto; (TARGET_ZDINX): Ditto; (TARGET_ZHINX): Ditto; (TARGET_ZHINXMIN): Ditto; (MASK_ZBKB): Ditto; (MASK_ZBKC): Ditto; (MASK_ZBKX): Ditto; (MASK_ZKNE): Ditto; (MASK_ZKND): Ditto; (MASK_ZKNH): Ditto; (MASK_ZKR): Ditto; (MASK_ZKSED):Ditto; (MASK_ZKSH): Ditto; (MASK_ZKT): Ditto; (TARGET_ZBKB): Ditto; (TARGET_ZBKC): Ditto; (TARGET_ZBKX): Ditto; (TARGET_ZKNE): Ditto; (TARGET_ZKND): Ditto; (TARGET_ZKNH): Ditto; (TARGET_ZKR):Ditto; (TARGET_ZKSED): Ditto; (TARGET_ZKSH): Ditto; (TARGET_ZKT):Ditto; (MASK_ZTSO): Ditto; (TARGET_ZTSO): Ditto; (MASK_VECTOR_ELEN_32): Ditto; (MASK_VECTOR_ELEN_64): Ditto; (MASK_VECTOR_ELEN_FP_32):Ditto; (MASK_VECTOR_ELEN_FP_64):Ditto; (MASK_VECTOR_ELEN_FP_16):Ditto; (TARGET_VECTOR_ELEN_32): Ditto; (TARGET_VECTOR_ELEN_64): Ditto; (TARGET_VECTOR_ELEN_FP_32):Ditto; (TARGET_VECTOR_ELEN_FP_64):Ditto; (TARGET_VECTOR_ELEN_FP_16):Ditto; (MASK_ZVBB): Ditto; (MASK_ZVBC): Ditto; (TARGET_ZVBB): Ditto; (TARGET_ZVBC): Ditto; (MASK_ZVKG): Ditto; (MASK_ZVKNED): Ditto; (MASK_ZVKNHA): Ditto; (MASK_ZVKNHB): Ditto; (MASK_ZVKSED): Ditto; (MASK_ZVKSH): Ditto; (MASK_ZVKN): Ditto; (MASK_ZVKNC): Ditto; (MASK_ZVKNG): Ditto; (MASK_ZVKS): Ditto; (MASK_ZVKSC): Ditto; (MASK_ZVKSG): Ditto; (MASK_ZVKT): Ditto; (TARGET_ZVKG): Ditto; (TARGET_ZVKNED): Ditto; (TARGET_ZVKNHA): Ditto; (TARGET_ZVKNHB): Ditto; (TARGET_ZVKSED): Ditto; (TARGET_ZVKSH):Ditto; (TARGET_ZVKN): Ditto; (TARGET_ZVKNC):Ditto; (TARGET_ZVKNG):Ditto; (TARGET_ZVKS): Ditto; (TARGET_ZVKSC):Ditto; (TARGET_ZVKSG):Ditto; (TARGET_ZVKT): Ditto; (MASK_ZVL32B): Ditto; (MASK_ZVL64B): Ditto; (MASK_ZVL128B):Ditto; (MASK_ZVL256B):Ditto; (MASK_ZVL512B):Ditto; (MASK_ZVL1024B): Ditto; (MASK_ZVL2048B): Ditto; (MASK_ZVL4096B): Ditto; (MASK_ZVL8192B): Ditto; (MASK_ZVL16384B): Ditto; (MASK_ZVL32768B): Ditto; (MASK_ZVL65536B): Ditto; (TARGET_ZVL32B): Ditto; (TARGET_ZVL64B): Ditto; (TARGET_ZVL128B): Ditto; (TARGET_ZVL256B): Ditto; (TARGET_ZVL512B): Ditto; (TARGET_ZVL1024B): Ditto; (TARGET_ZVL2048B): Ditto; (TARGET_ZVL4096B): Ditto; (TARGET_ZVL8192B): Ditto; (TARGET_ZVL16384B):Ditto; (TARGET_ZVL32768B):Ditto; (TARGET_ZVL65536B):Ditto; (MASK_ZICBOZ): Ditto; (MASK_ZICBOM): Ditto; (MASK_ZICBOP): Ditto; (TARGET_ZICBOZ): Ditto; (TARGET_ZICBOM): Ditto; (TARGET_ZICBOP): Ditto; (MASK_ZICOND): Ditto; (TARGET_ZICOND): Ditto; (MASK_ZFA):Ditto; (TARGET_ZFA): Ditto; (MASK_ZFHMIN): Ditto; (MASK_ZFH):Ditto; (MASK_ZVFHMIN):Ditto; (MASK_ZVFH): Ditto; (TARGET_ZFHMIN): Ditto; (TARGET_ZFH): Ditto; (TARGET_ZVFHMIN): Ditto;
Re: Re: [PATCH v3] RISC-V:Optimize the MASK opt generation
Thanks reminder, I should rebase again. -- Feng Wang >Hi, > >I will need to notify you that x_riscv_xventana_subext, >MASK_XVENTANACONDOPS and TARGET_XVENTANACONDOPS are added (I think you >want to rewrite those definitions like the rest). Also, be careful not >to remove TARGET_ZICOND_LIKE. > >Thanks, >Tsukasa > >On 2023/09/06 11:02, Feng Wang wrote: >> This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt >> generation" and add the new explanation in the options.texi. >> Please check the detail info on the >> "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html; >> gcc/ChangeLog: >> >> * config/riscv/riscv-opts.h (MASK_ZICSR): >> (MASK_ZIFENCEI): Delete; >> (MASK_ZIHINTNTL): Ditto; >> (MASK_ZIHINTPAUSE): Ditto; >> (TARGET_ZICSR): Ditto; >> (TARGET_ZIFENCEI): Ditto; >> (TARGET_ZIHINTNTL): Ditto; >> (TARGET_ZIHINTPAUSE):Ditto; >> (MASK_ZAWRS): Ditto; >> (TARGET_ZAWRS): Ditto; >> (MASK_ZBA): Ditto; >> (MASK_ZBB): Ditto; >> (MASK_ZBC): Ditto; >> (MASK_ZBS): Ditto; >> (TARGET_ZBA): Ditto; >> (TARGET_ZBB): Ditto; >> (TARGET_ZBC): Ditto; >> (TARGET_ZBS): Ditto; >> (MASK_ZFINX): Ditto; >> (MASK_ZDINX): Ditto; >> (MASK_ZHINX): Ditto; >> (MASK_ZHINXMIN): Ditto; >> (TARGET_ZFINX): Ditto; >> (TARGET_ZDINX): Ditto; >> (TARGET_ZHINX): Ditto; >> (TARGET_ZHINXMIN): Ditto; >> (MASK_ZBKB): Ditto; >> (MASK_ZBKC): Ditto; >> (MASK_ZBKX): Ditto; >> (MASK_ZKNE): Ditto; >> (MASK_ZKND): Ditto; >> (MASK_ZKNH): Ditto; >> (MASK_ZKR): Ditto; >> (MASK_ZKSED): Ditto; >> (MASK_ZKSH): Ditto; >> (MASK_ZKT): Ditto; >> (TARGET_ZBKB): Ditto; >> (TARGET_ZBKC): Ditto; >> (TARGET_ZBKX): Ditto; >> (TARGET_ZKNE): Ditto; >> (TARGET_ZKND): Ditto; >> (TARGET_ZKNH): Ditto; >> (TARGET_ZKR): Ditto; >> (TARGET_ZKSED): Ditto; >> (TARGET_ZKSH): Ditto; >> (TARGET_ZKT): Ditto; >> (MASK_ZTSO): Ditto; >> (TARGET_ZTSO): Ditto; >> (MASK_VECTOR_ELEN_32): Ditto; >> (MASK_VECTOR_ELEN_64): Ditto; >> (MASK_VECTOR_ELEN_FP_32):Ditto; >> (MASK_VECTOR_ELEN_FP_64):Ditto; >> (MASK_VECTOR_ELEN_FP_16):Ditto; >> (TARGET_VECTOR_ELEN_32): Ditto; >> (TARGET_VECTOR_ELEN_64): Ditto; >> (TARGET_VECTOR_ELEN_FP_32):Ditto; >> (TARGET_VECTOR_ELEN_FP_64):Ditto; >> (TARGET_VECTOR_ELEN_FP_16):Ditto; >> (MASK_ZVBB): Ditto; >> (MASK_ZVBC): Ditto; >> (TARGET_ZVBB): Ditto; >> (TARGET_ZVBC): Ditto; >> (MASK_ZVKG): Ditto; >> (MASK_ZVKNED): Ditto; >> (MASK_ZVKNHA): Ditto; >> (MASK_ZVKNHB): Ditto; >> (MASK_ZVKSED): Ditto; >> (MASK_ZVKSH): Ditto; >> (MASK_ZVKN): Ditto; >> (MASK_ZVKNC): Ditto; >> (MASK_ZVKNG): Ditto; >> (MASK_ZVKS): Ditto; >> (MASK_ZVKSC): Ditto; >> (MASK_ZVKSG): Ditto; >> (MASK_ZVKT): Ditto; >> (TARGET_ZVKG): Ditto; >> (TARGET_ZVKNED): Ditto; >> (TARGET_ZVKNHA): Ditto; >> (TARGET_ZVKNHB): Ditto; >> (TARGET_ZVKSED): Ditto; >> (TARGET_ZVKSH): Ditto; >> (TARGET_ZVKN): Ditto; >> (TARGET_ZVKNC): Ditto; >> (TARGET_ZVKNG): Ditto; >> (TARGET_ZVKS): Ditto; >> (TARGET_ZVKSC): Ditto; >> (TARGET_ZVKSG): Ditto; >> (TARGET_ZVKT): Ditto; >> (MASK_ZVL32B): Ditto; >> (MASK_ZVL64B): Ditto; >> (MASK_ZVL128B): Ditto; >> (MASK_ZVL256B): Ditto; >&g
Re: Re: [PATCH v3] RISC-V:Optimize the MASK opt generation
According to the doc, take“Mask(VECTOR_ELEN_32) Var(riscv_vector_elen_flags)”as example, it just generates the OPTION_MASK_VECTOR_ELEN_32, will not generate MASK_VECTOR_ELEN_32 and TARGET_VECTOR_ELEN_32. Do you want to use "MASK(name) Var(other_flags)" to generate the MASK and TARGET Macro? I think it will change a lot of code and the original meaning is changed. -- Feng Wang >Reading the manual again, it seems I missed something in the manual >before, the MASK syntax already says we can specify Var to select the >variable other than target_flags, but I tried that not work when we >only declare Mask with Var (e.g. "Mask(VECTOR_ELEN_32) >Var(riscv_vector_elen_flags)" still using target_flags) > >So maybe we should just fix that instead of extending the syntax? >e.g. >Mask(VECTOR_ELEN_32) Var(riscv_vector_elen_flags) >rather than >Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags) > > >On Wed, Sep 6, 2023 at 10:03 AM Feng Wang wrote: >> >> This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt >> generation" and add the new explanation in the options.texi. >> Please check the detail info on the >> "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html; >> gcc/ChangeLog: >> >> * config/riscv/riscv-opts.h (MASK_ZICSR): >> (MASK_ZIFENCEI): Delete; >> (MASK_ZIHINTNTL): Ditto; >> (MASK_ZIHINTPAUSE): Ditto; >> (TARGET_ZICSR): Ditto; >> (TARGET_ZIFENCEI): Ditto; >> (TARGET_ZIHINTNTL): Ditto; >> (TARGET_ZIHINTPAUSE):Ditto; >> (MASK_ZAWRS): Ditto; >> (TARGET_ZAWRS): Ditto; >> (MASK_ZBA): Ditto; >> (MASK_ZBB): Ditto; >> (MASK_ZBC): Ditto; >> (MASK_ZBS): Ditto; >> (TARGET_ZBA): Ditto; >> (TARGET_ZBB): Ditto; >> (TARGET_ZBC): Ditto; >> (TARGET_ZBS): Ditto; >> (MASK_ZFINX): Ditto; >> (MASK_ZDINX): Ditto; >> (MASK_ZHINX): Ditto; >> (MASK_ZHINXMIN): Ditto; >> (TARGET_ZFINX): Ditto; >> (TARGET_ZDINX): Ditto; >> (TARGET_ZHINX): Ditto; >> (TARGET_ZHINXMIN): Ditto; >> (MASK_ZBKB): Ditto; >> (MASK_ZBKC): Ditto; >> (MASK_ZBKX): Ditto; >> (MASK_ZKNE): Ditto; >> (MASK_ZKND): Ditto; >> (MASK_ZKNH): Ditto; >> (MASK_ZKR): Ditto; >> (MASK_ZKSED): Ditto; >> (MASK_ZKSH): Ditto; >> (MASK_ZKT): Ditto; >> (TARGET_ZBKB): Ditto; >> (TARGET_ZBKC): Ditto; >> (TARGET_ZBKX): Ditto; >> (TARGET_ZKNE): Ditto; >> (TARGET_ZKND): Ditto; >> (TARGET_ZKNH): Ditto; >> (TARGET_ZKR): Ditto; >> (TARGET_ZKSED): Ditto; >> (TARGET_ZKSH): Ditto; >> (TARGET_ZKT): Ditto; >> (MASK_ZTSO): Ditto; >> (TARGET_ZTSO): Ditto; >> (MASK_VECTOR_ELEN_32): Ditto; >> (MASK_VECTOR_ELEN_64): Ditto; >> (MASK_VECTOR_ELEN_FP_32):Ditto; >> (MASK_VECTOR_ELEN_FP_64):Ditto; >> (MASK_VECTOR_ELEN_FP_16):Ditto; >> (TARGET_VECTOR_ELEN_32): Ditto; >> (TARGET_VECTOR_ELEN_64): Ditto; >> (TARGET_VECTOR_ELEN_FP_32):Ditto; >> (TARGET_VECTOR_ELEN_FP_64):Ditto; >> (TARGET_VECTOR_ELEN_FP_16):Ditto; >> (MASK_ZVBB): Ditto; >> (MASK_ZVBC): Ditto; >> (TARGET_ZVBB): Ditto; >> (TARGET_ZVBC): Ditto; >> (MASK_ZVKG): Ditto; >> (MASK_ZVKNED): Ditto; >> (MASK_ZVKNHA): Ditto; >> (MASK_ZVKNHB): Ditto; >> (MASK_ZVKSED): Ditto; >> (MASK_ZVKSH): Ditto; >> (MASK_ZVKN): Ditto; >> (MASK_ZVKNC): Ditto; >> (MASK_ZVKNG): Ditto; >> (MASK_ZVKS): Ditto; >> (MASK_ZVKSC): Ditto; >> (MASK_ZVKSG): Ditto; >> (MASK_ZVKT): Ditto; >> (TARGET_ZVKG): Ditto; >> (TARGET_ZVKNED): Ditto; >> (TARGET_ZVKNHA)
[PATCH v3] RISC-V:Optimize the MASK opt generation
This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt generation" and add the new explanation in the options.texi. Please check the detail info on the "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html; gcc/ChangeLog: * config/riscv/riscv-opts.h (MASK_ZICSR): (MASK_ZIFENCEI): Delete; (MASK_ZIHINTNTL):Ditto; (MASK_ZIHINTPAUSE): Ditto; (TARGET_ZICSR): Ditto; (TARGET_ZIFENCEI): Ditto; (TARGET_ZIHINTNTL): Ditto; (TARGET_ZIHINTPAUSE):Ditto; (MASK_ZAWRS):Ditto; (TARGET_ZAWRS): Ditto; (MASK_ZBA): Ditto; (MASK_ZBB): Ditto; (MASK_ZBC): Ditto; (MASK_ZBS): Ditto; (TARGET_ZBA):Ditto; (TARGET_ZBB):Ditto; (TARGET_ZBC):Ditto; (TARGET_ZBS):Ditto; (MASK_ZFINX):Ditto; (MASK_ZDINX):Ditto; (MASK_ZHINX):Ditto; (MASK_ZHINXMIN): Ditto; (TARGET_ZFINX): Ditto; (TARGET_ZDINX): Ditto; (TARGET_ZHINX): Ditto; (TARGET_ZHINXMIN): Ditto; (MASK_ZBKB): Ditto; (MASK_ZBKC): Ditto; (MASK_ZBKX): Ditto; (MASK_ZKNE): Ditto; (MASK_ZKND): Ditto; (MASK_ZKNH): Ditto; (MASK_ZKR): Ditto; (MASK_ZKSED):Ditto; (MASK_ZKSH): Ditto; (MASK_ZKT): Ditto; (TARGET_ZBKB): Ditto; (TARGET_ZBKC): Ditto; (TARGET_ZBKX): Ditto; (TARGET_ZKNE): Ditto; (TARGET_ZKND): Ditto; (TARGET_ZKNH): Ditto; (TARGET_ZKR):Ditto; (TARGET_ZKSED): Ditto; (TARGET_ZKSH): Ditto; (TARGET_ZKT):Ditto; (MASK_ZTSO): Ditto; (TARGET_ZTSO): Ditto; (MASK_VECTOR_ELEN_32): Ditto; (MASK_VECTOR_ELEN_64): Ditto; (MASK_VECTOR_ELEN_FP_32):Ditto; (MASK_VECTOR_ELEN_FP_64):Ditto; (MASK_VECTOR_ELEN_FP_16):Ditto; (TARGET_VECTOR_ELEN_32): Ditto; (TARGET_VECTOR_ELEN_64): Ditto; (TARGET_VECTOR_ELEN_FP_32):Ditto; (TARGET_VECTOR_ELEN_FP_64):Ditto; (TARGET_VECTOR_ELEN_FP_16):Ditto; (MASK_ZVBB): Ditto; (MASK_ZVBC): Ditto; (TARGET_ZVBB): Ditto; (TARGET_ZVBC): Ditto; (MASK_ZVKG): Ditto; (MASK_ZVKNED): Ditto; (MASK_ZVKNHA): Ditto; (MASK_ZVKNHB): Ditto; (MASK_ZVKSED): Ditto; (MASK_ZVKSH): Ditto; (MASK_ZVKN): Ditto; (MASK_ZVKNC): Ditto; (MASK_ZVKNG): Ditto; (MASK_ZVKS): Ditto; (MASK_ZVKSC): Ditto; (MASK_ZVKSG): Ditto; (MASK_ZVKT): Ditto; (TARGET_ZVKG): Ditto; (TARGET_ZVKNED): Ditto; (TARGET_ZVKNHA): Ditto; (TARGET_ZVKNHB): Ditto; (TARGET_ZVKSED): Ditto; (TARGET_ZVKSH):Ditto; (TARGET_ZVKN): Ditto; (TARGET_ZVKNC):Ditto; (TARGET_ZVKNG):Ditto; (TARGET_ZVKS): Ditto; (TARGET_ZVKSC):Ditto; (TARGET_ZVKSG):Ditto; (TARGET_ZVKT): Ditto; (MASK_ZVL32B): Ditto; (MASK_ZVL64B): Ditto; (MASK_ZVL128B):Ditto; (MASK_ZVL256B):Ditto; (MASK_ZVL512B):Ditto; (MASK_ZVL1024B): Ditto; (MASK_ZVL2048B): Ditto; (MASK_ZVL4096B): Ditto; (MASK_ZVL8192B): Ditto; (MASK_ZVL16384B): Ditto; (MASK_ZVL32768B): Ditto; (MASK_ZVL65536B): Ditto; (TARGET_ZVL32B): Ditto; (TARGET_ZVL64B): Ditto; (TARGET_ZVL128B): Ditto; (TARGET_ZVL256B): Ditto; (TARGET_ZVL512B): Ditto; (TARGET_ZVL1024B): Ditto; (TARGET_ZVL2048B): Ditto; (TARGET_ZVL4096B): Ditto; (TARGET_ZVL8192B): Ditto; (TARGET_ZVL16384B):Ditto; (TARGET_ZVL32768B):Ditto; (TARGET_ZVL65536B):Ditto; (MASK_ZICBOZ): Ditto; (MASK_ZICBOM): Ditto; (MASK_ZICBOP): Ditto; (TARGET_ZICBOZ): Ditto; (TARGET_ZICBOM): Ditto; (TARGET_ZICBOP): Ditto; (MASK_ZICOND): Ditto; (TARGET_ZICOND): Ditto; (MASK_ZFA):Ditto; (TARGET_ZFA): Ditto; (MASK_ZFHMIN): Ditto; (MASK_ZFH):Ditto; (MASK_ZVFHMIN):Ditto; (MASK_ZVFH): Ditto;
[PATCH v2] RISC-V: Optimize the MASK opt generation
This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt generation". Please check the detail info on the "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html; gcc/ChangeLog: * config/riscv/riscv-opts.h (MASK_ZICSR): (MASK_ZIFENCEI): Delete; (MASK_ZIHINTNTL):Ditto; (MASK_ZIHINTPAUSE): Ditto; (TARGET_ZICSR): Ditto; (TARGET_ZIFENCEI): Ditto; (TARGET_ZIHINTNTL): Ditto; (TARGET_ZIHINTPAUSE):Ditto; (MASK_ZAWRS):Ditto; (TARGET_ZAWRS): Ditto; (MASK_ZBA): Ditto; (MASK_ZBB): Ditto; (MASK_ZBC): Ditto; (MASK_ZBS): Ditto; (TARGET_ZBA):Ditto; (TARGET_ZBB):Ditto; (TARGET_ZBC):Ditto; (TARGET_ZBS):Ditto; (MASK_ZFINX):Ditto; (MASK_ZDINX):Ditto; (MASK_ZHINX):Ditto; (MASK_ZHINXMIN): Ditto; (TARGET_ZFINX): Ditto; (TARGET_ZDINX): Ditto; (TARGET_ZHINX): Ditto; (TARGET_ZHINXMIN): Ditto; (MASK_ZBKB): Ditto; (MASK_ZBKC): Ditto; (MASK_ZBKX): Ditto; (MASK_ZKNE): Ditto; (MASK_ZKND): Ditto; (MASK_ZKNH): Ditto; (MASK_ZKR): Ditto; (MASK_ZKSED):Ditto; (MASK_ZKSH): Ditto; (MASK_ZKT): Ditto; (TARGET_ZBKB): Ditto; (TARGET_ZBKC): Ditto; (TARGET_ZBKX): Ditto; (TARGET_ZKNE): Ditto; (TARGET_ZKND): Ditto; (TARGET_ZKNH): Ditto; (TARGET_ZKR):Ditto; (TARGET_ZKSED): Ditto; (TARGET_ZKSH): Ditto; (TARGET_ZKT):Ditto; (MASK_ZTSO): Ditto; (TARGET_ZTSO): Ditto; (MASK_VECTOR_ELEN_32): Ditto; (MASK_VECTOR_ELEN_64): Ditto; (MASK_VECTOR_ELEN_FP_32):Ditto; (MASK_VECTOR_ELEN_FP_64):Ditto; (MASK_VECTOR_ELEN_FP_16):Ditto; (TARGET_VECTOR_ELEN_32): Ditto; (TARGET_VECTOR_ELEN_64): Ditto; (TARGET_VECTOR_ELEN_FP_32):Ditto; (TARGET_VECTOR_ELEN_FP_64):Ditto; (TARGET_VECTOR_ELEN_FP_16):Ditto; (MASK_ZVBB): Ditto; (MASK_ZVBC): Ditto; (TARGET_ZVBB): Ditto; (TARGET_ZVBC): Ditto; (MASK_ZVKG): Ditto; (MASK_ZVKNED): Ditto; (MASK_ZVKNHA): Ditto; (MASK_ZVKNHB): Ditto; (MASK_ZVKSED): Ditto; (MASK_ZVKSH): Ditto; (MASK_ZVKN): Ditto; (MASK_ZVKNC): Ditto; (MASK_ZVKNG): Ditto; (MASK_ZVKS): Ditto; (MASK_ZVKSC): Ditto; (MASK_ZVKSG): Ditto; (MASK_ZVKT): Ditto; (TARGET_ZVKG): Ditto; (TARGET_ZVKNED): Ditto; (TARGET_ZVKNHA): Ditto; (TARGET_ZVKNHB): Ditto; (TARGET_ZVKSED): Ditto; (TARGET_ZVKSH):Ditto; (TARGET_ZVKN): Ditto; (TARGET_ZVKNC):Ditto; (TARGET_ZVKNG):Ditto; (TARGET_ZVKS): Ditto; (TARGET_ZVKSC):Ditto; (TARGET_ZVKSG):Ditto; (TARGET_ZVKT): Ditto; (MASK_ZVL32B): Ditto; (MASK_ZVL64B): Ditto; (MASK_ZVL128B):Ditto; (MASK_ZVL256B):Ditto; (MASK_ZVL512B):Ditto; (MASK_ZVL1024B): Ditto; (MASK_ZVL2048B): Ditto; (MASK_ZVL4096B): Ditto; (MASK_ZVL8192B): Ditto; (MASK_ZVL16384B): Ditto; (MASK_ZVL32768B): Ditto; (MASK_ZVL65536B): Ditto; (TARGET_ZVL32B): Ditto; (TARGET_ZVL64B): Ditto; (TARGET_ZVL128B): Ditto; (TARGET_ZVL256B): Ditto; (TARGET_ZVL512B): Ditto; (TARGET_ZVL1024B): Ditto; (TARGET_ZVL2048B): Ditto; (TARGET_ZVL4096B): Ditto; (TARGET_ZVL8192B): Ditto; (TARGET_ZVL16384B):Ditto; (TARGET_ZVL32768B):Ditto; (TARGET_ZVL65536B):Ditto; (MASK_ZICBOZ): Ditto; (MASK_ZICBOM): Ditto; (MASK_ZICBOP): Ditto; (TARGET_ZICBOZ): Ditto; (TARGET_ZICBOM): Ditto; (TARGET_ZICBOP): Ditto; (MASK_ZICOND): Ditto; (TARGET_ZICOND): Ditto; (MASK_ZFA):Ditto; (TARGET_ZFA): Ditto; (MASK_ZFHMIN): Ditto; (MASK_ZFH):Ditto; (MASK_ZVFHMIN):Ditto; (MASK_ZVFH): Ditto; (TARGET_ZFHMIN): Ditto;
[Ping][PATCH] RISC-V: Optimize the MASK opt generation
Ping, I will rebase if the change is fine to you, thanks! On 2023-03-01 09:46 Feng Wang wrote: > >The Mask flag in the single TargetVariable is not enough due to more >and more extensions were added.So I optimize the defination of Mask >flag, please refer to the below case: >There are some new MASK flags for 'v' extension(ZVL32B,ZVL64B,...,ZVL65536B), >but these MASK flags can't store into x_target_flags,because the total number >of MASK flags exceed 32. In this patch we can write it like this in this >scence. > >TargetVariable >int riscv_zvl_flags > >Mask(ZVL32B) in TargetVariable(riscv_zvl_flags) > >The corresponding MASK and TARGET will be automatically generated. > >gcc/ChangeLog: > > * config/riscv/riscv-opts.h Delete below definations > (MASK_ZICSR): Delete; > (MASK_ZIFENCEI): Delete; > (TARGET_ZICSR): Delete; > (TARGET_ZIFENCEI): Delete; > (MASK_ZAWRS): Delete; > (TARGET_ZAWRS): Delete; > (MASK_ZBA): Delete; > (MASK_ZBB): Delete; > (MASK_ZBC): Delete; > (MASK_ZBS): Delete; > (TARGET_ZBA): Delete; > (TARGET_ZBB): Delete; > (TARGET_ZBC): Delete; > (TARGET_ZBS): Delete; > (MASK_ZFINX): Delete; > (MASK_ZDINX): Delete; > (MASK_ZHINX): Delete; > (MASK_ZHINXMIN): Delete; > (TARGET_ZFINX): Delete; > (TARGET_ZDINX): Delete; > (TARGET_ZHINX): Delete; > (TARGET_ZHINXMIN): Delete; > (MASK_ZBKB): Delete; > (MASK_ZBKC): Delete; > (MASK_ZBKX): Delete; > (MASK_ZKNE): Delete; > (MASK_ZKND): Delete; > (MASK_ZKNH): Delete; > (MASK_ZKR): Delete; > (MASK_ZKSED): Delete; > (MASK_ZKSH): Delete; > (MASK_ZKT): Delete; > (TARGET_ZBKB): Delete; > (TARGET_ZBKC): Delete; > (TARGET_ZBKX): Delete; > (TARGET_ZKNE): Delete; > (TARGET_ZKND): Delete; > (TARGET_ZKNH): Delete; > (TARGET_ZKR): Delete; > (TARGET_ZKSED): Delete; > (TARGET_ZKSH): Delete; > (TARGET_ZKT): Delete; > (MASK_VECTOR_ELEN_32): Delete; > (MASK_VECTOR_ELEN_64): Delete; > (MASK_VECTOR_ELEN_FP_32): Delete; > (MASK_VECTOR_ELEN_FP_64): Delete; > (TARGET_VECTOR_ELEN_32): Delete; > (TARGET_VECTOR_ELEN_64): Delete; > (TARGET_VECTOR_ELEN_FP_32): Delete; > (TARGET_VECTOR_ELEN_FP_64): Delete; > (MASK_ZVL32B): Delete; > (MASK_ZVL64B): Delete; > (MASK_ZVL128B): Delete; > (MASK_ZVL256B): Delete; > (MASK_ZVL512B): Delete; > (MASK_ZVL1024B): Delete; > (MASK_ZVL2048B): Delete; > (MASK_ZVL4096B): Delete; > (MASK_ZVL8192B): Delete; > (MASK_ZVL16384B): Delete; > (MASK_ZVL32768B): Delete; > (MASK_ZVL65536B): Delete; > (TARGET_ZVL32B): Delete; > (TARGET_ZVL64B): Delete; > (TARGET_ZVL128B): Delete; > (TARGET_ZVL256B): Delete; > (TARGET_ZVL512B): Delete; > (TARGET_ZVL1024B): Delete; > (TARGET_ZVL2048B): Delete; > (TARGET_ZVL4096B): Delete; > (TARGET_ZVL8192B): Delete; > (TARGET_ZVL16384B): Delete; > (TARGET_ZVL32768B): Delete; > (TARGET_ZVL65536B): Delete; > (MASK_ZICBOZ): Delete; > (MASK_ZICBOM): Delete; > (MASK_ZICBOP): Delete; > (TARGET_ZICBOZ): Delete; > (TARGET_ZICBOM): Delete; > (TARGET_ZICBOP): Delete; > (MASK_ZFHMIN): Delete; > (MASK_ZFH): Delete; > (TARGET_ZFHMIN): Delete; > (TARGET_ZFH): Delete; > (MASK_ZMMUL): Delete; > (TARGET_ZMMUL): Delete; > (MASK_SVINVAL): Delete; > (MASK_SVNAPOT): Delete; > (TARGET_SVINVAL): Delete; > (TARGET_SVNAPOT): Delete; > * config/riscv/riscv.opt: Add new Mask defination. > * opt-functions.awk: Add new function to find the index > of target variable from extra_target_vars. > * opt-read.awk: Add new function to store the Mask flags. > * opth-gen.awk: Add new function to output the defination of > Mask Macro and Target Macro. >--- > gcc/config/riscv/riscv-opts.h | 115 -- > gcc/config/riscv/riscv.opt | 90 ++ > gcc/opt-functions.awk | 11 > gcc/opt-read.awk | 16 - > gcc/opth-gen.awk | 22 +++ > 5 files changed, 138 insertions(+), 116 deletions(-) > >diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
Re: [PATCH] RISC-V: Optimize the MASK opt generation
On 2023-03-01 09:46 Feng Wang wrote: > >The Mask flag in the single TargetVariable is not enough due to more >and more extensions were added.So I optimize the defination of Mask >flag, please refer to the below case: >There are some new MASK flags for 'v' extension(ZVL32B,ZVL64B,...,ZVL65536B), >but these MASK flags can't store into x_target_flags,because the total number >of MASK flags exceed 32. In this patch we can write it like this in this >scence. > >TargetVariable >int riscv_zvl_flags > >Mask(ZVL32B) in TargetVariable(riscv_zvl_flags) > >The corresponding MASK and TARGET will be automatically generated. > >gcc/ChangeLog: > > * config/riscv/riscv-opts.h Delete below definations > (MASK_ZICSR): Delete; > (MASK_ZIFENCEI): Delete; > (TARGET_ZICSR): Delete; > (TARGET_ZIFENCEI): Delete; > (MASK_ZAWRS): Delete; > (TARGET_ZAWRS): Delete; > (MASK_ZBA): Delete; > (MASK_ZBB): Delete; > (MASK_ZBC): Delete; > (MASK_ZBS): Delete; > (TARGET_ZBA): Delete; > (TARGET_ZBB): Delete; > (TARGET_ZBC): Delete; > (TARGET_ZBS): Delete; > (MASK_ZFINX): Delete; > (MASK_ZDINX): Delete; > (MASK_ZHINX): Delete; > (MASK_ZHINXMIN): Delete; > (TARGET_ZFINX): Delete; > (TARGET_ZDINX): Delete; > (TARGET_ZHINX): Delete; > (TARGET_ZHINXMIN): Delete; > (MASK_ZBKB): Delete; > (MASK_ZBKC): Delete; > (MASK_ZBKX): Delete; > (MASK_ZKNE): Delete; > (MASK_ZKND): Delete; > (MASK_ZKNH): Delete; > (MASK_ZKR): Delete; > (MASK_ZKSED): Delete; > (MASK_ZKSH): Delete; > (MASK_ZKT): Delete; > (TARGET_ZBKB): Delete; > (TARGET_ZBKC): Delete; > (TARGET_ZBKX): Delete; > (TARGET_ZKNE): Delete; > (TARGET_ZKND): Delete; > (TARGET_ZKNH): Delete; > (TARGET_ZKR): Delete; > (TARGET_ZKSED): Delete; > (TARGET_ZKSH): Delete; > (TARGET_ZKT): Delete; > (MASK_VECTOR_ELEN_32): Delete; > (MASK_VECTOR_ELEN_64): Delete; > (MASK_VECTOR_ELEN_FP_32): Delete; > (MASK_VECTOR_ELEN_FP_64): Delete; > (TARGET_VECTOR_ELEN_32): Delete; > (TARGET_VECTOR_ELEN_64): Delete; > (TARGET_VECTOR_ELEN_FP_32): Delete; > (TARGET_VECTOR_ELEN_FP_64): Delete; > (MASK_ZVL32B): Delete; > (MASK_ZVL64B): Delete; > (MASK_ZVL128B): Delete; > (MASK_ZVL256B): Delete; > (MASK_ZVL512B): Delete; > (MASK_ZVL1024B): Delete; > (MASK_ZVL2048B): Delete; > (MASK_ZVL4096B): Delete; > (MASK_ZVL8192B): Delete; > (MASK_ZVL16384B): Delete; > (MASK_ZVL32768B): Delete; > (MASK_ZVL65536B): Delete; > (TARGET_ZVL32B): Delete; > (TARGET_ZVL64B): Delete; > (TARGET_ZVL128B): Delete; > (TARGET_ZVL256B): Delete; > (TARGET_ZVL512B): Delete; > (TARGET_ZVL1024B): Delete; > (TARGET_ZVL2048B): Delete; > (TARGET_ZVL4096B): Delete; > (TARGET_ZVL8192B): Delete; > (TARGET_ZVL16384B): Delete; > (TARGET_ZVL32768B): Delete; > (TARGET_ZVL65536B): Delete; > (MASK_ZICBOZ): Delete; > (MASK_ZICBOM): Delete; > (MASK_ZICBOP): Delete; > (TARGET_ZICBOZ): Delete; > (TARGET_ZICBOM): Delete; > (TARGET_ZICBOP): Delete; > (MASK_ZFHMIN): Delete; > (MASK_ZFH): Delete; > (TARGET_ZFHMIN): Delete; > (TARGET_ZFH): Delete; > (MASK_ZMMUL): Delete; > (TARGET_ZMMUL): Delete; > (MASK_SVINVAL): Delete; > (MASK_SVNAPOT): Delete; > (TARGET_SVINVAL): Delete; > (TARGET_SVNAPOT): Delete; > * config/riscv/riscv.opt: Add new Mask defination. > * opt-functions.awk: Add new function to find the index > of target variable from extra_target_vars. > * opt-read.awk: Add new function to store the Mask flags. > * opth-gen.awk: Add new function to output the defination of > Mask Macro and Target Macro. >--- > gcc/config/riscv/riscv-opts.h | 115 -- > gcc/config/riscv/riscv.opt | 90 ++ > gcc/opt-functions.awk | 11 > gcc/opt-read.awk | 16 - > gcc/opth-gen.awk | 22 +++ > 5 files changed, 138 insertions(+), 116 deletions(-) > >diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h >index 25fd85b09b1..7cf28838cb5 100644 >--- a/gcc/config/r
Re: Re: [PATCH] RISC-V: Optimize zbb ins sext.b and sext.h in rv64
On 2023-04-22 08:08 Jeff Law wrote:
>
>
>
>On 3/23/23 19:53, Feng Wang wrote:
>> This patch optimize the combine processing for sext.b/h in rv64.
>> Please refer to the following test case,
>> int sextb32(int x)
>> { return (x << 24) >> 24; }
>>
>> The rtl expression is as follows,
>> (insn 6 3 7 2 (set (reg:SI 138)
>> (ashift:SI (subreg/s/u:SI (reg/v:DI 136 [ xD.2271 ]) 0)
>> (const_int 24 [0x18]))) "sextb.c":2:13 195 {ashlsi3}
>> (expr_list:REG_DEAD (reg/v:DI 136 [ xD.2271 ])
>> (nil)))
>> (insn 7 6 8 2 (set (reg:SI 137)
>> (ashiftrt:SI (reg:SI 138)
>> (const_int 24 [0x18]))) "sextb.c":2:20 196 {ashrsi3}
>> (expr_list:REG_DEAD (reg:SI 138)
>> (nil)))
>>
>> During the combine phase, they will combine into
>> (set (reg:SI 137)
>> (ashiftrt:SI (subreg:SI (ashift:DI (reg:DI 140)
>> (const_int 24 [0x18])) 0)
>> (const_int 24 [0x18])))
>>
>> The optimal combine result is
>> (set (reg:SI 137)
>> (sign_extend:SI (subreg:QI (reg:DI 140) 0)))
>> This can be converted to the sext ins.
>>
>> Due to the influence of subreg,the current processing
>> can't obtain the imm of left shifts. Need to peel off
>> another layer of rtl to obtain it.
>>
>> gcc/ChangeLog:
>>
>> * combine.cc (extract_left_shift): Add SUBREG case.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/zbb-sext-rv64.c: New test.
>SUBREGs have painful semantics and we should be very careful just
>stripping them.
>
>For example, you might have a subreg that extracts the *high* part. Or
>you might have (subreg (mem)) or a paradoxical subreg, etc.
>
>At the *least* this case would need verification that you're getting the
>lowpart. However, I suspect there's other conditions that need to be
>checked to make this valid.
>
>But I would suggest we look elsewhere. It could be that combine is
>reassociating the subreg in ways that are undesirable and which
>ultimately makes our job harder. Additionally if we can fix this in a
>generic simplification/folder routine, then multiple passes can benefit.
>
>For example in simplify_context::simplify_binary_operation we get a form
>more amenable to optimization.
>
>> #0 simplify_context::simplify_binary_operation (this=0x7fffda68,
>> code=ASHIFTRT, mode=E_SImode,
>> op0=0x7fffea11eb40, op1=0x7fffea009610) at
>>/home/jlaw/riscv-persist/ventana/gcc/gcc/simplify-rtx.cc:2558
>> 2558 gcc_assert (GET_RTX_CLASS (code) != RTX_COMPARE);
>> (gdb) p code
>> $24 = ASHIFTRT
>> (gdb) p mode
>> $25 = E_SImode
>> (gdb) p debug_rtx (op0)
>> (ashift:SI (subreg/s/u:SI (reg/v:DI 74 [ x ]) 0)
>> (const_int 24 [0x18]))
>> $26 = void
>> (gdb) p debug_rtx (op1)
>> (const_int 24 [0x18])
>> $27 = void
>
>So that's (ashiftrt (ashift (object) 24) 24), ie sign extension.
>
>ie, we really don't have to think about the fact that the underlying
>object is a SUBREG because the outer operations are very clearly a sign
>extension regardless of the object they're operating on.
>
>With that in mind I would suggest you look at adding a case for detect
>zero/sign extension in simplify_context::simplify_binary_operation_1.
>
>Thanks,
>Jeff
You are right, I will modify it according to your suggestion.
Thanks.
Feng Wang
Re: Re: [PATCH] RISC-V: Optimize zbb ins sext.b and sext.h in rv64
On 2023-03-26 02:18 Jeff Law wrote: > > > >On 3/23/23 20:45, juzhe.zh...@rivai.ai wrote: >> Sounds like you are looking at redundant extension problem in RISC-V port. >> This is the issue I want to fix but I don't find the time to do that. >> My first impression is that we need to fix redundant extension in "ree" >> PASS. >> I am not sure. >It's actually quite a bit more complicated. > >Some extension elimination can and probably should be happening in >gimple. In gimple you have access to type information as well as range >information. So you have the opportunity to do things like rewrite the >IL to use different types when it's safe to do so, or to use range >information to identify when an object is already properly extended and >thus eliminate the extension before we expand gimple into RTL. > >Once in RTL, you can use forward propagation to eliminate extensions, or >at least fold them into existing operations. combine can eliminate >extensions and it has the ability to track (for example) if the upper >bits are copies of the sign bit, if they're known zero, etc. combine is >also capable of recognizing that a load implicitly extends and using >that knowledge to eliminate extensions or to discover that a pair of >shifts are just zero or sign extending a value, etc etc. combine also >interacts with simplify-rtx which is used by other passes, so there's a >chance that work in simplify-rtx can eliminate extensions not just in >combine, but in other passes as well. > >REE is a post-register allocation pass and kind of the last chance to >eliminate extensions. > >So for any given redundant extension, the way to go (IMHO) is to walk >through the optimizer pipeline to see where it can potentially be >eliminated. In general, the earlier in the optimizer pipeline the >extension can be eliminated, the better. > >Jeff Hi Jeff，Do you think my patch modification is suitable?What else needs to be improved？ Thanks. Feng Wang
Re: [PATCH] RISC-V: Optimize zbb ins sext.b and sext.h in rv64
Hi Juzhe, Thank you for your reply, I'm really doing some optimization work right now. I am very interested in the question you have raised, and I will take the time to try to optimize it. I hope I can communicate with you and learn from you more in the future. Thanks.
[PATCH] RISC-V: Optimize zbb ins sext.b and sext.h in rv64
This patch optimize the combine processing for sext.b/h in rv64.
Please refer to the following test case,
int sextb32(int x)
{ return (x << 24) >> 24; }
The rtl expression is as follows,
(insn 6 3 7 2 (set (reg:SI 138)
(ashift:SI (subreg/s/u:SI (reg/v:DI 136 [ xD.2271 ]) 0)
(const_int 24 [0x18]))) "sextb.c":2:13 195 {ashlsi3}
(expr_list:REG_DEAD (reg/v:DI 136 [ xD.2271 ])
(nil)))
(insn 7 6 8 2 (set (reg:SI 137)
(ashiftrt:SI (reg:SI 138)
(const_int 24 [0x18]))) "sextb.c":2:20 196 {ashrsi3}
(expr_list:REG_DEAD (reg:SI 138)
(nil)))
During the combine phase, they will combine into
(set (reg:SI 137)
(ashiftrt:SI (subreg:SI (ashift:DI (reg:DI 140)
(const_int 24 [0x18])) 0)
(const_int 24 [0x18])))
The optimal combine result is
(set (reg:SI 137)
(sign_extend:SI (subreg:QI (reg:DI 140) 0)))
This can be converted to the sext ins.
Due to the influence of subreg,the current processing
can't obtain the imm of left shifts. Need to peel off
another layer of rtl to obtain it.
gcc/ChangeLog:
* combine.cc (extract_left_shift): Add SUBREG case.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-sext-rv64.c: New test.
---
gcc/combine.cc | 5 +
gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c | 12
2 files changed, 17 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c
diff --git a/gcc/combine.cc b/gcc/combine.cc
index 053879500b7..fb396a3d974 100644
--- a/gcc/combine.cc
+++ b/gcc/combine.cc
@@ -7915,6 +7915,11 @@ extract_left_shift (scalar_int_mode mode, rtx x, int
count)
switch (code)
{
+case SUBREG:
+ x = XEXP (x, 0);
+ if (GET_CODE(x) != ASHIFT)
+break;
+
case ASHIFT:
/* This is the shift itself. If it is wide enough, we will return
either the value being shifted if the shift count is equal to
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c
b/gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c
new file mode 100644
index 000..4086ee56f57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_zbb -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+int sextb32(int x)
+{ return (x << 24) >> 24; }
+
+int sexth32(int x)
+{ return (x << 16) >> 16; }
+
+/* { dg-final { scan-assembler "sext.b" } } */
+/* { dg-final { scan-assembler "sext.h" } } */
\ No newline at end of file
--
2.17.1
[PATCH] RISC-V: Optimize load memory data in rv64
This patch optimize load one byte or halfword from memory in rv64.
Please refer to the following test case for loading one byte.
int sextb32_memory(int* x)
{ return (*x << 24) >> 24; }
The build flags are "-march=rv64g -mabi=lp64d -O2"
The current compilation results are as follows,
slliw a0,a0,0x18
sraiw a0,a0,0x18
ret
The compilation results after picking this patch are as follows,
lb a0,0(a0)
ret
The iusse is introduced by this patch
"RISC-V: Avoid zero/sign extend for volatile loads. Fix for 97417."
This patch expand
(set (reg:QI/HI/SI target) (mem:QI/HI/SI (address)))
to
(set (reg:DI temp) (zero_extend:DI (mem:QI/HI/SI (address
(set (reg:QI/HI/SI target) (subreg:QI/HI/SI (reg:DI temp) 0))
There is no problem with this transformation for QI and HI.
However,it will affect the subsequent combine processing for SI.
So I modified this operation to only take effect for QI and HI.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move):Modify length judgment
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rv64-load-byte.c: New test.
* gcc.target/riscv/rv64-load-halfword.c: New test.
---
gcc/config/riscv/riscv.cc | 2 +-
gcc/testsuite/gcc.target/riscv/rv64-load-byte.c | 8
gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c | 8
3 files changed, 17 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rv64-load-byte.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 1db12091b5a..4b596c7bb5b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2074,7 +2074,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx
src)
(set (reg:QI target) (subreg:QI (reg:DI temp) 0))
with auto-sign/zero extend. */
if (GET_MODE_CLASS (mode) == MODE_INT
- && GET_MODE_SIZE (mode).to_constant () < UNITS_PER_WORD
+ && GET_MODE_SIZE (mode).to_constant () < MIN_UNITS_PER_WORD
&& can_create_pseudo_p ()
&& MEM_P (src))
{
diff --git a/gcc/testsuite/gcc.target/riscv/rv64-load-byte.c
b/gcc/testsuite/gcc.target/riscv/rv64-load-byte.c
new file mode 100644
index 000..929aac79993
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rv64-load-byte.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+int sextb32_memory(int* x)
+{ return (*x << 24) >> 24; }
+
+/* { dg-final { scan-assembler "lb" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c
b/gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c
new file mode 100644
index 000..94e1bd7e135
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+int sexth32_memory(int* x)
+{ return (*x << 16) >> 16; }
+
+/* { dg-final { scan-assembler "lh" } } */
--
2.17.1
Re: Re: [PATCH] RISC-V: Optimize the MASK opt generation
On 2023-03-03 17:12 Feng Wang wrote: > >On 2023-03-03 16:54 jiawei wrote: >> >>The Mask flag in the single TargetVariable is not enough due to more >>and more extensions were added.So I optimize the defination of Mask >>flag, please refer to the below case: >>There are some new MASK flags for 'v' extension(ZVL32B,ZVL64B,...,ZVL65536B), >>but these MASK flags can't store into x_target_flags,because the total number >>of MASK flags exceed 32. In this patch we can write it like this in this >>scence. >> >>TargetVariable >>int riscv_zvl_flags >> >>Mask(ZVL32B) in TargetVariable(riscv_zvl_flags) >> >>The corresponding MASK and TARGET will be automatically generated. >> >>gcc/ChangeLog: >> >> * config/riscv/riscv-opts.h Delete below definations >> (MASK_ZICSR): Delete; >> (MASK_ZIFENCEI): Delete; >> (TARGET_ZICSR): Delete; >> (TARGET_ZIFENCEI): Delete; >> (MASK_ZAWRS): Delete; >> (TARGET_ZAWRS): Delete; >> (MASK_ZBA): Delete; >> (MASK_ZBB): Delete; >> (MASK_ZBC): Delete; >> (MASK_ZBS): Delete; >> (TARGET_ZBA): Delete; >> (TARGET_ZBB): Delete; >> (TARGET_ZBC): Delete; >> (TARGET_ZBS): Delete; >> (MASK_ZFINX): Delete; >> (MASK_ZDINX): Delete; >> (MASK_ZHINX): Delete; >> (MASK_ZHINXMIN): Delete; >> (TARGET_ZFINX): Delete; >> (TARGET_ZDINX): Delete; >> (TARGET_ZHINX): Delete; >> (TARGET_ZHINXMIN): Delete; >> (MASK_ZBKB): Delete; >> (MASK_ZBKC): Delete; >> (MASK_ZBKX): Delete; >> (MASK_ZKNE): Delete; >> (MASK_ZKND): Delete; >> (MASK_ZKNH): Delete; >> (MASK_ZKR): Delete; >> (MASK_ZKSED): Delete; >> (MASK_ZKSH): Delete; >> (MASK_ZKT): Delete; >> (TARGET_ZBKB): Delete; >> (TARGET_ZBKC): Delete; >> (TARGET_ZBKX): Delete; >> (TARGET_ZKNE): Delete; >> (TARGET_ZKND): Delete; >> (TARGET_ZKNH): Delete; >> (TARGET_ZKR): Delete; >> (TARGET_ZKSED): Delete; >> (TARGET_ZKSH): Delete; >> (TARGET_ZKT): Delete; >> (MASK_VECTOR_ELEN_32): Delete; >> (MASK_VECTOR_ELEN_64): Delete; >> (MASK_VECTOR_ELEN_FP_32): Delete; >> (MASK_VECTOR_ELEN_FP_64): Delete; >> (TARGET_VECTOR_ELEN_32): Delete; >> (TARGET_VECTOR_ELEN_64): Delete; >> (TARGET_VECTOR_ELEN_FP_32): Delete; >> (TARGET_VECTOR_ELEN_FP_64): Delete; >> (MASK_ZVL32B): Delete; >> (MASK_ZVL64B): Delete; >> (MASK_ZVL128B): Delete; >> (MASK_ZVL256B): Delete; >> (MASK_ZVL512B): Delete; >> (MASK_ZVL1024B): Delete; >> (MASK_ZVL2048B): Delete; >> (MASK_ZVL4096B): Delete; >> (MASK_ZVL8192B): Delete; >> (MASK_ZVL16384B): Delete; >> (MASK_ZVL32768B): Delete; >> (MASK_ZVL65536B): Delete; >> (TARGET_ZVL32B): Delete; >> (TARGET_ZVL64B): Delete; >> (TARGET_ZVL128B): Delete; >> (TARGET_ZVL256B): Delete; >> (TARGET_ZVL512B): Delete; >> (TARGET_ZVL1024B): Delete; >> (TARGET_ZVL2048B): Delete; >> (TARGET_ZVL4096B): Delete; >> (TARGET_ZVL8192B): Delete; >> (TARGET_ZVL16384B): Delete; >> (TARGET_ZVL32768B): Delete; >> (TARGET_ZVL65536B): Delete; >> (MASK_ZICBOZ): Delete; >> (MASK_ZICBOM): Delete; >> (MASK_ZICBOP): Delete; >> (TARGET_ZICBOZ): Delete; >> (TARGET_ZICBOM): Delete; >> (TARGET_ZICBOP): Delete; >> (MASK_ZFHMIN): Delete; >> (MASK_ZFH): Delete; >> (TARGET_ZFHMIN): Delete; >> (TARGET_ZFH): Delete; >> (MASK_ZMMUL): Delete; >> (TARGET_ZMMUL): Delete; >> (MASK_SVINVAL): Delete; >> (MASK_SVNAPOT): Delete; >> (TARGET_SVINVAL): Delete; >> (TARGET_SVNAPOT): Delete; >> * config/riscv/riscv.opt: Add new Mask defination. >> * opt-functions.awk: Add new function to find the index >> of target variable from extra_target_vars. >> * opt-read.awk: Add new function to store the Mask flags. >> * opth-gen.awk: Add new function to output the defination of >> Mask Macro and Target Macro
Re: Re: [PATCH] RISC-V: Optimize the MASK opt generation
On 2023-03-03 16:54 jiawei wrote:
>
>The Mask flag in the single TargetVariable is not enough due to more
>and more extensions were added.So I optimize the defination of Mask
>flag, please refer to the below case:
>There are some new MASK flags for 'v' extension(ZVL32B,ZVL64B,...,ZVL65536B),
>but these MASK flags can't store into x_target_flags,because the total number
>of MASK flags exceed 32. In this patch we can write it like this in this
>scence.
>
>TargetVariable
>int riscv_zvl_flags
>
>Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
>
>The corresponding MASK and TARGET will be automatically generated.
>
>gcc/ChangeLog:
>
> * config/riscv/riscv-opts.h Delete below definations
> (MASK_ZICSR): Delete;
> (MASK_ZIFENCEI): Delete;
> (TARGET_ZICSR): Delete;
> (TARGET_ZIFENCEI): Delete;
> (MASK_ZAWRS): Delete;
> (TARGET_ZAWRS): Delete;
> (MASK_ZBA): Delete;
> (MASK_ZBB): Delete;
> (MASK_ZBC): Delete;
> (MASK_ZBS): Delete;
> (TARGET_ZBA): Delete;
> (TARGET_ZBB): Delete;
> (TARGET_ZBC): Delete;
> (TARGET_ZBS): Delete;
> (MASK_ZFINX): Delete;
> (MASK_ZDINX): Delete;
> (MASK_ZHINX): Delete;
> (MASK_ZHINXMIN): Delete;
> (TARGET_ZFINX): Delete;
> (TARGET_ZDINX): Delete;
> (TARGET_ZHINX): Delete;
> (TARGET_ZHINXMIN): Delete;
> (MASK_ZBKB): Delete;
> (MASK_ZBKC): Delete;
> (MASK_ZBKX): Delete;
> (MASK_ZKNE): Delete;
> (MASK_ZKND): Delete;
> (MASK_ZKNH): Delete;
> (MASK_ZKR): Delete;
> (MASK_ZKSED): Delete;
> (MASK_ZKSH): Delete;
> (MASK_ZKT): Delete;
> (TARGET_ZBKB): Delete;
> (TARGET_ZBKC): Delete;
> (TARGET_ZBKX): Delete;
> (TARGET_ZKNE): Delete;
> (TARGET_ZKND): Delete;
> (TARGET_ZKNH): Delete;
> (TARGET_ZKR): Delete;
> (TARGET_ZKSED): Delete;
> (TARGET_ZKSH): Delete;
> (TARGET_ZKT): Delete;
> (MASK_VECTOR_ELEN_32): Delete;
> (MASK_VECTOR_ELEN_64): Delete;
> (MASK_VECTOR_ELEN_FP_32): Delete;
> (MASK_VECTOR_ELEN_FP_64): Delete;
> (TARGET_VECTOR_ELEN_32): Delete;
> (TARGET_VECTOR_ELEN_64): Delete;
> (TARGET_VECTOR_ELEN_FP_32): Delete;
> (TARGET_VECTOR_ELEN_FP_64): Delete;
> (MASK_ZVL32B): Delete;
> (MASK_ZVL64B): Delete;
> (MASK_ZVL128B): Delete;
> (MASK_ZVL256B): Delete;
> (MASK_ZVL512B): Delete;
> (MASK_ZVL1024B): Delete;
> (MASK_ZVL2048B): Delete;
> (MASK_ZVL4096B): Delete;
> (MASK_ZVL8192B): Delete;
> (MASK_ZVL16384B): Delete;
> (MASK_ZVL32768B): Delete;
> (MASK_ZVL65536B): Delete;
> (TARGET_ZVL32B): Delete;
> (TARGET_ZVL64B): Delete;
> (TARGET_ZVL128B): Delete;
> (TARGET_ZVL256B): Delete;
> (TARGET_ZVL512B): Delete;
> (TARGET_ZVL1024B): Delete;
> (TARGET_ZVL2048B): Delete;
> (TARGET_ZVL4096B): Delete;
> (TARGET_ZVL8192B): Delete;
> (TARGET_ZVL16384B): Delete;
> (TARGET_ZVL32768B): Delete;
> (TARGET_ZVL65536B): Delete;
> (MASK_ZICBOZ): Delete;
> (MASK_ZICBOM): Delete;
> (MASK_ZICBOP): Delete;
> (TARGET_ZICBOZ): Delete;
> (TARGET_ZICBOM): Delete;
> (TARGET_ZICBOP): Delete;
> (MASK_ZFHMIN): Delete;
> (MASK_ZFH): Delete;
> (TARGET_ZFHMIN): Delete;
> (TARGET_ZFH): Delete;
> (MASK_ZMMUL): Delete;
> (TARGET_ZMMUL): Delete;
> (MASK_SVINVAL): Delete;
> (MASK_SVNAPOT): Delete;
> (TARGET_SVINVAL): Delete;
> (TARGET_SVNAPOT): Delete;
> * config/riscv/riscv.opt: Add new Mask defination.
> * opt-functions.awk: Add new function to find the index
> of target variable from extra_target_vars.
> * opt-read.awk: Add new function to store the Mask flags.
> * opth-gen.awk: Add new function to output the defination of
> Mask Macro and Target Macro.
>---
> gcc/config/riscv/riscv-opts.h | 115 --
> gcc/config/riscv/riscv.opt | 90 ++
> gcc/opt-functions.awk | 11
> gcc/opt-read.awk | 16 -
> gcc/opth-gen.awk | 22 +++
> 5 files changed, 138 insertions(+), 116 deletions(-)
>
>diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
>index 25fd85b09b1..7cf28838cb5 100644
>--- a/gcc/config/riscv/riscv-opts.h
>+++ b/gcc/config/riscv/riscv-opts.h
>@@ -66,121 +66,6 @@ enum stack_protector_guard {
> SSP_TLS,/* per-thread canary in TLS block */
> SSP_GLOBAL /* global canary */
> };
>-
>-#define MASK_ZICSR (1 << 0)
>-#define MASK_ZIFENCEI (1 << 1)
>-
>-#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
>-#define TARGET_ZIFENCEI ((riscv_zi_subext &
[PATCH] RISC-V: Optimize the MASK opt generation
The Mask flag in the single TargetVariable is not enough due to more
and more extensions were added.So I optimize the defination of Mask
flag, please refer to the below case:
There are some new MASK flags for 'v' extension(ZVL32B,ZVL64B,...,ZVL65536B),
but these MASK flags can't store into x_target_flags,because the total number
of MASK flags exceed 32. In this patch we can write it like this in this scence.
TargetVariable
int riscv_zvl_flags
Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
The corresponding MASK and TARGET will be automatically generated.
gcc/ChangeLog:
* config/riscv/riscv-opts.h Delete below definations
(MASK_ZICSR): Delete;
(MASK_ZIFENCEI): Delete;
(TARGET_ZICSR): Delete;
(TARGET_ZIFENCEI): Delete;
(MASK_ZAWRS): Delete;
(TARGET_ZAWRS): Delete;
(MASK_ZBA): Delete;
(MASK_ZBB): Delete;
(MASK_ZBC): Delete;
(MASK_ZBS): Delete;
(TARGET_ZBA): Delete;
(TARGET_ZBB): Delete;
(TARGET_ZBC): Delete;
(TARGET_ZBS): Delete;
(MASK_ZFINX): Delete;
(MASK_ZDINX): Delete;
(MASK_ZHINX): Delete;
(MASK_ZHINXMIN): Delete;
(TARGET_ZFINX): Delete;
(TARGET_ZDINX): Delete;
(TARGET_ZHINX): Delete;
(TARGET_ZHINXMIN): Delete;
(MASK_ZBKB): Delete;
(MASK_ZBKC): Delete;
(MASK_ZBKX): Delete;
(MASK_ZKNE): Delete;
(MASK_ZKND): Delete;
(MASK_ZKNH): Delete;
(MASK_ZKR): Delete;
(MASK_ZKSED): Delete;
(MASK_ZKSH): Delete;
(MASK_ZKT): Delete;
(TARGET_ZBKB): Delete;
(TARGET_ZBKC): Delete;
(TARGET_ZBKX): Delete;
(TARGET_ZKNE): Delete;
(TARGET_ZKND): Delete;
(TARGET_ZKNH): Delete;
(TARGET_ZKR): Delete;
(TARGET_ZKSED): Delete;
(TARGET_ZKSH): Delete;
(TARGET_ZKT): Delete;
(MASK_VECTOR_ELEN_32): Delete;
(MASK_VECTOR_ELEN_64): Delete;
(MASK_VECTOR_ELEN_FP_32): Delete;
(MASK_VECTOR_ELEN_FP_64): Delete;
(TARGET_VECTOR_ELEN_32): Delete;
(TARGET_VECTOR_ELEN_64): Delete;
(TARGET_VECTOR_ELEN_FP_32): Delete;
(TARGET_VECTOR_ELEN_FP_64): Delete;
(MASK_ZVL32B): Delete;
(MASK_ZVL64B): Delete;
(MASK_ZVL128B): Delete;
(MASK_ZVL256B): Delete;
(MASK_ZVL512B): Delete;
(MASK_ZVL1024B): Delete;
(MASK_ZVL2048B): Delete;
(MASK_ZVL4096B): Delete;
(MASK_ZVL8192B): Delete;
(MASK_ZVL16384B): Delete;
(MASK_ZVL32768B): Delete;
(MASK_ZVL65536B): Delete;
(TARGET_ZVL32B): Delete;
(TARGET_ZVL64B): Delete;
(TARGET_ZVL128B): Delete;
(TARGET_ZVL256B): Delete;
(TARGET_ZVL512B): Delete;
(TARGET_ZVL1024B): Delete;
(TARGET_ZVL2048B): Delete;
(TARGET_ZVL4096B): Delete;
(TARGET_ZVL8192B): Delete;
(TARGET_ZVL16384B): Delete;
(TARGET_ZVL32768B): Delete;
(TARGET_ZVL65536B): Delete;
(MASK_ZICBOZ): Delete;
(MASK_ZICBOM): Delete;
(MASK_ZICBOP): Delete;
(TARGET_ZICBOZ): Delete;
(TARGET_ZICBOM): Delete;
(TARGET_ZICBOP): Delete;
(MASK_ZFHMIN): Delete;
(MASK_ZFH): Delete;
(TARGET_ZFHMIN): Delete;
(TARGET_ZFH): Delete;
(MASK_ZMMUL): Delete;
(TARGET_ZMMUL): Delete;
(MASK_SVINVAL): Delete;
(MASK_SVNAPOT): Delete;
(TARGET_SVINVAL): Delete;
(TARGET_SVNAPOT): Delete;
* config/riscv/riscv.opt: Add new Mask defination.
* opt-functions.awk: Add new function to find the index
of target variable from extra_target_vars.
* opt-read.awk: Add new function to store the Mask flags.
* opth-gen.awk: Add new function to output the defination of
Mask Macro and Target Macro.
---
gcc/config/riscv/riscv-opts.h | 115 --
gcc/config/riscv/riscv.opt| 90 ++
gcc/opt-functions.awk | 11
gcc/opt-read.awk | 16 -
gcc/opth-gen.awk | 22 +++
5 files changed, 138 insertions(+), 116 deletions(-)
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 25fd85b09b1..7cf28838cb5 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -66,121 +66,6 @@ enum stack_protector_guard {
SSP_TLS, /* per-thread canary in TLS block */
SSP_GLOBAL /* global canary */
};
-
-#define MASK_ZICSR(1 << 0)
-#define MASK_ZIFENCEI (1 << 1)
-
-#define TARGET_ZICSR((riscv_zi_subext & MASK_ZICSR) != 0)
-#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
-
-#define MASK_ZAWRS (1 << 0)
-#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
-
-#define MASK_ZBA (1 <<
[PATCH v2 1/1] RISC-V: Optimze the reverse conditions of rotate shift
From: wangfeng
There is no Immediate operand of ins "rol" according to the B-ext,
so the immediate operand should be loaded into register at first.
But we can convert it to the ins "rori" or "roriw", and then one
immediate load ins can be reduced.
So I added some conditions when reverse the rotate shift during RTL
expansion and RTL optimization.Reverse if the below two conditions
are met at the same time,
1. The current insn_code doesn't exist or it's operand doesn't match,
or the shift amount is beyond the half size of the machine mode;
2. The reversed insn_code exists and it's operand matches.
Please refer to the following use cases:
unsigned long foo2(unsigned long rs1)
{
return (rs1 << 10) | (rs1 >> 54);
}
The compiler result is:
li a1,10
rol a0,a0,a1
This patch will generate one ins
rori a0,a0,54
At the same time I add the missing "roriw" ins RTL pattern
Pass the linux-rv32imafdc-ilp32d-medany,linux-rv64imafdc-lp64d-medany,
newlib-rv32imafc-ilp32f-medany and newlib-rv64imafdc-lp64d-medany regression.
gcc/ChangeLog:
* config/riscv/bitmanip.md: Add "roriw" insn output
* expmed.cc (expand_shift_1):Call reverse_rotate_by_imm_p to judge
whether reverse the rotate direction when GIMPLE to RTL.
* rtl.h (reverse_rotate_by_imm_p): Add function declartion
* simplify-rtx.cc (reverse_rotate_by_imm_p): Add a function to judge
whether reverse rotate shift direction when simplify rtx.
Reverse if the below two conditions are met at the same time,
1. The current insn_code doesn't exist or it's operand doesn't
match,
or the shift amount is beyond the half size of the machine
mode;
2. The reversed insn_code exists and it's operand matches.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-rol-ror-04.c: New test.
* gcc.target/riscv/zbb-rol-ror-05.c: New test.
* gcc.target/riscv/zbb-rol-ror-06.c: New test.
* gcc.target/riscv/zbb-rol-ror-07.c: New test.
---
gcc/config/riscv/bitmanip.md | 4 +-
gcc/expmed.cc | 14 ++--
gcc/rtl.h | 1 +
gcc/simplify-rtx.cc | 49 ++
.../gcc.target/riscv/zbb-rol-ror-04.c | 52 +++
.../gcc.target/riscv/zbb-rol-ror-05.c | 24 +++
.../gcc.target/riscv/zbb-rol-ror-06.c | 36 +++
.../gcc.target/riscv/zbb-rol-ror-07.c | 64 +++
8 files changed, 219 insertions(+), 25 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index d17133d58c1..ba69d0134b2 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -292,9 +292,9 @@
(define_insn "rotrsi3_sext"
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
-(match_operand:QI 2 "register_operand"
"r"]
+(match_operand:QI 2 "arith_operand"
"rI"]
"TARGET_64BIT && TARGET_ZBB"
- "rorw\t%0,%1,%2"
+ "ror%i2%~\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
(define_insn "rotlsi3"
diff --git a/gcc/expmed.cc b/gcc/expmed.cc
index b12b0e000c2..907c259c624 100644
--- a/gcc/expmed.cc
+++ b/gcc/expmed.cc
@@ -2475,7 +2475,7 @@ expand_dec (rtx target, rtx dec)
if (value != target)
emit_move_insn (target, value);
}
-
+
/* Output a shift instruction for expression code CODE,
with SHIFTED being the rtx for the value to shift,
and AMOUNT the rtx for the amount to shift by.
@@ -2535,17 +2535,13 @@ expand_shift_1 (enum tree_code code, machine_mode mode,
rtx shifted,
op1 = SUBREG_REG (op1);
}
- /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
- prefer left rotation, if op1 is from bitsize / 2 + 1 to
- bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
- amount instead. */
+ /* Canonicalize rotates by constant amount. If the condition of
+ reversing direction is met, then reverse the direction. */
if (rotate
- && CONST_INT_P (op1)
- && IN_RANGE (INTVAL (op1), GET_MODE_BITSIZE (scalar_mode) / 2 + left,
- GET_MODE_BITSIZE (scalar_mode) - 1))
+ && reverse_rotate_by_imm_p (scalar_mode, left, op1))
{
op1 = gen_int_shift_amount (mode, (GET_MODE_BITSIZE (scalar_mode)
-- INTVAL (op1)));
+ - INTVAL (op1)));
left = !left;
code = left ? LROTATE_EXPR : RROTATE_EXPR;
}
diff --git
[PATCH v2 0/1] RISC-V: Optimze the reverse conditions of rotate shift
The first patch is https://gcc.gnu.org/pipermail/gcc-patches/2022-November/607332.html. Accroding to Jeff's suggestion I added some conditions when reverse the rotate shift during RTL expansion and RTL optimization. wangfeng (1): RISC-V: Optimze the reverse conditions of rotate shift gcc/config/riscv/bitmanip.md | 4 +- gcc/expmed.cc | 14 ++-- gcc/rtl.h | 1 + gcc/simplify-rtx.cc | 49 ++ .../gcc.target/riscv/zbb-rol-ror-04.c | 52 +++ .../gcc.target/riscv/zbb-rol-ror-05.c | 24 +++ .../gcc.target/riscv/zbb-rol-ror-06.c | 36 +++ .../gcc.target/riscv/zbb-rol-ror-07.c | 64 +++ 8 files changed, 219 insertions(+), 25 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c -- 2.17.1
Re: Re: [PATCH] RISC-V: Support the ins "rol" with immediate operand
on 2022-11-28 23:39 Jeff Law wrote:
>
>
>On 11/27/22 19:14, Feng Wang wrote:
>> From: wangfeng
>>
>> There is no Immediate operand of ins "rol" accroding to the B-ext,
>> so the immediate operand should be loaded into register at first.
>> But we can convert it to the ins "rori" or "roriw", and then one
>> immediate load ins can be reduced.
>>
>> Please refer to the following use cases:
>> unsigned long foo2(unsigned long rs1)
>> {
>> return (rs1 << 10) | (rs1 >> 54);
>> }
>>
>> The complier result is:
>> li a1,10
>> rol a0,a0,a1
>>
>> This patch will generate one ins
>> rori a0,a0,54
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/bitmanip.md: Add immediate_operand support in rotl
>>RTL pattern
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/zbb-rol-ror-04.c: New test.
>> * gcc.target/riscv/zbb-rol-ror-05.c: New test.
>
>So this arrived after stage1 close and I'm not aware of an existing BZ
>around this issue, so I'd tend to think this should wait for stage1 to
>re-open in the spring.
>
>
> From a technical standpoint, would it be better to hand this in a more
>generic way? ie, when converting from gimple into RTL, if we want to
>generate a rotate left by immediate and don't have a suitable insn, then
>change it to a rotate right by an adjusted immediate. This could
>probably be done in optabs.cc::expand_binop.
>
>
>We might need similar code in combine.cc or simplify-rtx.cc since some
>rotate cases (or exposure of the constant) may not show up until later
>in the RTL pipeline.
>
>
>Anyway, doing this in a more generic way seems like it's worth
>investigating.
>
>
>jeff
>
Hi jeff,
Thanks for your reply. In the currently it will judge the rotate shift number
when converting from
gimple into RTL, if the shift number bigger than mode_size/2, then reverse the
rotate direction.
I think the purpose of this process is to handle rotate shift quickly. I will
think about your advice
and try to modify it in the expand pass.
Wang Feng
Best regards
[PATCH] RISC-V: Support the ins "rol" with immediate operand
From: wangfeng
There is no Immediate operand of ins "rol" accroding to the B-ext,
so the immediate operand should be loaded into register at first.
But we can convert it to the ins "rori" or "roriw", and then one
immediate load ins can be reduced.
Please refer to the following use cases:
unsigned long foo2(unsigned long rs1)
{
return (rs1 << 10) | (rs1 >> 54);
}
The complier result is:
li a1,10
rol a0,a0,a1
This patch will generate one ins
rori a0,a0,54
gcc/ChangeLog:
* config/riscv/bitmanip.md: Add immediate_operand support in rotl RTL
pattern
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbb-rol-ror-04.c: New test.
* gcc.target/riscv/zbb-rol-ror-05.c: New test.
---
gcc/config/riscv/bitmanip.md | 36 +++
.../gcc.target/riscv/zbb-rol-ror-04.c | 24 +
.../gcc.target/riscv/zbb-rol-ror-05.c | 15
3 files changed, 69 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index d17133d58c1..cddfa2a4b19 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -300,25 +300,49 @@
(define_insn "rotlsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(rotate:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:QI 2 "register_operand" "r")))]
+ (match_operand:QI 2 "arith_operand" "rI")))]
"TARGET_ZBB"
- "rol%~\t%0,%1,%2"
+ {
+if (immediate_operand(operands[2], QImode))
+{
+ operands[2] = GEN_INT(GET_MODE_BITSIZE (SImode) - INTVAL(operands[2]));
+ return "rori\t%0,%1,%2";
+}
+else
+ return "rol\t%0,%1,%2";
+ }
[(set_attr "type" "bitmanip")])
(define_insn "rotldi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(rotate:DI (match_operand:DI 1 "register_operand" "r")
- (match_operand:QI 2 "register_operand" "r")))]
+ (match_operand:QI 2 "arith_operand" "rI")))]
"TARGET_64BIT && TARGET_ZBB"
- "rol\t%0,%1,%2"
+ {
+if (immediate_operand(operands[2], QImode))
+{
+ operands[2] = GEN_INT(GET_MODE_BITSIZE (DImode) - INTVAL(operands[2]));
+ return "rori\t%0,%1,%2";
+}
+else
+ return "rol\t%0,%1,%2";
+ }
[(set_attr "type" "bitmanip")])
(define_insn "rotlsi3_sext"
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:QI 2 "register_operand"
"r"]
+ (match_operand:QI 2 "arith_operand" "rI"]
"TARGET_64BIT && TARGET_ZBB"
- "rolw\t%0,%1,%2"
+ {
+if (immediate_operand(operands[2], QImode))
+{
+ operands[2] = GEN_INT(GET_MODE_BITSIZE (SImode) - INTVAL(operands[2]));
+ return "roriw\t%0,%1,%2";
+}
+else
+ return "rolw\t%0,%1,%2";
+ }
[(set_attr "type" "bitmanip")])
;; orc.b (or-combine) is added as an unspec for the benefit of the support
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
new file mode 100644
index 000..23883cc3a5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-g" } } */
+
+unsigned long foo1 (unsigned long rs1)
+{ return (rs1 >> (34)) | (rs1 << 30); }
+
+unsigned long foo2(unsigned long rs1)
+{
+return (rs1 << 10) | (rs1 >> 54);
+}
+
+unsigned int foo3(unsigned int rs1)
+{
+return (rs1 >> 20) | (rs1 << 12);
+}
+
+unsigned int foo4(unsigned int rs1)
+{
+return (rs1 << 10) | (rs1 >> 22);
+}
+
+/* { dg-final { scan-assembler-times "rori\t" 2 } } */
+/* { dg-final { scan-assembler-times "roriw" 2 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
new file mode 100644
index 000..3e300a30b9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zbb -mabi=ilp32" } */
+/* { dg-skip-if "" { rv64-*-* } { "-g" } } */
+
+unsigned int foo1(unsigned int rs1)
+{
+return (rs1 >> 20) | (rs1 << 12);
+}
+
+unsigned int foo2(unsigned int rs1)
+{
+return (rs1 << 10) | (rs1 >> 22);
+}
+
+/* { dg-final { scan-assembler-times "rori" 2 } } */
\ No newline at end of file
--
2.17.1
