Re: [PATCH V2] RISC-V: Fix missing boolean_expression in zmmul extension

[Kito Cheng]

LGTM

Liao Shihua  於 2024年5月24日 週五 13:05 寫道：

> Update v1->v2
> Add testcase for this patch.
>
> Missing boolean_expression TARGET_ZMMUL in riscv_rtx_costs() cause
> different instructions when
> multiplying an integer with a constant. (
> https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1482 )
>
> int foo(int *ib) {
> *ib = *ib * 33938;
> return 0;
> }
>
> rv64im:
> lw  a4,0(a1)
> li  a5,32768
> addiw   a5,a5,1170
> mulwa5,a5,a4
> sw  a5,0(a1)
> ret
>
> rv64i_zmmul:
> lw  a4,0(a1)
> slliw   a5,a4,5
> addwa5,a5,a4
> slliw   a5,a5,3
> addwa5,a5,a4
> slliw   a5,a5,3
> addwa5,a5,a4
> slliw   a5,a5,3
> addwa5,a5,a4
> slliw   a5,a5,1
> sw  a5,0(a1)
> ret
>
> Fixed.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_rtx_costs): Add TARGET_ZMMUL.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zmmul-3.c: New test.
>
> ---
>  gcc/config/riscv/riscv.cc| 2 +-
>  gcc/testsuite/gcc.target/riscv/zmmul-3.c | 8 
>  2 files changed, 9 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-3.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 85df5b7ab49..580ae007181 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -3753,7 +3753,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
> outer_code, int opno ATTRIBUTE_UN
>  case MULT:
>if (float_mode_p)
> *total = tune_param->fp_mul[mode == DFmode];
> -  else if (!TARGET_MUL)
> +  else if (!(TARGET_MUL || TARGET_ZMMUL))
> /* Estimate the cost of a library call.  */
> *total = COSTS_N_INSNS (speed ? 32 : 6);
>else if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD)
> diff --git a/gcc/testsuite/gcc.target/riscv/zmmul-3.c
> b/gcc/testsuite/gcc.target/riscv/zmmul-3.c
> new file mode 100644
> index 000..ae9752462e4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zmmul-3.c
> @@ -0,0 +1,8 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64iafdc_zmmul -mabi=lp64d" } */
> +int foo1(int a)
> +{
> +return a * 99;
> +}
> +
> +/* { dg-final { scan-assembler-times "mulw\t" 1 } } */
> \ No newline at end of file
> --
> 2.34.1
>
>

Re: [PATCH] RISC-V: Fix missing boolean_expression in zmmul extension

[Kito Cheng]

Could you add a testcase to make sure zmmul will generate mul instruction?

Liao Shihua  於 2024年5月23日 週四 18:48 寫道：

> Missing boolean_expression TARGET_ZMMUL in riscv_rtx_costs() casuse
> different instructions when multiplying an integer with a constant.
> ( https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1482 )
>
> int foo(int *ib) {
> *ib = *ib * 33938;
> return 0;
> }
>
> rv64im:
> lw  a4,0(a1)
> li  a5,32768
> addiw   a5,a5,1170
> mulwa5,a5,a4
> sw  a5,0(a1)
> ret
>
> rv64i_zmmul:
> lw  a4,0(a1)
> slliw   a5,a4,5
> addwa5,a5,a4
> slliw   a5,a5,3
> addwa5,a5,a4
> slliw   a5,a5,3
> addwa5,a5,a4
> slliw   a5,a5,3
> addwa5,a5,a4
> slliw   a5,a5,1
> sw  a5,0(a1)
> ret
>
> Fixed.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_rtx_costs): Add TARGET_ZMMUL.
>
> ---
>  gcc/config/riscv/riscv.cc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 85df5b7ab49..580ae007181 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -3753,7 +3753,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
> outer_code, int opno ATTRIBUTE_UN
>  case MULT:
>if (float_mode_p)
> *total = tune_param->fp_mul[mode == DFmode];
> -  else if (!TARGET_MUL)
> +  else if (!(TARGET_MUL || TARGET_ZMMUL))
> /* Estimate the cost of a library call.  */
> *total = COSTS_N_INSNS (speed ? 32 : 6);
>else if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD)
> --
> 2.34.1
>
>

Re: [PATCH] RISC-V: Modify _Bfloat16 to __bf16

[Kito Cheng]

LGTM, thanks for fixing this :)

On Fri, May 17, 2024 at 4:05 PM Xiao Zeng  wrote:
>
> According to the description in:
> <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367>,
> the type representation symbol of BF16 has been corrected.
>
> Kito Cheng pointed out relevant information in the email:
> <https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651850.html>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-builtins.cc (riscv_init_builtin_types):
> Modify _Bfloat16 to __bf16.
> * config/riscv/riscv.cc (riscv_mangle_type): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/_Bfloat16-nanboxing.c: Move to...
> * gcc.target/riscv/__bf16-nanboxing.c: ...here.
> * gcc.target/riscv/bf16_arithmetic.c: Modify _Bfloat16 to __bf16.
> * gcc.target/riscv/bf16_call.c: Ditto.
> * gcc.target/riscv/bf16_comparison.c: Ditto.
> * gcc.target/riscv/bf16_float_libcall_convert.c: Ditto.
> * gcc.target/riscv/bf16_integer_libcall_convert.c: Ditto.
> ---
>  gcc/config/riscv/riscv-builtins.cc   |  6 +++---
>  gcc/config/riscv/riscv.cc|  2 +-
>  .../{_Bfloat16-nanboxing.c => __bf16-nanboxing.c}| 12 ++--
>  gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c |  6 +++---
>  gcc/testsuite/gcc.target/riscv/bf16_call.c   |  4 ++--
>  gcc/testsuite/gcc.target/riscv/bf16_comparison.c |  6 +++---
>  .../gcc.target/riscv/bf16_float_libcall_convert.c|  2 +-
>  .../gcc.target/riscv/bf16_integer_libcall_convert.c  |  2 +-
>  8 files changed, 20 insertions(+), 20 deletions(-)
>  rename gcc/testsuite/gcc.target/riscv/{_Bfloat16-nanboxing.c => 
> __bf16-nanboxing.c} (83%)
>
> diff --git a/gcc/config/riscv/riscv-builtins.cc 
> b/gcc/config/riscv/riscv-builtins.cc
> index 4c08834288a..dc54e1a59b5 100644
> --- a/gcc/config/riscv/riscv-builtins.cc
> +++ b/gcc/config/riscv/riscv-builtins.cc
> @@ -275,7 +275,7 @@ riscv_init_builtin_types (void)
>  lang_hooks.types.register_builtin_type (riscv_float16_type_node,
> "_Float16");
>
> -  /* Provide the _Bfloat16 type and bfloat16_type_node if needed.  */
> +  /* Provide the __bf16 type and bfloat16_type_node if needed.  */
>if (!bfloat16_type_node)
>  {
>riscv_bfloat16_type_node = make_node (REAL_TYPE);
> @@ -286,9 +286,9 @@ riscv_init_builtin_types (void)
>else
>  riscv_bfloat16_type_node = bfloat16_type_node;
>
> -  if (!maybe_get_identifier ("_Bfloat16"))
> +  if (!maybe_get_identifier ("__bf16"))
>  lang_hooks.types.register_builtin_type (riscv_bfloat16_type_node,
> -   "_Bfloat16");
> +   "__bf16");
>  }
>
>  /* Implement TARGET_INIT_BUILTINS.  */
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 4067505270e..cf15a12de3a 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -10262,7 +10262,7 @@ riscv_asan_shadow_offset (void)
>  static const char *
>  riscv_mangle_type (const_tree type)
>  {
> -  /* Half-precision float, _Float16 is "DF16_" and _Bfloat16 is "DF16b".  */
> +  /* Half-precision float, _Float16 is "DF16_" and __bf16 is "DF16b".  */
>if (SCALAR_FLOAT_TYPE_P (type) && TYPE_PRECISION (type) == 16)
>  {
>if (TYPE_MODE (type) == HFmode)
> diff --git a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c 
> b/gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c
> similarity index 83%
> rename from gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
> rename to gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c
> index 11a73d22234..a9a586c98b9 100644
> --- a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
> +++ b/gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c
> @@ -1,14 +1,14 @@
>  /* { dg-do compile } */
>  /* { dg-options "-march=rv64ifd -mabi=lp64d -mcmodel=medlow -O" } */
>
> -_Bfloat16 gvar = 9.87654;
> +__bf16 gvar = 9.87654;
>  union U
>  {
>unsigned short i16;
> -  _Bfloat16 f16;
> +  __bf16 f16;
>  };
>
> -_Bfloat16
> +__bf16
>  test1 (unsigned short input)
>  {
>union U tmp;
> @@ -16,19 +16,19 @@ test1 (unsigned short input)
>return tmp.f16;
>  }
>
> -_Bfloat16
> +__bf16
>  test2 ()
>  {
>return 1.234f;
>  }
>
> -_Bfloat16
> +__bf16
>  test3 ()
>  {
>return gvar;
>  }
>
> -_Bfloat16
> +__bf16
>  test ()
>  {
>return 0.0f;
> diff --git a/gcc/testsuite/gcc.target/riscv/bf16_

Re: [PATCH] RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi tests

[Kito Cheng]

LGTM

On Thu, May 16, 2024 at 5:09 PM Christoph Müllner
 wrote:
>
> The tests cmpmemsi-1.c and cpymemsi-1.c are execution ("dg-do run")
> tests, which does not have any restrictions for the enabled extensions.
> Further, no other listed options are required.
> Let's drop the options, so that the test can also be executed on
> non-f and non-d targets.  However, we need to set options to the
> defaults without '-ansi', because the included test file uses the
> 'asm' keyword, which is not part of ANSI C.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/cmpmemsi-1.c: Drop options.
> * gcc.target/riscv/cpymemsi-1.c: Likewise.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/testsuite/gcc.target/riscv/cmpmemsi-1.c | 3 +--
>  gcc/testsuite/gcc.target/riscv/cpymemsi-1.c | 4 +---
>  2 files changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/cmpmemsi-1.c 
> b/gcc/testsuite/gcc.target/riscv/cmpmemsi-1.c
> index d7e0bc47407..698f27d89fb 100644
> --- a/gcc/testsuite/gcc.target/riscv/cmpmemsi-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/cmpmemsi-1.c
> @@ -1,6 +1,5 @@
>  /* { dg-do run } */
> -/* { dg-options "-march=rv32gc_zbb -save-temps -g0 -fno-lto" { target { rv32 
> } } } */
> -/* { dg-options "-march=rv64gc_zbb -save-temps -g0 -fno-lto" { target { rv64 
> } } } */
> +/* { dg-options "-pedantic-errors" } */
>  /* { dg-timeout-factor 2 } */
>
>  #include "../../gcc.dg/memcmp-1.c"
> diff --git a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c 
> b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> index 983b564ccaf..30e9f119bed 100644
> --- a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> @@ -1,7 +1,5 @@
>  /* { dg-do run } */
> -/* { dg-options "-march=rv32gc -save-temps -g0 -fno-lto" { target { rv32 } } 
> } */
> -/* { dg-options "-march=rv64gc -save-temps -g0 -fno-lto" { target { rv64 } } 
> } */
> -/* { dg-additional-options "-DRUN_FRACTION=11" { target simulator } } */
> +/* { dg-options "-pedantic-errors" } */
>  /* { dg-timeout-factor 2 } */
>
>  #include "../../gcc.dg/memcmp-1.c"
> --
> 2.44.0
>

Re: [NOT CODE REVIEW] [PATCH v3 1/1] [RISC-V] Add support for _Bfloat16

[Kito Cheng]

Hi Xiao Zeng:

Just wondering why use _Bfloat16 rather than __bf16? you mention
__bf16 in comment, but implementation use _Bfloat16? I would like to
use __bf16 to make it consistent between LLVM and psABI if possible :)

Re: [PATCH] RISC-V: testsuite: Drop march-string in cpymemsi-1.c

[Kito Cheng]

Just one minor question

> diff --git a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c 
> b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> index 983b564ccaf..aee54d9aa00 100644
> --- a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> @@ -1,6 +1,5 @@
>  /* { dg-do run } */
> -/* { dg-options "-march=rv32gc -save-temps -g0 -fno-lto" { target { rv32 } } 
> } */
> -/* { dg-options "-march=rv64gc -save-temps -g0 -fno-lto" { target { rv64 } } 
> } */
> +/* { dg-options "-save-temps -g0 -fno-lto" } */

I know -save-temps -g0 already exists, but I am wondering why we need
those 2 options here?

Re: [PATCH] RISC-V: Fix cbo.zero expansion for rv32

[Kito Cheng]

LGTM :)

On Wed, May 15, 2024 at 2:48 PM Christoph Müllner
 wrote:
>
> Emitting a DI pattern won't find a match for rv32 and manifests in
> the failing test case gcc.target/riscv/cmo-zicboz-zic64-1.c.
> Let's fix this in the expansion and also address the different
> code that gets generated for rv32/rv64.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-string.cc 
> (riscv_expand_block_clear_zicboz_zic64b):
> Fix expansion for rv32.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/cmo-zicboz-zic64-1.c: Fix for rv32.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/config/riscv/riscv-string.cc  |  5 ++-
>  .../gcc.target/riscv/cmo-zicboz-zic64-1.c | 36 ++-
>  2 files changed, 14 insertions(+), 27 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-string.cc 
> b/gcc/config/riscv/riscv-string.cc
> index 87f5fdee3c1..b515f44d17a 100644
> --- a/gcc/config/riscv/riscv-string.cc
> +++ b/gcc/config/riscv/riscv-string.cc
> @@ -827,7 +827,10 @@ riscv_expand_block_clear_zicboz_zic64b (rtx dest, rtx 
> length)
>  {
>rtx mem = adjust_address (dest, BLKmode, offset);
>rtx addr = force_reg (Pmode, XEXP (mem, 0));
> -  emit_insn (gen_riscv_zero_di (addr));
> +  if (TARGET_64BIT)
> +   emit_insn (gen_riscv_zero_di (addr));
> +  else
> +   emit_insn (gen_riscv_zero_si (addr));
>offset += cbo_bytes;
>  }
>
> diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c 
> b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c
> index c2d79eb7ae6..9192b391b11 100644
> --- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c
> @@ -1,25 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zic64b_zicboz" { target { rv64 } } } */
>  /* { dg-options "-march=rv32gc_zic64b_zicboz" { target { rv32 } } } */
> +/* { dg-options "-march=rv64gc_zic64b_zicboz" { target { rv64 } } } */
>  /* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
> -/* { dg-final { check-function-bodies "**" "" } } */
> -/* { dg-allow-blank-lines-in-output 1 } */
>
> -/*
> -**clear_buf_123:
> -**...
> -**cbo\.zero\t0\(a[0-9]+\)
> -**sd\tzero,64\(a[0-9]+\)
> -**sd\tzero,72\(a[0-9]+\)
> -**sd\tzero,80\(a[0-9]+\)
> -**sd\tzero,88\(a[0-9]+\)
> -**sd\tzero,96\(a[0-9]+\)
> -**sd\tzero,104\(a[0-9]+\)
> -**sd\tzero,112\(a[0-9]+\)
> -**sh\tzero,120\(a[0-9]+\)
> -**sb\tzero,122\(a[0-9]+\)
> -**...
> -*/
> +// 1x cbo.zero, 7x sd (rv64) or 14x sw (rv32), 1x sh, 1x sb
>  int
>  clear_buf_123 (void *p)
>  {
> @@ -27,17 +11,17 @@ clear_buf_123 (void *p)
>__builtin_memset (p, 0, 123);
>  }
>
> -/*
> -**clear_buf_128:
> -**...
> -**cbo\.zero\t0\(a[0-9]+\)
> -**addi\ta[0-9]+,a[0-9]+,64
> -**cbo\.zero\t0\(a[0-9]+\)
> -**...
> -*/
> +// 2x cbo.zero, 1x addi 64
>  int
>  clear_buf_128 (void *p)
>  {
>p = __builtin_assume_aligned(p, 64);
>__builtin_memset (p, 0, 128);
>  }
> +
> +/* { dg-final { scan-assembler-times "cbo\.zero\t" 3 } } */
> +/* { dg-final { scan-assembler-times "addi\ta\[0-9\]+,a\[0-9\]+,64" 1 } } */
> +/* { dg-final { scan-assembler-times "sd\t" 7 { target { rv64 } } } } */
> +/* { dg-final { scan-assembler-times "sw\t" 14 { target { rv32 } } } } */
> +/* { dg-final { scan-assembler-times "sh\t" 1 } } */
> +/* { dg-final { scan-assembler-times "sb\t" 1 } } */
> --
> 2.44.0
>

Re: [PATCH] RISC-V: Add Zvfbfwma extension to the -march= option

[Kito Cheng]

LGTM, I agree we should only implement what Embedded Processor
implies, we have no way to know that from the arch string

On Wed, May 15, 2024 at 1:35 PM Xiao Zeng  wrote:
>
> This patch would like to add new sub extension (aka Zvfbfwma) to the
> -march= option. It introduces a new data type BF16.
>
> 1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin 
> extension."
>   1.1 In EmbeddedProcessor: Zvfbfwma -> Zvfbfmin -> Zve32f
>   1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V
>   1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin
>
> 2 Zvfbfmin's information is in:
> 
>
> 3 Zfbfmin's formation is in:
> 
>
> 4 Depending on different usage scenarios, the Zvfbfwma extension may
> depend on 'V' or 'Zve32f'. This patch only implements dependencies in
> scenario of Embedded Processor. This is consistent with the processing
> strategy in Zvfbfmin. In scenario of Application Processor, it is
> necessary to explicitly indicate the dependent 'V' extension.
>
> 5 You can locate more information about Zvfbfwma from below spec doc:
> 
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfbfwma item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv.opt:
> (MASK_ZVFBFWMA): New macro.
> (TARGET_ZVFBFWMA): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-37.c: New test.
> * gcc.target/riscv/arch-38.c: New test.
> * gcc.target/riscv/predef-36.c: New test.
> * gcc.target/riscv/predef-37.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc|  5 +++
>  gcc/config/riscv/riscv.opt |  2 +
>  gcc/testsuite/gcc.target/riscv/arch-37.c   |  5 +++
>  gcc/testsuite/gcc.target/riscv/arch-38.c   |  5 +++
>  gcc/testsuite/gcc.target/riscv/predef-36.c | 48 ++
>  gcc/testsuite/gcc.target/riscv/predef-37.c | 48 ++
>  6 files changed, 113 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-37.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-38.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-36.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-37.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index fb76017ffbc..88204393fde 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -162,6 +162,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
>{"zfa", "f"},
>
>{"zvfbfmin", "zve32f"},
> +  {"zvfbfwma", "zvfbfmin"},
> +  {"zvfbfwma", "zfbfmin"},
>{"zvfhmin", "zve32f"},
>{"zvfh", "zve32f"},
>{"zvfh", "zfhmin"},
> @@ -336,6 +338,7 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>{"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
>{"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
>{"zvfbfmin",  ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zvfbfwma",  ISA_SPEC_CLASS_NONE, 1, 0},
>{"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
>{"zvfh",  ISA_SPEC_CLASS_NONE, 1, 0},
>
> @@ -1667,6 +1670,7 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"zve64f",   _options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_32},
>{"zve64d",   _options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_64},
>{"zvfbfmin", _options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_BF_16},
> +  {"zvfbfwma", _options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_BF_16},
>{"zvfhmin",  _options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_16},
>{"zvfh", _options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_16},
>
> @@ -1704,6 +1708,7 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"zfhmin",_options::x_riscv_zf_subext, MASK_ZFHMIN},
>{"zfh",   _options::x_riscv_zf_subext, MASK_ZFH},
>{"zvfbfmin",  _options::x_riscv_zf_subext, MASK_ZVFBFMIN},
> +  {"zvfbfwma",  _options::x_riscv_zf_subext, MASK_ZVFBFWMA},
>{"zvfhmin",   _options::x_riscv_zf_subext, MASK_ZVFHMIN},
>{"zvfh",  _options::x_riscv_zf_subext, MASK_ZVFH},
>
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 1252834aec5..d209ac896fd 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -401,6 +401,8 @@ Mask(ZFH) Var(riscv_zf_subext)
>
>  Mask(ZVFBFMIN) Var(riscv_zf_subext)
>
> +Mask(ZVFBFWMA) Var(riscv_zf_subext)
> +
>  Mask(ZVFHMIN) Var(riscv_zf_subext)
>
>  Mask(ZVFH)Var(riscv_zf_subext)
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-37.c 
> 

Re: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar

[Kito Cheng]

LGTM as well :)

On Sat, May 11, 2024 at 3:58 PM juzhe.zh...@rivai.ai
 wrote:
>
> LGTM from my side. Wait for kito chime in.
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: pan2.li
> Date: 2024-05-11 15:54
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; Pan Li
> Subject: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 
> scalar
> From: Pan Li 
>
> For the vfw vx format RVV intrinsic, the scalar type _Float16 also
> requires the zvfh extension.  Unfortunately,  we only check the
> vector tree type and miss the scalar _Float16 type checking.  For
> example:
>
> vfloat32mf2_t test_vfwsub_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1, size_t 
> vl)
> {
>   return __riscv_vfwsub_wf_f32mf2(vs2, rs1, vl);
> }
>
> It should report some error message like zvfh extension is required
> instead of ICE for unreg insn.
>
> This patch would like to make up such kind of validation for _Float16
> in the RVV intrinsic API.  It will report some error like below when
> there is no zvfh enabled.
>
> error: built-in function '__riscv_vfwsub_wf_f32mf2(vs2,  rs1,  vl)'
>   requires the zvfhmin or zvfh ISA extension
>
> PR target/114988
>
> Passed the rv64gcv fully regression tests, included c/c++/fortran.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc
> (validate_instance_type_required_extensions): New func impl to
> validate the intrinisc func type ops.
> (expand_builtin): Validate instance type before expand.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr114988-1.c: New test.
> * gcc.target/riscv/rvv/base/pr114988-2.c: New test.
>
> Signed-off-by: Pan Li 
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 51 +++
> .../gcc.target/riscv/rvv/base/pr114988-1.c|  9 
> .../gcc.target/riscv/rvv/base/pr114988-2.c|  9 
> 3 files changed, 69 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-2.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc 
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index 192a6c230d1..3fdb4400d70 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -4632,6 +4632,54 @@ gimple_fold_builtin (unsigned int code, 
> gimple_stmt_iterator *gsi, gcall *stmt)
>return gimple_folder (rfn.instance, rfn.decl, gsi, stmt).fold ();
> }
> +static bool
> +validate_instance_type_required_extensions (const rvv_type_info type,
> + tree exp)
> +{
> +  uint64_t exts = type.required_extensions;
> +
> +  if ((exts & RVV_REQUIRE_ELEN_FP_16) &&
> +!TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags))
> +{
> +  error_at (EXPR_LOCATION (exp),
> + "built-in function %qE requires the "
> + "zvfhmin or zvfh ISA extension",
> + exp);
> +  return false;
> +}
> +
> +  if ((exts & RVV_REQUIRE_ELEN_FP_32) &&
> +!TARGET_VECTOR_ELEN_FP_32_P (riscv_vector_elen_flags))
> +{
> +  error_at (EXPR_LOCATION (exp),
> + "built-in function %qE requires the "
> + "zve32f, zve64f, zve64d or v ISA extension",
> + exp);
> +  return false;
> +}
> +
> +  if ((exts & RVV_REQUIRE_ELEN_FP_64) &&
> +!TARGET_VECTOR_ELEN_FP_64_P (riscv_vector_elen_flags))
> +{
> +  error_at (EXPR_LOCATION (exp),
> + "built-in function %qE requires the zve64d or v ISA extension",
> + exp);
> +  return false;
> +}
> +
> +  if ((exts & RVV_REQUIRE_ELEN_64) &&
> +!TARGET_VECTOR_ELEN_64_P (riscv_vector_elen_flags))
> +{
> +  error_at (EXPR_LOCATION (exp),
> + "built-in function %qE requires the "
> + "zve64x, zve64f, zve64d or v ISA extension",
> + exp);
> +  return false;
> +}
> +
> +  return true;
> +}
> +
> /* Expand a call to the RVV function with subcode CODE.  EXP is the call
> expression and TARGET is the preferred location for the result.
> Return the value of the lhs.  */
> @@ -4649,6 +4697,9 @@ expand_builtin (unsigned int code, tree exp, rtx target)
>return target;
>  }
> +  if (!validate_instance_type_required_extensions (rfn.instance.type, exp))
> +return target;
> +
>return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
> }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c
> new file mode 100644
> index 000..b8474804c88
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +vfloat32mf2_t test_vfwsub_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1, size_t 
> vl)
> +{
> +  return __riscv_vfwsub_wf_f32mf2(vs2, rs1, vl); /* { dg-error {built-in 
> function '__riscv_vfwsub_wf_f32mf2\(vs2,  rs1,  vl\)' requires the zvfhmin or 
> zvfh ISA extension} } */
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-2.c 
> 

[committed] RISC-V: Fix typos in code or comment [NFC]

[Kito Cheng]

Just found some typo when fixing bugs and then use aspell to find few
more typos, this patch didn't do anything other than fix typo.

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc: Fix typos in comments.
(get_all_predecessors): Ditto.
(pre_vsetvl::m_unknow_info): Rename to...
(pre_vsetvl::m_unknown_info): this.
(pre_vsetvl::compute_vsetvl_def_data): Rename m_unknow_info to
m_unknown_info.
(pre_vsetvl::cleaup): Rename to...
(pre_vsetvl::cleanup): this.
(pre_vsetvl::compute_vsetvl_def_data): Fix typos.
(pass_vsetvl::lazy_vsetvl): Update function name and fix typos.
* config/riscv/riscv.cc: Fix typos in comments.
(struct machine_function): Fix typo in comments.
(riscv_valid_lo_sum_p): Ditto.
(riscv_force_address): Ditto.
(riscv_immediate_operand_p): Ditto.
(riscv_in_small_data_p): Ditto.
(riscv_first_stack_step): Ditto.
(riscv_expand_prologue): Ditto.
(riscv_convert_vector_chunks): Ditto.
(riscv_override_options_internal): Ditto.
(get_common_costs): Ditto.
---
 gcc/config/riscv/riscv-vsetvl.cc | 64 
 gcc/config/riscv/riscv.cc| 36 +-
 2 files changed, 50 insertions(+), 50 deletions(-)

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 48ce757a6ee..bbea2b5fd4f 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -95,7 +95,7 @@ using namespace riscv_vector;
It's a bit different from bitmap_union_of_preds in cfganal.cc. This function
takes into account the case where pred is ENTRY basic block. The main reason
for this difference is to make it easier to insert some special value into
-   the ENTRY base block. For example, vsetvl_info with a status of UNKNOW.  */
+   the ENTRY base block. For example, vsetvl_info with a status of UNKNOWN.  */
 static void
 bitmap_union_of_preds_with_entry (sbitmap dst, sbitmap *src, basic_block b)
 {
@@ -126,9 +126,9 @@ bitmap_union_of_preds_with_entry (sbitmap dst, sbitmap 
*src, basic_block b)
   }
 }
 
-/* Compute the reaching defintion in and out based on the gen and KILL
-   informations in each Base Blocks.
-   This function references the compute_avaiable implementation in lcm.cc  */
+/* Compute the reaching definition in and out based on the gen and KILL
+   information's in each Base Blocks.
+   This function references the compute_available implementation in lcm.cc  */
 static void
 compute_reaching_defintion (sbitmap *gen, sbitmap *kill, sbitmap *in,
sbitmap *out)
@@ -719,7 +719,7 @@ get_all_predecessors (basic_block bb)
require SEW and LMUL to be fixed.
Therefore, if the former RVV instruction needs DEMAND_RATIO_P and the latter
instruction needs DEMAND_SEW_LMUL_P and its SEW/LMUL is the same as that of
-   the former instruction, then we can make the minimu demand of the former
+   the former instruction, then we can make the minimum demand of the former
instruction strict to DEMAND_SEW_LMUL_P, and its required SEW and LMUL are
the SEW and LMUL of the latter instruction, and the vsetvl instruction
generated according to the new demand can also be used for the latter
@@ -741,7 +741,7 @@ enum demand_flags : unsigned
 /* We split the demand information into three parts. They are sew and lmul
related (sew_lmul_demand_type), tail and mask policy related
(policy_demand_type) and avl related (avl_demand_type). Then we define three
-   interfaces avaiable_with, compatible_p and merge. avaiable_with is
+   interfaces available_p, compatible_p and merge. available_p is
used to determine whether the two vsetvl infos prev_info and next_info are
available or not. If prev_info is available for next_info, it means that the
RVV insn corresponding to next_info on the path from prev_info to next_info
@@ -1361,17 +1361,17 @@ public:
 
 /* Demand system is the RVV-based VSETVL info analysis tools wrapper.
It defines compatible rules for SEW/LMUL, POLICY and AVL.
-   Also, it provides 3 iterfaces avaiable_p, compatible_p and
+   Also, it provides 3 interfaces available_p, compatible_p and
merge for the VSETVL PASS analysis and optimization.
 
- - avaiable_p: Determine whether the next info can get the
-   avaiable VSETVL status from previous info.
+ - available_p: Determine whether the next info can get the
+   available VSETVL status from previous info.
e.g. bb 2 (demand SEW = 32, LMUL = M2) -> bb 3 (demand RATIO = 16).
Since bb 2 demand info (SEW/LMUL = 32/2 = 16) satisfies the bb 3
demand, the VSETVL instruction in bb 3 can be elided.
-   avaiable_p (previous, next) is true in such situation.
+   available_p (previous, next) is true in such situation.
  - compatible_p: Determine whether prev_info is compatible with next_info
-   so that we can 

Re: [PATCH][GCC 13] RISC-V: Fix vsetvli local eliminate [PR114747]

[Kito Cheng]

Committed to gcc 13 branch, thanks:)

On Tue, May 7, 2024 at 9:20 AM juzhe.zh...@rivai.ai
 wrote:
>
> LGTM。
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2024-05-07 09:17
> To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong; pan2.li
> CC: Kito Cheng
> Subject: [PATCH][GCC 13] RISC-V: Fix vsetvli local eliminate [PR114747]
> vsetvli local eliminate is only consider the current demand instead of
> full demand, and it will use that incomplete info to remove vsetvli.
>
> Give following example from PR114747:
>
> vsetvli a5,a1,e8,m4,ta,mu   # 57, ratio=2, sew=8, lmul=4
> vsetvli zero,a5,e16,m8,ta,ma# 58, ratio=2, sew=16, lmul=8
> vle8.v  v8,0(a0)# 13, demand ratio=2
> vzext.vf2   v24,v8  # 14, demand sew=16 and lmul=8
>
> Insn #58 will removed because #57 has satisfied demand of #13, but it's
> not consider #14.
>
> It should doing more demand analyze, but this bug only present in GCC 13
> branch, and we should not change too much on this release branch, so the best
> way is make the check more conservative - remove only if the target
> vsetvl_discard_result having same SEW and LMUL as the source vsetvli.
>
> gcc/ChangeLog:
>
> PR target/114747
> * config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn):
> Check target vsetvl_discard_result and source vsetvli has same
> SEW and LMUL.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/pr114747.c: New.
> ---
> gcc/config/riscv/riscv-vsetvl.cc   | 10 ++
> .../gcc.target/riscv/rvv/vsetvl/pr114747.c | 18 ++
> 2 files changed, 28 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 587c6975a70..e6606b1e4de 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1106,6 +1106,16 @@ local_eliminate_vsetvl_insn (const vector_insn_info 
> )
>   if (!new_info.skip_avl_compatible_p (dem))
> return;
> +   /* Be more conservative here since we don't really get full
> + demand info for following instructions, also that instruction
> + isn't exist in RTL-SSA yet so we need parse that by low level
> + API rather than vector_insn_info::parse_insn, see PR114747.  */
> +   unsigned last_vsetvli_sew = ::get_sew (PREV_INSN (i->rtl ()));
> +   unsigned last_vsetvli_lmul = ::get_vlmul (PREV_INSN (i->rtl ()));
> +   if (new_info.get_sew() != last_vsetvli_sew ||
> +   new_info.get_vlmul() != last_vsetvli_lmul)
> + return;
> +
>   new_info.set_avl_info (dem.get_avl_info ());
>   new_info = dem.merge (new_info, LOCAL_MERGE);
>   change_vsetvl_insn (insn, new_info);
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c
> new file mode 100644
> index 000..c478405e8d6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize 
> -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +typedef unsigned short char16_t;
> +
> +size_t convert_latin1_to_utf16le(const char *src, size_t len, char16_t *dst) 
> {
> +  char16_t *beg = dst;
> +  for (size_t vl; len > 0; len -= vl, src += vl, dst += vl) {
> +vl = __riscv_vsetvl_e8m4(len);
> +vuint8m4_t v = __riscv_vle8_v_u8m4((uint8_t*)src, vl);
> +__riscv_vse16_v_u16m8((uint16_t*)dst, __riscv_vzext_vf2_u16m8(v, vl), 
> vl);
> +  }
> +  return dst - beg;
> +}
> +
> +/* { dg-final { scan-assembler 
> {vsetvli\s+[a-z0-9]+,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} } } */
> --
> 2.34.1
>
>

[PATCH][GCC 13] RISC-V: Fix vsetvli local eliminate [PR114747]

[Kito Cheng]

vsetvli local eliminate is only consider the current demand instead of
full demand, and it will use that incomplete info to remove vsetvli.

Give following example from PR114747:

vsetvli a5,a1,e8,m4,ta,mu   # 57, ratio=2, sew=8, lmul=4
vsetvli zero,a5,e16,m8,ta,ma# 58, ratio=2, sew=16, lmul=8
vle8.v  v8,0(a0)# 13, demand ratio=2
vzext.vf2   v24,v8  # 14, demand sew=16 and lmul=8

Insn #58 will removed because #57 has satisfied demand of #13, but it's
not consider #14.

It should doing more demand analyze, but this bug only present in GCC 13
branch, and we should not change too much on this release branch, so the best
way is make the check more conservative - remove only if the target
vsetvl_discard_result having same SEW and LMUL as the source vsetvli.

gcc/ChangeLog:

PR target/114747
* config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn):
Check target vsetvl_discard_result and source vsetvli has same
SEW and LMUL.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr114747.c: New.
---
 gcc/config/riscv/riscv-vsetvl.cc   | 10 ++
 .../gcc.target/riscv/rvv/vsetvl/pr114747.c | 18 ++
 2 files changed, 28 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 587c6975a70..e6606b1e4de 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1106,6 +1106,16 @@ local_eliminate_vsetvl_insn (const vector_insn_info )
  if (!new_info.skip_avl_compatible_p (dem))
return;
 
+ /* Be more conservative here since we don't really get full
+demand info for following instructions, also that instruction
+isn't exist in RTL-SSA yet so we need parse that by low level
+API rather than vector_insn_info::parse_insn, see PR114747.  */
+ unsigned last_vsetvli_sew = ::get_sew (PREV_INSN (i->rtl ()));
+ unsigned last_vsetvli_lmul = ::get_vlmul (PREV_INSN (i->rtl ()));
+ if (new_info.get_sew() != last_vsetvli_sew ||
+ new_info.get_vlmul() != last_vsetvli_lmul)
+   return;
+
  new_info.set_avl_info (dem.get_avl_info ());
  new_info = dem.merge (new_info, LOCAL_MERGE);
  change_vsetvl_insn (insn, new_info);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c
new file mode 100644
index 000..c478405e8d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize 
-fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+typedef unsigned short char16_t;
+
+size_t convert_latin1_to_utf16le(const char *src, size_t len, char16_t *dst) {
+  char16_t *beg = dst;
+  for (size_t vl; len > 0; len -= vl, src += vl, dst += vl) {
+vl = __riscv_vsetvl_e8m4(len);
+vuint8m4_t v = __riscv_vle8_v_u8m4((uint8_t*)src, vl);
+__riscv_vse16_v_u16m8((uint16_t*)dst, __riscv_vzext_vf2_u16m8(v, vl), vl);
+  }
+  return dst - beg;
+}
+
+/* { dg-final { scan-assembler 
{vsetvli\s+[a-z0-9]+,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} } } */
-- 
2.34.1

Re: [PATCH v2] RISC-V: Fix ICE for legitimize move on subreg const_poly_int [PR114885]

[Kito Cheng]

Hi Pan:

LGTM.

Hi Jakub:

Is this OK for GCC 14 branch? it's fix ICE on valid code, thanks :)

On Mon, Apr 29, 2024 at 3:40 PM  wrote:
>
> From: Pan Li 
>
> When we build with isl, there will be a ICE for graphite in both
> the c/c++ and fortran.  The legitimize move cannot take care of
> below rtl.
>
> (set (subreg:DI (reg:TI 237) 8) (subreg:DI (const_poly_int:TI [4, 2]) 8))
>
> Then we will have ice similar to below:
>
> internal compiler error: in extract_insn, at recog.cc:2812.
>
> This patch would like to take care of the above rtl.  Given the value of
> const_poly_int can hardly excceed the max of int64,  we can simply
> consider the highest 8 bytes of TImode is zero and then set the dest
> to (const_int 0).
>
> The below test cases are fixed by this PATCH.
>
> C:
> FAIL: gcc.dg/graphite/pr111878.c (internal compiler error: in
> extract_insn, at recog.cc:2812)
> FAIL: gcc.dg/graphite/pr111878.c (test for excess errors)
>
> Fortran:
> FAIL: gfortran.dg/graphite/vect-pr40979.f90   -O  (internal compiler
> error: in extract_insn, at recog.cc:2812)
> FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -fomit-frame-pointer
> -funroll-loops -fpeel-loops -ftracer -finline-functions  (internal
> compiler error: in extract_insn, at recog.cc:2812)
> FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -g  (test for excess
> errors)
> FAIL: gfortran.dg/graphite/pr14741.f90   -O  (test for excess errors)
> FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -fomit-frame-pointer
> -funroll-loops -fpeel-loops -ftracer -finline-functions  (test for
> excess errors)
> FAIL: gfortran.dg/graphite/vect-pr40979.f90   -O  (test for excess
> errors)
> FAIL: gfortran.dg/graphite/id-27.f90   -O  (internal compiler error: in
> extract_insn, at recog.cc:2812)
> FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -g  (internal compiler
> error: in extract_insn, at recog.cc:2812)
> FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -g  (test for excess
> errors)
> FAIL: gfortran.dg/graphite/id-27.f90   -O  (test for excess errors)
> FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -fomit-frame-pointer
> -funroll-loops -fpeel-loops -ftracer -finline-functions  (test for
> excess errors)
> FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -fomit-frame-pointer
> -funroll-loops -fpeel-loops -ftracer -finline-functions  (internal
> compiler error: in extract_insn, at recog.cc:2812)
> FAIL: gfortran.dg/graphite/pr14741.f90   -O  (internal compiler error:
> in extract_insn, at recog.cc:2812)
> FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -g  (internal compiler
> error: in extract_insn, at recog.cc:2812)
>
> The below test suites are passed for this patch:
> * The rv64gcv fully regression test.
> * The rv64gc fully regression test.
>
> Try to write some RTL code for test but not works well according to
> existing test cases.  Thus, take above as test cases.  Please note
> graphite require the gcc build with isl.
>
> PR target/114885
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_subreg_const_poly_move): New
> func impl to take care of (const_int_poly:TI 8).
> (riscv_legitimize_move): Handle subreg is const_int_poly,
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv.cc | 44 +++
>  1 file changed, 44 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 0519e0679ed..0f62b295b96 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2786,6 +2786,45 @@ riscv_v_adjust_scalable_frame (rtx target, poly_int64 
> offset, bool epilogue)
>REG_NOTES (insn) = dwarf;
>  }
>
> +/* Take care below subreg const_poly_int move:
> +
> +   1. (set (subreg:DI (reg:TI 237) 8)
> +  (subreg:DI (const_poly_int:TI [4, 2]) 8))
> +  =>
> +  (set (subreg:DI (reg:TI 237) 8)
> +  (const_int 0)) */
> +
> +static bool
> +riscv_legitimize_subreg_const_poly_move (machine_mode mode, rtx dest, rtx 
> src)
> +{
> +  gcc_assert (SUBREG_P (src) && CONST_POLY_INT_P (SUBREG_REG (src)));
> +  gcc_assert (SUBREG_BYTE (src).is_constant ());
> +
> +  int byte_offset = SUBREG_BYTE (src).to_constant ();
> +  rtx const_poly = SUBREG_REG (src);
> +  machine_mode subreg_mode = GET_MODE (const_poly);
> +
> +  if (subreg_mode != TImode) /* Only TImode is needed for now.  */
> +return false;
> +
> +  if (byte_offset == 8)
> +{
> +  /* The const_poly_int cannot exceed int64, just set zero here.  */
> +  emit_move_insn (dest, CONST0_RTX (mode));
> +  return true;
> +}
> +
> +  /* The below transform will be covered in somewhere else.
> + Thus, ignore this here.
> + (set (subreg:DI (reg:TI 237) 0)
> + (subreg:DI (const_poly_int:TI [4, 2]) 0))
> + =>
> + (set (subreg:DI (reg:TI 237) 0)
> + (const_poly_int:DI [4, 2])) */
> +
> +  return false;
> +}
> +
>  /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
> sequence that is valid.  */
>
> @@ -2839,6 +2878,11 @@ 

Re: [PATCH v1] RISC-V: Fix ICE for legitimize move on subreg const_poly_move

[Kito Cheng]

> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 0519e0679ed..bad23ea487f 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2786,6 +2786,44 @@ riscv_v_adjust_scalable_frame (rtx target, poly_int64 
> offset, bool epilogue)
>REG_NOTES (insn) = dwarf;
> }
> +/* Take care below subreg const_poly_int move:
> +
> +   1. (set (subreg:DI (reg:TI 237) 8)
> +(subreg:DI (const_poly_int:TI [4, 2]) 8))
> +  =>
> +  (set (subreg:DI (reg:TI 237) 8)
> +(const_int 0)) */
> +
> +static bool
> +riscv_legitimize_subreg_const_poly_move (machine_mode mode, rtx dest, rtx 
> src)
> +{
> +  gcc_assert (SUBREG_P (src) && CONST_POLY_INT_P (SUBREG_REG (src)));
> +  gcc_assert (SUBREG_BYTE (src).is_constant ());
> +
> +  int byte_offset = SUBREG_BYTE (src).to_constant ();
> +  rtx const_poly = SUBREG_REG (src);
> +  machine_mode subreg_mode = GET_MODE (const_poly);
> +
> +  if (subreg_mode != TImode) /* Only TImode is needed for now.  */
> +return false;
> +
> +  if (byte_offset == 8)
> +{ /* The const_poly_int cannot exceed int64, just set zero here.  */

{
 /* The const_poly_int cannot exceed int64, just set zero here.  */

New line for the comment.

> +  emit_move_insn (dest, CONST0_RTX (mode));
> +  return true;
> +}
> +
> +  /* The below transform will be covered in somewhere else.
> + Thus, ignore this here.
> +   1. (set (subreg:DI (reg:TI 237) 0)
> +(subreg:DI (const_poly_int:TI [4, 2]) 0))
> +  =>
> +  (set (subreg:DI (reg:TI 237) 0)
> +(const_poly_int:DI [4, 2])) */
> +
> +  return false;
> +}
> +
> /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
> sequence that is valid.  */
> @@ -2839,6 +2877,11 @@ riscv_legitimize_move (machine_mode mode, rtx dest, 
> rtx src)
> }
>return true;
>  }
> +
> +  if (SUBREG_P (src) && CONST_POLY_INT_P (SUBREG_REG (src))
> +&& riscv_legitimize_subreg_const_poly_move (mode, dest, src))
> +return true;
> +
>/* Expand
> (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
>   Expand this data movement instead of simply forbid it since
> --
> 2.34.1
>
>

Re: [PATCH] RISC-V: Fix parsing of Zic* extensions

[Kito Cheng]

OK for trunk, and my understanding is that flag isn't really used in
code gen yet, so it's not necessary to port to GCC 14 branch?

On Mon, Apr 29, 2024 at 7:05 AM Christoph Müllner
 wrote:
>
> The extension parsing table entries for a range of Zic* extensions
> does not match the mask definition in riscv.opt.
> This results in broken TARGET_ZIC* macros, because the values of
> riscv_zi_subext and riscv_zicmo_subext are set wrong.
>
> This patch fixes this by moving Zic64b into riscv_zicmo_subext
> and all other affected Zic* extensions to riscv_zi_subext.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc: Move ziccamoa, ziccif,
> zicclsm, and ziccrse into riscv_zi_subext.
> * config/riscv/riscv.opt: Define MASK_ZIC64B for
> riscv_ziccmo_subext.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/common/config/riscv/riscv-common.cc | 8 
>  gcc/config/riscv/riscv.opt  | 4 ++--
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 43b7549e3ec..8cc0e727737 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -1638,15 +1638,15 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>
>{"zihintntl", _options::x_riscv_zi_subext, MASK_ZIHINTNTL},
>{"zihintpause", _options::x_riscv_zi_subext, MASK_ZIHINTPAUSE},
> +  {"ziccamoa", _options::x_riscv_zi_subext, MASK_ZICCAMOA},
> +  {"ziccif", _options::x_riscv_zi_subext, MASK_ZICCIF},
> +  {"zicclsm", _options::x_riscv_zi_subext, MASK_ZICCLSM},
> +  {"ziccrse", _options::x_riscv_zi_subext, MASK_ZICCRSE},
>
>{"zicboz", _options::x_riscv_zicmo_subext, MASK_ZICBOZ},
>{"zicbom", _options::x_riscv_zicmo_subext, MASK_ZICBOM},
>{"zicbop", _options::x_riscv_zicmo_subext, MASK_ZICBOP},
>{"zic64b", _options::x_riscv_zicmo_subext, MASK_ZIC64B},
> -  {"ziccamoa", _options::x_riscv_zicmo_subext, MASK_ZICCAMOA},
> -  {"ziccif", _options::x_riscv_zicmo_subext, MASK_ZICCIF},
> -  {"zicclsm", _options::x_riscv_zicmo_subext, MASK_ZICCLSM},
> -  {"ziccrse", _options::x_riscv_zicmo_subext, MASK_ZICCRSE},
>
>{"zve32x",   _options::x_target_flags, MASK_VECTOR},
>{"zve32f",   _options::x_target_flags, MASK_VECTOR},
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index b14888e9816..ee824756381 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -237,8 +237,6 @@ Mask(ZIHINTPAUSE) Var(riscv_zi_subext)
>
>  Mask(ZICOND)  Var(riscv_zi_subext)
>
> -Mask(ZIC64B)  Var(riscv_zi_subext)
> -
>  Mask(ZICCAMOA)Var(riscv_zi_subext)
>
>  Mask(ZICCIF)  Var(riscv_zi_subext)
> @@ -390,6 +388,8 @@ Mask(ZICBOM) Var(riscv_zicmo_subext)
>
>  Mask(ZICBOP) Var(riscv_zicmo_subext)
>
> +Mask(ZIC64B) Var(riscv_zicmo_subext)
> +
>  TargetVariable
>  int riscv_zf_subext
>
> --
> 2.44.0
>

Re: [PATCH] RISC-V: Add -X to link spec

[Kito Cheng]

LGTM :)

Fangrui Song  於 2024年4月23日 週二 12:27 寫道：

> From: Fangrui Song 
>
> --discard-locals (-X) instructs the linker to remove local .L* symbols,
> which occur a lot due to label differences for linker relaxation. The
> arm port has a similar need and passes -X to ld.
>
> In contrast, the RISC-V port does not pass -X to ld and rely on the
> default --discard-locals in GNU ld's riscv port. The arm way is more
> conventional (compiler driver instead of the linker customizes the
> default behavior) and works with lld.
> ---
>  gcc/config/riscv/elf.h | 1 +
>  gcc/config/riscv/freebsd.h | 1 +
>  gcc/config/riscv/linux.h   | 1 +
>  3 files changed, 3 insertions(+)
>
> diff --git a/gcc/config/riscv/elf.h b/gcc/config/riscv/elf.h
> index f533764d9f8..c97f13c0cca 100644
> --- a/gcc/config/riscv/elf.h
> +++ b/gcc/config/riscv/elf.h
> @@ -20,6 +20,7 @@ along with GCC; see the file COPYING3.  If not see
>  #define LINK_SPEC "\
>  -melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv \
>  %{mno-relax:--no-relax} \
> +-X \
>  %{mbig-endian:-EB} \
>  %{mlittle-endian:-EL} \
>  %{shared}"
> diff --git a/gcc/config/riscv/freebsd.h b/gcc/config/riscv/freebsd.h
> index bd08a985285..5dd4d51c42b 100644
> --- a/gcc/config/riscv/freebsd.h
> +++ b/gcc/config/riscv/freebsd.h
> @@ -44,6 +44,7 @@ along with GCC; see the file COPYING3.  If not see
>%{p:%nconsider using `-pg' instead of `-p' with gprof (1)}   \
>%{v:-V}  \
>%{assert*} %{R*} %{rpath*} %{defsym*}\
> +  -X   \
>%{mbig-endian:-EB}   \
>%{mlittle-endian:-EL}\
>%{shared:-Bshareable %{h*} %{soname*}}   \
> diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
> index 15851f653bc..3c356227134 100644
> --- a/gcc/config/riscv/linux.h
> +++ b/gcc/config/riscv/linux.h
> @@ -50,6 +50,7 @@ along with GCC; see the file COPYING3.  If not see
>  #define LINK_SPEC "\
>  -melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \
>  %{mno-relax:--no-relax} \
> +-X \
>  %{mbig-endian:-EB} \
>  %{mlittle-endian:-EL} \
>  %{shared} \
> --
> 2.44.0.769.g3c40516874-goog
>
>

Re: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll

[Kito Cheng]

LGTM, thanks :)

On Thu, Apr 25, 2024 at 9:26 AM juzhe.zh...@rivai.ai
 wrote:
>
> lgtm
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: pan2.li
> Date: 2024-04-25 09:25
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
> Subject: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
> From: Pan Li 
>
> We missed the existing early clobber for the dest operand of vwsll
> pattern when resolve the conflict of revert register overlap.  Thus
> add it back to the pattern.  Unfortunately, we have no test to cover
> this part and will improve this after GCC-15 open.
>
> The below tests are passed for this patch:
> * The rv64gcv fully regression test with isl build.
>
> gcc/ChangeLog:
>
> * config/riscv/vector-crypto.md: Add early clobber to the
> dest operand of vwsll.
>
> Signed-off-by: Pan Li 
> ---
> gcc/config/riscv/vector-crypto.md | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/vector-crypto.md 
> b/gcc/config/riscv/vector-crypto.md
> index 8a4888a7653..e474ddf5da7 100755
> --- a/gcc/config/riscv/vector-crypto.md
> +++ b/gcc/config/riscv/vector-crypto.md
> @@ -303,7 +303,7 @@ (define_insn "@pred_vwsll"
> (set_attr "mode" "")])
> (define_insn "@pred_vwsll_scalar"
> -  [(set (match_operand:VWEXTI 0 "register_operand"  "=vr, 
> vr")
> +  [(set (match_operand:VWEXTI 0 "register_operand"  "=,
> ")
>   (if_then_else:VWEXTI
> (unspec:
>   [(match_operand: 1 "vector_mask_operand"   "vmWc1, 
> vmWc1")
> --
> 2.34.1
>
>

Re: [PATCH v1] RISC-V: Add xfail test case for highpart register overlap of vwcvt

[Kito Cheng]

LGTM

juzhe.zh...@rivai.ai  於 2024年4月25日 週四 09:26 寫道：

> lgtm
>
> --
> juzhe.zh...@rivai.ai
>
>
> *From:* pan2.li 
> *Date:* 2024-04-25 09:25
> *To:* gcc-patches 
> *CC:* juzhe.zhong ; kito.cheng
> ; rdapp.gcc ; Pan Li
> 
> *Subject:* [PATCH v1] RISC-V: Add xfail test case for highpart register
> overlap of vwcvt
> From: Pan Li 
>
> We reverted below patch for register group overlap, add the related
> insn test and mark it as xfail.  And we will remove the xfail
> after we support the register overlap in GCC-15.
>
> bdad036da32 RISC-V: Support highpart register overlap for vwcvt
>
> The below test suites are passed for this patch
> * The rv64gcv fully regression test with isl build.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr112431-1.c: New test.
> * gcc.target/riscv/rvv/base/pr112431-2.c: New test.
> * gcc.target/riscv/rvv/base/pr112431-3.c: New test.
>
> Signed-off-by: Pan Li 
> ---
> .../gcc.target/riscv/rvv/base/pr112431-1.c| 104 ++
> .../gcc.target/riscv/rvv/base/pr112431-2.c|  68 
> .../gcc.target/riscv/rvv/base/pr112431-3.c|  51 +
> 3 files changed, 223 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
> new file mode 100644
> index 000..6f9c6f7bd8c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
> @@ -0,0 +1,104 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +size_t __attribute__ ((noinline))
> +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,
> +   size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9,
> +   size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14,
> +   size_t sum15)
> +{
> +  return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 +
> sum9
> + + sum10 + sum11 + sum12 + sum13 + sum14 + sum15;
> +}
> +
> +size_t
> +foo (char const *buf, size_t len)
> +{
> +  size_t sum = 0;
> +  size_t vl = __riscv_vsetvlmax_e8m8 ();
> +  size_t step = vl * 4;
> +  const char *it = buf, *end = buf + len;
> +  for (; it + step <= end;)
> +{
> +  vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v8 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v9 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v10 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v11 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v12 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v13 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v14 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v15 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +
> +  asm volatile("nop" ::: "memory");
> +  vint16m2_t vw0 = __riscv_vwcvt_x_x_v_i16m2 (v0, vl);
> +  vint16m2_t vw1 = __riscv_vwcvt_x_x_v_i16m2 (v1, vl);
> +  vint16m2_t vw2 = __riscv_vwcvt_x_x_v_i16m2 (v2, vl);
> +  vint16m2_t vw3 = __riscv_vwcvt_x_x_v_i16m2 (v3, vl);
> +  vint16m2_t vw4 = __riscv_vwcvt_x_x_v_i16m2 (v4, vl);
> +  vint16m2_t vw5 = __riscv_vwcvt_x_x_v_i16m2 (v5, vl);
> +  vint16m2_t vw6 = __riscv_vwcvt_x_x_v_i16m2 (v6, vl);
> +  vint16m2_t vw7 = __riscv_vwcvt_x_x_v_i16m2 (v7, vl);
> +  vint16m2_t vw8 = __riscv_vwcvt_x_x_v_i16m2 (v8, vl);
> +  vint16m2_t vw9 = __riscv_vwcvt_x_x_v_i16m2 (v9, vl);
> +  vint16m2_t vw10 = __riscv_vwcvt_x_x_v_i16m2 (v10, vl);
> +  vint16m2_t vw11 = __riscv_vwcvt_x_x_v_i16m2 (v11, vl);
> +  vint16m2_t vw12 = __riscv_vwcvt_x_x_v_i16m2 (v12, vl);
> +  vint16m2_t vw13 = __riscv_vwcvt_x_x_v_i16m2 (v13, vl);
> +  vint16m2_t vw14 = __riscv_vwcvt_x_x_v_i16m2 (v14, vl);
> +  vint16m2_t vw15 = __riscv_vwcvt_x_x_v_i16m2 (v15, vl);
> +
> +  asm volatile("nop" ::: "memory");
> +  size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0);
> +  size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1);

Re: [PATCH][GCC 13] RISC-V: Fix recursive vsetvli checking [PR114172]

[Kito Cheng]

thanks, committed :)

On Wed, Apr 24, 2024 at 6:12 PM juzhe.zh...@rivai.ai
 wrote:
>
> lgtm.
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2024-04-24 18:09
> To: gcc-patches; kito.cheng; rdapp; juzhe.zhong
> CC: Kito Cheng
> Subject: [PATCH][GCC 13] RISC-V: Fix recursive vsetvli checking [PR114172]
> extract_single_source will recursive checking the sources to
> make sure if it's single source, however it may cause infinite
> recursive when the source is come from itself, so it should just skip
> first source to prevent that.
>
> NOTE: This logic has existing on trunk/GCC 14, but it included in a big
> vsetvli improvement patch, which is not backport to GCC 13.
>
> ```
>
> void saxpy_rvv_m8(float *y, long vl)
> {
> for (;;)
> {
> vl = __riscv_vsetvl_e32m8(vl); //ICE
> vfloat32m8_t y_vec;
> __riscv_vse32_v_f32m8(y, y_vec, vl);
> }
> }
> ```
>
> gcc/ChangeLog:
>
> PR target/114172
> * gcc/config/riscv/riscv-vsetvl.cc (extract_single_source):
> Skip first set.
>
> gcc/testsuite/ChangeLog:
>
> PR target/114172
> * gcc.target/riscv/rvv/vsetvl/pr114172.c: New.
> ---
> gcc/config/riscv/riscv-vsetvl.cc   |  4 
> .../gcc.target/riscv/rvv/vsetvl/pr114172.c | 14 ++
> 2 files changed, 18 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 9dca2ce709d..36d2e6e6f20 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1196,6 +1196,10 @@ extract_single_source (set_info *set)
>  return nullptr;
>for (const set_info *set : sets)
>  {
> +  /* Skip first set, this can prevent us run into infinite recursive
> + checking if first set is come from itself.  */
> +  if (set == *sets.begin ())
> + continue;
>/* If there is a head or end insn, we conservative return
> NULL so that VSETVL PASS will insert vsetvl directly.  */
>if (set->insn ()->is_artificial ())
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c
> new file mode 100644
> index 000..ed1494666d6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -fno-tree-vectorize" } */
> +
> +#include "riscv_vector.h"
> +
> +void e(long, vfloat32m4_t);
> +
> +void b(long c) {
> +  for (;;) {
> +c = __riscv_vsetvl_e32m4(c);
> +vfloat32m4_t d;
> +e(c, d);
> +  }
> +}
> --
> 2.34.1
>
>

Re: [PATCH v1] Revert "RISC-V: Support highpart register overlap for vwcvt"

[Kito Cheng]

LGTM, thanks Pan, although the revert patch series look a little bit
scary, but I believe it's the safest way for now since we don't really
fully understand how register filters work, and it's not really good
timing to figure out all the detail around that.

On Wed, Apr 24, 2024 at 9:02 PM Li, Pan2  wrote:
>
> Request review as this revert patch contains some manually resolved conflict 
> changes.
>
> Passed the rv64gcv fully regression test with isl build.
>
> Pan
>
> -Original Message-
> From: Li, Pan2 
> Sent: Wednesday, April 24, 2024 8:59 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com; Li, Pan2 
> 
> Subject: [PATCH v1] Revert "RISC-V: Support highpart register overlap for 
> vwcvt"
>
> From: Pan Li 
>
> This reverts commit bdad036da32f72b84a96070518e7d75c21706dc2.
> ---
>  gcc/config/riscv/constraints.md   |  23 
>  gcc/config/riscv/riscv.md |  24 
>  gcc/config/riscv/vector-crypto.md |  21 ++--
>  gcc/config/riscv/vector.md|  19 ++--
>  .../gcc.target/riscv/rvv/base/pr112431-1.c| 104 --
>  .../gcc.target/riscv/rvv/base/pr112431-2.c|  68 
>  .../gcc.target/riscv/rvv/base/pr112431-3.c|  51 -
>  .../gcc.target/riscv/rvv/base/pr112431-39.c   |   2 +-
>  .../gcc.target/riscv/rvv/base/pr112431-40.c   |   2 +-
>  .../gcc.target/riscv/rvv/base/pr112431-41.c   |   2 +-
>  10 files changed, 22 insertions(+), 294 deletions(-)
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c
>
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index e37c6936bfa..a590df545d7 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -159,29 +159,6 @@ (define_register_constraint "vd" "TARGET_VECTOR ? 
> VD_REGS : NO_REGS"
>  (define_register_constraint "vm" "TARGET_VECTOR ? VM_REGS : NO_REGS"
>"A vector mask register (if available).")
>
> -;; These following constraints are used by RVV instructions with dest EEW > 
> src EEW.
> -;; RISC-V 'V' Spec 5.2. Vector Operands:
> -;; The destination EEW is greater than the source EEW, the source EMUL is at 
> least 1,
> -;; and the overlap is in the highest-numbered part of the destination 
> register group.
> -;; (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or 
> v4 is not).
> -(define_register_constraint "W21" "TARGET_VECTOR ? V_REGS : NO_REGS"
> -  "A vector register has register number % 2 == 1." "regno % 2 == 1")
> -
> -(define_register_constraint "W42" "TARGET_VECTOR ? V_REGS : NO_REGS"
> -  "A vector register has register number % 4 == 2." "regno % 4 == 2")
> -
> -(define_register_constraint "W84" "TARGET_VECTOR ? V_REGS : NO_REGS"
> -  "A vector register has register number % 8 == 4." "regno % 8 == 4")
> -
> -(define_register_constraint "W41" "TARGET_VECTOR ? V_REGS : NO_REGS"
> -  "A vector register has register number % 4 == 1." "regno % 4 == 1")
> -
> -(define_register_constraint "W81" "TARGET_VECTOR ? V_REGS : NO_REGS"
> -  "A vector register has register number % 8 == 1." "regno % 8 == 1")
> -
> -(define_register_constraint "W82" "TARGET_VECTOR ? V_REGS : NO_REGS"
> -  "A vector register has register number % 8 == 2." "regno % 8 == 2")
> -
>  ;; This constraint is used to match instruction "csrr %0, vlenb" which is 
> generated in "mov".
>  ;; VLENB is a run-time constant which represent the vector register length 
> in bytes.
>  ;; BYTES_PER_RISCV_VECTOR represent runtime invariant of vector register 
> length in bytes.
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 1693d4008c6..455715ab2f7 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -538,27 +538,6 @@ (define_attr "fp_vector_disabled" "no,yes"
>]
>(const_string "no")))
>
> -(define_attr "vconstraint" "no,W21,W42,W84,W41,W81,W82"
> -  (const_string "no"))
> -
> -(define_attr "vconstraint_enabled" "no,yes"
> -  (cond [(eq_attr "vconstraint" "no")
> - (const_string "yes")
> -
> - (and (eq_attr "vconstraint" "W21")
> - (match_test "riscv_get_v_regno_alignment (GET_MODE 
> (operands[0])) != 2"))
> -(const_string "no")
> -
> - (and (eq_attr "vconstraint" "W42,W41")
> - (match_test "riscv_get_v_regno_alignment (GET_MODE 
> (operands[0])) != 4"))
> -(const_string "no")
> -
> - (and (eq_attr "vconstraint" "W84,W81,W82")
> - (match_test "riscv_get_v_regno_alignment (GET_MODE 
> (operands[0])) != 8"))
> -(const_string "no")
> -]
> -   (const_string "yes")))
> -
>  ;; This attribute marks the alternatives not matching the constraints
>  ;; described in spec as disabled.
>  (define_attr "spec_restriction" 

[PATCH][GCC 13] RISC-V: Fix recursive vsetvli checking [PR114172]

[Kito Cheng]

extract_single_source will recursive checking the sources to
make sure if it's single source, however it may cause infinite
recursive when the source is come from itself, so it should just skip
first source to prevent that.

NOTE: This logic has existing on trunk/GCC 14, but it included in a big
vsetvli improvement patch, which is not backport to GCC 13.

```

void saxpy_rvv_m8(float *y, long vl)
{
for (;;)
{
vl = __riscv_vsetvl_e32m8(vl); //ICE
vfloat32m8_t y_vec;
__riscv_vse32_v_f32m8(y, y_vec, vl);
}
}
```

gcc/ChangeLog:

PR target/114172
* gcc/config/riscv/riscv-vsetvl.cc (extract_single_source):
Skip first set.

gcc/testsuite/ChangeLog:

PR target/114172
* gcc.target/riscv/rvv/vsetvl/pr114172.c: New.
---
 gcc/config/riscv/riscv-vsetvl.cc   |  4 
 .../gcc.target/riscv/rvv/vsetvl/pr114172.c | 14 ++
 2 files changed, 18 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 9dca2ce709d..36d2e6e6f20 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1196,6 +1196,10 @@ extract_single_source (set_info *set)
 return nullptr;
   for (const set_info *set : sets)
 {
+  /* Skip first set, this can prevent us run into infinite recursive
+checking if first set is come from itself.  */
+  if (set == *sets.begin ())
+   continue;
   /* If there is a head or end insn, we conservative return
 NULL so that VSETVL PASS will insert vsetvl directly.  */
   if (set->insn ()->is_artificial ())
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c
new file mode 100644
index 000..ed1494666d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void e(long, vfloat32m4_t);
+
+void b(long c) {
+  for (;;) {
+c = __riscv_vsetvl_e32m4(c);
+vfloat32m4_t d;
+e(c, d);
+  }
+}
-- 
2.34.1

Re: [PATCH] [RISC-V] optimize Zicond conditional select cases.

[Kito Cheng]

It's simple enough, so LGTM for trunk :)

Fei Gao  於 2024年4月15日 週一 14:38 寫道：

> When one of the two input operands is 0, ADD and IOR are functionally
> equivalent.
> ADD is slightly preferred over IOR because ADD has a higher likelihood
> of being implemented as a compressed instruction when compared to IOR.
> C.ADD uses the CR format with any of the 32 RVI registers availble,
> while C.OR uses the CA format with limit to just 8 of them.
>
> Conditional select, if zero case:
> rd = (rc == 0) ? rs1 : rs2
>
> before patch:
>
>   czero.nez rd, rs1, rc
>   czero.eqz rtmp, rs2, rc
>   or rd, rd, rtmp
>
> after patch:
>
>   czero.eqz rd, rs1, rc
>   czero.nez rtmp, rs2, rc
>   add rd, rd, rtmp
>
> Same trick applies for the conditional select, if non-zero case:
> rd = (rc != 0) ? rs1 : rs2
>
> riscv-gnu-toolchain regression tests have been passed with no new failure.
> ---
>  gcc/config/riscv/riscv.cc|  2 +-
>  .../gcc.target/riscv/zicond-prefer-add-to-or.c   | 16 
>  2 files changed, 17 insertions(+), 1 deletion(-)
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index e5f00806bb9..93c736549c9 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -4709,7 +4709,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx
> cons, rtx alt)
>   gen_rtx_IF_THEN_ELSE (mode, cond1,
> CONST0_RTX (mode),
> alt)));
> - riscv_emit_binary (IOR, dest, reg1, reg2);
> + riscv_emit_binary (PLUS, dest, reg1, reg2);
>   return true;
> }
>  }
> diff --git a/gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c
> b/gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c
> new file mode 100644
> index 000..f3f7beb0b5e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" {
> target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=4" {
> target { rv32 } } } */
> +/* { dg-skip-if "" { *-*-* } {"-O0" "-Og" "-Os" "-Oz"} } */
> +
> +long cond_select_if_zero(long a, long b, long c) {
> +  return a == 0 ? c : b;
> +}
> +
> +long cond_select_if_non_zero(long a, long b, long c) {
> +  return a != 0 ? c : b;
> +}
> +
> +/* { dg-final { scan-assembler-times {add\t}  2 } } */
> +/* { dg-final { scan-assembler-not {or\t} } } */
> +
> --
> 2.17.1
>
>

Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P

[Kito Cheng]

Does FP reg also need gurared with TARGET_HARD_FLOAT? could you try to
compile that case without F?

On Fri, Apr 12, 2024 at 2:19 PM Li, Pan2  wrote:
>
> Committed, thanks Juzhe.
>
>
>
> Pan
>
>
>
> From: juzhe.zh...@rivai.ai 
> Sent: Friday, April 12, 2024 2:11 PM
> To: Li, Pan2 ; gcc-patches 
> Cc: kito.cheng ; Li, Pan2 
> Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in 
> TARGET_FUNCTION_VALUE_REGNO_P
>
>
>
> LGTM。
>
>
>
> 
>
> juzhe.zh...@rivai.ai
>
>
>
> From: pan2.li
>
> Date: 2024-04-12 14:08
>
> To: gcc-patches
>
> CC: juzhe.zhong; kito.cheng; Pan Li
>
> Subject: [PATCH v1] RISC-V: Bugfix ICE non-vector in 
> TARGET_FUNCTION_VALUE_REGNO_P
>
> From: Pan Li 
>
>
>
> This patch would like to fix one ICE when vector is not enabled
>
> in hook TARGET_FUNCTION_VALUE_REGNO_P implementation.  The vector
>
> regno is available if and only if the TARGET_VECTOR is true.  The
>
> previous implement missed this condition and then result in ICE
>
> when rv64gc build option without vector.
>
>
>
> PR target/114639
>
>
>
> The below test suite is passed for this patch.
>
>
>
> * The rv64gcv fully regression tests.
>
> * The rv64gc fully regression tests.
>
>
>
> gcc/ChangeLog:
>
>
>
> * config/riscv/riscv.cc (riscv_function_value_regno_p): Add
>
> TARGET_VECTOR predicate for V_RETURN regno.
>
>
>
> gcc/testsuite/ChangeLog:
>
>
>
> * gcc.target/riscv/pr114639-1.c: New test.
>
> * gcc.target/riscv/pr114639-2.c: New test.
>
> * gcc.target/riscv/pr114639-3.c: New test.
>
> * gcc.target/riscv/pr114639-4.c: New test.
>
>
>
> Signed-off-by: Pan Li 
>
> ---
>
> gcc/config/riscv/riscv.cc   |  2 +-
>
> gcc/testsuite/gcc.target/riscv/pr114639-1.c | 11 +++
>
> gcc/testsuite/gcc.target/riscv/pr114639-2.c | 11 +++
>
> gcc/testsuite/gcc.target/riscv/pr114639-3.c | 11 +++
>
> gcc/testsuite/gcc.target/riscv/pr114639-4.c | 11 +++
>
> 5 files changed, 45 insertions(+), 1 deletion(-)
>
> create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-1.c
>
> create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-2.c
>
> create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-3.c
>
> create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-4.c
>
>
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>
> index 91f017dd52a..e5f00806bb9 100644
>
> --- a/gcc/config/riscv/riscv.cc
>
> +++ b/gcc/config/riscv/riscv.cc
>
> @@ -11008,7 +11008,7 @@ riscv_function_value_regno_p (const unsigned regno)
>
>if (FP_RETURN_FIRST <= regno && regno <= FP_RETURN_LAST)
>
>  return true;
>
> -  if (regno == V_RETURN)
>
> +  if (TARGET_VECTOR && regno == V_RETURN)
>
>  return true;
>
>return false;
>
> diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-1.c 
> b/gcc/testsuite/gcc.target/riscv/pr114639-1.c
>
> new file mode 100644
>
> index 000..f41723193a4
>
> --- /dev/null
>
> +++ b/gcc/testsuite/gcc.target/riscv/pr114639-1.c
>
> @@ -0,0 +1,11 @@
>
> +/* Test that we do not have ice when compile */
>
> +/* { dg-do compile } */
>
> +/* { dg-options "-march=rv64gc -mabi=lp64d -std=gnu89 -O3" } */
>
> +
>
> +g (a, b) {}
>
> +
>
> +f (xx)
>
> + void* xx;
>
> +{
>
> +  __builtin_apply ((void*)g, xx, 200);
>
> +}
>
> diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-2.c 
> b/gcc/testsuite/gcc.target/riscv/pr114639-2.c
>
> new file mode 100644
>
> index 000..0c402c4b254
>
> --- /dev/null
>
> +++ b/gcc/testsuite/gcc.target/riscv/pr114639-2.c
>
> @@ -0,0 +1,11 @@
>
> +/* Test that we do not have ice when compile */
>
> +/* { dg-do compile } */
>
> +/* { dg-options "-march=rv64imac -mabi=lp64 -std=gnu89 -O3" } */
>
> +
>
> +g (a, b) {}
>
> +
>
> +f (xx)
>
> + void* xx;
>
> +{
>
> +  __builtin_apply ((void*)g, xx, 200);
>
> +}
>
> diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-3.c 
> b/gcc/testsuite/gcc.target/riscv/pr114639-3.c
>
> new file mode 100644
>
> index 000..ffb0d6d162d
>
> --- /dev/null
>
> +++ b/gcc/testsuite/gcc.target/riscv/pr114639-3.c
>
> @@ -0,0 +1,11 @@
>
> +/* Test that we do not have ice when compile */
>
> +/* { dg-do compile } */
>
> +/* { dg-options "-march=rv32gc -mabi=ilp32d -std=gnu89 -O3" } */
>
> +
>
> +g (a, b) {}
>
> +
>
> +f (xx)
>
> + void* xx;
>
> +{
>
> +  __builtin_apply ((void*)g, xx, 200);
>
> +}
>
> diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-4.c 
> b/gcc/testsuite/gcc.target/riscv/pr114639-4.c
>
> new file mode 100644
>
> index 000..a6e229101ef
>
> --- /dev/null
>
> +++ b/gcc/testsuite/gcc.target/riscv/pr114639-4.c
>
> @@ -0,0 +1,11 @@
>
> +/* Test that we do not have ice when compile */
>
> +/* { dg-do compile } */
>
> +/* { dg-options "-march=rv32imac -mabi=ilp32 -std=gnu89 -O3" } */
>
> +
>
> +g (a, b) {}
>
> +
>
> +f (xx)
>
> + void* xx;
>
> +{
>
> +  __builtin_apply ((void*)g, xx, 200);
>
> +}
>
> --
>
> 2.34.1
>
>
>
>

Re: [PATCH] wwwdocs: gcc-14: Add RISC-V changes

[Kito Cheng]

Committed with fixes, thanks :)

On Thu, Apr 11, 2024 at 12:18 AM Palmer Dabbelt  wrote:

> On Wed, 10 Apr 2024 00:58:00 PDT (-0700), kito.ch...@sifive.com wrote:
> > ---
> >  htdocs/gcc-14/changes.html | 155 -
> >  1 file changed, 154 insertions(+), 1 deletion(-)
> >
> > diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
> > index 2d8968cf..6cbb2e8f 100644
> > --- a/htdocs/gcc-14/changes.html
> > +++ b/htdocs/gcc-14/changes.html
> > @@ -739,7 +739,160 @@ __asm (".global __flmap_lock"  "\n\t"
> >
> >  
> >
> > -
> > +RISC-V
> > +
> > +  The SLP and loop vectorizer is now enabled for RISC-V when the
> vector
>
> I think "are now enabled"?
>
> > +  extension is enabled, thanks to Ju-Zhe Zhong from
> > +  RiVAI,
> > +  Pan Li from Intel, and
> Robin Dapp
> > +  from Ventana Micro
> for
> > +  contributing most of the implementation!
> > +  The -mrvv-max-lmul= option has been introduced for
> > +  performance tuning of the loop vectorizer. The default value is
> > +  -mrvv-max-lmul=m1, which limits the maximum LMUL to
> 1.
> > +  The -mrvv-max-lmul=dynamic setting can dynamically
> select
> > +  the maximum LMUL value based on register pressure.
> > +  Atomic code generation has been improved and is now in
> conformance with
> > +  the latest psABI specification, thanks to Patrick O'Neill from
> > +  Rivos.
> > +  Support for the vector intrinsics as specified in
> > +  
> > +  version 1.0 of the RISC-V vector intrinsic specification.
> > +  Support for the experimental vector crypto intrinsics as
> specified in
> > +  
> > +  RISC-V vector intrinsic specification, thanks to Feng Wang et
> al.
> > +  from https://eswincomputing.com/;>ESWIN
> Computing
> > +  Support for the T-head vector intrinsics.
> > +  Support for the scalar bitmanip and scalar crypto  intrinsics,
> thanks to
> > +  Liao Shihua from https://plctlab.org/;>PLCT.
> > +  Support for the large code model via option
> -mcmodel=large,
> > +  thanks to Kuan-Lin Chen from
> > +  https://www.andestech.com/;>Andes Technology.
> > +  Support for the standard vector calling convention variant,
> thanks to
> > +  Lehua Ding from RiVAI.
> > +  Supports the target attribute, which allows users to
> compile
> > +  a function with specific extensions.
> > +  -march= option no longer requires the architecture
> string
> > +  to be in canonical order, with only a few constraints remaining:
> the
> > +  architecture string must start with
> rv[32|64][i|g|e], and
> > +  must use an underscore as the separator after a multi-letter
> extension.
> > +  
> > +  -march=help option has been introduced to dump all
> > +  supported extensions.
> > +  Added experimental support for the
> -mrvv-vector-bits=zvl
> > +  option and the riscv_rvv_vector_bits attribute, which
> > +  specify a fixed length for scalable vector types. This option is
> > +  optimized for specific vector core implementations; however, the
> code
> > +  generated with this option is NOT portable,
>
> IIUC the code is just optimized for a specific vector length, not any
> specific core.  It's portable to other cores, just not portable to cores
> with different vector lengths.
>
> So I think we can soften the language a bit there, as it's not like
> we're emitting vendor-specific code on this one.
>
> > +  thanks to Pan Li from https://www.intel.com/;>Intel.
> > +  
> > +  Support for TLS descriptors has been introduced, which can be
> enabled by
> > +  the -mtls-dialect=desc option. The default behavior
> can be
> > +  configured with --with-tls=[trad|desc].
> > +  Support for the TLS descriptors, this can be enabled by
> > +  -mtls-dialect=desc and the default behavior can be
> configure
> > +  by --with-tls=[trad|desc], thanks to Tatsuyuki Ishi from
> > +  https://bluewhale.systems/;>Blue Whale
> Systems
>
> Maybe should call out that this will require the next glibc release to
> function correctly?
>
> > +  
> > +  Support for the following standard extensions has been added:
> > +
> > +  Vector crypto extensions:
> > + 
> > +   Zvbb
> > +   Zvkb
> > +   Zvbc
> > +   Zvkg
> > +   Zvkned
> > +   Zvkhna
> > +   Zvkhnb
> > +   Zvksed
> > +   Zvksh
> > +   Zvkn
> > +   Zvknc
> > +   Zvkng
> > +   Zvks
> > +   Zvksc
> > +   Zvksg
> > +   Zvkt
> > + 
> > +  
> > +  Code size reduction extensions:
> > + 
> > +   Zca
> > +   Zcb
> > +   Zce
> > +   Zcf
> > +   Zcd
> > +   Zcmp
> > +   Zcmt
> > + 
> > +  
> > +  Zicond
> > +  Zfa
> > +  Ztso
> > +  Zvfbfmin
> > +  Zvfhmin
> > +  Zvfh
> > +  Za64rs
> > +  Za128rs
> > +  Ziccif
> > +  Ziccrse
> > +  Ziccamoa
> > +  Zicclsm
> > +  Zic64b
> > +  Smaia
> > +  Smepmp
> > +  

Re: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode switch

[Kito Cheng]

I was thinking we may guarded with TARGET_VECTOR and TARGET_HARD_FLOAT
or checking with ABI in riscv_function_value_regno_p, however I think
it's fine with current implementation (no checking) after checking all
use site of `targetm.calls.function_value_regno_p`, so LGTM :)

Thanks Pan for fixing this issue!

On Thu, Apr 11, 2024 at 10:23 AM juzhe.zh...@rivai.ai
 wrote:
>
> Thanks for fixing it. LGTM from my side.
>
> I prefer wait kito for another ACK.
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: pan2.li
> Date: 2024-04-11 10:16
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; Pan Li
> Subject: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode 
> switch
> From: Pan Li 
>
> This patch would like to fix a ICE in mode sw for below example code.
>
> during RTL pass: mode_sw
> test.c: In function ‘vbool16_t j(vuint64m4_t)’:
> test.c:15:1: internal compiler error: in create_pre_exit, at
> mode-switching.cc:451
>15 | }
>   | ^
> 0x3978f12 create_pre_exit
> __RISCV_BUILD__/../gcc/mode-switching.cc:451
> 0x3979e9e optimize_mode_switching
> __RISCV_BUILD__/../gcc/mode-switching.cc:849
> 0x397b9bc execute
> __RISCV_BUILD__/../gcc/mode-switching.cc:1324
>
> extern size_t get_vl ();
>
> vbool16_t
> test (vuint64m4_t a)
> {
>   unsigned long b;
>   return __riscv_vmsne_vx_u64m4_b16 (a, b, get_vl ());
> }
>
> The create_pre_exit would like to find a return value copy.  If
> not, there will be a reason in assert but not available for above
> sample code when vector calling convension is enabled by default.
> This patch would like to override the TARGET_FUNCTION_VALUE_REGNO_P
> for vector register and then we will have hard_regno_nregs for copy_num,
> aka there is a return value copy.
>
> As a side-effect of allow vector in TARGET_FUNCTION_VALUE_REGNO_P, the
> TARGET_GET_RAW_RESULT_MODE will have vector mode and which is sizeless
> cannot be converted to fixed_size_mode.  Thus override the hook
> TARGET_GET_RAW_RESULT_MODE and return VOIDmode when the regno is-not-a
> fixed_size_mode.
>
> The below tests are passed for this patch.
> * The fully riscv regression tests.
> * The reproducing test in bugzilla PR114639.
>
> PR target/114639
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_function_value_regno_p): New func
> impl for hook TARGET_FUNCTION_VALUE_REGNO_P.
> (riscv_get_raw_result_mode): New func imple for hook
> TARGET_GET_RAW_RESULT_MODE.
> (TARGET_FUNCTION_VALUE_REGNO_P): Impl the hook.
> (TARGET_GET_RAW_RESULT_MODE): Ditto.
> * config/riscv/riscv.h (V_RETURN): New macro for vector return.
> (GP_RETURN_FIRST): New macro for the first GPR in return.
> (GP_RETURN_LAST): New macro for the last GPR in return.
> (FP_RETURN_FIRST): Diito but for FPR.
> (FP_RETURN_LAST): Ditto.
> (FUNCTION_VALUE_REGNO_P): Remove as deprecated and replace by
> TARGET_FUNCTION_VALUE_REGNO_P.
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/riscv/rvv/base/pr114639-1.C: New test.
> * gcc.target/riscv/rvv/base/pr114639-1.c: New test.
>
> Signed-off-by: Pan Li 
> ---
> gcc/config/riscv/riscv.cc | 34 +++
> gcc/config/riscv/riscv.h  |  8 +++--
> .../g++.target/riscv/rvv/base/pr114639-1.C| 25 ++
> .../gcc.target/riscv/rvv/base/pr114639-1.c| 14 
> 4 files changed, 79 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr114639-1.C
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 00defa69fd8..91f017dd52a 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -10997,6 +10997,34 @@ riscv_vector_mode_supported_any_target_p 
> (machine_mode)
>return true;
> }
> +/* Implements hook TARGET_FUNCTION_VALUE_REGNO_P.  */
> +
> +static bool
> +riscv_function_value_regno_p (const unsigned regno)
> +{
> +  if (GP_RETURN_FIRST <= regno && regno <= GP_RETURN_LAST)
> +return true;
> +
> +  if (FP_RETURN_FIRST <= regno && regno <= FP_RETURN_LAST)
> +return true;
> +
> +  if (regno == V_RETURN)
> +return true;
> +
> +  return false;
> +}
> +
> +/* Implements hook TARGET_GET_RAW_RESULT_MODE.  */
> +
> +static fixed_size_mode
> +riscv_get_raw_result_mode (int regno)
> +{
> +  if (!is_a  (reg_raw_mode[regno]))
> +return as_a  (VOIDmode);
> +
> +  return default_get_reg_raw_mode (regno);
> +}
> +
> /* Initialize the GCC target structure.  */
> #undef TARGET_ASM_ALIGNED_HI_OP
> #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
> @@ -11343,6 +11371,12 @@ riscv_vector_mode_supported_any_target_p 
> (machine_mode)
> #undef TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P
> #define TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P 
> riscv_vector_mode_supported_any_target_p
> +#undef TARGET_FUNCTION_VALUE_REGNO_P
> +#define TARGET_FUNCTION_VALUE_REGNO_P riscv_function_value_regno_p
> +
> +#undef TARGET_GET_RAW_RESULT_MODE
> +#define 

[PATCH] wwwdocs: gcc-14: Add RISC-V changes

[Kito Cheng]

---
 htdocs/gcc-14/changes.html | 155 -
 1 file changed, 154 insertions(+), 1 deletion(-)

diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 2d8968cf..6cbb2e8f 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -739,7 +739,160 @@ __asm (".global __flmap_lock"  "\n\t"
 
 
 
-
+RISC-V
+
+  The SLP and loop vectorizer is now enabled for RISC-V when the vector
+  extension is enabled, thanks to Ju-Zhe Zhong from
+  RiVAI,
+  Pan Li from Intel, and Robin Dapp
+  from Ventana Micro for
+  contributing most of the implementation!
+  The -mrvv-max-lmul= option has been introduced for
+  performance tuning of the loop vectorizer. The default value is
+  -mrvv-max-lmul=m1, which limits the maximum LMUL to 1.
+  The -mrvv-max-lmul=dynamic setting can dynamically select
+  the maximum LMUL value based on register pressure.
+  Atomic code generation has been improved and is now in conformance with
+  the latest psABI specification, thanks to Patrick O'Neill from
+  Rivos.
+  Support for the vector intrinsics as specified in
+  
+  version 1.0 of the RISC-V vector intrinsic specification.
+  Support for the experimental vector crypto intrinsics as specified in
+  
+  RISC-V vector intrinsic specification, thanks to Feng Wang et al.
+  from https://eswincomputing.com/;>ESWIN Computing
+  Support for the T-head vector intrinsics.
+  Support for the scalar bitmanip and scalar crypto  intrinsics, thanks to
+  Liao Shihua from https://plctlab.org/;>PLCT.
+  Support for the large code model via option -mcmodel=large,
+  thanks to Kuan-Lin Chen from
+  https://www.andestech.com/;>Andes Technology.
+  Support for the standard vector calling convention variant, thanks to
+  Lehua Ding from RiVAI.
+  Supports the target attribute, which allows users to compile
+  a function with specific extensions.
+  -march= option no longer requires the architecture string
+  to be in canonical order, with only a few constraints remaining: the
+  architecture string must start with rv[32|64][i|g|e], and
+  must use an underscore as the separator after a multi-letter extension.
+  
+  -march=help option has been introduced to dump all
+  supported extensions.
+  Added experimental support for the -mrvv-vector-bits=zvl
+  option and the riscv_rvv_vector_bits attribute, which
+  specify a fixed length for scalable vector types. This option is
+  optimized for specific vector core implementations; however, the code
+  generated with this option is NOT portable,
+  thanks to Pan Li from https://www.intel.com/;>Intel.
+  
+  Support for TLS descriptors has been introduced, which can be enabled by
+  the -mtls-dialect=desc option. The default behavior can be
+  configured with --with-tls=[trad|desc].
+  Support for the TLS descriptors, this can be enabled by
+  -mtls-dialect=desc and the default behavior can be configure
+  by --with-tls=[trad|desc], thanks to Tatsuyuki Ishi from
+  https://bluewhale.systems/;>Blue Whale Systems
+  
+  Support for the following standard extensions has been added:
+
+  Vector crypto extensions:
+   
+ Zvbb
+ Zvkb
+ Zvbc
+ Zvkg
+ Zvkned
+ Zvkhna
+ Zvkhnb
+ Zvksed
+ Zvksh
+ Zvkn
+ Zvknc
+ Zvkng
+ Zvks
+ Zvksc
+ Zvksg
+ Zvkt
+   
+  
+  Code size reduction extensions:
+   
+ Zca
+ Zcb
+ Zce
+ Zcf
+ Zcd
+ Zcmp
+ Zcmt
+   
+  
+  Zicond
+  Zfa
+  Ztso
+  Zvfbfmin
+  Zvfhmin
+  Zvfh
+  Za64rs
+  Za128rs
+  Ziccif
+  Ziccrse
+  Ziccamoa
+  Zicclsm
+  Zic64b
+  Smaia
+  Smepmp
+  Smstateen
+  Ssaia
+  Sscofpmf
+  Ssstateen
+  Sstc
+  Svinval
+  Svnapot
+  Svpbmt
+
+  
+  Support for the following vendor extensions has been added:
+
+  T-Head:
+   
+ XTheadVector
+   
+  
+  CORE-V:
+   
+ XCVmac
+ XCValu
+ XCVelw
+ XCVsimd
+ XCVbi
+   
+  
+  Ventana Micro:
+   
+ XVentanaCondops
+   
+  
+
+  
+  The following new CPUs are supported through the -mcpu
+  option (GCC identifiers in parentheses).
+
+  SiFive's X280 (sifive-x280).
+  SiFive's P450 (sifive-p450).
+  SiFive's P670 (sifive-p670).
+
+  
+  The following new CPUs are supported through the -mtune
+  option (GCC identifiers in parentheses).
+
+  Generic out-of-order core (generic-ooo).
+  SiFive's P400 series (sifive-p400-series).
+  SiFive's P600 series (sifive-p600-series).
+  XiangShan's Nanhu microarchitecture 
(xiangshan-nanhu).
+
+  
+
 
 
 
-- 
2.34.1

Re: [PATCH v5] RISC-V: Implement TLS Descriptors.

[Kito Cheng]

Committed to trunk, thanks Tatsuyuki!

On Fri, Mar 29, 2024 at 2:32 PM Kito Cheng  wrote:
>
> Hi Tatsuyuki:
>
> Thanks for your hard work and keep updating, the patch set is LGTM, I
> plan to commit this next week if no further comments :)
>
> Hi MaskRay:
>
> Thanks for your review on the patchset! just put you into the cc list
> in case you have few more comments :)
>
>
> On Fri, Mar 29, 2024 at 1:53 PM Tatsuyuki Ishi  
> wrote:
> >
> > This implements TLS Descriptors (TLSDESC) as specified in [1].
> >
> > The 4-instruction sequence is implemented as a single RTX insn for
> > simplicity, but this can be revisited later if instruction scheduling or
> > more flexible RA is desired.
> >
> > The default remains to be the traditional TLS model, but can be configured
> > with --with-tls={trad,desc}. The choice can be revisited once toolchain
> > and libc support ships.
> >
> > [1]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/373.
> >
> > gcc/Changelog:
> > * config/riscv/riscv.opt: Add -mtls-dialect to configure TLS flavor.
> > * config.gcc: Add --with-tls configuration option to change the
> > default TLS flavor.
> > * config/riscv/riscv.h: Add TARGET_TLSDESC determined from
> > -mtls-dialect and with_tls defaults.
> > * config/riscv/riscv-opts.h: Define enum riscv_tls_type for the
> > two TLS flavors.
> > * config/riscv/riscv-protos.h: Define SYMBOL_TLSDESC symbol type.
> > * config/riscv/riscv.md: Add instruction sequence for TLSDESC.
> > * config/riscv/riscv.cc (riscv_symbol_insns): Add instruction
> > sequence length data for TLSDESC.
> > (riscv_legitimize_tls_address): Add lowering of TLSDESC.
> > * doc/install.texi: Document --with-tls for RISC-V.
> > * doc/invoke.texi: Document -mtls-dialect for RISC-V.
> > * testsuite/gcc.target/riscv/tls_1.x: Add TLSDESC GD test case.
> > * testsuite/gcc.target/riscv/tlsdesc.c: Same as above.
> > ---
> > No regression in gcc tests for rv32gcv and rv64gcv, tested alongside
> > the binutils and glibc implementation. Tested with --with-tls=desc.
> >
> > v2: Add with_tls configuration option, and a few readability improvements.
> > Added Changelog.
> > v3: Add documentation per Kito's suggestion.
> > Fix minor issues pointed out by Kito and Jeff.
> > Thanks Kito Cheng and Jeff Law for review.
> > v4: Add TLSDESC GD assembly test.
> > Rebase on top of trunk.
> > v5: Trivial rebase on top of trunk.
> >
> > I have recently addressed relaxation concerns on binutils and RVV
> > register save/restore on glibc, so I'm sending out a trivial rebase
> > with the hope that the full set can be merged soon.
> >
> >  gcc/config.gcc   | 15 ++-
> >  gcc/config/riscv/riscv-opts.h|  6 ++
> >  gcc/config/riscv/riscv-protos.h  |  5 +++--
> >  gcc/config/riscv/riscv.cc| 24 
> >  gcc/config/riscv/riscv.h |  9 +++--
> >  gcc/config/riscv/riscv.md| 20 +++-
> >  gcc/config/riscv/riscv.opt   | 14 ++
> >  gcc/doc/install.texi |  3 +++
> >  gcc/doc/invoke.texi  | 13 -
> >  gcc/testsuite/gcc.target/riscv/tls_1.x   |  5 +
> >  gcc/testsuite/gcc.target/riscv/tlsdesc.c | 12 
> >  11 files changed, 115 insertions(+), 11 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/tls_1.x
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/tlsdesc.c
> >
> > diff --git a/gcc/config.gcc b/gcc/config.gcc
> > index 17873ac2103..1a5870672d2 100644
> > --- a/gcc/config.gcc
> > +++ b/gcc/config.gcc
> > @@ -2492,6 +2492,7 @@ riscv*-*-linux*)
> > # Force .init_array support.  The configure script cannot always
> > # automatically detect that GAS supports it, yet we require it.
> > gcc_cv_initfini_array=yes
> > +   with_tls=${with_tls:-trad}
> > ;;
> >  riscv*-*-elf* | riscv*-*-rtems*)
> > tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
> > @@ -2534,6 +2535,7 @@ riscv*-*-freebsd*)
> > # Force .init_array support.  The configure script cannot always
> > # automatically detect that GAS supports it, yet we require it.
> > gcc_cv_initfini_array=yes
> > +   with_tls=${with_tls:-trad}
> > ;;

Re: [PATCH] RISC-V: Fix misspelled term builtin in error message

[Kito Cheng]

lgtm

On Sat, Mar 30, 2024 at 8:07 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to fix below misspelled term in error message.
>
> ../../gcc/config/riscv/riscv-vector-builtins.cc:4592:16: error:
> misspelled term 'builtin function' in format; use 'built-in function' instead 
> [-Werror=format-diag]
>  4592 |   "builtin function %qE requires the V ISA extension", 
> exp);
>
> The below tests are passed for this patch.
> * The riscv regression test on rvv.exp and riscv.exp.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc (expand_builtin): Take
> the term built-in over builtin.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c:
> Adjust test dg-error.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c:
> Ditto.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-vector-builtins.cc   | 2 +-
>  .../riscv/rvv/base/target_attribute_v_with_intrinsic-7.c| 2 +-
>  .../riscv/rvv/base/target_attribute_v_with_intrinsic-8.c| 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc 
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index e07373d8b57..db9246eed2d 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -4589,7 +4589,7 @@ expand_builtin (unsigned int code, tree exp, rtx target)
>
>if (!TARGET_VECTOR)
>  error_at (EXPR_LOCATION (exp),
> - "builtin function %qE requires the V ISA extension", exp);
> + "built-in function %qE requires the V ISA extension", exp);
>
>return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
>  }
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
>  
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> index 520b2e59fae..a4cd67f4f95 100644
> --- 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> +++ 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> @@ -5,5 +5,5 @@
>
>  size_t test_1 (size_t vl)
>  {
> -  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function 
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> +  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function 
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
>  }
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
>  
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> index 9032d9d0b43..06ed9a9eddc 100644
> --- 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> +++ 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> @@ -19,5 +19,5 @@ test_2 ()
>  size_t
>  test_3 (size_t vl)
>  {
> -  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function 
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> +  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function 
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
>  }
> --
> 2.34.1
>

Re: [PATCH] RISC-V: Fix one unused varable in riscv_subset_list::parse

[Kito Cheng]

LGTM

On Sat, Mar 30, 2024 at 9:35 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to fix one unused variable as below:
>
> ../../gcc/common/config/riscv/riscv-common.cc: In static member function
> 'static riscv_subset_list* riscv_subset_list::parse(const char*, location_t)':
> ../../gcc/common/config/riscv/riscv-common.cc:1501:19: error: unused variable 
> 'itr'
>   [-Werror=unused-variable]
>  1501 |   riscv_subset_t *itr;
>
> The variable consume code was removed but missed the var itself in
> previous.  Thus, we have unused variable here.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
> Remove unused var decl.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/common/config/riscv/riscv-common.cc | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 7095f303cbb..43b7549e3ec 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -1498,7 +1498,6 @@ riscv_subset_list::parse (const char *arch, location_t 
> loc)
>  return NULL;
>
>riscv_subset_list *subset_list = new riscv_subset_list (arch, loc);
> -  riscv_subset_t *itr;
>const char *p = arch;
>p = subset_list->parse_base_ext (p);
>if (p == NULL)
> --
> 2.34.1
>

Re: [PATCH v5] RISC-V: Implement TLS Descriptors.

[Kito Cheng]

Hi Tatsuyuki:

Thanks for your hard work and keep updating, the patch set is LGTM, I
plan to commit this next week if no further comments :)

Hi MaskRay:

Thanks for your review on the patchset! just put you into the cc list
in case you have few more comments :)


On Fri, Mar 29, 2024 at 1:53 PM Tatsuyuki Ishi  wrote:
>
> This implements TLS Descriptors (TLSDESC) as specified in [1].
>
> The 4-instruction sequence is implemented as a single RTX insn for
> simplicity, but this can be revisited later if instruction scheduling or
> more flexible RA is desired.
>
> The default remains to be the traditional TLS model, but can be configured
> with --with-tls={trad,desc}. The choice can be revisited once toolchain
> and libc support ships.
>
> [1]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/373.
>
> gcc/Changelog:
> * config/riscv/riscv.opt: Add -mtls-dialect to configure TLS flavor.
> * config.gcc: Add --with-tls configuration option to change the
> default TLS flavor.
> * config/riscv/riscv.h: Add TARGET_TLSDESC determined from
> -mtls-dialect and with_tls defaults.
> * config/riscv/riscv-opts.h: Define enum riscv_tls_type for the
> two TLS flavors.
> * config/riscv/riscv-protos.h: Define SYMBOL_TLSDESC symbol type.
> * config/riscv/riscv.md: Add instruction sequence for TLSDESC.
> * config/riscv/riscv.cc (riscv_symbol_insns): Add instruction
> sequence length data for TLSDESC.
> (riscv_legitimize_tls_address): Add lowering of TLSDESC.
> * doc/install.texi: Document --with-tls for RISC-V.
> * doc/invoke.texi: Document -mtls-dialect for RISC-V.
> * testsuite/gcc.target/riscv/tls_1.x: Add TLSDESC GD test case.
> * testsuite/gcc.target/riscv/tlsdesc.c: Same as above.
> ---
> No regression in gcc tests for rv32gcv and rv64gcv, tested alongside
> the binutils and glibc implementation. Tested with --with-tls=desc.
>
> v2: Add with_tls configuration option, and a few readability improvements.
> Added Changelog.
> v3: Add documentation per Kito's suggestion.
> Fix minor issues pointed out by Kito and Jeff.
> Thanks Kito Cheng and Jeff Law for review.
> v4: Add TLSDESC GD assembly test.
> Rebase on top of trunk.
> v5: Trivial rebase on top of trunk.
>
> I have recently addressed relaxation concerns on binutils and RVV
> register save/restore on glibc, so I'm sending out a trivial rebase
> with the hope that the full set can be merged soon.
>
>  gcc/config.gcc   | 15 ++-
>  gcc/config/riscv/riscv-opts.h|  6 ++
>  gcc/config/riscv/riscv-protos.h  |  5 +++--
>  gcc/config/riscv/riscv.cc| 24 
>  gcc/config/riscv/riscv.h |  9 +++--
>  gcc/config/riscv/riscv.md| 20 +++-
>  gcc/config/riscv/riscv.opt   | 14 ++
>  gcc/doc/install.texi |  3 +++
>  gcc/doc/invoke.texi  | 13 -
>  gcc/testsuite/gcc.target/riscv/tls_1.x   |  5 +
>  gcc/testsuite/gcc.target/riscv/tlsdesc.c | 12 
>  11 files changed, 115 insertions(+), 11 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/tls_1.x
>  create mode 100644 gcc/testsuite/gcc.target/riscv/tlsdesc.c
>
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index 17873ac2103..1a5870672d2 100644
> --- a/gcc/config.gcc
> +++ b/gcc/config.gcc
> @@ -2492,6 +2492,7 @@ riscv*-*-linux*)
> # Force .init_array support.  The configure script cannot always
> # automatically detect that GAS supports it, yet we require it.
> gcc_cv_initfini_array=yes
> +   with_tls=${with_tls:-trad}
> ;;
>  riscv*-*-elf* | riscv*-*-rtems*)
> tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
> @@ -2534,6 +2535,7 @@ riscv*-*-freebsd*)
> # Force .init_array support.  The configure script cannot always
> # automatically detect that GAS supports it, yet we require it.
> gcc_cv_initfini_array=yes
> +   with_tls=${with_tls:-trad}
> ;;
>
>  loongarch*-*-linux*)
> @@ -4671,7 +4673,7 @@ case "${target}" in
> ;;
>
> riscv*-*-*)
> -   supported_defaults="abi arch tune riscv_attribute isa_spec"
> +   supported_defaults="abi arch tune riscv_attribute isa_spec 
> tls"
>
> case "${target}" in
> riscv-* | riscv32*) xlen=32 ;;
> @@ -4801,6 +4803,17 @@ case "${target}" in
> ;;
>

Re: [PATCH v1] RISC-V: Allow RVV intrinsic for more function target

[Kito Cheng]

Just tried something interesting:

$ riscv64-unknown-linux-gnu-gcc -march=rv64gc -O
target_attribute_v_with_intrinsic-9.c -S # Work
$ riscv64-unknown-linux-gnu-gcc -march=rv64gc_zve32x -O
target_attribute_v_with_intrinsic-9.c -S # Not work

Also I guess all zvk* and zvbb may also need to be added as well,
but...I suspect it's not scalable way?

Re: [PATCH] RISC-V: Add vxsat as a register

[Kito Cheng]

LGTM, and committed to trunk :)

On Thu, Mar 28, 2024 at 5:37 AM Palmer Dabbelt  wrote:
>
> We aren't doing anything with vxsat right now, but I'd like to add it as
> an accepted register to the clobber list.  If we get this into GCC-14
> then we'll avoid some preprocessor-based twiddling if we ever start
> using vxsat in the future.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.h (REGISTER_NAMES): Add vxsat.
> ---
> IIUC we aren't using these N/A regnos for anything, they're just there to pad
> out the types.  So I think this is safe, but Juzhe would likely know best 
> here.
>
> See
> https://inbox.sourceware.org/libc-alpha/20240327193601.28903-2-pal...@rivosinc.com/
> a use of this.
> ---
>  gcc/config/riscv/riscv.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index da089a03e9d..d5779512994 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -933,7 +933,7 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
>"fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",  \
>"fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",  \
>"fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11", \
> -  "arg", "frame", "vl", "vtype", "vxrm", "frm", "N/A", "N/A",   \
> +  "arg", "frame", "vl", "vtype", "vxrm", "frm", "vxsat", "N/A", \
>"N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A",  \
>"N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A",  \
>"N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A", "N/A",  \
> --
> 2.44.0
>

Re: [PATCH v1] RISC-V: Allow RVV intrinsic when function target("arch=+v")

[Kito Cheng]

LGTM, thanks :)

On Mon, Mar 25, 2024 at 3:42 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to allow the RVV intrinsic when function is
> attributed as target("arch=+v") and build with rv64gc.  For example:
>
> vint32m1_t
> __attribute__((target("arch=+v")))
> test_1 (vint32m1_t a, vint32m1_t b, size_t vl)
> {
>   return __riscv_vadd_vv_i32m1 (a, b, vl);
> }
>
> build with -march=rv64gc -mabi=lp64d -O3, we will have asm like below:
> test_1:
>   .option push
>   .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_\
> zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
>   vsetvli zero,a0,e32,m1,ta,ma
>   vadd.vv v8,v8,v9
>   ret
>
> The riscv_vector.h must be included when leverage intrinisc type(s) and
> API(s).  And the scope of this attribute should not excced the function
> body.  Meanwhile, to make rvv types and API(s) available for this attribute,
> include riscv_vector.h will not report error for now if v is not present
> in march.
>
> Below test are passed for this patch:
> * The riscv fully regression test.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Remove error
> when V is disabled and init the RVV types and intrinic APIs.
> * config/riscv/riscv-vector-builtins.cc (expand_builtin): Report
> error if V ext is disabled.
> * config/riscv/riscv.cc (riscv_return_value_is_vector_type_p):
> Ditto.
> (riscv_arguments_is_vector_type_p): Ditto.
> (riscv_vector_cc_function_p): Ditto.
> * config/riscv/riscv_vector.h: Remove error if V is disable.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pragma-1.c: Remove.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-1.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-2.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-4.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-5.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-6.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c: 
> New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-c.cc   | 18 +++
>  gcc/config/riscv/riscv-vector-builtins.cc |  5 
>  gcc/config/riscv/riscv.cc | 30 ---
>  gcc/config/riscv/riscv_vector.h   |  4 ---
>  .../gcc.target/riscv/rvv/base/pragma-1.c  |  4 ---
>  .../target_attribute_v_with_intrinsic-1.c |  5 
>  .../target_attribute_v_with_intrinsic-2.c | 18 +++
>  .../target_attribute_v_with_intrinsic-3.c | 13 
>  .../target_attribute_v_with_intrinsic-4.c | 10 +++
>  .../target_attribute_v_with_intrinsic-5.c | 12 
>  .../target_attribute_v_with_intrinsic-6.c | 12 
>  .../target_attribute_v_with_intrinsic-7.c |  9 ++
>  .../target_attribute_v_with_intrinsic-8.c | 23 ++
>  13 files changed, 145 insertions(+), 18 deletions(-)
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-4.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-5.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-6.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
>
> diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
> index edb866d51e4..01314037461 100644
> --- a/gcc/config/riscv/riscv-c.cc
> +++ b/gcc/config/riscv/riscv-c.cc
> @@ -201,14 +201,20 @@ riscv_pragma_intrinsic (cpp_reader *)
>if (strcmp (name, "vector") == 0
>|| strcmp (name, "xtheadvector") == 0)
>  {
> -  if (!TARGET_VECTOR)
> +  if (TARGET_VECTOR)
> +   riscv_vector::handle_pragma_vector ();
> +  else /* Indicates riscv_vector.h is included but v is missing in arch  
> */
> {
> - error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or "
> -"'XTHEADVECTOR' extension enabled",
> -name);
> - return;
> + /* To make the 

Re: [PATCH v4] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV

[Kito Cheng]

LGTM, thanks :)

On Fri, Mar 22, 2024 at 2:55 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to introduce one new gcc attribute for RVV.
> This attribute is used to define fixed-length variants of one
> existing sizeless RVV types.
>
> This attribute is valid if and only if the mrvv-vector-bits=zvl, the only
> one args should be the integer constant and its' value is terminated
> by the LMUL and the vector register bits in zvl*b.  For example:
>
> typedef vint32m2_t fixed_vint32m2_t 
> __attribute__((riscv_rvv_vector_bits(128)));
>
> The above type define is valid when -march=rv64gc_zve64d_zvl64b
> (aka 2(m2) * 64 = 128 for vin32m2_t), and will report error when
> -march=rv64gcv_zvl128b similar to below.
>
> "error: invalid RVV vector size '128', expected size is '256' based on
> LMUL of type and '-mrvv-vector-bits=zvl'"
>
> Meanwhile, a pre-define macro __riscv_v_fixed_vlen is introduced to
> represent the fixed vlen in a RVV vector register.
>
> For the vint*m*_t below operations are allowed.
> * The sizeof.
> * The global variable(s).
> * The element of union and struct.
> * The cast to other equalities.
> * CMP: >, <, ==, !=, <=, >=
> * ALU: +, -, *, /, %, &, |, ^, >>, <<, ~, -
>
> The CMP will return vint*m*_t the same as aarch64 sve. For example:
> typedef vint32m1_t fixed_vint32m1_t 
> __attribute__((riscv_rvv_vector_bits(128)));
> fixed_vint32m1_t less_than (fixed_vint32m1_t a, fixed_vint32m1_t b)
> {
>   return a < b;
> }
>
> For the vfloat*m*_t below operations are allowed.
> * The sizeof.
> * The global variable(s).
> * The element of union and struct.
> * The cast to other equalities.
> * CMP: >, <, ==, !=, <=, >=
> * ALU: +, -, *, /, -
>
> The CMP will return vfloat*m*_t the same as aarch64 sve. For example:
> typedef vfloat32m1_t fixed_vfloat32m1_t 
> __attribute__((riscv_rvv_vector_bits(128)));
> fixed_vfloat32m1_t less_than (fixed_vfloat32m1_t a, fixed_vfloat32m1_t b)
> {
>   return a < b;
> }
>
> For the vbool*_t types only below operations are allowed except
> the CMP and ALU. The CMP and ALU operations on vbool*_t is not
> well defined currently.
> * The sizeof.
> * The global variable(s).
> * The element of union and struct.
> * The cast to other equalities.
>
> For the vint*x*m*_t tuple types are not suppored in this patch which is
> compatible with clang.
>
> This patch passed the below testsuites.
> * The riscv fully regression tests.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
> macro __riscv_v_fixed_vlen when zvl.
> * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
> New static func to take care of the RVV types decorated by
> the attributes.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-1.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-10.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-11.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-12.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-13.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-14.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-15.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-16.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-17.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-18.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-2.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-3.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-4.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-5.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-6.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-7.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-8.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-9.c: New test.
> * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits.h: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-c.cc   |   3 +
>  gcc/config/riscv/riscv.cc |  87 +-
>  .../riscv/rvv/base/riscv_rvv_vector_bits-1.c  |   6 +
>  .../riscv/rvv/base/riscv_rvv_vector_bits-10.c |  53 +
>  .../riscv/rvv/base/riscv_rvv_vector_bits-11.c |  76 
>  .../riscv/rvv/base/riscv_rvv_vector_bits-12.c |  14 +++
>  .../riscv/rvv/base/riscv_rvv_vector_bits-13.c |  10 ++
>  .../riscv/rvv/base/riscv_rvv_vector_bits-14.c |  10 ++
>  .../riscv/rvv/base/riscv_rvv_vector_bits-15.c |  10 ++
>  .../riscv/rvv/base/riscv_rvv_vector_bits-16.c |  11 ++
>  .../riscv/rvv/base/riscv_rvv_vector_bits-17.c |  10 ++
>  .../riscv/rvv/base/riscv_rvv_vector_bits-18.c |  45 
>  .../riscv/rvv/base/riscv_rvv_vector_bits-2.c  

Re: [PATCH v2] RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))

[Kito Cheng]

LGTM, thanks :)

On Fri, Mar 22, 2024 at 9:13 AM  wrote:
>
> From: Pan Li 
>
> This patch would like to fix one ICE for __attribute__((target("arch=+v"))
> and likewise extension(s). Given we have sample code as below:
>
> void __attribute__((target("arch=+v")))
> test_2 (int *a, int *b, int *out, unsigned count)
> {
>   unsigned i;
>   for (i = 0; i < count; i++)
>out[i] = a[i] + b[i];
> }
>
> It will have ICE when build with -march=rv64gc -O3.
>
> test.c: In function ‘test_2’:
> test.c:4:1: internal compiler error: Floating point exception
> 4 | {
>   | ^
> 0x1a5891b crash_signal
> .../__RISC-V_BUILD__/../gcc/toplev.cc:319
> 0x7f0a7884251f ???
> ./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0
> 0x1f51ba4 riscv_hard_regno_nregs
> .../__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:8143
> 0x1967bb9 init_reg_modes_target()
> .../__RISC-V_BUILD__/../gcc/reginfo.cc:471
> 0x13fc029 init_emit_regs()
> .../__RISC-V_BUILD__/../gcc/emit-rtl.cc:6237
> 0x1a5b83d target_reinit()
> .../__RISC-V_BUILD__/../gcc/toplev.cc:1936
> 0x35e374d save_target_globals()
> .../__RISC-V_BUILD__/../gcc/target-globals.cc:92
> 0x35e381f save_target_globals_default_opts()
> .../__RISC-V_BUILD__/../gcc/target-globals.cc:122
> 0x1f544cc riscv_save_restore_target_globals(tree_node*)
> .../__RISC-V_BUILD__/../gcc/config/riscv/riscv.cc:9138
> 0x1f55c36 riscv_set_current_function
> ...
>
> There are two reasons for this ICE.
> 1. The implied extension(s) of v are not well handled and the
>TARGET_MIN_VLEN is 0 which is not reinitialized.  Then the
>size / TARGET_MIN_VLEN will have DivideByZero.
> 2. The machine modes of the vector types will be vary after
>the v extension is introduced.
>
> This patch passed below testsuite:
> 1. The riscv fully regression test.
>
> PR target/114352
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
> Replace implied, combine and check to func finalize.
> (riscv_subset_list::finalize): New func impl to take care of
> implied, combine ext and related checks.
> * config/riscv/riscv-subset.h: Add func decl for finalize.
> * config/riscv/riscv-target-attr.cc 
> (riscv_target_attr_parser::parse_arch):
> Finalize the ext before return succeed.
> * config/riscv/riscv.cc (riscv_set_current_function): Reinit the
> machine mode before when set cur function.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr114352-1.c: New test.
> * gcc.target/riscv/rvv/base/pr114352-2.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/common/config/riscv/riscv-common.cc   | 31 ++
>  gcc/config/riscv/riscv-subset.h   |  2 +
>  gcc/config/riscv/riscv-target-attr.cc |  2 +
>  gcc/config/riscv/riscv.cc |  4 ++
>  .../gcc.target/riscv/rvv/base/pr114352-1.c| 58 +++
>  .../gcc.target/riscv/rvv/base/pr114352-2.c| 27 +
>  6 files changed, 114 insertions(+), 10 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-2.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 440127a2af0..15d44245b3c 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -1428,16 +1428,7 @@ riscv_subset_list::parse (const char *arch, location_t 
> loc)
>if (p == NULL)
>  goto fail;
>
> -  for (itr = subset_list->m_head; itr != NULL; itr = itr->next)
> -{
> -  subset_list->handle_implied_ext (itr->name.c_str ());
> -}
> -
> -  /* Make sure all implied extensions are included. */
> -  gcc_assert (subset_list->check_implied_ext ());
> -
> -  subset_list->handle_combine_ext ();
> -  subset_list->check_conflict_ext ();
> +  subset_list->finalize ();
>
>return subset_list;
>
> @@ -1467,6 +1458,26 @@ riscv_subset_list::set_loc (location_t loc)
>m_loc = loc;
>  }
>
> +/* Make sure the implied or combined extension is included after add
> +   a new std extension to subset list or likewise.  For exmaple as below,
> +
> +   void __attribute__((target("arch=+v"))) func () with -march=rv64gc.
> +
> +   The implied zvl128b and zve64d of the std v should be included.  */
> +void
> +riscv_subset_list::finalize ()
> +{
> +  riscv_subset_t *subset;
> +
> +  for (subset = m_head; subset != NULL; subset = subset->next)
> +handle_implied_ext (subset->name.c_str ());
> +
> +  gcc_assert (check_implied_ext ());
> +
> +  handle_combine_ext ();
> +  check_conflict_ext ();
> +}
> +
>  /* Return the current arch string.  */
>
>  std::string
> diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
> index ae849e2a302..ec979040e8c 100644
> --- a/gcc/config/riscv/riscv-subset.h
> +++ 

Re: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV

[Kito Cheng]

> > &, ^, | has supported on clang, so I think we should support that as well
>
> Looks gcc lack of such operation right now, so mark the TYPE_INDIVISIBLE_P 
> (type) = 0 as aarch64 did.
> I have a try but I am afraid we need separated patch to take care of it for 
> risk control consideration.

Yeah, agree, that's defer this part to GCC 15 :)

Re: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV

[Kito Cheng]

Hi Stefan:

I admit that's kinda bad practice here, the spec should appear before
implementation or at least come together, however we have long
discussion on the RISC-V gcc community on this, and we give a waiver
for this feature due to the clang compatibility, and this features
also used on some project, so we would like to moving this forward
even it's incomplete.

For the spec part, we are working in progress and will put the draft soon.

On Fri, Mar 15, 2024 at 9:46 AM Li, Pan2  wrote:
>
> > Shouldn't a major user-facing change like this be discussed in a PR against
> > https://github.com/riscv-non-isa/riscv-c-api-doc/ or
> > https://github.com/riscv-non-isa/rvv-intrinsic-doc before or concurrent with
> > compiler implementation?
>
> I think Kito is working on the spec doc already.
>
> Hi Kito
> Could you please help to correct me the behavior of the riscv_rvv_vector_bits 
> attribute?
> Sort of details and I suspect there is something missing, or different 
> behavior compared with clang side.
>
> Pan
>
> -Original Message-
> From: Stefan O'Rear 
> Sent: Tuesday, March 12, 2024 9:25 PM
> To: Li, Pan2 ; gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; Kito Cheng ; Wang, Yanzhang 
> ; rdapp@gmail.com; Vineet Gupta 
> ; Palmer Dabbelt 
> Subject: Re: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits 
> for RVV
>
> On Tue, Mar 12, 2024, at 2:15 AM, pan2...@intel.com wrote:
> > From: Pan Li 
> >
> > Update in v3:
> > * Add pre-defined __riscv_v_fixed_vlen when zvl.
> >
> > Update in v2:
> > * Cleanup some unused code.
> > * Fix some typo of commit log.
> >
> > Original log:
> >
> > This patch would like to introduce one new gcc attribute for RVV.
> > This attribute is used to define fixed-length variants of one
> > existing sizeless RVV types.
> >
> > This attribute is valid if and only if the mrvv-vector-bits=zvl, the only
> > one args should be the integer constant and its' value is terminated
> > by the LMUL and the vector register bits in zvl*b.  For example:
> >
> > typedef vint32m2_t fixed_vint32m2_t 
> > __attribute__((riscv_rvv_vector_bits(128)));
> >
> > The above type define is valid when -march=rv64gc_zve64d_zvl64b
> > (aka 2(m2) * 64 = 128 for vin32m2_t), and will report error when
> > -march=rv64gcv_zvl128b similar to below.
> >
> > "error: invalid RVV vector size '128', expected size is '256' based on
> > LMUL of type and '-mrvv-vector-bits=zvl'"
> >
> > Meanwhile, a pre-define macro __riscv_v_fixed_vlen is introduced to
> > represent the fixed vlen in a RVV vector register.
>
> Shouldn't a major user-facing change like this be discussed in a PR against
> https://github.com/riscv-non-isa/riscv-c-api-doc/ or
> https://github.com/riscv-non-isa/rvv-intrinsic-doc before or concurrent with
> compiler implementation?
>
> -s
>
> > For the vint*m*_t below operations are allowed.
> > * The sizeof.
> > * The global variable(s).
> > * The element of union and struct.
> > * The cast to other equalities.
> > * CMP: >, <, ==, !=, <=, >=
> > * ALU: +, -, *, /, %, &, |, ^, >>, <<, ~, -
> >
> > For the vfloat*m*_t below operations are allowed.
> > * The sizeof.
> > * The global variable(s).
> > * The element of union and struct.
> > * The cast to other equalities.
> > * CMP: >, <, ==, !=, <=, >=
> > * ALU: +, -, *, /, -
> >
> > For the vbool*_t types only below operations are allowed except
> > the CMP and ALU. The CMP and ALU operations on vbool*_t is not
> > well defined currently.
> > * The sizeof.
> > * The global variable(s).
> > * The element of union and struct.
> > * The cast to other equalities.
> >
> > For the vint*x*m*_t tuple types are not suppored in this patch
> > which is compatible with clang.
> >
> > This patch passed the below testsuites.
> > * The riscv fully regression tests.
> >
> > gcc/ChangeLog:
> >
> >   * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
> >   macro __riscv_v_fixed_vlen when zvl.
> >   * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
> >   New static func to take care of the RVV types decorated by
> >   the attributes.
> >
> > gcc/testsuite/ChangeLog:
> >
> >   * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-1.c: New test.
> >   * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-10.c: New test.
> >   * gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-11.c: New

Re: [PATCH v3] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV

[Kito Cheng]

> For the vint*m*_t below operations are allowed.
> * The sizeof.
> * The global variable(s).
> * The element of union and struct.
> * The cast to other equalities.
> * CMP: >, <, ==, !=, <=, >=

The result of comparison should be vbool* rather than v[u]int*.

> * ALU: +, -, *, /, %, &, |, ^, >>, <<, ~, -
>
> For the vfloat*m*_t below operations are allowed.
> * The sizeof.
> * The global variable(s).
> * The element of union and struct.
> * The cast to other equalities.
> * CMP: >, <, ==, !=, <=, >=

The result of comparison should be vbool* rather than vfloat*,
otherwise all 1 is not really meanful for floating point value.

But I know clang generates the same strange/wrong code here...

> * ALU: +, -, *, /, -
>
> For the vbool*_t types only below operations are allowed except
> the CMP and ALU. The CMP and ALU operations on vbool*_t is not
> well defined currently.
> * The sizeof.
> * The global variable(s).
> * The element of union and struct.
> * The cast to other equalities.

&, ^, | has supported on clang, so I think we should support that as well

Re: [PATCH v1] RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))

[Kito Cheng]

> +
> +  /* Make sure the implied or combined extension is included after add
> + a new std extension to subset list.  For exmaple as below,
> +
> + void __attribute__((target("arch=+v"))) func () with -march=rv64gc.
> +
> + The implied zvl128b and zve64d of the std v should be included.  */
> +  handle_implied_ext (p);
> +  handle_combine_ext ();
> +  check_conflict_ext ();

Extract those 3 function calls to a public function
riscv_subset_list::finalize(),
and then call that at riscv_target_attr_parser::parse_arch rather than here.

> +
> +  return end_of_ext;
>  }

Re: [PATCH v2] RISC-V: Introduce option -mrvv-max-lmul for RVV autovec

[Kito Cheng]

LGTM too :)

On Mon, Mar 18, 2024 at 11:35 PM Robin Dapp  wrote:
>
> LGTM as well.
>
> Regards
>  Robin
>

Re: [PATCH v1] RISC-V: Bugfix function target attribute pollution

[Kito Cheng]

LGTM, thanks :)

On Wed, Mar 20, 2024 at 2:07 PM  wrote:
>
> From: Pan Li 
>
> This patch depends on below ICE fix.
>
> https://gcc.gnu.org/pipermail/gcc-patches/2024-March/647915.html
>
> The function target attribute should be on a per-function basis.
> For example, we have 3 function as below:
>
> void test_1 () {}
>
> void __attribute__((target("arch=+v"))) test_2 () {}
>
> void __attribute__((target("arch=+zfh"))) test_3 () {}
>
> void test_4 () {}
>
> The scope of the target attribute should not extend the function body.
> Aka, test_3 cannot have the 'v' extension, as well as the test_4
> cannot have both the 'v' and 'zfh' extension.
>
> Unfortunately, for now the test_4 is able to leverage the 'v' and
> the 'zfh' extension which is incorrect.  This patch would like to
> fix the sticking attribute by introduce the commandline subset_list.
> When parse_arch, we always clone from the cmdline_subset_list instead
> of the current_subset_list.
>
> Meanwhile, we correct the print information about arch like below.
>
> .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zbb1p0
>
> The riscv_declare_function_name hook is always after the hook
> riscv_process_target_attr.  Thus, we introduce one hash_map to record
> the 1:1 mapping from fndel to its' subset_list in advance.  And later
> the riscv_declare_function_name is able to get the right information
> about the arch.
>
> Below test are passed for this patch
> * The riscv fully regression test.
>
> PR target/114352
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
> New struct for func decl and target name.
> (struct riscv_func_target_hasher): New hasher for hash table mapping
> from the fn_decl to fn_target_name.
> (riscv_func_decl_hash): New func to compute the hash for fn_decl.
> (riscv_func_target_hasher::hash): New func to impl hash interface.
> (riscv_func_target_hasher::equal): New func to impl equal interface.
> (riscv_cmdline_subset_list): New static var for cmdline subset list.
> (riscv_func_target_table_lazy_init): New func to lazy init the func
> target hash table.
> (riscv_func_target_get): New func to get target name from hash table.
> (riscv_func_target_put): New func to put target name into hash table.
> (riscv_func_target_remove_and_destory): New func to remove target
> info from the hash table and destory it.
> (riscv_parse_arch_string): Set the static var cmdline_subset_list.
> * config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New static
> var for cmdline subset list.
> (riscv_func_target_get): New func decl.
> (riscv_func_target_put): Ditto.
> (riscv_func_target_remove_and_destory): Ditto.
> * config/riscv/riscv-target-attr.cc 
> (riscv_target_attr_parser::parse_arch):
> Take cmdline_subset_list instead of current_subset_list when clone.
> (riscv_process_target_attr): Record the func target info to hash 
> table.
> (riscv_option_valid_attribute_p): Add new arg tree fndel.
> * config/riscv/riscv.cc (riscv_declare_function_name): Consume the
> func target info and print the arch message.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr114352-3.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/common/config/riscv/riscv-common.cc   | 105 +++-
>  gcc/config/riscv/riscv-subset.h   |   4 +
>  gcc/config/riscv/riscv-target-attr.cc |  18 ++-
>  gcc/config/riscv/riscv.cc |   7 +-
>  .../gcc.target/riscv/rvv/base/pr114352-3.c| 113 ++
>  5 files changed, 240 insertions(+), 7 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index d32bf147eca..76ec9bf846c 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -425,11 +425,108 @@ bool riscv_subset_list::parse_failed = false;
>
>  static riscv_subset_list *current_subset_list = NULL;
>
> +static riscv_subset_list *cmdline_subset_list = NULL;
> +
> +struct riscv_func_target_info
> +{
> +  tree fn_decl;
> +  std::string fn_target_name;
> +
> +  riscv_func_target_info (const tree , const std::string _name)
> +: fn_decl (decl), fn_target_name (target_name)
> +  {
> +  }
> +};
> +
> +struct riscv_func_target_hasher : nofree_ptr_hash riscv_func_target_info>
> +{
> +  typedef tree compare_type;
> +
> +  static hashval_t hash (value_type);
> +  static bool equal (value_type, const compare_type &);
> +};
> +
> +static hash_table *func_target_table = NULL;
> +
> +static inline hashval_t riscv_func_decl_hash (tree fn_decl)
> +{
> +  inchash::hash h;
> +
> +  h.add_ptr (fn_decl);
> +
> +  return h.end ();
> +}
> +
> +inline hashval_t
> 

Re: [PATCH v1] RISC-V: Fix some code style issue(s) in riscv-c.cc [NFC]

[Kito Cheng]

LGTM :)

On Tue, Mar 12, 2024 at 3:07 PM  wrote:
>
> From: Pan Li 
>
> Notice some code style issue(s) when add __riscv_v_fixed_vlen, includes:
>
> * Meanless empty line.
> * Line greater than 80 chars.
> * Indent with 3 space(s).
> * Argument unalignment.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
> code style greater than 80 chars.
> (riscv_cpu_cpp_builtins): Fix useless empty line, indent
> with 3 space(s) and argument unalignment.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-c.cc | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
> index 3755ec0b8ef..7029ba88186 100644
> --- a/gcc/config/riscv/riscv-c.cc
> +++ b/gcc/config/riscv/riscv-c.cc
> @@ -37,7 +37,8 @@ along with GCC; see the file COPYING3.  If not see
>  static int
>  riscv_ext_version_value (unsigned major, unsigned minor)
>  {
> -  return (major * RISCV_MAJOR_VERSION_BASE) + (minor * 
> RISCV_MINOR_VERSION_BASE);
> +  return (major * RISCV_MAJOR_VERSION_BASE)
> ++ (minor * RISCV_MINOR_VERSION_BASE);
>  }
>
>  /* Implement TARGET_CPU_CPP_BUILTINS.  */
> @@ -110,7 +111,6 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
>  case CM_MEDANY:
>builtin_define ("__riscv_cmodel_medany");
>break;
> -
>  }
>
>if (riscv_user_wants_strict_align)
> @@ -142,9 +142,9 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
>  riscv_ext_version_value (0, 12));
>  }
>
> -   if (TARGET_XTHEADVECTOR)
> - builtin_define_with_int_value ("__riscv_th_v_intrinsic",
> -riscv_ext_version_value (0, 11));
> +  if (TARGET_XTHEADVECTOR)
> +builtin_define_with_int_value ("__riscv_th_v_intrinsic",
> +  riscv_ext_version_value (0, 11));
>
>/* Define architecture extension test macros.  */
>builtin_define_with_int_value ("__riscv_arch_test", 1);
> --
> 2.34.1
>

Re: [PATCH v2] RISC-V: Add riscv_vector_cc function attribute

[Kito Cheng]

LGTM, thanks :)

On Fri, Mar 1, 2024 at 5:10 PM Li Xu  wrote:
>
> From: xuli 
>
> Standard vector calling convention variant will only enabled when function
> has vector argument or returning value by default, however user may also
> want to invoke function without that during a vectorized loop at some 
> situation,
> but it will cause a huge performance penalty due to vector register 
> store/restore.
>
> So user can declare function with this riscv_vector_cc attribute like below, 
> that could enforce
> function will use standard vector calling convention variant.
>
> void foo() __attribute__((riscv_vector_cc));
> [[riscv::vector_cc]] void foo(); // For C++11 and C23
>
> For more details please reference the below link.
> https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
> attribute to riscv_attribute_table.
> (riscv_vector_cc_function_p): Return true if FUNC is a 
> riscv_vector_cc function.
> (riscv_fntype_abi): Add riscv_vector_cc attribute check.
> * doc/extend.texi: Add riscv_vector_cc attribute description.
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C: New 
> test.
> * gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c: 
> New test.
> * gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c: New 
> test.
> ---
>  gcc/config/riscv/riscv.cc | 55 ---
>  gcc/doc/extend.texi   | 10 
>  .../base/attribute-riscv_vector_cc-error.C| 21 +++
>  .../attribute-riscv_vector_cc-callee-saved.c  | 30 ++
>  .../base/attribute-riscv_vector_cc-error.c| 11 
>  5 files changed, 119 insertions(+), 8 deletions(-)
>  create mode 100644 
> gcc/testsuite/g++.target/riscv/rvv/base/attribute-riscv_vector_cc-error.C
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-error.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 4100abc9dd1..7f37f231796 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -537,24 +537,52 @@ static tree riscv_handle_fndecl_attribute (tree *, 
> tree, tree, int, bool *);
>  static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);
>
>  /* Defining target-specific uses of __attribute__.  */
> -TARGET_GNU_ATTRIBUTES (riscv_attribute_table,
> +static const attribute_spec riscv_gnu_attributes[] =
>  {
>/* Syntax: { name, min_len, max_len, decl_required, type_required,
>function_type_required, affects_type_identity, handler,
>exclude } */
>
>/* The attribute telling no prologue/epilogue.  */
> -  { "naked",   0,  0, true, false, false, false,
> -riscv_handle_fndecl_attribute, NULL },
> +  {"naked", 0, 0, true, false, false, false, riscv_handle_fndecl_attribute,
> +   NULL},
>/* This attribute generates prologue/epilogue for interrupt handlers.  */
> -  { "interrupt", 0, 1, false, true, true, false,
> -riscv_handle_type_attribute, NULL },
> +  {"interrupt", 0, 1, false, true, true, false, riscv_handle_type_attribute,
> +   NULL},
>
>/* The following two are used for the built-in properties of the Vector 
> type
>   and are not used externally */
>{"RVV sizeless type", 4, 4, false, true, false, true, NULL, NULL},
> -  {"RVV type", 0, 0, false, true, false, true, NULL, NULL}
> -});
> +  {"RVV type", 0, 0, false, true, false, true, NULL, NULL},
> +  /* This attribute is used to declare a function, forcing it to use the
> +standard vector calling convention variant. Syntax:
> +__attribute__((riscv_vector_cc)). */
> +  {"riscv_vector_cc", 0, 0, false, true, true, true, NULL, NULL}
> +};
> +
> +static const scoped_attribute_specs riscv_gnu_attribute_table  =
> +{
> +  "gnu", {riscv_gnu_attributes}
> +};
> +
> +static const attribute_spec riscv_attributes[] =
> +{
> +  /* This attribute is used to declare a function, forcing it to use the
> + standard vector calling convention variant. Syntax:
> + [[riscv::vector_cc]]. */
> +  {"vector_cc", 0, 0, false, true, true, true, NULL, NULL}
> +};
> +
> +static const scoped_attribute_specs riscv_nongnu_attribute_table =
> +{
> +  "riscv", {riscv_attributes}
> +};
> +
> +static const scoped_attribute_specs *const riscv_attribute_table[] =
> +{
> +  _gnu_attribute_table,
> +  _nongnu_attribute_table
> +};
>
>  /* Order for the CLOBBERs/USEs of gpr_save.  */
>  static const unsigned gpr_save_reg_order[] = {
> @@ -5425,6 +5453,16 @@ riscv_arguments_is_vector_type_p (const_tree fntype)
>return false;
>  }
>
> +/* Return true if FUNC is a riscv_vector_cc function.
> +   For more details please reference the below link.
> +   

Re: [PATCH] RISC-V: Add riscv_vector_cc function attribute

[Kito Cheng]

Thanks for your patch! this is generally in good shape, just a few
minor comments :)


> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index 2135dfde9c8..afe486ba47b 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -6314,6 +6314,18 @@ Permissible values for this parameter are @code{user}, 
> @code{supervisor},
>  and @code{machine}.  If there is no parameter, then it defaults to
>  @code{machine}.
>
> +@cindex @code{riscv_vector_cc} function attribute, RISC-V
> +@item riscv_vector_cc
> +Use this attribute to force the function to use the vector calling
> +convention variant.
> +For more information on riscv_vector_cc, please see
> +@uref{https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67}

Please remove above two line, I guess it's not good idea to reference
a pull request link here :P

> +
> +@smallexample
> +void foo() __attribute__((riscv_vector_cc));
> +[[riscv::vector_cc]] void foo(); // For C++11 and C23
> +@end smallexample
> +
>  @end table
>
>  The following target-specific function attributes are available for the

> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c
>  
> b/gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c
> new file mode 100644
> index 000..7db9d874bcd
> --- /dev/null
> +++ 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/attribute-riscv_vector_cc-callee-saved.c
> @@ -0,0 +1,117 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O1" } */
> +/* { dg-final { check-function-bodies "**" "" } } */

I would like to prevent scanning the asm body if possible, since it
might cause problem when we improving code gen, so could you try to
scan .variant_cc\t like
gcc/testsuite/gcc.target/aarch64/pcs_attribute-3.c?

Then we can also drop -O1 in the option :)

> +
> +#include 

Drop this.


> +void __attribute__((riscv_vector_cc))
> +foo2 (int a)
> +{
> +  int8_t data[1024];

Just char rather than int8_t, I would like to remove unnecessary
header including if possible :)

Re: [PATCH] RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64

[Kito Cheng]

Committed with Palmer's suggestions for the commit message, also I
plan to back port that to 11, 12 and 13 release branches :)

On Thu, Feb 29, 2024 at 4:27 AM Palmer Dabbelt  wrote:
>
> On Wed, 28 Feb 2024 09:36:38 PST (-0800), Patrick O'Neill wrote:
> >
> > On 2/28/24 07:02, Palmer Dabbelt wrote:
> >> On Wed, 28 Feb 2024 06:57:53 PST (-0800), jeffreya...@gmail.com wrote:
> >>>
> >>>
> >>> On 2/28/24 05:23, Kito Cheng wrote:
> >>>> atomic_compare_and_swapsi will use lr.w and sc.w to do the atomic
> >>>> operation on
> >>>> RV64, however lr.w is doing sign extend to DI and compare
> >>>> instruction only have
> >>>> DI mode on RV64, so the expected value should be sign extend before
> >>>> compare as
> >>>> well, so that we can get right compare result.
> >>>>
> >>>> gcc/ChangeLog:
> >>>>
> >>>> PR target/114130
> >>>> * config/riscv/sync.md (atomic_compare_and_swap): Sign
> >>>> extend the expected value if needed.
> >>>>
> >>>> gcc/testsuite/ChangeLog:
> >>>>
> >>>> * gcc.target/riscv/pr114130.c: New.
> >>> Nearly rejected this as I think the description was a bit ambiguous and
> >>> I thought you were extending the result of the lr.w.  But it's actually
> >>> the other value you're ensuring gets properly extended.
> >>
> >> I had the same response, but after reading it I'm not quite sure how
> >> to say it better.
>
> Maybe something like
>
> atomic_compare_and_swapsi will use lr.w to do obtain the original value,
> which sign extends to DI.  RV64 only has DI comparisons, so we also need
> to sign extend the expected value to DI as otherwise the comparison will
> fail when the expected value has the 32nd bit set.
>
> would do it?  Either way
>
> Reviewed-by: Palmer Dabbelt 
>
> as I've managed to convince myself it's correct.  We should probably
> backport this one, the bug has likely been around for a while.
>
> >>
> >>> OK.
> >>
> >> I was looking at the code to try and ask if we have the same bug for
> >> the short inline CAS routines, but I've got to run to some meetings...
> >
> > I don't think subword AMO CAS is impacted.
> >
> > As part of the CAS we mask both the expected value [2] and the retrieved
> > value[1] before comparing.
>
> I'm always a bit lost when it comes to bit arithmetic, but I think it's
> OK.  It smells like it's being a little loose with the
> extensions/comparisons, but just looking at some generated code for this
> simple case:
>
> void foo(uint16_t *p, uint16_t *e, uint16_t *d) {
> __atomic_compare_exchange(p, e, d, 0, __ATOMIC_RELAXED, 
> __ATOMIC_RELAXED);
> }
>
> foo:
> lhu a3,0(a2)
> lhu a2,0(a1)
> andia4,a0,3
> li  a5,65536
> slliw   a4,a4,3
> addiw   a5,a5,-1
> sllwa5,a5,a4
> sllwa3,a3,a4
> sllwa7,a2,a4
> andia0,a0,-4
> and a3,a3,a5
> not t1,a5
> and a7,a7,a5
> 1:
> lr.wa6, 0(a0)
> and t3, a6, a5// Both a6 (from the lr.w) and a5
>   // (from the sllw) are sign extended,
>   // so the result in t3 is sign extended.
> bne t3, a7, 1f// a7 is also sign extended (before
>   // and after the masking above), so
>   // it's safe for comparison
> and t3, a6, t1
> or  t3, t3, a3
> sc.wt3, t3, 0(a0) // The top bits of t3 end up polluted
>   // with sign extension, but it doesn't
>   // matter because of the sc.w.
> bnezt3, 1b
> 1:
> srawa6,a6,a4
> slliw   a2,a2,16
> slliw   a5,a6,16
> sraiw   a2,a2,16
> sraiw   a5,a5,16
> subwa5,a5,a2
> beq a5,zero,.L1
> sh  a6,0(a1)
> .L1:
> ret
>
> So I think we're OK -- that masking of a7 looks redundant here, but I
> don't think we could get away with just
>
> diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
> index 54bb0a66518..15956940032 100644
&

Re: Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Kito Cheng]

Hmm, maybe only keep --param=riscv-autovec-preference=none and remove other
two if we think that might still useful? But anyway I have no strong
opinion to keep that, I mean I am ok to remove whole
--param=riscv-autovec-preference.

钟居哲  於 2024年2月28日 週三 21:59 寫道：

> I think it makes more sense to remove --param=riscv-autovec-preference and
> add -mrvv-vector-bits
>
> --
> juzhe.zh...@rivai.ai
>
>
> *From:* Kito Cheng 
> *Date:* 2024-02-28 20:56
> *To:* pan2.li 
> *CC:* gcc-patches ; juzhe.zhong
> ; yanzhang.wang ; rdapp.gcc
> ; jeffreyalaw 
> *Subject:* Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits
> for RVV
> Take one more look, I think this option should work and integrate with
> --param=riscv-autovec-preference= since they have similar jobs but
> slightly different.
>
> We have 3 value for  --param=riscv-autovec-preference=: none, scalable
> and fixed-vlmax
>
> -mrvv-vector-bits=scalable is work like
> --param=riscv-autovec-preference=scalable and
> -mrvv-vector-bits=zvl is work like
> --param=riscv-autovec-preference=fixed-vlmax.
>
> So I think...we need to do some conflict check, like:
>
> -mrvv-vector-bits=zvl can't work with
> --param=riscv-autovec-preference=scalable
> -mrvv-vector-bits=scalable can't work with
> --param=riscv-autovec-preference=fixed-vlmax
>
> but it may not just alias since there is some useful combinations like:
>
> -mrvv-vector-bits=zvl with --param=riscv-autovec-preference=none:
> NO auto vectorization but intrinsic code still could benefit from the
> -mrvv-vector-bits=zvl option.
>
> -mrvv-vector-bits=scalable with --param=riscv-autovec-preference=none
> Should still work for VLS code gen, but just disable auto
> vectorization per the option semantic.
>
> However here is something we need some fix, since
> --param=riscv-autovec-preference=none still disable VLS code gen for
> now, you can see some example here:
> https://godbolt.org/z/fMTr3eW7K
>
> But I think it's really the right behavior here, this part might need
> to be fixed in vls_mode_valid_p and some other places.
>
>
> Anyway I think we need to check all use sites with RVV_FIXED_VLMAX and
> RVV_SCALABLE, and need to make sure all use site of RVV_FIXED_VLMAX
> also checked with RVV_VECTOR_BITS_ZVL.
>
>
>
> > -/* Return the VLEN value associated with -march.
> > +static int
> > +riscv_convert_vector_bits (int min_vlen)
>
> Not sure if we really need this function, it seems it always returns
> min_vlen?
>
> > +{
> > +  int rvv_bits = 0;
> > +
> > +  switch (rvv_vector_bits)
> > +{
> > +  case RVV_VECTOR_BITS_ZVL:
> > +  case RVV_VECTOR_BITS_SCALABLE:
> > +   rvv_bits = min_vlen;
> > +   break;
> > +  default:
> > +   gcc_unreachable ();
> > +}
> > +
> > +  return rvv_bits;
> > +}
> > +
> > +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
>
>
>

Re: [PATCH v3] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Kito Cheng]

Take one more look, I think this option should work and integrate with
--param=riscv-autovec-preference= since they have similar jobs but
slightly different.

We have 3 value for  --param=riscv-autovec-preference=: none, scalable
and fixed-vlmax

-mrvv-vector-bits=scalable is work like
--param=riscv-autovec-preference=scalable and
-mrvv-vector-bits=zvl is work like
--param=riscv-autovec-preference=fixed-vlmax.

So I think...we need to do some conflict check, like:

-mrvv-vector-bits=zvl can't work with --param=riscv-autovec-preference=scalable
-mrvv-vector-bits=scalable can't work with
--param=riscv-autovec-preference=fixed-vlmax

but it may not just alias since there is some useful combinations like:

-mrvv-vector-bits=zvl with --param=riscv-autovec-preference=none:
NO auto vectorization but intrinsic code still could benefit from the
-mrvv-vector-bits=zvl option.

-mrvv-vector-bits=scalable with --param=riscv-autovec-preference=none
Should still work for VLS code gen, but just disable auto
vectorization per the option semantic.

However here is something we need some fix, since
--param=riscv-autovec-preference=none still disable VLS code gen for
now, you can see some example here:
https://godbolt.org/z/fMTr3eW7K

But I think it's really the right behavior here, this part might need
to be fixed in vls_mode_valid_p and some other places.


Anyway I think we need to check all use sites with RVV_FIXED_VLMAX and
RVV_SCALABLE, and need to make sure all use site of RVV_FIXED_VLMAX
also checked with RVV_VECTOR_BITS_ZVL.



> -/* Return the VLEN value associated with -march.
> +static int
> +riscv_convert_vector_bits (int min_vlen)

Not sure if we really need this function, it seems it always returns min_vlen?

> +{
> +  int rvv_bits = 0;
> +
> +  switch (rvv_vector_bits)
> +{
> +  case RVV_VECTOR_BITS_ZVL:
> +  case RVV_VECTOR_BITS_SCALABLE:
> +   rvv_bits = min_vlen;
> +   break;
> +  default:
> +   gcc_unreachable ();
> +}
> +
> +  return rvv_bits;
> +}
> +
> +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.

[PATCH] RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64

[Kito Cheng]

atomic_compare_and_swapsi will use lr.w and sc.w to do the atomic operation on
RV64, however lr.w is doing sign extend to DI and compare instruction only have
DI mode on RV64, so the expected value should be sign extend before compare as
well, so that we can get right compare result.

gcc/ChangeLog:

PR target/114130
* config/riscv/sync.md (atomic_compare_and_swap): Sign
extend the expected value if needed.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr114130.c: New.
---
 gcc/config/riscv/sync.md  |  9 +
 gcc/testsuite/gcc.target/riscv/pr114130.c | 12 
 2 files changed, 21 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr114130.c

diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 54bb0a66518..6f0b5aae08d 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -353,6 +353,15 @@
(match_operand:SI 7 "const_int_operand" "")] ;; mod_f
   "TARGET_ATOMIC"
 {
+  if (word_mode != mode && operands[3] != const0_rtx)
+{
+  /* We don't have SI mode compare on RV64, so we need to make sure 
expected
+value is sign-extended.  */
+  rtx tmp0 = gen_reg_rtx (word_mode);
+  emit_insn (gen_extend_insn (tmp0, operands[3], word_mode, mode, 
0));
+  operands[3] = simplify_gen_subreg (mode, tmp0, word_mode, 0);
+}
+
   emit_insn (gen_atomic_cas_value_strong (operands[1], operands[2],
operands[3], operands[4],
operands[6], operands[7]));
diff --git a/gcc/testsuite/gcc.target/riscv/pr114130.c 
b/gcc/testsuite/gcc.target/riscv/pr114130.c
new file mode 100644
index 000..647e27dab32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr114130.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64" } */
+#include 
+
+void foo(uint32_t *p) {
+uintptr_t x = *(uintptr_t *)p;
+uint32_t e = !p ? 0 : (uintptr_t)p >> 1;
+uint32_t d = (uintptr_t)x;
+__atomic_compare_exchange(p, , , 0, __ATOMIC_RELAXED, 
__ATOMIC_RELAXED);
+}
+
+/* { dg-final { scan-assembler-bound {sext.w\t} >= 1 } } */
-- 
2.34.1

Re: [PATCH v2] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Kito Cheng]

Keep SCALABLE, since it has different semantics with ZVL:

-mrvv-vector-bits=scalble means zvl*b specify the minimal VLEN
-mrvv-vector-bits=zvl means zvl*b specify the exactly VLEN

What's difference exactly?

-mrvv-vector-bits=scalble with zvl128b can run on any machine with VLEN >= 128
-mrvv-vector-bits=zvl with zvl128b can *only* run on the machine with
VLEN == 128

Sizeof vint32m1_t is VLEN under -mrvv-vector-bits=scalble with zvl128b
Sizeof vint32m1_t is 128 under -mrvv-vector-bits=zvl with zvl128b

Give more practical example on codegen with clang:
https://godbolt.org/z/vhdnGvK37

So it more like alias of
--param=riscv-autovec-preference=fixed-vlmax/--param=riscv-autovec-preference=scalable.

On Wed, Feb 28, 2024 at 12:17 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to introduce one new gcc option for RVV. To
> appoint the bits size of one RVV vector register. Valid arguments to
> '-mrvv-vector-bits=' are:
>
> * zvl
>
> The zvl will pick up the zvl*b from the march option. For example,
> the mrvv-vector-bits will be 1024 when march=rv64gcv_zvl1024b.
>
> The below test are passed for this patch.
>
> * The riscv fully regression test.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for
> different RVV vector bits.
> * config/riscv/riscv.cc (riscv_convert_vector_bits): New func to
> get the RVV vector bits, with given min_vlen.
> (riscv_convert_vector_chunks): Combine the mrvv-vector-bits
> option with min_vlen to RVV vector chunks.
> (riscv_override_options_internal): Update comments and rename the
> vector chunks.
> * config/riscv/riscv.opt: Add option mrvv-vector-bits.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
> * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
> * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-opts.h |  7 +
>  gcc/config/riscv/riscv.cc | 31 +++
>  gcc/config/riscv/riscv.opt| 11 +++
>  .../riscv/rvv/base/rvv-vector-bits-1.c|  7 +
>  .../riscv/rvv/base/rvv-vector-bits-2.c|  7 +
>  .../riscv/rvv/base/rvv-vector-bits-3.c| 25 +++
>  6 files changed, 82 insertions(+), 6 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 4edddbadc37..0162e00515b 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -129,6 +129,13 @@ enum vsetvl_strategy_enum {
>VSETVL_OPT_NO_FUSION,
>  };
>
> +/* RVV vector bits for option -mrvv-vector-bits
> +   zvl indicates take the bits of zvl*b provided by march as vector bits.
> + */
> +enum rvv_vector_bits_enum {
> +  RVV_VECTOR_BITS_ZVL,
> +};
> +
>  #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && 
> TARGET_64BIT))
>
>  /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 5e984ee2a55..d18e5226bce 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -8801,13 +8801,32 @@ riscv_init_machine_status (void)
>return ggc_cleared_alloc ();
>  }
>
> -/* Return the VLEN value associated with -march.
> +static int
> +riscv_convert_vector_bits (int min_vlen)
> +{
> +  int rvv_bits = 0;
> +
> +  switch (rvv_vector_bits)
> +{
> +  case RVV_VECTOR_BITS_ZVL:
> +   rvv_bits = min_vlen;
> +   break;
> +  default:
> +   gcc_unreachable ();
> +}
> +
> +  return rvv_bits;
> +}
> +
> +/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
> TODO: So far we only support length-agnostic value. */
>  static poly_uint16
> -riscv_convert_vector_bits (struct gcc_options *opts)
> +riscv_convert_vector_chunks (struct gcc_options *opts)
>  {
>int chunk_num;
>int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
> +  int rvv_bits = riscv_convert_vector_bits (min_vlen);
> +
>if (min_vlen > 32)
>  {
>/* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
> @@ -8826,7 +8845,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
>- TARGET_MIN_VLEN = 2048bit: [256,256]
>- TARGET_MIN_VLEN = 4096bit: [512,512]
>FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit.  */
> -  chunk_num = min_vlen / 64;
> +  chunk_num = rvv_bits / 64;
>  }
>else
>  {
> @@ -8848,7 +8867,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
>if (TARGET_VECTOR_OPTS_P (opts))
>  {
>if 

Re: [PATCH v1] RISC-V: Upgrade RVV intrinsic version to 0.12

[Kito Cheng]

On Fri, Feb 23, 2024 at 3:48 AM Palmer Dabbelt  wrote:
>
> On Wed, 21 Feb 2024 16:02:50 PST (-0800), Kito Cheng wrote:
> > Palmer Dabbelt  於 2024年2月22日 週四 07:42 寫道：
> >
> >> On Wed, 21 Feb 2024 15:34:32 PST (-0800), Kito Cheng wrote:
> >> > LGTM for the patch
> >> >
> >> > Li, Pan2  於 2024年2月21日 週三 12:31 寫道：
> >> >
> >> >> Hi kito and juzhe.
> >> >>
> >> >> There may be 2 items for double-confirm. Thanks a lot.
> >> >>
> >> >> 1. Not very sure if we need to upgrade the version for
> >> >> __riscv_th_v_intrinsic.
> >> >>
> >> >
> >> > Yes since 0.11 and 0.12 is not really compatible
> >>
> >> Where are the incompatibilities?  The whole reason we accepted the
> >> intrinsics in the first place is because the RVI folks said they
> >> wouldn't break compatibility, if that's changed then just dropping the
> >> old version is going to break users.
> >>
> >
> > 0.12 have interface for segment load store and new fixed points intrinsic
> > compare to 0.11, the first one item is not incompatible change since it's
> > new added and gcc 13 isn't implemented the legacy one, the later one is
> > kinda broken on both llvm and gcc which is made is not really useful in
> > practice.
> >
> > Other than that, everything are same, it's not 100% compatible so I am not
> > intend to cheating my self to say it's compatible, but we do think it's
> > necessary evil since fixing point stuff are not right design and
> > implementation.
>
> OK, those don't seem so scary.  So maybe let's just put it in a NEWS
> entry or something?  It's mildly interesting to users, but I agree the
> earlier intrinsics spec was vague enough in some areas we can get away
> with the diffs I've seen.

Yeah, thanks for the reminder, I guess we need to prepare to update
more NEWS entries...

>
> > Anyway it's became frozen mode, 1.0 rc0 has been tagged, no API will
> > change/remove.
>
> OK, so I guess we should move to 1.0, then?  Are you guys going to pick
> that up?

No difference between 0.12 and 1.0...here is just some paperwork for
the process that is still ongoing...but anyway we will handle that.

Re: [PATCH v1] RISC-V: Introduce gcc option mrvv-vector-bits for RVV

[Kito Cheng]

I would prefer to only keep zvl and scalable or zvl only, since I
don't see too much value in specifying a value which different from
zvl*b, that's a legacy option used before zvl*b option was introduced,
and the reason to add that is that could used for compatible with
clang/LLVM for riscv_rvv_vector_bits attribute I think?

On Fri, Feb 23, 2024 at 4:06 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to introduce one new gcc option for RVV. To
> appoint the bits size of one RVV vector register. Valid arguments to
> '-mrvv-vector-bits=' are:
>
> * 64
> * 128
> * 256
> * 512
> * 1024
> * 2048
> * 4096
> * 8192
> * 16384
> * 32768
> * 65536
> * scalable
> * zvl
>
> 1. The scalable will be the default values which take min_vlen for
>the riscv_vector_chunks.
> 2. The zvl will pick up the zvl*b from the march option. For example,
>the mrvv-vector-bits will be 1024 when march=rv64gcv_zvl1024b.
> 3. Otherwise, it will take the value provide and complain error if none
>of above valid value is given.
>
> This option may influence the code gen when auto-vector. For example,
>
> void test_rvv_vector_bits (int *a, int *b, int *out)
> {
>   for (int i = 0; i < 8; i++)
> out[i] = a[i] + b[i];
> }
>
> It will generate code similar to below when build with
>   -march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl
>
> test_rvv_vector_bits:
>   ...
>   vsetivli  zero,4,e32,m1,ta,ma
>   vle32.v   v1,0(a0)
>   vle32.v   v2,0(a1)
>   vadd.vv   v1,v1,v2
>   vse32.v   v1,0(a2)
>   ...
>   vle32.v   v1,0(a0)
>   vle32.v   v2,0(a1)
>   vadd.vv   v1,v1,v2
>   vse32.v   v1,0(a2)
>
> And it will become more simply similar to below when build with
>   -march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=256
>
> test_rvv_vector_bits:
>   ...
>   vsetivli  zero,8,e32,m2,ta,ma
>   vle32.v   v2,0(a0)
>   vle32.v   v4,0(a1)
>   vadd.vv   v2,v2,v4
>   vse32.v   v2,0(a2)
>
> Passed the regression test of rvv.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for
> different RVV vector bits.
> * config/riscv/riscv.cc (riscv_convert_vector_bits): New func to
> get the RVV vector bits, with given min_vlen.
> (riscv_convert_vector_chunks): Combine the mrvv-vector-bits
> option with min_vlen to RVV vector chunks.
> (riscv_override_options_internal): Update comments and rename the
> vector chunks.
> * config/riscv/riscv.opt: Add option mrvv-vector-bits.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
> * gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
> * gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.
> * gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-opts.h | 16 ++
>  gcc/config/riscv/riscv.cc | 49 ---
>  gcc/config/riscv/riscv.opt| 47 ++
>  .../riscv/rvv/base/rvv-vector-bits-1.c|  6 +++
>  .../riscv/rvv/base/rvv-vector-bits-2.c| 20 
>  .../riscv/rvv/base/rvv-vector-bits-3.c| 25 ++
>  .../riscv/rvv/base/rvv-vector-bits-4.c|  6 +++
>  7 files changed, 163 insertions(+), 6 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 4edddbadc37..b2141190731 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -129,6 +129,22 @@ enum vsetvl_strategy_enum {
>VSETVL_OPT_NO_FUSION,
>  };
>
> +enum rvv_vector_bits_enum {
> +  RVV_VECTOR_BITS_SCALABLE,
> +  RVV_VECTOR_BITS_ZVL,
> +  RVV_VECTOR_BITS_64 = 64,
> +  RVV_VECTOR_BITS_128 = 128,
> +  RVV_VECTOR_BITS_256 = 256,
> +  RVV_VECTOR_BITS_512 = 512,
> +  RVV_VECTOR_BITS_1024 = 1024,
> +  RVV_VECTOR_BITS_2048 = 2048,
> +  RVV_VECTOR_BITS_4096 = 4096,
> +  RVV_VECTOR_BITS_8192 = 8192,
> +  RVV_VECTOR_BITS_16384 = 16384,
> +  RVV_VECTOR_BITS_32768 = 32768,
> +  RVV_VECTOR_BITS_65536 = 65536,
> +};
> +
>  #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && 
> TARGET_64BIT))
>
>  /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 5e984ee2a55..366d7ece383 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -8801,13 +8801,50 @@ riscv_init_machine_status (void)
>return ggc_cleared_alloc ();
>  }
>
> -/* Return the VLEN value associated with -march.
> +static int
> 

Re: [PATCH] RISC-V: Point our Python scripts at python3

[Kito Cheng]

I guess Palmer is too busy, so committed to trunk :P

On Tue, Feb 13, 2024 at 11:55 PM Jeff Law  wrote:
>
>
>
> On 2/9/24 09:53, Palmer Dabbelt wrote:
> > This builds for me, and I frequently have python-is-python3 type
> > packages installed so I think I've been implicitly testing it for a
> > while.  Looks like Kito's tested similar configurations, and the
> > bugzilla indicates we should be moving over.
> >
> > gcc/ChangeLog:
> >
> >   PR 109668
> >   * config/riscv/arch-canonicalize: Move to python3
> >   * config/riscv/multilib-generator: Likewise
> Just to summarize from the coordination call this morning.  We've agreed
> this should go forward.  While there is minor risk (this code is rarely
> run), it's something we're prepared to handle if there is fallout.
>
> Jeff

Re: [PATCH] doc: RISC-V: Document that -mcpu doesn't override -march or -mtune

[Kito Cheng]

LGTM, and committed :)

On Tue, Feb 20, 2024 at 11:46 PM Palmer Dabbelt  wrote:
>
> This came up recently as Edwin was looking through the test suite.  A
> few of us were talking about this during the patchwork meeting and were
> surprised.  Looks like this is the desired behavior, so let's at least
> document it.
>
> gcc/ChangeLog:
>
> * doc/invoke.texi: Document -mcpu.
>
> Signed-off-by: Palmer Dabbelt 
> ---
>  gcc/doc/invoke.texi | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 6ec56493e59..4a4bba9f1cd 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -30670,6 +30670,8 @@ Permissible values for this option are: 
> @samp{sifive-e20}, @samp{sifive-e21},
>  @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76},
>  @samp{sifive-u54}, @samp{sifive-u74}, and @samp{sifive-x280}.
>
> +Note that @option{-mcpu} does not override @option{-march} or 
> @option{-mtune}.
> +
>  @opindex mtune
>  @item -mtune=@var{processor-string}
>  Optimize the output for the given processor, specified by microarchitecture 
> or
> --
> 2.43.0
>

Re: [PATCH] RISC-V: Add tests for constraints "i" and "s"

[Kito Cheng]

LGTM, but I am OoO today, will commit that once I have laptop :p

Fangrui Song  於 2024年2月22日 週四 05:54 寫道：

> On Tue, Feb 13, 2024 at 10:36 PM Fangrui Song  wrote:
> >
> > The constraints "i" and "s" can be used with a symbol that binds
> > externally, e.g.
> > ```
> > namespace ns { extern int var, a[4]; }
> > void foo() {
> >   asm(".pushsection .xxx,\"aw\"; .dc.a %0; .popsection" ::
> "s"(::var));
> >   asm(".reloc ., BFD_RELOC_NONE, %0" :: "s"(::a[3]));
> > }
> > ```
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/asm-raw-symbol.c: New test.
> > ---
> >  gcc/doc/md.texi |  2 +-
> >  gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c | 14 ++
> >  2 files changed, 15 insertions(+), 1 deletion(-)
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c
> >
> > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> > index b0c61925120..c75e5bf259d 100644
> > --- a/gcc/doc/md.texi
> > +++ b/gcc/doc/md.texi
> > @@ -1947,7 +1947,7 @@ Integer constant that is valid as an immediate
> operand in a 64-bit @code{MOV}
> >  pseudo instruction
> >
> >  @item S
> > -An absolute symbolic address or a label reference
> > +A symbolic reference or label reference.
> >
> >  @item Y
> >  Floating point constant zero
> > diff --git a/gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c
> b/gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c
> > new file mode 100644
> > index 000..28305a8b1f0
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c
> > @@ -0,0 +1,14 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-fpic" } */
> > +
> > +extern int var, arr[2][2];
> > +
> > +void
> > +test (void)
> > +{
> > +  __asm__ ("@ %0" : : "i"());
> > +  __asm__ ("@ %0 %1 %2" : : "s"(), "s"([1][1]), "s"(test));
> > +}
> > +
> > +/* { dg-final { scan-assembler "@ var arr\\+12 test" } } */
> > +/* { dg-final { scan-assembler "@ var" } } */
> > --
> > 2.43.0.687.g38aa6559b0-goog
> >
>
> Ping:)
>
>
> --
> 宋方睿
>

Re: [PATCH v1] RISC-V: Upgrade RVV intrinsic version to 0.12

[Kito Cheng]

Palmer Dabbelt  於 2024年2月22日 週四 07:42 寫道：

> On Wed, 21 Feb 2024 15:34:32 PST (-0800), Kito Cheng wrote:
> > LGTM for the patch
> >
> > Li, Pan2  於 2024年2月21日 週三 12:31 寫道：
> >
> >> Hi kito and juzhe.
> >>
> >> There may be 2 items for double-confirm. Thanks a lot.
> >>
> >> 1. Not very sure if we need to upgrade the version for
> >> __riscv_th_v_intrinsic.
> >>
> >
> > Yes since 0.11 and 0.12 is not really compatible
>
> Where are the incompatibilities?  The whole reason we accepted the
> intrinsics in the first place is because the RVI folks said they
> wouldn't break compatibility, if that's changed then just dropping the
> old version is going to break users.
>

0.12 have interface for segment load store and new fixed points intrinsic
compare to 0.11, the first one item is not incompatible change since it's
new added and gcc 13 isn't implemented the legacy one, the later one is
kinda broken on both llvm and gcc which is made is not really useful in
practice.

Other than that, everything are same, it's not 100% compatible so I am not
intend to cheating my self to say it's compatible, but we do think it's
necessary evil since fixing point stuff are not right design and
implementation.

Anyway it's became frozen mode, 1.0 rc0 has been tagged, no API will
change/remove.


> > 2. Do we need to upgrade the even a newer version (like 1.0) for the GCC
> 14
> >> release, or we can do it later.
> >>
> >
> > Yeah, Ideal case is we can update that before release made :p
> >
> >
> >
> >
> >> Pan
> >>
> >> -Original Message-
> >> From: Li, Pan2 
> >> Sent: Wednesday, February 21, 2024 12:27 PM
> >> To: gcc-patches@gcc.gnu.org
> >> Cc: juzhe.zh...@rivai.ai; Li, Pan2 ; Wang, Yanzhang
> <
> >> yanzhang.w...@intel.com>; kito.ch...@gmail.com
> >> Subject: [PATCH v1] RISC-V: Upgrade RVV intrinsic version to 0.12
> >>
> >> From: Pan Li 
> >>
> >> Upgrade the version of RVV intrinsic from 0.11 to 0.12.
> >>
> >> PR target/114017
> >>
> >> gcc/ChangeLog:
> >>
> >> * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
> >> the version to 0.12.
> >>
> >> gcc/testsuite/ChangeLog:
> >>
> >> * gcc.target/riscv/predef-__riscv_v_intrinsic.c: Update the
> >> version to 0.12.
> >> * gcc.target/riscv/rvv/base/pr114017-1.c: New test.
> >>
> >> Signed-off-by: Pan Li 
> >> ---
> >>  gcc/config/riscv/riscv-c.cc   |  2 +-
> >>  .../riscv/predef-__riscv_v_intrinsic.c|  2 +-
> >>  .../gcc.target/riscv/rvv/base/pr114017-1.c| 19 +++
> >>  3 files changed, 21 insertions(+), 2 deletions(-)
> >>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c
> >>
> >> diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
> >> index 3ef06dcfd2d..3755ec0b8ef 100644
> >> --- a/gcc/config/riscv/riscv-c.cc
> >> +++ b/gcc/config/riscv/riscv-c.cc
> >> @@ -139,7 +139,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
> >>  {
> >>builtin_define ("__riscv_vector");
> >>builtin_define_with_int_value ("__riscv_v_intrinsic",
> >> -riscv_ext_version_value (0, 11));
> >> +riscv_ext_version_value (0, 12));
> >>  }
> >>
> >> if (TARGET_XTHEADVECTOR)
> >> diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
> >> b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
> >> index dbbedf54f87..07f1f159a8f 100644
> >> --- a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
> >> +++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
> >> @@ -3,7 +3,7 @@
> >>
> >>  int main () {
> >>
> >> -#if __riscv_v_intrinsic != 11000
> >> +#if __riscv_v_intrinsic != 12000
> >>  #error "__riscv_v_intrinsic"
> >>  #endif
> >>
> >> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c
> >> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c
> >> new file mode 100644
> >> index 000..8eee7c68f71
> >> --- /dev/null
> >> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c
> >> @@ -0,0 +1,19 @@
> >> +/* { dg-do compile } */
> >> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> >> +
> >> +#include "riscv_vector.h"
> >> +
> >> +vuint8mf2_t
> >> +test (vuint16m1_t val, size_t shift, size_t vl)
> >> +{
> >> +#if __riscv_v_intrinsic == 11000
> >> +  #warning "RVV Intrinsics v0.11"
> >> +  return __riscv_vnclipu (val, shift, vl);
> >> +#endif
> >> +
> >> +#if __riscv_v_intrinsic == 12000
> >> +  #warning "RVV Intrinsics v0.12" /* { dg-warning "RVV Intrinsics
> v0.12"
> >> } */
> >> +  return __riscv_vnclipu (val, shift, 0, vl);
> >> +#endif
> >> +}
> >> +
> >> --
> >> 2.34.1
> >>
> >>
>

Re: [PATCH v1] RISC-V: Upgrade RVV intrinsic version to 0.12

[Kito Cheng]

LGTM for the patch

Li, Pan2  於 2024年2月21日 週三 12:31 寫道：

> Hi kito and juzhe.
>
> There may be 2 items for double-confirm. Thanks a lot.
>
> 1. Not very sure if we need to upgrade the version for
> __riscv_th_v_intrinsic.
>

Yes since 0.11 and 0.12 is not really compatible


2. Do we need to upgrade the even a newer version (like 1.0) for the GCC 14
> release, or we can do it later.
>

Yeah, Ideal case is we can update that before release made :p




> Pan
>
> -Original Message-
> From: Li, Pan2 
> Sent: Wednesday, February 21, 2024 12:27 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; Li, Pan2 ; Wang, Yanzhang <
> yanzhang.w...@intel.com>; kito.ch...@gmail.com
> Subject: [PATCH v1] RISC-V: Upgrade RVV intrinsic version to 0.12
>
> From: Pan Li 
>
> Upgrade the version of RVV intrinsic from 0.11 to 0.12.
>
> PR target/114017
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
> the version to 0.12.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/predef-__riscv_v_intrinsic.c: Update the
> version to 0.12.
> * gcc.target/riscv/rvv/base/pr114017-1.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-c.cc   |  2 +-
>  .../riscv/predef-__riscv_v_intrinsic.c|  2 +-
>  .../gcc.target/riscv/rvv/base/pr114017-1.c| 19 +++
>  3 files changed, 21 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c
>
> diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
> index 3ef06dcfd2d..3755ec0b8ef 100644
> --- a/gcc/config/riscv/riscv-c.cc
> +++ b/gcc/config/riscv/riscv-c.cc
> @@ -139,7 +139,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
>  {
>builtin_define ("__riscv_vector");
>builtin_define_with_int_value ("__riscv_v_intrinsic",
> -riscv_ext_version_value (0, 11));
> +riscv_ext_version_value (0, 12));
>  }
>
> if (TARGET_XTHEADVECTOR)
> diff --git a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
> b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
> index dbbedf54f87..07f1f159a8f 100644
> --- a/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
> +++ b/gcc/testsuite/gcc.target/riscv/predef-__riscv_v_intrinsic.c
> @@ -3,7 +3,7 @@
>
>  int main () {
>
> -#if __riscv_v_intrinsic != 11000
> +#if __riscv_v_intrinsic != 12000
>  #error "__riscv_v_intrinsic"
>  #endif
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c
> new file mode 100644
> index 000..8eee7c68f71
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114017-1.c
> @@ -0,0 +1,19 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +vuint8mf2_t
> +test (vuint16m1_t val, size_t shift, size_t vl)
> +{
> +#if __riscv_v_intrinsic == 11000
> +  #warning "RVV Intrinsics v0.11"
> +  return __riscv_vnclipu (val, shift, vl);
> +#endif
> +
> +#if __riscv_v_intrinsic == 12000
> +  #warning "RVV Intrinsics v0.12" /* { dg-warning "RVV Intrinsics v0.12"
> } */
> +  return __riscv_vnclipu (val, shift, 0, vl);
> +#endif
> +}
> +
> --
> 2.34.1
>
>

Re: [PATCH V2] RISC-V: Specify mtune and march for PR113742

[Kito Cheng]

LGTM, thanks for fixing that issue :)

On Wed, Feb 21, 2024 at 6:03 AM Edwin Lu  wrote:
>
> The testcase pr113742.c is failing for 32 bit targets due to the following cc1
> error:
> cc1: error: ABI requries '-march=rv64'
>
> Specify '-march=rv64gc' with '-mtune=sifive-p600-series'
>
> V1: https://gcc.gnu.org/pipermail/gcc-patches/2024-February/645609.html
>
> PR target/113742
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/pr113742.c: change mcpu to mtune and add march
>
> Signed-off-by: Edwin Lu 
> ---
> V1: use require-effective-target
> V2: switch to specifying march and mtune
> ---
>  gcc/testsuite/gcc.target/riscv/pr113742.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/pr113742.c 
> b/gcc/testsuite/gcc.target/riscv/pr113742.c
> index ab8934c2a8a..573afd6f0ad 100644
> --- a/gcc/testsuite/gcc.target/riscv/pr113742.c
> +++ b/gcc/testsuite/gcc.target/riscv/pr113742.c
> @@ -1,4 +1,4 @@
> -//* { dg-do compile } */
> -/* { dg-options "-O2 -finstrument-functions -mabi=lp64d -mcpu=sifive-p670" } 
> */
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -finstrument-functions -march=rv64gc -mabi=lp64d 
> -mtune=sifive-p600-series" } */
>
>  void foo(void) {}
> --
> 2.34.1
>

Re: [PATCH] RISC-V: Fix riscv/arch-19.c with different ISA spec version

[Kito Cheng]

LGTM :)

On Tue, Feb 20, 2024 at 12:03 PM Alexandre Oliva  wrote:
>
> This testcase is failing with riscv64-elf and riscv32-elf in the gcc-13
> branch, if configured to use an assembler that supports -misa-spec; with
> an assembler that doesn't, the test passes both with and without the
> following backport from the trunk, so I'd like to install it in gcc-13.
> Regstrapped on x86_64-linux-gnu, along with other backports, and tested
> manually on riscv64-elf.  Ok to install?
>
> From: Kito Cheng 
>
> In newer ISA spec, F will implied zicsr, add that into -march option to
> prevent different test result on different default -misa-spec version.
>
> gcc/testsuite/
>
> * gcc.target/riscv/arch-19.c: Add -misa-spec.
>
> (cherry picked from commit 9fde76a3be8e1717d9d38492c40675e742611e45)
> ---
>  gcc/testsuite/gcc.target/riscv/arch-19.c |4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-19.c 
> b/gcc/testsuite/gcc.target/riscv/arch-19.c
> index b042e1a49fe6f..95204ede26a69 100644
> --- a/gcc/testsuite/gcc.target/riscv/arch-19.c
> +++ b/gcc/testsuite/gcc.target/riscv/arch-19.c
> @@ -1,4 +1,4 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64if_zfinx -mabi=lp64" } */
> +/* { dg-options "-march=rv64if_zicsr_zfinx -mabi=lp64" } */
>  int foo() {}
> -/* { dg-error "'-march=rv64if_zfinx': z\\*inx conflicts with floating-point 
> extensions" "" { target *-*-* } 0 } */
> +/* { dg-error "'-march=rv64if_zicsr_zfinx': z\\*inx conflicts with 
> floating-point extensions" "" { target *-*-* } 0 } */
>
> --
> Alexandre Oliva, happy hackerhttps://FSFLA.org/blogs/lxo/
>Free Software Activist   GNU Toolchain Engineer
> More tolerance and less prejudice are key for inclusion and diversity
> Excluding neuro-others for not behaving ""normal"" is *not* inclusive

Re: [PATCH v2] RISC-V: Suppress the vsetvl fusion for conflict successors

[Kito Cheng]

LGTM

On Mon, Feb 19, 2024 at 3:42 PM juzhe.zh...@rivai.ai
 wrote:
>
> Ping this patch which is simple fix on VSETVL PASS.
> Ok for trunk ?
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Juzhe-Zhong
> Date: 2024-02-01 17:02
> To: gcc-patches
> CC: kito.cheng; kito.cheng; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
> Subject: [PATCH v2] RISC-V: Suppress the vsetvl fusion for conflict successors
> Update in v2: Add dump information.
>
> This patch fixes the following ineffective vsetvl insertion:
>
> #include "riscv_vector.h"
>
> void f (int32_t * restrict in, int32_t * restrict out, size_t n, size_t cond, 
> size_t cond2)
> {
>   for (size_t i = 0; i < n; i++)
> {
>   if (i == cond) {
> vint8mf8_t v = *(vint8mf8_t*)(in + i + 100);
> *(vint8mf8_t*)(out + i + 100) = v;
>   } else if (i == cond2) {
> vfloat32mf2_t v = *(vfloat32mf2_t*)(in + i + 200);
> *(vfloat32mf2_t*)(out + i + 200) = v;
>   } else if (i == (cond2 - 1)) {
> vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 300);
> *(vuint16mf2_t*)(out + i + 300) = v;
>   } else {
> vint8mf4_t v = *(vint8mf4_t*)(in + i + 400);
> *(vint8mf4_t*)(out + i + 400) = v;
>   }
> }
> }
>
> Before this patch:
>
> f:
> .LFB0:
> .cfi_startproc
> beq a2,zero,.L12
> addia7,a0,400
> addia6,a1,400
> addia0,a0,1600
> addia1,a1,1600
> li  a5,0
> addit6,a4,-1
> vsetvli t3,zero,e8,mf8,ta,ma ---> ineffective uplift
> .L7:
> beq a3,a5,.L15
> beq a4,a5,.L16
> beq t6,a5,.L17
> vsetvli t1,zero,e8,mf4,ta,ma
> vle8.v  v1,0(a0)
> vse8.v  v1,0(a1)
> vsetvli t3,zero,e8,mf8,ta,ma
> .L4:
> addia5,a5,1
> addia7,a7,4
> addia6,a6,4
> addia0,a0,4
> addia1,a1,4
> bne a2,a5,.L7
> .L12:
> ret
> .L15:
> vle8.v  v1,0(a7)
> vse8.v  v1,0(a6)
> j   .L4
> .L17:
> vsetvli t1,zero,e8,mf4,ta,ma
> addit5,a0,-400
> addit4,a1,-400
> vle16.v v1,0(t5)
> vse16.v v1,0(t4)
> vsetvli t3,zero,e8,mf8,ta,ma
> j   .L4
> .L16:
> addit5,a0,-800
> addit4,a1,-800
> vle32.v v1,0(t5)
> vse32.v v1,0(t4)
> j   .L4
>
> It's obvious that we are hoisting the e8mf8 vsetvl to the top. It's 
> ineffective since e8mf8 comes from
> low probability block which is if (i == cond).
>
> For this case, we disable such fusion.
>
> After this patch:
>
> f:
> beq a2,zero,.L12
> addi a7,a0,400
> addi a6,a1,400
> addi a0,a0,1600
> addi a1,a1,1600
> li a5,0
> addi t6,a4,-1
> .L7:
> beq a3,a5,.L15
> beq a4,a5,.L16
> beq t6,a5,.L17
> vsetvli t1,zero,e8,mf4,ta,ma
> vle8.v v1,0(a0)
> vse8.v v1,0(a1)
> .L4:
> addi a5,a5,1
> addi a7,a7,4
> addi a6,a6,4
> addi a0,a0,4
> addi a1,a1,4
> bne a2,a5,.L7
> .L12:
> ret
> .L15:
> vsetvli t3,zero,e8,mf8,ta,ma
> vle8.v v1,0(a7)
> vse8.v v1,0(a6)
> j .L4
> .L17:
> addi t5,a0,-400
> addi t4,a1,-400
> vsetvli t1,zero,e8,mf4,ta,ma
> vle16.v v1,0(t5)
> vse16.v v1,0(t4)
> j .L4
> .L16:
> addi t5,a0,-800
> addi t4,a1,-800
> vsetvli t3,zero,e32,mf2,ta,ma
> vle32.v v1,0(t5)
> vse32.v v1,0(t4)
> j .L4
>
> Tested on both RV32/RV64 no regression. Ok for trunk ?
>
> PR target/113696
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): 
> Suppress vsetvl fusion.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/pr113696.c: New test.
>
> ---
> gcc/config/riscv/riscv-vsetvl.cc  | 25 ++
> .../gcc.target/riscv/rvv/vsetvl/pr113696.c| 26 +++
> 2 files changed, 51 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr113696.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index cec862329c5..28b7534d970 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -2959,6 +2959,31 @@ pre_vsetvl::earliest_fuse_vsetvl_info (int iter)
>   src_block_info.set_empty_info ();
>   src_block_info.probability
> = profile_probability::uninitialized ();
> +   /* See PR113696, we should reset immediate dominator to
> + empty since we may uplift ineffective vsetvl which
> + locate at low probability block.  */
> +   basic_block dom
> + = get_immediate_dominator (CDI_DOMINATORS, eg->src);
> +   auto _block_info = get_block_info (dom);
> +   if (dom_block_info.has_info ()
> +   && !m_dem.compatible_p (
> + dom_block_info.get_exit_info (), curr_info))
> + {
> +   dom_block_info.set_empty_info ();
> +   dom_block_info.probability
> + = profile_probability::uninitialized ();
> +   if (dump_file && (dump_flags & TDF_DETAILS))
> + {
> +   fprintf (dump_file,
> +"  Reset dominator bb %u:",
> +dom->index);

[committed] RISC-V: Fix *sge_ pattern

[Kito Cheng]

*sge_ pattern has referenced operand[2] which is
invalid...it should just use `slti` rather than `slti%i2`.

gcc/ChangeLog:

PR target/106543
* config/riscv/riscv.md (*sge_): Fix asm
pattern.
---
 gcc/config/riscv/riscv.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 39b29795cd6..3f7a023d941 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3107,7 +3107,7 @@
(any_ge:GPR (match_operand:X 1 "register_operand" " r")
(const_int 1)))]
   ""
-  "slt%i2\t%0,zero,%1"
+  "slti\t%0,zero,%1"
   [(set_attr "type" "slt")
(set_attr "mode" "")])
 
-- 
2.34.1

Re: [PATCH] RISC-V: Add new option -march=help to print all supported extensions

[Kito Cheng]

Thanks for the test and review, pushed :)

On Thu, Feb 15, 2024 at 6:43 PM Christoph Müllner
 wrote:
>
> On Thu, Feb 15, 2024 at 10:56 AM Kito Cheng  wrote:
> >
> > The output of -march=help is like below:
> >
> > ```
> > All available -march extensions for RISC-V:
> > NameVersion
> > i   2.0, 2.1
> > e   2.0
> > m   2.0
> > a   2.0, 2.1
> > f   2.0, 2.2
> > d   2.0, 2.2
> > ...
> > ```
> >
> > Also support -print-supported-extensions and --print-supported-extensions 
> > for
> > clang compatibility.
>
> If I remember correctly, then this feature was requested several times
> in the past.
> Thanks for working on this!
>
> Reviewed-by: Christoph Müllner 
>
> I have done a quick feature test (no bootstrapping, no check for
> compiler warnings) as well.
> Below you find all supported RISC-V extension in today's master branch:
>
> All available -march extensions for RISC-V:
> NameVersion
> i   2.0, 2.1
> e   2.0
> m   2.0
> a   2.0, 2.1
> f   2.0, 2.2
> d   2.0, 2.2
> c   2.0
> v   1.0
> h   1.0
> zic64b  1.0
> zicbom  1.0
> zicbop  1.0
> zicboz  1.0
> ziccamoa1.0
> ziccif  1.0
> zicclsm 1.0
> ziccrse 1.0
> zicntr  2.0
> zicond  1.0
> zicsr   2.0
> zifencei2.0
> zihintntl   1.0
> zihintpause 2.0
> zihpm   2.0
> zmmul   1.0
> za128rs 1.0
> za64rs  1.0
> zawrs   1.0
> zfa 1.0
> zfh 1.0
> zfhmin  1.0
> zfinx   1.0
> zdinx   1.0
> zca 1.0
> zcb 1.0
> zcd 1.0
> zce 1.0
> zcf 1.0
> zcmp1.0
> zcmt1.0
> zba 1.0
> zbb 1.0
> zbc 1.0
> zbkb1.0
> zbkc1.0
> zbkc1.0
> zbkx1.0
> zbs 1.0
> zk  1.0
> zkn 1.0
> zknd1.0
> zkne1.0
> zknh1.0
> zkr 1.0
> zks 1.0
> zksed   1.0
> zksh1.0
> zkt 1.0
> ztso1.0
> zvbb1.0
> zvbc1.0
> zve32f  1.0
> zve32x  1.0
> zve64d  1.0
> zve64f  1.0
> zve64x  1.0
> zvfbfmin1.0
> zvfh1.0
> zvfhmin 1.0
> zvkb1.0
> zvkg1.0
> zvkn1.0
> zvknc   1.0
> zvkned  1.0
> zvkng   1.0
> zvknha  1.0
> zvknhb  1.0
> zvks1.0
> zvksc   1.0
> zvksed  1.0
> zvksg   1.0
> zvksh   1.0
> zvkt1.0
> zvl1024b1.0
> zvl128b 1.0
> zvl16384b   1.0
> zvl2048b1.0
> zvl256b 1.0
> zvl32768b   1.0
> zvl32b  1.0
> 

[PATCH] RISC-V: Add new option -march=help to print all supported extensions

[Kito Cheng]

The output of -march=help is like below:

```
All available -march extensions for RISC-V:
NameVersion
i   2.0, 2.1
e   2.0
m   2.0
a   2.0, 2.1
f   2.0, 2.2
d   2.0, 2.2
...
```

Also support -print-supported-extensions and --print-supported-extensions for
clang compatibility.

gcc/ChangeLog:

PR target/109349

* common/config/riscv/riscv-common.cc (riscv_arch_help): New.
* config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
(RISCV_MINOR_VERSION_BASE): Ditto.
(RISCV_REVISION_VERSION_BASE): Ditto.
* config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
rather than magic number.
* config/riscv/riscv.h (riscv_arch_help): New.
(EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
(DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
--print-supported-extensions.
* config/riscv/riscv.opt (march=help): New.
(print-supported-extensions): New.
(-print-supported-extensions): New.
* doc/invoke.texi (RISC-V Options): Document -march=help.
---
 gcc/common/config/riscv/riscv-common.cc | 46 +
 gcc/config/riscv/riscv-c.cc |  2 +-
 gcc/config/riscv/riscv-protos.h |  7 
 gcc/config/riscv/riscv.h|  7 +++-
 gcc/config/riscv/riscv.opt  | 12 +++
 gcc/doc/invoke.texi |  3 +-
 6 files changed, 74 insertions(+), 3 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 631ce8309a0..8974fa4a128 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -21,6 +21,8 @@ along with GCC; see the file COPYING3.  If not see
 #include 
 
 #define INCLUDE_STRING
+#define INCLUDE_SET
+#define INCLUDE_MAP
 #include "config.h"
 #include "system.h"
 #include "coretypes.h"
@@ -2225,6 +2227,50 @@ riscv_get_valid_option_values (int option_code,
   return v;
 }
 
+const char *
+riscv_arch_help (int argc, const char **argv)
+{
+  /* Collect all exts, and sort it in canonical order.  */
+  struct extension_comparator {
+bool operator()(const std::string& a, const std::string& b) const {
+  return subset_cmp(a, b) >= 1;
+}
+  };
+  std::map, extension_comparator> all_exts;
+  for (const riscv_ext_version  : riscv_ext_version_table)
+{
+  if (!ext.name)
+   break;
+  if (ext.name[0] == 'g')
+   continue;
+  unsigned version_value = (ext.major_version * RISCV_MAJOR_VERSION_BASE)
+   + (ext.minor_version
+  * RISCV_MINOR_VERSION_BASE);
+  all_exts[ext.name].insert(version_value);
+}
+
+  printf("All available -march extensions for RISC-V:\n");
+  printf("\t%-20sVersion\n", "Name");
+  for (auto const _info : all_exts)
+{
+  printf("\t%-20s\t", ext_info.first.c_str());
+  bool first = true;
+  for (auto version : ext_info.second)
+   {
+ if (first)
+   first = false;
+ else
+   printf(", ");
+ unsigned major = version / RISCV_MAJOR_VERSION_BASE;
+ unsigned minor = (version % RISCV_MAJOR_VERSION_BASE)
+   / RISCV_MINOR_VERSION_BASE;
+ printf("%u.%u", major, minor);
+   }
+  printf("\n");
+}
+  exit (0);
+}
+
 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
 static const struct default_options riscv_option_optimization_table[] =
   {
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 94c3871c760..3ef06dcfd2d 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -37,7 +37,7 @@ along with GCC; see the file COPYING3.  If not see
 static int
 riscv_ext_version_value (unsigned major, unsigned minor)
 {
-  return (major * 100) + (minor * 1000);
+  return (major * RISCV_MAJOR_VERSION_BASE) + (minor * 
RISCV_MINOR_VERSION_BASE);
 }
 
 /* Implement TARGET_CPU_CPP_BUILTINS.  */
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index ae1685850ac..80efdf2b7e5 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -780,4 +780,11 @@ const struct riscv_tune_info *
 riscv_parse_tune (const char *, bool);
 const cpu_vector_cost *get_vector_costs ();
 
+enum
+{
+  RISCV_MAJOR_VERSION_BASE = 100,
+  RISCV_MINOR_VERSION_BASE = 1000,
+  RISCV_REVISION_VERSION_BASE = 1,
+};
+
 #endif /* ! GCC_RISCV_PROTOS_H */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 669308cc96d..da089a03e9d 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -50,12 +50,14 @@ extern const char *riscv_expand_arch (int argc, const char 
**argv);
 extern const char *riscv_expand_arch_from_cpu (int argc, 

Re: [PATCH] Skip gnat.dg/div_zero.adb on RISC-V

[Kito Cheng]

LGTM, thanks :)

On Wed, Feb 14, 2024 at 10:11 PM Andreas Schwab  wrote:
>
> Like AArch64 and POWER, RISC-V does not support trap on zero divide.
>
> gcc/testsuite/
> * gnat.dg/div_zero.adb: Skip on RISC-V.
> ---
>  gcc/testsuite/gnat.dg/div_zero.adb | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/testsuite/gnat.dg/div_zero.adb 
> b/gcc/testsuite/gnat.dg/div_zero.adb
> index dedf3928db7..fb1c98caeff 100644
> --- a/gcc/testsuite/gnat.dg/div_zero.adb
> +++ b/gcc/testsuite/gnat.dg/div_zero.adb
> @@ -1,5 +1,5 @@
>  -- { dg-do run }
> --- { dg-skip-if "divide does not trap" { aarch64*-*-* powerpc*-*-* } }
> +-- { dg-skip-if "divide does not trap" { aarch64*-*-* powerpc*-*-* 
> riscv*-*-* } }
>
>  -- This test requires architecture- and OS-specific support code for 
> unwinding
>  -- through signal frames (typically located in *-unwind.h) to pass.  Feel 
> free
> --
> 2.43.1
>
>
> --
> Andreas Schwab, SUSE Labs, sch...@suse.de
> GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
> "And now for something completely different."

Re: [PATCH V1] RISC-V: Add mininal support for zabha extension.

[Kito Cheng]

I am not sure it's worth adding a dedicated instruction pattern for
those instructions? In theory those instructions should just be used
by those atomic builin when zabha has enabled, but I think that would
be kinda of a bigger work item.

On Tue, Feb 6, 2024 at 5:18 PM  wrote:
>
> From: yulong 
>
> This patch add the mininal support for zabha extension.
> The doc url as follow: 
> https://github.com/riscv/riscv-zabha/blob/v1.0-rc1/zabha.adoc
> There are have no amocas.[b|h] instructions, because the zacas extension is 
> not merged.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc: Add zabha extension name.
> * config/riscv/riscv.md (amo_addqi3): New mode.
> (amo_addhi3): Ditto.
> (amo_minqi3): Ditto.
> (amo_minuqi3): Ditto.
> (amo_minhi3): Ditto.
> (amo_minuhi3): Ditto.
> (amo_maxqi3): Ditto.
> (amo_maxuqi3): Ditto.
> (amo_maxhi3): Ditto.
> (amo_maxuhi3): Ditto.
> (amo_andqi3): Ditto.
> (amo_andhi3): Ditto.
> (amo_orqi3): Ditto.
> (amo_orhi3): Ditto.
> (amo_xorqi3): Ditto.
> (amo_xorhi3): Ditto.
> (amo_swapqi3): Ditto.
> (amo_swaphi3): Ditto.
> * config/riscv/riscv.opt: Add zabha extension.
>
> ---
>  gcc/common/config/riscv/riscv-common.cc |   2 +
>  gcc/config/riscv/riscv.md   | 167 
>  gcc/config/riscv/riscv.opt  |   2 +
>  3 files changed, 171 insertions(+)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 631ce8309a0..9c3be0d7651 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -250,6 +250,7 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>{"za64rs",  ISA_SPEC_CLASS_NONE, 1, 0},
>{"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
>{"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zabha", ISA_SPEC_CLASS_NONE, 1, 0},
>
>{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
>{"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1504,6 +1505,7 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"za64rs", _options::x_riscv_za_subext, MASK_ZA64RS},
>{"za128rs", _options::x_riscv_za_subext, MASK_ZA128RS},
>{"zawrs", _options::x_riscv_za_subext, MASK_ZAWRS},
> +  {"zabha", _options::x_riscv_za_subext, MASK_ZABHA},
>
>{"zba",_options::x_riscv_zb_subext, MASK_ZBA},
>{"zbb",_options::x_riscv_zb_subext, MASK_ZBB},
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 39b29795cd6..058b63ac7f0 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -134,6 +134,9 @@
>;; XTheadInt unspec
>UNSPECV_XTHEADINT_PUSH
>UNSPECV_XTHEADINT_POP
> +
> +  ;; Zabha instructions.
> +  UNSPEC_AMO_SWAP
>  ])
>
>  (define_constants
> @@ -849,6 +852,24 @@
>[(set_attr "type" "arith")
> (set_attr "mode" "SI")])
>
> +(define_insn "amo_addqi3"
> +  [(set (match_operand:QI  0 "register_operand" "=r,r")
> +   (plus:QI (match_operand:QI 1 "register_operand" " r,r")
> +(match_operand:QI 2 "arith_operand"" r,r")))]
> +  "TARGET_ZABHA"
> +  "amoadd.b\t%0,%1,%2"
> +  [(set_attr "type" "atomic")
> +   (set_attr "mode" "QI")])
> +
> +(define_insn "amo_addhi3"
> +  [(set (match_operand:HI  0 "register_operand" "=r,r")
> +   (plus:HI (match_operand:HI 1 "register_operand" " r,r")
> +(match_operand:HI 2 "arith_operand"" r,r")))]
> +  "TARGET_ZABHA"
> +  "amoadd.h\t%0,%1,%2"
> +  [(set_attr "type" "atomic")
> +   (set_attr "mode" "HI")])
> +
>  ;;
>  ;;  
>  ;;
> @@ -1645,6 +1666,78 @@
>[(set_attr "type" "fmove")
> (set_attr "mode" "")])
>
> +(define_insn "amo_minqi3"
> +  [(set (match_operand:QI0 "register_operand" "=r")
> +   (smin:QI (match_operand:QI 1 "register_operand" " r")
> +  (match_operand:QI 2 "register_operand" " r")))]
> +  "TARGET_ZABHA"
> +  "amomin.b\t%0,%1,%2"
> +  [(set_attr "type" "atomic")
> +   (set_attr "mode" "QI")])
> +
> +(define_insn "amo_minuqi3"
> +  [(set (match_operand:QI0 "register_operand" "=r")
> +   (umin:QI (match_operand:QI 1 "register_operand" " r")
> +  (match_operand:QI 2 "register_operand" " r")))]
> +  "TARGET_ZABHA"
> +  "amominu.b\t%0,%1,%2"
> +  [(set_attr "type" "atomic")
> +   (set_attr "mode" "QI")])
> +
> +(define_insn "amo_minhi3"
> +  [(set (match_operand:HI0 "register_operand" "=r")
> +   (smin:HI (match_operand:HI 1 "register_operand" " r")
> +  (match_operand:HI 2 "register_operand" " r")))]
> +  "TARGET_ZABHA"
> +  "amomin.h\t%0,%1,%2"
> +  [(set_attr "type" "atomic")
> +   (set_attr "mode" "HI")])
> +
> +(define_insn "amo_minuhi3"
> +  [(set (match_operand:HI0 "register_operand" "=r")
> +   (umin:HI (match_operand:HI 1 "register_operand" " r")
> +

Re: [PATCH 2/2] RISC-V: Add sifive-p450, sifive-p67 to -mcpu

[Kito Cheng]

pushed, thanks :)

On Fri, Feb 2, 2024 at 11:59 AM Monk Chiang  wrote:
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
> * doc/invoke.texi (RISC-V Options): Add sifive-p450,
> sifive-p670.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/mcpu-sifive-p450.c: New test.
> * gcc.target/riscv/mcpu-sifive-p670.c: New test.
> ---
>  gcc/config/riscv/riscv-cores.def  |  9 +
>  gcc/doc/invoke.texi   |  3 +-
>  .../gcc.target/riscv/mcpu-sifive-p450.c   | 34 
>  .../gcc.target/riscv/mcpu-sifive-p670.c   | 40 +++
>  4 files changed, 85 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c
>
> diff --git a/gcc/config/riscv/riscv-cores.def 
> b/gcc/config/riscv/riscv-cores.def
> index 0785e8f3fbd..57928bccdc8 100644
> --- a/gcc/config/riscv/riscv-cores.def
> +++ b/gcc/config/riscv/riscv-cores.def
> @@ -76,6 +76,15 @@ RISCV_CORE("sifive-s76",  "rv64imafdc", 
> "sifive-7-series")
>  RISCV_CORE("sifive-u54",  "rv64imafdc", "sifive-5-series")
>  RISCV_CORE("sifive-u74",  "rv64imafdc", "sifive-7-series")
>  RISCV_CORE("sifive-x280", "rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b", 
> "sifive-7-series")
> +RISCV_CORE("sifive-p450", 
> "rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_"
> + 
> "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_"
> + 
> "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs",
> + "sifive-p400-series")
> +RISCV_CORE("sifive-p670", 
> "rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_"
> + 
> "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_"
> + 
> "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_"
> + "zvl128b_zvbb_zvknc_zvkng_zvksc_zvksg",
> + "sifive-p600-series")
>
>  RISCV_CORE("thead-c906",  
> "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
>   "xtheadcondmov_xtheadfmemidx_xtheadmac_"
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index f8645822ca4..71339b8b30f 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -30707,7 +30707,8 @@ by particular CPU name.
>  Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21},
>  @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76},
>  @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76},
> -@samp{sifive-u54}, @samp{sifive-u74}, and @samp{sifive-x280}.
> +@samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, 
> @samp{sifive-xp450},
> +@samp{sifive-x670}.
>
>  @opindex mtune
>  @item -mtune=@var{processor-string}
> diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c 
> b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c
> new file mode 100644
> index 000..563041821e7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c
> @@ -0,0 +1,34 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
> +/* { dg-options "-mcpu=sifive-p450 -mabi=lp64d" } */
> +/* SiFive p450 => 
> rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs
>  */
> +
> +#if !((__riscv_xlen == 64) \
> +  && !defined(__riscv_32e) \
> +  && (__riscv_flen == 64)  \
> +  && defined(__riscv_c)\
> +  && defined(__riscv_za64rs)   \
> +  && defined(__riscv_zic64b)   \
> +  && defined(__riscv_zicbom)   \
> +  && defined(__riscv_zicbop)   \
> +  && defined(__riscv_zicboz)   \
> +  && defined(__riscv_ziccamoa) \
> +  && defined(__riscv_ziccif)   \
> +  && defined(__riscv_zicclsm)  \
> +  && defined(__riscv_ziccrse)  \
> +  && defined(__riscv_zicsr)\
> +  && defined(__riscv_zifencei) \
> +  && defined(__riscv_zihintntl)\
> +  && defined(__riscv_zihintpause)  \
> +  && defined(__riscv_zihpm)\
> +  && defined(__riscv_zfhmin)   \
> +  && defined(__riscv_zba)  \
> +  && defined(__riscv_zbb)  \
> +  && defined(__riscv_zbs))
> +#error "unexpected arch"
> +#endif
> +
> +int main()
> +{
> +  return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c 
> b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c
> new file mode 100644
> index 000..8dfd490f440
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c
> @@ -0,0 +1,40 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
> +/* { dg-options "-mcpu=sifive-p670 -mabi=lp64d" } */
> +/* SiFive p670 => 
> 

Re: [PATCH 1/2] RISC-V: Support scheduling for sifive p400 series

[Kito Cheng]

pushed, thanks :)

On Fri, Feb 2, 2024 at 11:59 AM Monk Chiang  wrote:
>
> Add sifive p400 series scheduler module. For more information
> see https://www.sifive.com/cores/performance-p450-470.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Include sifive-p400.md.
> * config/riscv/sifive-p400.md: New file.
> * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
> * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
> Add sifive_p400.
> * config/riscv/riscv.cc (sifive_p400_tune_info): New.
> * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
> * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
> ---
>  gcc/config/riscv/riscv-cores.def |   1 +
>  gcc/config/riscv/riscv-opts.h|   1 +
>  gcc/config/riscv/riscv.cc|  17 +++
>  gcc/config/riscv/riscv.h |   1 +
>  gcc/config/riscv/riscv.md|   3 +-
>  gcc/config/riscv/sifive-p400.md  | 174 +++
>  gcc/doc/invoke.texi  |   4 +-
>  7 files changed, 198 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/config/riscv/sifive-p400.md
>
> diff --git a/gcc/config/riscv/riscv-cores.def 
> b/gcc/config/riscv/riscv-cores.def
> index a07a79e2cb7..0785e8f3fbd 100644
> --- a/gcc/config/riscv/riscv-cores.def
> +++ b/gcc/config/riscv/riscv-cores.def
> @@ -37,6 +37,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info)
>  RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
>  RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
>  RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
> +RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info)
>  RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
>  RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
>  RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 25951665b13..4edddbadc37 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -55,6 +55,7 @@ extern enum riscv_isa_spec_class riscv_isa_spec;
>  enum riscv_microarchitecture_type {
>generic,
>sifive_7,
> +  sifive_p400,
>sifive_p600,
>generic_ooo
>  };
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index cead76fe1a2..4b24e4b9a0a 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -447,6 +447,23 @@ static const struct riscv_tune_param sifive_7_tune_info 
> = {
>NULL,/* vector cost */
>  };
>
> +/* Costs to use when optimizing for Sifive p400 Series.  */
> +static const struct riscv_tune_param sifive_p400_tune_info = {
> +  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},  /* fp_add */
> +  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},  /* fp_mul */
> +  {COSTS_N_INSNS (20), COSTS_N_INSNS (20)},/* fp_div */
> +  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},  /* int_mul */
> +  {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},  /* int_div */
> +  3,   /* issue_rate */
> +  4,   /* branch_cost */
> +  3,   /* memory_cost */
> +  4,   /* fmv_cost */
> +  true,/* 
> slow_unaligned_access */
> +  false,   /* use_divmod_expansion */
> +  RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI,  /* fusible_ops */
> +  _vector_cost,/* vector cost */
> +};
> +
>  /* Costs to use when optimizing for Sifive p600 Series.  */
>  static const struct riscv_tune_param sifive_p600_tune_info = {
>{COSTS_N_INSNS (4), COSTS_N_INSNS (4)},  /* fp_add */
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index e0cb3ba08d4..669308cc96d 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -898,6 +898,7 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
>
>  #define TARGET_SFB_ALU \
>   ((riscv_microarchitecture == sifive_7) \
> +  || (riscv_microarchitecture == sifive_p400) \
>|| (riscv_microarchitecture == sifive_p600))
>
>  #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 2a164a03dbd..39b29795cd6 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -687,7 +687,7 @@
>  ;; Microarchitectures we know how to tune for.
>  ;; Keep this in sync with enum riscv_microarchitecture.
>  (define_attr "tune"
> -  "generic,sifive_7,sifive_p600,generic_ooo"
> +  "generic,sifive_7,sifive_p400,sifive_p600,generic_ooo"
>(const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
>
>  ;; Describe a user's asm statement.
> @@ -3850,6 +3850,7 @@
>  (include "pic.md")
>  (include "generic.md")
>  (include "sifive-7.md")
> +(include "sifive-p400.md")
>  (include 

Re: [PATCH] RISC-V: Expand VLMAX scalar move in reduction

[Kito Cheng]

LGTM :)

On Fri, Feb 2, 2024 at 9:58 AM Juzhe-Zhong  wrote:
>
> This patch fixes the following:
>
> vsetvli a5,a1,e32,m1,tu,ma
> sllia4,a5,2
> sub a1,a1,a5
> vle32.v v2,0(a0)
> add a0,a0,a4
> vadd.vv v1,v2,v1
> bne a1,zero,.L3
> vsetivlizero,1,e32,m1,ta,ma
> vmv.s.x v2,zero
> vsetvli a5,zero,e32,m1,ta,ma  ---> Redundant vsetvl.
> vredsum.vs  v1,v1,v2
> vmv.x.s a0,v1
> ret
>
> VSETVL PASS is able to fuse avl = 1 of scalar move and VLMAX avl of reduction.
>
> However, this following RTL blocks the fusion in dependence analysis in 
> VSETVL PASS:
>
> (insn 49 24 50 5 (set (reg:RVVM1SI 98 v2 [148])
> (if_then_else:RVVM1SI (unspec:RVVMF32BI [
> (const_vector:RVVMF32BI [
> (const_int 1 [0x1])
> repeat [
> (const_int 0 [0])
> ]
> ])
> (const_int 1 [0x1])
> (const_int 2 [0x2]) repeated x2
> (const_int 0 [0])
> (reg:SI 66 vl)
> (reg:SI 67 vtype)
> ] UNSPEC_VPREDICATE)
> (const_vector:RVVM1SI repeat [
> (const_int 0 [0])
> ])
> (unspec:RVVM1SI [
> (reg:DI 0 zero)
> ] UNSPEC_VUNDEF))) 3813 {*pred_broadcastrvvm1si_zero}
>  (nil))
> (insn 50 49 51 5 (set (reg:DI 15 a5 [151])  >  It 
> set a5, blocks the following VLMAX into the scalar move above.
> (unspec:DI [
> (const_int 32 [0x20])
> ] UNSPEC_VLMAX)) 2566 {vlmax_avldi}
>  (expr_list:REG_EQUIV (unspec:DI [
> (const_int 32 [0x20])
> ] UNSPEC_VLMAX)
> (nil)))
> (insn 51 50 52 5 (set (reg:RVVM1SI 97 v1 [150])
> (unspec:RVVM1SI [
> (unspec:RVVMF32BI [
> (const_vector:RVVMF32BI repeat [
> (const_int 1 [0x1])
> ])
> (reg:DI 15 a5 [151])
> (const_int 2 [0x2])
> (const_int 1 [0x1])
> (reg:SI 66 vl)
> (reg:SI 67 vtype)
> ] UNSPEC_VPREDICATE)
> (unspec:RVVM1SI [
> (reg:RVVM1SI 97 v1 [orig:134 vect_result_14.6 ] [134])
> (reg:RVVM1SI 98 v2 [148])
> ] UNSPEC_REDUC_SUM)
> (unspec:RVVM1SI [
> (reg:DI 0 zero)
> ] UNSPEC_VUNDEF)
> ] UNSPEC_REDUC)) 17541 {pred_redsumrvvm1si}
>  (expr_list:REG_DEAD (reg:RVVM1SI 98 v2 [148])
> (expr_list:REG_DEAD (reg:SI 66 vl)
> (expr_list:REG_DEAD (reg:DI 15 a5 [151])
> (expr_list:REG_DEAD (reg:DI 0 zero)
> (nil))
>
> Such situation can only happen on auto-vectorization, never happen on 
> intrinsic codes.
> Since the reduction is passed VLMAX AVL, it should be more natural to pass 
> VLMAX to the scalar move which initial the value of the reduction.
>
> After this patch:
>
> vsetvli a5,a1,e32,m1,tu,ma
> sllia4,a5,2
> sub a1,a1,a5
> vle32.v v2,0(a0)
> add a0,a0,a4
> vadd.vv v1,v2,v1
> bne a1,zero,.L3
> vsetvli a5,zero,e32,m1,ta,ma
> vmv.s.x v2,zero
> vredsum.vs  v1,v1,v2
> vmv.x.s a0,v1
> ret
>
> Tested on both RV32/RV64 no regression.
>
> PR target/113697
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to 
> scalar move.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/pr113697.c: New test.
>
> ---
>  gcc/config/riscv/riscv-v.cc| 12 +++-
>  .../gcc.target/riscv/rvv/autovec/pr113697.c| 14 ++
>  2 files changed, 21 insertions(+), 5 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113697.c
>
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 4bacb7fea45..0cfbd21ce6f 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -4151,13 +4151,15 @@ expand_reduction (unsigned unspec, unsigned 
> insn_flags, rtx *ops, rtx init)
>
>rtx m1_tmp = gen_reg_rtx (m1_mode);
>rtx scalar_move_ops[] = {m1_tmp, init};
> -  emit_nonvlmax_insn (code_for_pred_broadcast (m1_mode), SCALAR_MOVE_OP,
> - scalar_move_ops,
> - need_mask_operand_p (insn_flags) ? ops[3]
> -  : CONST1_RTX (Pmode));
> +  insn_code icode = code_for_pred_broadcast (m1_mode);
> +  if 

Re: [PATCH] RISC-V: Allow LICM hoist POLY_INT configuration code sequence

[Kito Cheng]

LGTM :)

On Thu, Feb 1, 2024 at 11:46 PM Juzhe-Zhong  wrote:
>
> Realize in recent benchmark evaluation (coremark-pro zip-test):
>
> vid.v   v2
> vmv.v.i v5,0
> .L9:
> vle16.v v3,0(a4)
> vrsub.vxv4,v2,a6   ---> LICM failed to hoist it outside the 
> loop.
>
> The root cause is:
>
> (insn 56 47 57 4 (set (subreg:DI (reg:HI 220) 0)
> (reg:DI 223)) "rvv.c":11:9 208 {*movdi_64bit}  -> Its result used by 
> the following vrsub.vx then supress the hoist of the vrsub.vx
>  (nil))
>
> (insn 57 56 59 4 (set (reg:RVVMF2HI 216)
> (if_then_else:RVVMF2HI (unspec:RVVMF32BI [
> (const_vector:RVVMF32BI repeat [
> (const_int 1 [0x1])
> ])
> (reg:DI 350)
> (const_int 2 [0x2]) repeated x2
> (const_int 1 [0x1])
> (reg:SI 66 vl)
> (reg:SI 67 vtype)
> ] UNSPEC_VPREDICATE)
> (minus:RVVMF2HI (vec_duplicate:RVVMF2HI (reg:HI 220))
> (reg:RVVMF2HI 217))
> (unspec:RVVMF2HI [
> (reg:DI 0 zero)
> ] UNSPEC_VUNDEF))) "rvv.c":11:9 6938 
> {pred_subrvvmf2hi_reverse_scalar}
>  (expr_list:REG_DEAD (reg:HI 220)
> (nil)))
>
> This patch fixes it generate (set (reg:HI) (subreg:HI (reg:DI))) instead of 
> (set (subreg:DI (reg:DI)) (reg:DI)).
>
> After this patch:
>
> vid.v   v2
> vrsub.vxv2,v2,a7
> vmv.v.i v4,0
> .L3:
> vle16.v v3,0(a4)
>
> Tested on both RV32 and RV64 no regression.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest 
> generation.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/poly_licm-1.c: New test.
> * gcc.target/riscv/rvv/autovec/poly_licm-2.c: New test.
>
> ---
>  gcc/config/riscv/riscv.cc |  9 ---
>  .../riscv/rvv/autovec/poly_licm-1.c   | 18 +
>  .../riscv/rvv/autovec/poly_licm-2.c   | 27 +++
>  3 files changed, 50 insertions(+), 4 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-2.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 529ef5e84b7..6e22b43e618 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2711,16 +2711,17 @@ riscv_legitimize_move (machine_mode mode, rtx dest, 
> rtx src)
> (const_poly_int:HI [m, n])
> (const_poly_int:SI [m, n]).  */
>   rtx tmp = gen_reg_rtx (Pmode);
> - riscv_legitimize_poly_move (Pmode, gen_lowpart (Pmode, dest), tmp,
> - src);
> + rtx tmp2 = gen_reg_rtx (Pmode);
> + riscv_legitimize_poly_move (Pmode, tmp2, tmp, src);
> + emit_move_insn (dest, gen_lowpart (mode, tmp2));
> }
>else
> {
>   /* In RV32 system, handle (const_poly_int:SI [m, n])
> (const_poly_int:DI [m, n]).
>  In RV64 system, handle (const_poly_int:DI [m, n]).
> -   FIXME: Maybe we could gen SImode in RV32 and then sign-extend to 
> DImode,
> -   the offset should not exceed 4GiB in general.  */
> +FIXME: Maybe we could gen SImode in RV32 and then sign-extend to
> +DImode, the offset should not exceed 4GiB in general.  */
>   rtx tmp = gen_reg_rtx (mode);
>   riscv_legitimize_poly_move (mode, dest, tmp, src);
> }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-1.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-1.c
> new file mode 100644
> index 000..b7da65f0996
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-1.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
> -fno-schedule-insns2" } */
> +
> +extern int wsize;
> +
> +typedef unsigned short Posf;
> +#define NIL 0
> +
> +void foo (Posf *p)
> +{
> +  register unsigned n, m;
> +  do {
> +  m = *--p;
> +  *p = (Posf)(m >= wsize ? m-wsize : NIL);
> +  } while (--n);
> +}
> +
> +/* { dg-final { scan-assembler-times 
> {vid\.v\s+v[0-9]+\s+addi\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*-1\s+vrsub\.vx\s+} 1 
> } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-2.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-2.c
> new file mode 100644
> index 000..ffb3c63149f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/poly_licm-2.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns 
> -fno-schedule-insns2" } */
> +
> +typedef unsigned short uint16_t;
> +
> +void 

Re: Re: [PATCH v2] RISC-V: Support scheduling for sifive p600 series

[Kito Cheng]

Yeah, that's the plan for the longer term, we would like to build the
schedule model first and then run more benchmarks with that, then
enable dynamic lmul by default, most SiFive cores prefer larger LMUL
if possible/no spill.

On Thu, Feb 1, 2024 at 4:14 PM juzhe.zh...@rivai.ai
 wrote:
>
> Thanks. I wonder whether p600 will enable dynamic lmul by default ?
> Does dynamic LMUL help with sifive p600 chip ?
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Monk Chiang
> Date: 2024-02-01 16:10
> To: juzhe.zh...@rivai.ai
> CC: gcc-patches; kito.cheng
> Subject: Re: [PATCH v2] RISC-V: Support scheduling for sifive p600 series
> Hi Juzhe,
>   The vector part is complicated, I will add it last.
>
> On Thu, Feb 1, 2024 at 11:08 AM juzhe.zh...@rivai.ai  
> wrote:
>>
>> Hi, Monk.
>>
>> This model doesn't include vector.  Will you add vector pipeline in the 
>> followup patches ?
>>
>> 
>> juzhe.zh...@rivai.ai

Re: [PATCH v2] RISC-V: Support scheduling for sifive p600 series

[Kito Cheng]

thanks, pushed to trunk :)

On Thu, Feb 1, 2024 at 11:02 AM Monk Chiang  wrote:
>
> Add sifive p600 series scheduler module. For more information
> see https://www.sifive.com/cores/performance-p650-670.
> Add sifive-p650, sifive-p670 for mcpu option will come in separate patches.
>
> gcc/ChangeLog:
> * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
> attribute, and include sifive-p600.md.
> * config/riscv/generic-ooo.md: Update type attribute.
> * config/riscv/sifive-7.md: Update type attribute.
> * config/riscv/sifive-p600.md: New file.
> * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
> * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
> Add sifive_p600.
> * config/riscv/riscv.c (sifive_p600_tune_info): New.
> * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
> * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
> ---
>  gcc/config/riscv/generic-ooo.md  |   2 +-
>  gcc/config/riscv/generic.md  |   2 +-
>  gcc/config/riscv/riscv-cores.def |   1 +
>  gcc/config/riscv/riscv-opts.h|   1 +
>  gcc/config/riscv/riscv.cc|  17 +++
>  gcc/config/riscv/riscv.h |   4 +-
>  gcc/config/riscv/riscv.md|  19 ++--
>  gcc/config/riscv/sifive-7.md |   2 +-
>  gcc/config/riscv/sifive-p600.md  | 178 +++
>  gcc/doc/invoke.texi  |   3 +-
>  10 files changed, 216 insertions(+), 13 deletions(-)
>  create mode 100644 gcc/config/riscv/sifive-p600.md
>
> diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
> index 421a7bb929d..a22f8a3e079 100644
> --- a/gcc/config/riscv/generic-ooo.md
> +++ b/gcc/config/riscv/generic-ooo.md
> @@ -127,7 +127,7 @@
>
>  (define_insn_reservation "generic_ooo_fcvt" 3
>(and (eq_attr "tune" "generic_ooo")
> -   (eq_attr "type" "fcvt"))
> +   (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i"))
>"generic_ooo_issue,generic_ooo_fxu")
>
>  (define_insn_reservation "generic_ooo_fcmp" 2
> diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
> index b99ae345bb3..3f0eaa2ea08 100644
> --- a/gcc/config/riscv/generic.md
> +++ b/gcc/config/riscv/generic.md
> @@ -42,7 +42,7 @@
>
>  (define_insn_reservation "generic_xfer" 3
>(and (eq_attr "tune" "generic")
> -   (eq_attr "type" "mfc,mtc,fcvt,fmove,fcmp"))
> +   (eq_attr "type" "mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fcmp"))
>"alu")
>
>  (define_insn_reservation "generic_branch" 1
> diff --git a/gcc/config/riscv/riscv-cores.def 
> b/gcc/config/riscv/riscv-cores.def
> index b30f4dfb08e..a07a79e2cb7 100644
> --- a/gcc/config/riscv/riscv-cores.def
> +++ b/gcc/config/riscv/riscv-cores.def
> @@ -37,6 +37,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info)
>  RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
>  RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
>  RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
> +RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
>  RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
>  RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
>  RISCV_TUNE("size", generic, optimize_size_tune_info)
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 1500f8811ef..25951665b13 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -55,6 +55,7 @@ extern enum riscv_isa_spec_class riscv_isa_spec;
>  enum riscv_microarchitecture_type {
>generic,
>sifive_7,
> +  sifive_p600,
>generic_ooo
>  };
>  extern enum riscv_microarchitecture_type riscv_microarchitecture;
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 7b6111aa545..476533395b5 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -447,6 +447,23 @@ static const struct riscv_tune_param sifive_7_tune_info 
> = {
>NULL,/* vector cost */
>  };
>
> +/* Costs to use when optimizing for Sifive p600 Series.  */
> +static const struct riscv_tune_param sifive_p600_tune_info = {
> +  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},  /* fp_add */
> +  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},  /* fp_mul */
> +  {COSTS_N_INSNS (20), COSTS_N_INSNS (20)},/* fp_div */
> +  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},  /* int_mul */
> +  {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},  /* int_div */
> +  4,   /* issue_rate */
> +  4,   /* branch_cost */
> +  3,   /* memory_cost */
> +  4,   /* fmv_cost */
> +  true,/* 
> slow_unaligned_access */
> +  false,   /* use_divmod_expansion */
> +  RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI,  /* fusible_ops */
> +  _vector_cost, 

Re: [PATCH] RISC-V: Remove vsetvl_pre bogus instructions in VSETVL PASS

[Kito Cheng]

LGTM

On Thu, Feb 1, 2024 at 8:25 PM Juzhe-Zhong  wrote:
>
> I realize there is a RTL regression between GCC-14 and GCC-13.
> https://godbolt.org/z/Ga7K6MqaT
>
> GCC-14:
> (insn 9 13 31 2 (set (reg:DI 15 a5 [138])
> (unspec:DI [
> (const_int 64 [0x40])
> ] UNSPEC_VLMAX)) "/app/example.c":5:15 2566 {vlmax_avldi}
>  (expr_list:REG_EQUIV (unspec:DI [
> (const_int 64 [0x40])
> ] UNSPEC_VLMAX)
> (nil)))
> (insn 31 9 10 2 (parallel [
> (set (reg:DI 15 a5 [138])
> (unspec:DI [
> (reg:DI 0 zero)
> (const_int 32 [0x20])
> (const_int 7 [0x7])
> (const_int 1 [0x1]) repeated x2
> ] UNSPEC_VSETVL))
> (set (reg:SI 66 vl)
> (unspec:SI [
> (reg:DI 0 zero)
> (const_int 32 [0x20])
> (const_int 7 [0x7])
> ] UNSPEC_VSETVL))
> (set (reg:SI 67 vtype)
> (unspec:SI [
> (const_int 32 [0x20])
> (const_int 7 [0x7])
> (const_int 1 [0x1]) repeated x2
> ] UNSPEC_VSETVL))
> ]) "/app/example.c":5:15 3281 {vsetvldi}
>  (nil))
>
> GCC-13:
> (insn 10 7 26 2 (set (reg/f:DI 11 a1 [139])
> (plus:DI (reg:DI 11 a1 [142])
> (const_int 800 [0x320]))) "/app/example.c":6:32 5 {adddi3}
>  (nil))
> (insn 26 10 9 2 (parallel [
> (set (reg:DI 15 a5)
> (unspec:DI [
> (reg:DI 0 zero)
> (const_int 32 [0x20])
> (const_int 7 [0x7])
> (const_int 1 [0x1]) repeated x2
> ] UNSPEC_VSETVL))
> (set (reg:SI 66 vl)
> (unspec:SI [
> (reg:DI 0 zero)
> (const_int 32 [0x20])
> (const_int 7 [0x7])
> ] UNSPEC_VSETVL))
> (set (reg:SI 67 vtype)
> (unspec:SI [
> (const_int 32 [0x20])
> (const_int 7 [0x7])
> (const_int 1 [0x1]) repeated x2
> ] UNSPEC_VSETVL))
> ]) "/app/example.c":5:15 792 {vsetvldi}
>  (nil))
>
> GCC-13 doesn't have:
> (insn 9 13 31 2 (set (reg:DI 15 a5 [138])
> (unspec:DI [
> (const_int 64 [0x40])
> ] UNSPEC_VLMAX)) "/app/example.c":5:15 2566 {vlmax_avldi}
>  (expr_list:REG_EQUIV (unspec:DI [
> (const_int 64 [0x40])
> ] UNSPEC_VLMAX)
> (nil)))
>
> vsetvl_pre doesn't emit any assembler which is just used for occupying scalar 
> register.
> It should be removed in VSETVL PASS.
>
> Tested on both RV32 and RV64 no regression.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
> (pre_vsetvl::cleaup): Remove vsetvl_pre.
> (pre_vsetvl::remove_vsetvl_pre_insns): New function.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c: New test.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc  | 64 +++
>  .../riscv/rvv/vsetvl/vsetvl_pre-1.c   | 12 
>  2 files changed, 76 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl_pre-1.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 28b7534d970..4732d4fc77f 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -315,6 +315,48 @@ vsetvl_insn_p (rtx_insn *rinsn)
>   || INSN_CODE (rinsn) == CODE_FOR_vsetvlsi);
>  }
>
> +/* Return true if it is the bogus vsetvl_pre instruction:
> +
> +   (define_insn "@vlmax_avl"
> + [(set (match_operand:P 0 "register_operand" "=r")
> +   (unspec:P [(match_operand:P 1 "const_int_operand" "i")] 
> UNSPEC_VLMAX))]
> + "TARGET_VECTOR"
> + ""
> + [(set_attr "type" "vsetvl_pre")])
> +
> +   As described above, it's the bogus instruction which doesn't any assembler
> +   and should be removed eventually.  It's used for occupying a scalar 
> register
> +   for VLMAX avl RVV instruction before register allocation.
> +
> +   Before RA:
> +
> +   ...
> +   vsetvl_pre (set r136)
> +   vadd.vv (use r136 with VLMAX avl)
> +   ...
> +
> +   After RA:
> +
> +   ...
> +   vsetvl_pre (set a5)
> +   vadd.vv (use r136 with VLMAX avl)
> +   ...
> +
> +   VSETVL PASS:
> +
> +   ...
> +   vsetvl_pre (set a5) ---> removed.
> +   vsetvl a5,zero,...  ---> Inserted.
> +   vadd.vv
> +   ...
> +*/
> +static bool
> +vsetvl_pre_insn_p (rtx_insn *rinsn)
> +{
> +  return recog_memoized (rinsn) >= 0
> +&& get_attr_type (rinsn) == TYPE_VSETVL_PRE;
> +}
> +
>  /* Return true if it is vsetvl zero, rs1.  

Re: [PATCH v2] RISC-V: Add minimal support for 7 new unprivileged extensions

[Kito Cheng]

Pushed to trunk, thanks :)

On Thu, Feb 1, 2024 at 5:16 PM Monk Chiang  wrote:
>
> The RISC-V Profiles specification here:
> https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
>
> These extensions don't add any new features but
> describe existing features. So this patch only adds parsing.
>
> Za64rs: Reservation set size of 64 bytes
> Za128rs: Reservation set size of 128 bytes
> Ziccif: Main memory supports instruction fetch with atomicity requirement
> Ziccrse: Main memory supports forward progress on LR/SC sequences
> Ziccamoa: Main memory supports all atomics in A
> Zicclsm: Main memory supports misaligned loads/stores
> Zic64b: Cache block size isf 64 bytes
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
> Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
> * config/riscv/riscv.opt: New macro for 7 new unprivileged
> extensions.
> * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
> Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/za-ext.c: New test.
> * gcc.target/riscv/zi-ext.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc | 14 
>  gcc/config/riscv/riscv.opt  | 14 
>  gcc/doc/invoke.texi | 28 
>  gcc/testsuite/gcc.target/riscv/za-ext.c | 17 +++
>  gcc/testsuite/gcc.target/riscv/zi-ext.c | 29 +
>  5 files changed, 102 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/za-ext.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zi-ext.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 6ac0422ac13..631ce8309a0 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -247,6 +247,8 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>
>{"zicond", ISA_SPEC_CLASS_NONE, 1, 0},
>
> +  {"za64rs",  ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
>{"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
>
>{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -276,6 +278,11 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>{"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
>{"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
>{"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zic64b",   ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"ziccamoa", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"ziccif",   ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},
>
>{"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
>{"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},
> @@ -1494,6 +1501,8 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"zifencei", _options::x_riscv_zi_subext, MASK_ZIFENCEI},
>{"zicond",   _options::x_riscv_zi_subext, MASK_ZICOND},
>
> +  {"za64rs", _options::x_riscv_za_subext, MASK_ZA64RS},
> +  {"za128rs", _options::x_riscv_za_subext, MASK_ZA128RS},
>{"zawrs", _options::x_riscv_za_subext, MASK_ZAWRS},
>
>{"zba",_options::x_riscv_zb_subext, MASK_ZBA},
> @@ -1523,6 +1532,11 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"zicboz", _options::x_riscv_zicmo_subext, MASK_ZICBOZ},
>{"zicbom", _options::x_riscv_zicmo_subext, MASK_ZICBOM},
>{"zicbop", _options::x_riscv_zicmo_subext, MASK_ZICBOP},
> +  {"zic64b", _options::x_riscv_zicmo_subext, MASK_ZIC64B},
> +  {"ziccamoa", _options::x_riscv_zicmo_subext, MASK_ZICCAMOA},
> +  {"ziccif", _options::x_riscv_zicmo_subext, MASK_ZICCIF},
> +  {"zicclsm", _options::x_riscv_zicmo_subext, MASK_ZICCLSM},
> +  {"ziccrse", _options::x_riscv_zicmo_subext, MASK_ZICCRSE},
>
>{"zve32x",   _options::x_target_flags, MASK_VECTOR},
>{"zve32f",   _options::x_target_flags, MASK_VECTOR},
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index b6d8e9a3f74..f6ff70b2b30 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -225,11 +225,25 @@ Mask(ZIHINTPAUSE) Var(riscv_zi_subext)
>
>  Mask(ZICOND)  Var(riscv_zi_subext)
>
> +Mask(ZIC64B)  Var(riscv_zi_subext)
> +
> +Mask(ZICCAMOA)Var(riscv_zi_subext)
> +
> +Mask(ZICCIF)  Var(riscv_zi_subext)
> +
> +Mask(ZICCLSM) Var(riscv_zi_subext)
> +
> +Mask(ZICCRSE) Var(riscv_zi_subext)
> +
>  TargetVariable
>  int riscv_za_subext
>
>  Mask(ZAWRS) Var(riscv_za_subext)
>
> +Mask(ZA64RS)  Var(riscv_za_subext)
> +
> +Mask(ZA128RS) Var(riscv_za_subext)
> +
>  TargetVariable
>  int riscv_zb_subext
>
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index ca2c0e90452..09abd2aef31 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -30262,6 +30262,14 @@ Supported extension are listed below:
>  @tab 1.0
>  @tab Integer conditional operations extension.
>
> +@item za64rs
> +@tab 1.0
> 

Re: [PATCH] RISC-V: Add minimal support for 7 new unprivileged extensions

[Kito Cheng]

Could you add some document for doc/invoke.texi, I just added a list
for listing all supported extensions before[1].

[1] 
https://github.com/gcc-mirror/gcc/commit/19260a04ba6f75b1fae52afab50dcb43d44eb259

On Thu, Feb 1, 2024 at 4:29 PM Monk Chiang  wrote:
>
> The RISC-V Profiles specification here:
> https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#7-new-isa-extensions
>
> These extensions don't add any new features but
> describe existing features. So this patch only adds parsing.
>
> Za64rs: Reservation set size of 64 bytes
> Za128rs: Reservation set size of 128 bytes
> Ziccif: Main memory supports instruction fetch with atomicity requirement
> Ziccrse: Main memory supports forward progress on LR/SC sequences
> Ziccamoa: Main memory supports all atomics in A
> Zicclsm: Main memory supports misaligned loads/stores
> Zic64b: Cache block size isf 64 bytes
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
> Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
> * config/riscv/riscv.opt: New macro for 7 new unprivileged
> extensions.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/za-ext.c: New test.
> * gcc.target/riscv/zi-ext.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc | 14 
>  gcc/config/riscv/riscv.opt  | 14 
>  gcc/testsuite/gcc.target/riscv/za-ext.c | 17 +++
>  gcc/testsuite/gcc.target/riscv/zi-ext.c | 29 +
>  4 files changed, 74 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/za-ext.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zi-ext.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 6ac0422ac13..631ce8309a0 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -247,6 +247,8 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>
>{"zicond", ISA_SPEC_CLASS_NONE, 1, 0},
>
> +  {"za64rs",  ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
>{"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
>
>{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -276,6 +278,11 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>{"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
>{"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
>{"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zic64b",   ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"ziccamoa", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"ziccif",   ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},
>
>{"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
>{"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},
> @@ -1494,6 +1501,8 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"zifencei", _options::x_riscv_zi_subext, MASK_ZIFENCEI},
>{"zicond",   _options::x_riscv_zi_subext, MASK_ZICOND},
>
> +  {"za64rs", _options::x_riscv_za_subext, MASK_ZA64RS},
> +  {"za128rs", _options::x_riscv_za_subext, MASK_ZA128RS},
>{"zawrs", _options::x_riscv_za_subext, MASK_ZAWRS},
>
>{"zba",_options::x_riscv_zb_subext, MASK_ZBA},
> @@ -1523,6 +1532,11 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"zicboz", _options::x_riscv_zicmo_subext, MASK_ZICBOZ},
>{"zicbom", _options::x_riscv_zicmo_subext, MASK_ZICBOM},
>{"zicbop", _options::x_riscv_zicmo_subext, MASK_ZICBOP},
> +  {"zic64b", _options::x_riscv_zicmo_subext, MASK_ZIC64B},
> +  {"ziccamoa", _options::x_riscv_zicmo_subext, MASK_ZICCAMOA},
> +  {"ziccif", _options::x_riscv_zicmo_subext, MASK_ZICCIF},
> +  {"zicclsm", _options::x_riscv_zicmo_subext, MASK_ZICCLSM},
> +  {"ziccrse", _options::x_riscv_zicmo_subext, MASK_ZICCRSE},
>
>{"zve32x",   _options::x_target_flags, MASK_VECTOR},
>{"zve32f",   _options::x_target_flags, MASK_VECTOR},
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index b6d8e9a3f74..f6ff70b2b30 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -225,11 +225,25 @@ Mask(ZIHINTPAUSE) Var(riscv_zi_subext)
>
>  Mask(ZICOND)  Var(riscv_zi_subext)
>
> +Mask(ZIC64B)  Var(riscv_zi_subext)
> +
> +Mask(ZICCAMOA)Var(riscv_zi_subext)
> +
> +Mask(ZICCIF)  Var(riscv_zi_subext)
> +
> +Mask(ZICCLSM) Var(riscv_zi_subext)
> +
> +Mask(ZICCRSE) Var(riscv_zi_subext)
> +
>  TargetVariable
>  int riscv_za_subext
>
>  Mask(ZAWRS) Var(riscv_za_subext)
>
> +Mask(ZA64RS)  Var(riscv_za_subext)
> +
> +Mask(ZA128RS) Var(riscv_za_subext)
> +
>  TargetVariable
>  int riscv_zb_subext
>
> diff --git a/gcc/testsuite/gcc.target/riscv/za-ext.c 
> b/gcc/testsuite/gcc.target/riscv/za-ext.c
> new file mode 100644
> index 000..126da2fcadd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/za-ext.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_za64rs_za128rs" { target { rv64 } } } */
> 

Re: [PATCH] RISC-V: Allow constraint "S" even if the symbol does not bind locally

[Kito Cheng]

I realized there is 's' constraint which is defined in GCC generic
infra[1], and that's kinda what same as the new semantic of 'S' here,

(define_constraint "s"
 "Matches a symbolic integer constant."
 (and (match_test "CONSTANT_P (op)")
  (match_test "!CONST_SCALAR_INT_P (op)")
  (match_test "!flag_pic || LEGITIMATE_PIC_OPERAND_P (op)")))

Where const, symbol_ref and label_ref is match CONSTANT_P &&
!CONST_SCALAR_INT_P,
and LEGITIMATE_PIC_OPERAND_P is always 1 for RISC-V

The only difference is it also allows high, which is something like
%hi(sym), but I think it's harmless in the use case.

However I found LLVM also not work on " asm(".reloc ., BFD_RELOC_NONE,
%0" :: "S"(::a[3]));",
so maybe we could consider implement 's' in LLVM? and also add some
document in riscv-c-api.md

And just clarify, I don't have strong prefer on using 's', I am ok
with relaxing 'S' too,
propose using 's' is because that is work fine on RISC-V gcc for long
time and no backward compatible issue,
But I guess you have this proposal may came from ClangBuiltLinux, so
's' may not work for clang well due to backward compatible.

[1] 
https://gcc.gnu.org/onlinedocs/gcc/Simple-Constraints.html#index-s-in-constraint
[2] 
https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#constraints-on-operands-of-inline-assembly-statements

On Wed, Jan 31, 2024 at 1:02 PM Fangrui Song  wrote:
>
> The constraint "S" can only be used with a symbol that binds locally, so
> the following does not work for -fpie/-fpic (GOT access is used).
> ```
> namespace ns { extern int var, a[4]; }
> void foo() {
>   asm(".pushsection .xxx,\"aw\"; .dc.a %0; .popsection" :: "S"(::var));
>   asm(".reloc ., BFD_RELOC_NONE, %0" :: "S"(::a[3]));
> }
> ```
>
> This is overly restrictive, as many references like an absolute
> relocation in a writable section or a non-SHF_ALLOC section should be
> totally fine.  Allow symbols that do not bind locally, similar to
> aarch64 "S" and x86-64 "Ws" (commit d7250100381b817114447d91fff4748526d4fb21).
>
> gcc/ChangeLog:
>
> * config/riscv/constraints.md: Relax the condition for "S".
> * doc/md.texi: Update.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/asm-raw-symbol.c: New test.
> ---
>  gcc/config/riscv/constraints.md |  4 ++--
>  gcc/doc/md.texi |  2 +-
>  gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c | 17 +
>  3 files changed, 20 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c
>
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 41acaea04eb..bb012668fcb 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -121,8 +121,8 @@ (define_memory_constraint "A"
> (match_test "GET_CODE(XEXP(op,0)) == REG")))
>
>  (define_constraint "S"
> -  "A constraint that matches an absolute symbolic address."
> -  (match_operand 0 "absolute_symbolic_operand"))
> +  "A symbolic reference or label reference."
> +  (match_code "const,symbol_ref,label_ref"))
>
>  (define_constraint "U"
>"@internal
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index b0c61925120..c75e5bf259d 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -1947,7 +1947,7 @@ Integer constant that is valid as an immediate operand 
> in a 64-bit @code{MOV}
>  pseudo instruction
>
>  @item S
> -An absolute symbolic address or a label reference
> +A symbolic reference or label reference.
>
>  @item Y
>  Floating point constant zero
> diff --git a/gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c 
> b/gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c
> new file mode 100644
> index 000..eadf6d23fe1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/asm-raw-symbol.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-fpic" } */
> +
> +extern int var;
> +
> +void
> +func (void)
> +{
> +label:
> +  __asm__ ("@ %0" : : "S" (func));
> +  __asm__ ("@ %0" : : "S" ( + 1));
> +  __asm__ ("@ %0" : : "S" (&));
> +}
> +
> +/* { dg-final { scan-assembler "@ func" } } */
> +/* { dg-final { scan-assembler "@ var\\+4" } } */
> +/* { dg-final { scan-assembler "@ .L" } } */
> --
> 2.43.0.429.g432eaa2c6b-goog
>

Re: [PATCH v2] RISC-V: Bugfix for vls mode aggregated in GPR calling convention

[Kito Cheng]

Thanks for fixing this bug! LGTM with one minor comment :)


> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 7b6111aa545..1de69019cd4 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1382,6 +1382,38 @@ riscv_v_ext_mode_p (machine_mode mode)
>  || riscv_v_ext_vls_mode_p (mode);
>  }
>
> +static unsigned
> +riscv_v_vls_mode_aggregate_gpr_count (unsigned vls_unit_size,
> + unsigned scalar_unit_size)
> +{
> +  gcc_assert (vls_unit_size != 0 && scalar_unit_size != 0);
> +
> +  if (vls_unit_size < scalar_unit_size)
> +return 1;
> +

Add gcc_assert ((vls_unit_size % scalar_unit_size) == 0); here to make
sure no accident :P

> +  return vls_unit_size / scalar_unit_size;
> +}
> +

Re: [PATCH] riscv: Move UNSPEC_XTHEAD* from unspecv to unspec

[Kito Cheng]

Yeah, that should be put in unspec rather than unspecv, LGTM :)

On Tue, Jan 30, 2024 at 5:29 PM Christoph Müllner
 wrote:
>
> The UNSPEC_XTHEAD* macros ended up in the unspecv enum,
> which broke gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c.
> The INSNs expect these unspecs to be not volatile.
> Further, there is not reason to have them defined volatile.
> So let's simply move the macros into the unspec enum.
>
> With this patch we have again 0 fails in riscv.exp.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/config/riscv/riscv.md | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index edcaec4a786..b320ad0210e 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -89,6 +89,10 @@ (define_c_enum "unspec" [
>
>;; Workaround for HFmode without hardware extension
>UNSPEC_FMV_SFP16_X
> +
> +  ;; XTheadFmv moves
> +  UNSPEC_XTHEADFMV
> +  UNSPEC_XTHEADFMV_HW
>  ])
>
>  (define_c_enum "unspecv" [
> @@ -127,10 +131,6 @@ (define_c_enum "unspecv" [
>;; Zihintpause unspec
>UNSPECV_PAUSE
>
> -  ;; XTheadFmv unspec
> -  UNSPEC_XTHEADFMV
> -  UNSPEC_XTHEADFMV_HW
> -
>;; XTheadInt unspec
>UNSPECV_XTHEADINT_PUSH
>UNSPECV_XTHEADINT_POP
> --
> 2.43.0
>

Re: [PATCH v1] RISC-V: Bugfix for vls integer mode calling convention

[Kito Cheng]

> @@ -4868,6 +4968,63 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned 
> regno1,
>GEN_INT (offset2;
>  }
>
> +static rtx
> +riscv_pass_vls_aggregate_in_gpr_or_fpr (struct riscv_arg_info *info,
> +   machine_mode mode, unsigned gpr_base,
> +   unsigned fpr_base)

Tried a few more clang and GCC code gen and I found VLS vector is
always passed in
GPR, and never passed in FPR, so I think I should update psABI rather than fix
that on GCC side.

> @@ -4997,9 +5170,7 @@ riscv_get_arg_info (struct riscv_arg_info *info, const 
> CUMULATIVE_ARGS *cum,
>info->gpr_offset = cum->num_gprs;
>info->fpr_offset = cum->num_fprs;
>
> -  /* When disable vector_abi or scalable vector argument is anonymous, this
> - argument is passed by reference.  */
> -  if (riscv_v_ext_mode_p (mode) && (!riscv_vector_abi || !named))
> +  if (riscv_mode_pass_by_reference_p (mode, named))

Keep as it is fine since riscv_vector_abi is gone.

>  return NULL_RTX;
>
>if (named)

Re: [PATCH v2] RISC-V: THEAD: Fix improper immediate value for MODIFY_DISP instruction on 32-bit systems.

[Kito Cheng]

LGTM

Jin Ma  於 2024年1月29日 週一 17:57 寫道：

> When using  '%ld' to print 'long long int' variable, 'fprintf' will
> produce messy output on a 32-bit system, in an incorrect instruction
> being generated, such as 'th.lwib a1,(a0),-16,4294967295'. And the
> following error occurred during compilation:
>
> Assembler messages:
> Error: improper immediate value (18446744073709551615)
>
> gcc/ChangeLog:
>
> * config/riscv/thead.cc (th_print_operand_address): Change %ld
> to %lld.
> ---
>  gcc/config/riscv/thead.cc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
> index 2955bc5f8a9..e4b8c37bc28 100644
> --- a/gcc/config/riscv/thead.cc
> +++ b/gcc/config/riscv/thead.cc
> @@ -1141,7 +1141,7 @@ th_print_operand_address (FILE *file, machine_mode
> mode, rtx x)
>return true;
>
>  case ADDRESS_REG_WB:
> -  fprintf (file, "(%s),%ld,%u", reg_names[REGNO (addr.reg)],
> +  fprintf (file, "(%s),"HOST_WIDE_INT_PRINT_DEC",%u", reg_names[REGNO
> (addr.reg)],
>INTVAL (addr.offset) >> addr.shift, addr.shift);
> return true;
>
> --
> 2.17.1
>
>

Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension

[Kito Cheng]

pushed :)

On Thu, Jan 25, 2024 at 9:53 PM Kito Cheng  wrote:
>
> It's stage 4, so I think it would be great to not disturb code base
> too much, and adding intrinsic without adding VLS modes should be
> better way to go, and  here is not really something serious coding
> style issue, just few minor indentation issue, so I gonna run
> regression to make not break anything else and then commit to trunk :)

Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension

[Kito Cheng]

It's stage 4, so I think it would be great to not disturb code base
too much, and adding intrinsic without adding VLS modes should be
better way to go, and  here is not really something serious coding
style issue, just few minor indentation issue, so I gonna run
regression to make not break anything else and then commit to trunk :)

Re: [PATCH] RISC-V: Fix incorrect LCM delete bug [VSETVL PASS]

[Kito Cheng]

Use this reduced testcase, but please verify this in your end again.
For the code change part, I would like to let other to review :P

struct a {
 int b;
 int c : 1;
 int : 1;
} d();
typedef struct
{
 int e;
 struct {
   int f;
 };
} g;
int i;
char k, l, n;
void *m;
char *o;
void h();
char *j();
void p(int buf, __builtin_va_list ab, int q) {
 do {
   void *r[] = {&, &, &, &, &};
   int c;
   goto *m;
 s:
   c = 1;
   while (1) {
   t:
   u:
   ae:
 void *af = __builtin_va_arg(ab, void *);
 h(p);
 o = j(i);
 if (o == 0)
   goto ae;
 l = 'S';
 break;
   v:
 g ah;
 __builtin_memset(, '\0', sizeof(g));
 h(n, __builtin_va_arg(ab, int), );
 break;
   w:
 if (__builtin_expect(q, 0))
   c = 0;
 struct a ai = {'S', c};
 d(buf, ai, af);
   }
 } while (k);
}

On Thu, Jan 25, 2024 at 8:34 PM Juzhe-Zhong  wrote:
>
> This patch fixes the recent noticed bug in RV32 glibc.
>
> We incorrectly deleted a vsetvl:
>
> ...
> and a4,a4,a3
> vmv.v.i v1,0 ---> Missed vsetvl cause illegal 
> instruction report.
> vse8.v  v1,0(a5)
>
> The root cause the laterin in LCM is incorrect.
>
>   BB 358:
> avloc: n_bits = 2, set = {}
> kill: n_bits = 2, set = {}
> antloc: n_bits = 2, set = {}
> transp: n_bits = 2, set = {}
> avin: n_bits = 2, set = {}
> avout: n_bits = 2, set = {}
> del: n_bits = 2, set = {}
>
> cause LCM let BB 360 delete the vsetvl:
>
>   BB 360:
> avloc: n_bits = 2, set = {}
> kill: n_bits = 2, set = {}
> antloc: n_bits = 2, set = {}
> transp: n_bits = 2, set = {0 1 }
> avin: n_bits = 2, set = {}
> avout: n_bits = 2, set = {}
> del: n_bits = 2, set = {1}
>
> Also, remove unknown vsetvl info into local computation since it is 
> unnecessary.
>
> Tested on both RV32/RV64 no regression.
>
> PR target/113469
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc 
> (pre_vsetvl::compute_lcm_local_properties): Fix bug.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/pr113469.c: New test.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc  |   21 +-
>  .../gcc.target/riscv/rvv/autovec/pr113469.c   | 1841 +
>  2 files changed, 1853 insertions(+), 9 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113469.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index da258b964fc..f300f00e62a 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -2543,8 +2543,10 @@ pre_vsetvl::compute_lcm_local_properties ()
>vsetvl_info _info = block_info.get_entry_info ();
>vsetvl_info _info = block_info.get_exit_info ();
>gcc_assert (footer_info.valid_p () || footer_info.unknown_p ());
> -  add_expr (m_exprs, header_info);
> -  add_expr (m_exprs, footer_info);
> +  if (header_info.valid_p ())
> +   add_expr (m_exprs, header_info);
> +  if (footer_info.valid_p ())
> +   add_expr (m_exprs, footer_info);
>  }
>
>int num_exprs = m_exprs.length ();
> @@ -2699,13 +2701,6 @@ pre_vsetvl::compute_lcm_local_properties ()
>   }
>  }
>
> -  for (const bb_info *bb : crtl->ssa->bbs ())
> -{
> -  unsigned bb_index = bb->index ();
> -  bitmap_ior (m_kill[bb_index], m_transp[bb_index], m_avloc[bb_index]);
> -  bitmap_not (m_kill[bb_index], m_kill[bb_index]);
> -}
> -
>for (const bb_info *bb : crtl->ssa->bbs ())
>  {
>unsigned bb_index = bb->index ();
> @@ -2713,8 +2708,16 @@ pre_vsetvl::compute_lcm_local_properties ()
> {
>   bitmap_clear (m_antloc[bb_index]);
>   bitmap_clear (m_transp[bb_index]);
> + bitmap_clear (m_avloc[bb_index]);
> }
>  }
> +
> +  for (const bb_info *bb : crtl->ssa->bbs ())
> +{
> +  unsigned bb_index = bb->index ();
> +  bitmap_ior (m_kill[bb_index], m_transp[bb_index], m_avloc[bb_index]);
> +  bitmap_not (m_kill[bb_index], m_kill[bb_index]);
> +}
>  }
>
>  void
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113469.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113469.c
> new file mode 100644
> index 000..2502040772b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113469.c
> @@ -0,0 +1,1841 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +static int read_int (const unsigned char * *pstr) {};
> +static const char null[] = "(null)";
> +extern size_t __strnlen (const char *__string, size_t __maxlen) 
> __attribute__ ((__pure__));
> +
> +struct printf_info
> +{
> +  int prec;
> +  int width;
> +  wchar_t spec;
> +  unsigned int is_long_double:1;
> +  unsigned int is_short:1;
> +  unsigned int is_long:1;
> +  unsigned int alt:1;

Re: [PATCH] RISC-V: Add LCM delete block predecessors dump information

[Kito Cheng]

LGTM, it's always good to improve some debug for vsetvli insertion
pass, it's really non-trivial optimization.

On Thu, Jan 25, 2024 at 4:59 PM Juzhe-Zhong  wrote:
>
> While looking into PR113469, I notice the LCM delete a vsetvl incorrectly.
>
> This patch add dump information of all predecessors for LCM delete vsetvl 
> block
> for better debugging.
>
> Tested no regression.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
> (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all 
> predecessors dump information.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 42 
>  1 file changed, 42 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 72c5a127d9e..da258b964fc 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -654,6 +654,31 @@ invalid_opt_bb_p (basic_block cfg_bb)
>return false;
>  }
>
> +/* Get all predecessors of BB.  */
> +static hash_set
> +get_all_predecessors (basic_block bb)
> +{
> +  hash_set blocks;
> +  auto_vec work_list;
> +  hash_set visited_list;
> +  work_list.safe_push (bb);
> +
> +  while (!work_list.is_empty ())
> +{
> +  basic_block new_bb = work_list.pop ();
> +  visited_list.add (new_bb);
> +  edge e;
> +  edge_iterator ei;
> +  FOR_EACH_EDGE (e, ei, new_bb->preds)
> +   {
> + if (!visited_list.contains (e->src))
> +   work_list.safe_push (e->src);
> + blocks.add (e->src);
> +   }
> +}
> +  return blocks;
> +}
> +
>  /* This flags indicates the minimum demand of the vl and vtype values by the
> RVV instruction. For example, DEMAND_RATIO_P indicates that this RVV
> instruction only needs the SEW/LMUL ratio to remain the same, and does not
> @@ -3142,6 +3167,23 @@ pre_vsetvl::pre_global_vsetvl_info ()
>const vsetvl_block_info _info = get_block_info (info.get_bb ());
>gcc_assert (block_info.get_entry_info () == info);
>info.set_delete ();
> +  if (dump_file && (dump_flags & TDF_DETAILS))
> +   {
> + fprintf (dump_file,
> +  "\nLCM deleting vsetvl of block %d, it has predecessors: 
> \n",
> +  bb->index ());
> + hash_set all_preds
> +   = get_all_predecessors (bb->cfg_bb ());
> + int i = 0;
> + for (const auto pred : all_preds)
> +   {
> + fprintf (dump_file, "%d ", pred->index);
> + i++;
> + if (i % 32 == 0)
> +   fprintf (dump_file, "\n");
> +   }
> + fprintf (dump_file, "\n");
> +   }
>  }
>
>/* Remove vsetvl infos if all precessors are available to the block.  */
> --
> 2.36.3
>

Re: [PATCH] RISC-V: Fix vfirst/vmsbf/vmsif/vmsof ratio attributes

[Kito Cheng]

LGTM :)

On Mon, Jan 22, 2024 at 10:49 AM Juzhe-Zhong  wrote:
>
> vfirst/vmsbf/vmsif/vmsof instructions are supposed to demand ratio instead of 
> demanding sew_lmul.
> But my previous typo makes VSETVL PASS miss honor the risc-v v spec.
>
> Consider this following simple case:
>
> int foo4 (void * in, void * out)
> {
>   vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
>   v = __riscv_vadd_vv_i32m1 (v, v, 4);
>   vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32(v);
>   mask = __riscv_vmsof_m_b32(mask, 4);
>   return __riscv_vfirst_m_b32(mask, 4);
> }
>
> Before this patch:
>
> foo4:
> vsetivlizero,4,e32,m1,ta,ma
> vle32.v v1,0(a0)
> vadd.vv v1,v1,v1
> vsetvli zero,zero,e8,mf4,ta,ma> redundant.
> vmsof.m v2,v1
> vfirst.ma0,v2
> ret
>
> After this patch:
>
> foo4:
> vsetivlizero,4,e32,m1,ta,ma
> vle32.v v1,0(a0)
> vadd.vv v1,v1,v1
> vmsof.m v2,v1
> vfirst.ma0,v2
> ret
>
> Confirm RVV spec and Clang, this patch makes VSETVL PASS match the correct 
> behavior.
>
> Tested on both RV32/RV64, no regression.
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/attribute-1.c: New test.
>
> ---
>  gcc/config/riscv/vector.md|  2 +-
>  .../gcc.target/riscv/rvv/vsetvl/attribute-1.c | 47 +++
>  2 files changed, 48 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c
>
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index cfc54ae5eac..307d9a8c952 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -433,7 +433,7 @@
>   vialu,vshift,vicmp,vimul,vidiv,vsalu,\
>   vext,viwalu,viwmul,vicalu,vnshift,\
>   vimuladd,vimerge,vaalu,vsmul,vsshift,\
> - vnclip,viminmax,viwmuladd,vmffs,vmsfs,\
> + vnclip,viminmax,viwmuladd,\
>   vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,\
>   vfwalu,vfwmul,vfsqrt,vfrecp,vfsgnj,vfcmp,\
>   vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c
> new file mode 100644
> index 000..28dcf986bac
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c
> @@ -0,0 +1,47 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +int
> +foo (void *in, void *out)
> +{
> +  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
> +  v = __riscv_vadd_vv_i32m1 (v, v, 4);
> +  vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32 (v);
> +  return __riscv_vfirst_m_b32 (mask, 4);
> +}
> +
> +int
> +foo2 (void *in, void *out)
> +{
> +  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
> +  v = __riscv_vadd_vv_i32m1 (v, v, 4);
> +  vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32 (v);
> +  mask = __riscv_vmsbf_m_b32 (mask, 4);
> +  return __riscv_vfirst_m_b32 (mask, 4);
> +}
> +
> +int
> +foo3 (void *in, void *out)
> +{
> +  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
> +  v = __riscv_vadd_vv_i32m1 (v, v, 4);
> +  vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32 (v);
> +  mask = __riscv_vmsif_m_b32 (mask, 4);
> +  return __riscv_vfirst_m_b32 (mask, 4);
> +}
> +
> +int
> +foo4 (void *in, void *out)
> +{
> +  vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
> +  v = __riscv_vadd_vv_i32m1 (v, v, 4);
> +  vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32 (v);
> +  mask = __riscv_vmsof_m_b32 (mask, 4);
> +  return __riscv_vfirst_m_b32 (mask, 4);
> +}
> +
> +/* { dg-final { scan-assembler-times 
> {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 4 } } */
> +/* { dg-final { scan-assembler-times {vsetivli} 4 } } */
> +/* { dg-final { scan-assembler-not {vsetvli} } } */
> --
> 2.36.3
>

[committed] RISC-V: Update testcase due to message update

[Kito Cheng]

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-27.c: Update scan message.
* gcc.target/riscv/arch-28.c: Ditto.
* gcc.target/riscv/attribute-10.c: Ditto.
* gcc.target/riscv/rvv/base/big_endian-2.c: Ditto.
* gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: Ditto.
* gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: Ditto.
---
 gcc/testsuite/gcc.target/riscv/arch-27.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/arch-28.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/attribute-10.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c| 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/arch-27.c 
b/gcc/testsuite/gcc.target/riscv/arch-27.c
index 03f07deedd1..95cebc1a2da 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-27.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-27.c
@@ -4,4 +4,4 @@ int foo()
 {
 }
 
-/* { dg-error "'i', 'e' or 'g' must be the first extension" "" { target *-*-* 
} 0 } */
+/* { dg-error "i, e or g must be the first extension" "" { target *-*-* } 0 } 
*/
diff --git a/gcc/testsuite/gcc.target/riscv/arch-28.c 
b/gcc/testsuite/gcc.target/riscv/arch-28.c
index 0f83c03ad3d..21c748edf5c 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-28.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-28.c
@@ -4,4 +4,4 @@ int foo()
 {
 }
 
-/* { dg-error "'i', 'e' or 'g' must be the first extension" "" { target *-*-* 
} 0 } */
+/* { dg-error "i, e or g must be the first extension" "" { target *-*-* } 0 } 
*/
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-10.c 
b/gcc/testsuite/gcc.target/riscv/attribute-10.c
index 8a7f0a8ac49..4aaa2bbcd45 100644
--- a/gcc/testsuite/gcc.target/riscv/attribute-10.c
+++ b/gcc/testsuite/gcc.target/riscv/attribute-10.c
@@ -5,4 +5,4 @@ int foo()
 }
 /* { dg-error "extension 'u' is unsupported standard single letter extension" 
"" { target { "riscv*-*-*" } } 0 } */
 /* { dg-error "extension 'n' is unsupported standard single letter extension" 
"" { target { "riscv*-*-*" } } 0 } */
-/* { dg-error "'i', 'e' or 'g' must be the first extension" "" { target { 
"riscv*-*-*" } } 0 } */
+/* { dg-error "i, e or g must be the first extension" "" { target { 
"riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c
index 86cf58370bf..45cc97e1f01 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c
@@ -2,4 +2,4 @@
 /* { dg-options "-march=rv64gc_zve32x -mabi=lp64d -mbig-endian -O3" } */
 
 #pragma riscv intrinsic "vector"
-vint32m1_t foo (vint32m1_t) {} // { dg-excess-errors "sorry, unimplemented: 
Current RISC-V GCC cannot support RVV in big-endian mode" }
+vint32m1_t foo (vint32m1_t) {} // { dg-excess-errors "sorry, unimplemented: 
Current RISC-V GCC does not support RVV in big-endian mode" }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
index 03f67035ca4..1912a2457c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
 /* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param 
riscv-autovec-preference=fixed-vlmax" } */
 
-void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC 
can not support VLEN > 4096bit for 'V' Extension" }
+void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC 
does not support VLEN > 4096bit for 'V' Extension" }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
index 075112f2f81..884e834fb90 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
@@ -1,4 +1,4 @@
 /* { dg-do compile } */
 /* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param 
riscv-autovec-preference=scalable" } */
 
-void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC 
can not support VLEN > 4096bit for 'V' Extension" }
+void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC 
does not support VLEN > 4096bit for 'V' Extension" }
-- 
2.34.1

Re: [PATCH v2] RISC-V: Documnet the list of supported extensions

[Kito Cheng]

Pushed to trunk, thanks :)

On Fri, Jan 19, 2024 at 5:41 PM juzhe.zh...@rivai.ai
 wrote:
>
> LGTM.
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2024-01-19 17:40
> To: gcc-patches; kito.cheng; jim.wilson.gcc; palmer; andrew; jeffreyalaw; 
> christoph.muellner; juzhe.zhong; rep.dot.nop
> CC: Kito Cheng
> Subject: [PATCH v2] RISC-V: Documnet the list of supported extensions
> Try to list all supported extensions: name, version and few description
> for each extension.
>
> v2 changes:
> - Fix several typo.
> - Add expantion info for vector crypto extensions.
> - Drop zvl8192b, zvl16384b, zvl32768b and zvl65536b.
> - Aadd zicntr and zihpm
>
> gcc/ChangeLog:
>
> * doc/invoke.texi (RISC-V Options): Add list of supported
> extensions.
> ---
> gcc/doc/invoke.texi | 461 
> 1 file changed, 461 insertions(+)
>
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index c0e513c8f27..313f363f5f2 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -30113,6 +30113,467 @@ syntax @samp{p} or @samp{}, 
> (e.g.@: @samp{m2p1} or
> @samp{m2}).
> @end table
> +Supported extension are listed below:
> +@multitable @columnfractions .10 .10 .80
> +@headitem Extension Name @tab Supported Version @tab Description
> +@item i
> +@tab 2.0, 2.1
> +@tab Base integer extension.
> +
> +@item e
> +@tab 2.0
> +@tab Reduced base integer extension.
> +
> +@item g
> +@tab -
> +@tab General-purpose computing base extension, @samp{g} will expand to
> +@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and
> +@samp{zifencei}.
> +
> +@item m
> +@tab 2.0
> +@tab Integer multiplication and division extension.
> +
> +@item a
> +@tab 2.0, 2.1
> +@tab Atomic extension.
> +
> +@item f
> +@tab 2.0, 2.2
> +@tab Single-precision floating-point extension.
> +
> +@item d
> +@tab 2.0, 2.2
> +@tab Double-precision floating-point extension.
> +
> +@item c
> +@tab 2.0
> +@tab Compressed extension.
> +
> +@item h
> +@tab 1.0
> +@tab Hypervisor extension.
> +
> +@item v
> +@tab 1.0
> +@tab Vector extension.
> +
> +@item zicsr
> +@tab 2.0
> +@tab Control and status register access extension.
> +
> +@item zifencei
> +@tab 2.0
> +@tab Instruction-fetch fence extension.
> +
> +@item zicond
> +@tab 1.0
> +@tab Integer conditional operations extension.
> +
> +@item zawrs
> +@tab 1.0
> +@tab Wait-on-reservation-set extension.
> +
> +@item zba
> +@tab 1.0
> +@tab Address calculation extension.
> +
> +@item zbb
> +@tab 1.0
> +@tab Basic bit manipulation extension.
> +
> +@item zbc
> +@tab 1.0
> +@tab Carry-less multiplication extension.
> +
> +@item zbs
> +@tab 1.0
> +@tab Single-bit operation extension.
> +
> +@item zfinx
> +@tab 1.0
> +@tab Single-precision floating-point in integer registers extension.
> +
> +@item zdinx
> +@tab 1.0
> +@tab Double-precision floating-point in integer registers extension.
> +
> +@item zhinx
> +@tab 1.0
> +@tab Half-precision floating-point in integer registers extension.
> +
> +@item zhinxmin
> +@tab 1.0
> +@tab Minimal half-precision floating-point in integer registers extension.
> +
> +@item zbkb
> +@tab 1.0
> +@tab Cryptography bit-manipulation extension.
> +
> +@item zbkc
> +@tab 1.0
> +@tab Cryptography carry-less multiply extension.
> +
> +@item zbkx
> +@tab 1.0
> +@tab Cryptography crossbar permutation extension.
> +
> +@item zkne
> +@tab 1.0
> +@tab AES Encryption extension.
> +
> +@item zknd
> +@tab 1.0
> +@tab AES Decryption extension.
> +
> +@item zknh
> +@tab 1.0
> +@tab Hash function extension.
> +
> +@item zkr
> +@tab 1.0
> +@tab Entropy source extension.
> +
> +@item zksed
> +@tab 1.0
> +@tab SM4 block cipher extension.
> +
> +@item zksh
> +@tab 1.0
> +@tab SM3 hash function extension.
> +
> +@item zkt
> +@tab 1.0
> +@tab Data independent execution latency extension.
> +
> +@item zk
> +@tab 1.0
> +@tab Standard scalar cryptography extension.
> +
> +@item zkn
> +@tab 1.0
> +@tab NIST algorithm suite extension.
> +
> +@item zks
> +@tab 1.0
> +@tab ShangMi algorithm suite extension.
> +
> +@item zihintntl
> +@tab 1.0
> +@tab Non-temporal locality hints extension.
> +
> +@item zihintpause
> +@tab 1.0
> +@tab Pause hint extension.
> +
> +@item zicboz
> +@tab 1.0
> +@tab Cache-block zero extension.
> +
> +@item zicbom
> +@tab 1.0
> +@tab Cache-block management extension.
> +
> +@item zicbop
> +@tab 1.0
> +@t

Re: [PATCH] RISC-V: Documnet the list of supported extensions

[Kito Cheng]

Hi Bernhard:

Thanks for such careful review! V2 send :)

On Tue, Jan 16, 2024 at 4:08 AM Bernhard Reutner-Fischer
 wrote:
>
> Hi Kito!
>
> On Thu, 11 Jan 2024 17:06:09 +0800
> Kito Cheng  wrote:
>
> > Try to list all supported extensions: name, version and few description
> > for each extension.
> >
> > gcc/ChangeLog:
> >
> >   * doc/invoke.texi (RISC-V Options): Add list of supported
> >   extensions.
> > ---
> >  gcc/doc/invoke.texi | 463 
> >  1 file changed, 463 insertions(+)
> >
> > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> > index 68d1f364ac0..58271f2f28e 100644
> > --- a/gcc/doc/invoke.texi
> > +++ b/gcc/doc/invoke.texi
> > @@ -30037,6 +30037,469 @@ Generate code for given RISC-V ISA (e.g.@: 
> > @samp{rv64im}).  ISA strings must be
> >  lower-case.  Examples include @samp{rv64i}, @samp{rv32g}, @samp{rv32e}, and
> >  @samp{rv32imaf}.
> >
> > +Supported extension are list below:
>
> are listed
>
> > +@multitable @columnfractions .10 .10 .80
> > +@headitem Extension Name @tab Supported Version @tab Description
> > +@item i
> > +@tab 2.0, 2.1
> > +@tab Base integer extension.
> > +
> > +@item e
> > +@tab 2.0
> > +@tab Reduced base integer extension.
> > +
> > +@item g
> > +@tab -
> > +@tab General-purpose computing base extension, @samp{g} will expand to
> > +@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and
> > +@samp{zifencei}.
> > +
> > +@item m
> > +@tab 2.0
> > +@tab Integer multiplication and division extension.
> > +
> > +@item a
> > +@tab 2.0, 2.1
> > +@tab Atomic extension.
> > +
> > +@item f
> > +@tab 2.0, 2.2
> > +@tab Single-precision floating-point extension.
> > +
> > +@item d
> > +@tab 2.0, 2.2
> > +@tab Double-precision floating-point extension.
> > +
> > +@item c
> > +@tab 2.0
> > +@tab Compressed extension.
> > +
> > +@item h
> > +@tab 1.0
> > +@tab Hypervisor extension.
> > +
> > +@item v
> > +@tab 1.0
> > +@tab Vector extension.
> > +
> > +@item zicsr
> > +@tab 2.0
> > +@tab Control and status register access extension.
> > +
> > +@item zifencei
> > +@tab 2.0
> > +@tab Instruction-fetch fence extension.
> > +
> > +@item zicond
> > +@tab 1.0
> > +@tab Integer conditional operations extension.
> > +
> > +@item zawrs
> > +@tab 1.0
> > +@tab Wait-on-reservation-set extension.
> > +
> > +@item zba
> > +@tab 1.0
> > +@tab Address calculation extension.
> > +
> > +@item zbb
> > +@tab 1.0
> > +@tab Basic bit manipulation extension.
> > +
> > +@item zbc
> > +@tab 1.0
> > +@tab Carry-less multiplication extension.
> > +
> > +@item zbs
> > +@tab 1.0
> > +@tab Single-bit operation extension.
> > +
> > +@item zfinx
> > +@tab 1.0
> > +@tab Single-precision floating-ioint in integer registers extension.
>
> s/ioint/point/g
> above and below.
>
> > +
> > +@item zdinx
> > +@tab 1.0
> > +@tab Double-precision floating-ioint in integer registers extension.
> > +
> > +@item zhinx
> > +@tab 1.0
> > +@tab Half-precision floating-ioint in integer registers extension.
> > +
> > +@item zhinxmin
> > +@tab 1.0
> > +@tab Minimal half-precision floating-ioint in integer registers extension.
> > +
> > +@item zbkb
> > +@tab 1.0
> > +@tab Cryptography bit-manipulation extension.
> > +
> > +@item zbkc
> > +@tab 1.0
> > +@tab Cryptography carry-less multiply extension.
> > +
> > +@item zbkx
> > +@tab 1.0
> > +@tab Cryptography crossbar permutation extension.
> > +
> > +@item zkne
> > +@tab 1.0
> > +@tab AES Encryption extension.
> > +
> > +@item zknd
> > +@tab 1.0
> > +@tab AES Decryption extension.
> > +
> > +@item zknh
> > +@tab 1.0
> > +@tab Hash function extension.
> > +
> > +@item zkr
> > +@tab 1.0
> > +@tab Entropy source extension.
> > +
> > +@item zksed
> > +@tab 1.0
> > +@tab SM4 block cipher extension.
> > +
> > +@item zksh
> > +@tab 1.0
> > +@tab SM3 hash function extension.
> > +
> > +@item zkt
> > +@tab 1.0
> > +@tab Data independent execution latency extension.
> > +
> > +@item zk
> > +@tab 1.0
> > +@tab Standard scalar cryptography extension.
>

[PATCH v2] RISC-V: Documnet the list of supported extensions

[Kito Cheng]

Try to list all supported extensions: name, version and few description
for each extension.

v2 changes:
 - Fix several typo.
 - Add expantion info for vector crypto extensions.
 - Drop zvl8192b, zvl16384b, zvl32768b and zvl65536b.
 - Aadd zicntr and zihpm

gcc/ChangeLog:

* doc/invoke.texi (RISC-V Options): Add list of supported
extensions.
---
 gcc/doc/invoke.texi | 461 
 1 file changed, 461 insertions(+)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index c0e513c8f27..313f363f5f2 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -30113,6 +30113,467 @@ syntax @samp{p} or @samp{}, 
(e.g.@: @samp{m2p1} or
 @samp{m2}).
 @end table
 
+Supported extension are listed below:
+@multitable @columnfractions .10 .10 .80
+@headitem Extension Name @tab Supported Version @tab Description
+@item i
+@tab 2.0, 2.1
+@tab Base integer extension.
+
+@item e
+@tab 2.0
+@tab Reduced base integer extension.
+
+@item g
+@tab -
+@tab General-purpose computing base extension, @samp{g} will expand to
+@samp{i}, @samp{m}, @samp{a}, @samp{f}, @samp{d}, @samp{zicsr} and
+@samp{zifencei}.
+
+@item m
+@tab 2.0
+@tab Integer multiplication and division extension.
+
+@item a
+@tab 2.0, 2.1
+@tab Atomic extension.
+
+@item f
+@tab 2.0, 2.2
+@tab Single-precision floating-point extension.
+
+@item d
+@tab 2.0, 2.2
+@tab Double-precision floating-point extension.
+
+@item c
+@tab 2.0
+@tab Compressed extension.
+
+@item h
+@tab 1.0
+@tab Hypervisor extension.
+
+@item v
+@tab 1.0
+@tab Vector extension.
+
+@item zicsr
+@tab 2.0
+@tab Control and status register access extension.
+
+@item zifencei
+@tab 2.0
+@tab Instruction-fetch fence extension.
+
+@item zicond
+@tab 1.0
+@tab Integer conditional operations extension.
+
+@item zawrs
+@tab 1.0
+@tab Wait-on-reservation-set extension.
+
+@item zba
+@tab 1.0
+@tab Address calculation extension.
+
+@item zbb
+@tab 1.0
+@tab Basic bit manipulation extension.
+
+@item zbc
+@tab 1.0
+@tab Carry-less multiplication extension.
+
+@item zbs
+@tab 1.0
+@tab Single-bit operation extension.
+
+@item zfinx
+@tab 1.0
+@tab Single-precision floating-point in integer registers extension.
+
+@item zdinx
+@tab 1.0
+@tab Double-precision floating-point in integer registers extension.
+
+@item zhinx
+@tab 1.0
+@tab Half-precision floating-point in integer registers extension.
+
+@item zhinxmin
+@tab 1.0
+@tab Minimal half-precision floating-point in integer registers extension.
+
+@item zbkb
+@tab 1.0
+@tab Cryptography bit-manipulation extension.
+
+@item zbkc
+@tab 1.0
+@tab Cryptography carry-less multiply extension.
+
+@item zbkx
+@tab 1.0
+@tab Cryptography crossbar permutation extension.
+
+@item zkne
+@tab 1.0
+@tab AES Encryption extension.
+
+@item zknd
+@tab 1.0
+@tab AES Decryption extension.
+
+@item zknh
+@tab 1.0
+@tab Hash function extension.
+
+@item zkr
+@tab 1.0
+@tab Entropy source extension.
+
+@item zksed
+@tab 1.0
+@tab SM4 block cipher extension.
+
+@item zksh
+@tab 1.0
+@tab SM3 hash function extension.
+
+@item zkt
+@tab 1.0
+@tab Data independent execution latency extension.
+
+@item zk
+@tab 1.0
+@tab Standard scalar cryptography extension.
+
+@item zkn
+@tab 1.0
+@tab NIST algorithm suite extension.
+
+@item zks
+@tab 1.0
+@tab ShangMi algorithm suite extension.
+
+@item zihintntl
+@tab 1.0
+@tab Non-temporal locality hints extension.
+
+@item zihintpause
+@tab 1.0
+@tab Pause hint extension.
+
+@item zicboz
+@tab 1.0
+@tab Cache-block zero extension.
+
+@item zicbom
+@tab 1.0
+@tab Cache-block management extension.
+
+@item zicbop
+@tab 1.0
+@tab Cache-block prefetch extension.
+
+@item zicntr
+@tab 2.0
+@tab Standard extension for base counters and timers.
+
+@item zihpm
+@tab 2.0
+@tab Standard extension for hardware performance counters.
+
+@item ztso
+@tab 1.0
+@tab Total store ordering extension.
+
+@item zve32x
+@tab 1.0
+@tab Vector extensions for embedded processors.
+
+@item zve32f
+@tab 1.0
+@tab Vector extensions for embedded processors.
+
+@item zve64x
+@tab 1.0
+@tab Vector extensions for embedded processors.
+
+@item zve64f
+@tab 1.0
+@tab Vector extensions for embedded processors.
+
+@item zve64d
+@tab 1.0
+@tab Vector extensions for embedded processors.
+
+@item zvl32b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl64b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl128b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl256b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl512b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl1024b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl2048b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvl4096b
+@tab 1.0
+@tab Minimum vector length standard extensions
+
+@item zvbb
+@tab 1.0
+@tab Vector basic bit-manipulation extension.
+
+@item zvbc
+@tab 1.0
+@tab Vector carryless multiplication extension.

Re: [PATCH 0/5] RISC-V: Relax the -march string for accept any order

[Kito Cheng]

Oh, ok, I must have missed something during testing.

On Fri, Jan 19, 2024 at 5:37 PM juzhe.zh...@rivai.ai
 wrote:
>
> Hi, kito.
>
> I found these following regression:
>
> FAIL: gcc.target/riscv/arch-27.c   -O0   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-27.c   -O0  (test for excess errors)
> FAIL: gcc.target/riscv/arch-27.c   -O1   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-27.c   -O1  (test for excess errors)
> FAIL: gcc.target/riscv/arch-27.c   -O2   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-27.c   -O2  (test for excess errors)
> FAIL: gcc.target/riscv/arch-27.c   -O2 -flto -fno-use-linker-plugin 
> -flto-partition=none   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-27.c   -O2 -flto -fno-use-linker-plugin 
> -flto-partition=none  (test for excess errors)
> FAIL: gcc.target/riscv/arch-27.c   -O2 -flto -fuse-linker-plugin 
> -fno-fat-lto-objects   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-27.c   -O2 -flto -fuse-linker-plugin 
> -fno-fat-lto-objects  (test for excess errors)
> FAIL: gcc.target/riscv/arch-27.c   -O3 -g   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-27.c   -O3 -g  (test for excess errors)
> FAIL: gcc.target/riscv/arch-27.c   -Os   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-27.c   -Os  (test for excess errors)
> FAIL: gcc.target/riscv/arch-28.c   -O0   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-28.c   -O0  (test for excess errors)
> FAIL: gcc.target/riscv/arch-28.c   -O1   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-28.c   -O1  (test for excess errors)
> FAIL: gcc.target/riscv/arch-28.c   -O2   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-28.c   -O2  (test for excess errors)
> FAIL: gcc.target/riscv/arch-28.c   -O2 -flto -fno-use-linker-plugin 
> -flto-partition=none   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-28.c   -O2 -flto -fno-use-linker-plugin 
> -flto-partition=none  (test for excess errors)
> FAIL: gcc.target/riscv/arch-28.c   -O2 -flto -fuse-linker-plugin 
> -fno-fat-lto-objects   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-28.c   -O2 -flto -fuse-linker-plugin 
> -fno-fat-lto-objects  (test for excess errors)
> FAIL: gcc.target/riscv/arch-28.c   -O3 -g   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-28.c   -O3 -g  (test for excess errors)
> FAIL: gcc.target/riscv/arch-28.c   -Os   at line 7 (test for errors, line )
> FAIL: gcc.target/riscv/arch-28.c   -Os  (test for excess errors)
> FAIL: gcc.target/riscv/attribute-10.c   -O0   at line 8 (test for errors, 
> line )
> FAIL: gcc.target/riscv/attribute-10.c   -O0  (test for excess errors)
> FAIL: gcc.target/riscv/attribute-10.c   -O1   at line 8 (test for errors, 
> line )
> FAIL: gcc.target/riscv/attribute-10.c   -O1  (test for excess errors)
> FAIL: gcc.target/riscv/attribute-10.c   -O2   at line 8 (test for errors, 
> line )
> FAIL: gcc.target/riscv/attribute-10.c   -O2  (test for excess errors)
> FAIL: gcc.target/riscv/attribute-10.c   -O2 -flto -fno-use-linker-plugin 
> -flto-partition=none   at line 8 (test for errors, line )
> FAIL: gcc.target/riscv/attribute-10.c   -O2 -flto -fno-use-linker-plugin 
> -flto-partition=none  (test for excess errors)
> FAIL: gcc.target/riscv/attribute-10.c   -O2 -flto -fuse-linker-plugin 
> -fno-fat-lto-objects   at line 8 (test for errors, line )
> FAIL: gcc.target/riscv/attribute-10.c   -O2 -flto -fuse-linker-plugin 
> -fno-fat-lto-objects  (test for excess errors)
> FAIL: gcc.target/riscv/attribute-10.c   -O3 -g   at line 8 (test for errors, 
> line )
> FAIL: gcc.target/riscv/attribute-10.c   -O3 -g  (test for excess errors)
> FAIL: gcc.target/riscv/attribute-10.c   -Os   at line 8 (test for errors, 
> line )
> FAIL: gcc.target/riscv/attribute-10.c   -Os  (test for excess errors)
>
> Could you take a look at it ?
> I am not sure whether they are caused by this patch.  But I find only this 
> patch looks related.
> 
> juzhe.zh...@rivai.ai

Re: [PATCH] RISC-V: Fix RVV_VLMAX

[Kito Cheng]

LGTM, nice catch, I wasn't aware that would be a problem.

On Fri, Jan 19, 2024 at 4:12 PM Juzhe-Zhong  wrote:
>
> This patch fixes memory hog found in SPEC2017 wrf benchmark which caused by
> RVV_VLMAX since RVV_VLMAX generate brand new rtx by gen_rtx_REG (Pmode, 
> X0_REGNUM)
> every time we call RVV_VLMAX, that is, we are always generating garbage and 
> redundant
> (reg:DI 0 zero) rtx.
>
> After this patch fix, the memory hog is gone.
>
> Time variable   usr   sys  
> wall   GGC
>  machine dep reorg  :   1.99 (  9%)   0.35 ( 56%)   2.33 ( 
> 10%)   939M ( 80%) [Before this patch]
>  machine dep reorg  :   1.71 (  6%)   0.16 ( 27%)   3.77 (  
> 6%)   659k (  0%) [After this patch]
>
> Time variable   usr   sys  
> wall   GGC
>  machine dep reorg  :  75.93 ( 18%)  14.23 ( 88%)  90.15 ( 
> 21%) 33383M ( 95%) [Before this patch]
>  machine dep reorg  :  56.00 ( 14%)   7.92 ( 77%)  63.93 ( 
> 15%)  4361k (  0%) [After this patch]
>
> Test is running. Ok for trunk if I passed the test with no regresion ?
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (RVV_VLMAX): Change to 
> regno_reg_rtx[X0_REGNUM].
> (RVV_VUNDEF): Ditto.
> * config/riscv/riscv-vsetvl.cc: Add timevar.
>
> ---
>  gcc/config/riscv/riscv-protos.h  | 5 ++---
>  gcc/config/riscv/riscv-vsetvl.cc | 2 +-
>  2 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
> index 7853b488838..7fe26fcd939 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -299,10 +299,9 @@ void riscv_run_selftests (void);
>  #endif
>
>  namespace riscv_vector {
> -#define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM)
> +#define RVV_VLMAX regno_reg_rtx[X0_REGNUM]
>  #define RVV_VUNDEF(MODE) 
>   \
> -  gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)),  
>   \
> - UNSPEC_VUNDEF)
> +  gen_rtx_UNSPEC (MODE, gen_rtvec (1, RVV_VLMAX), UNSPEC_VUNDEF)
>
>  /* These flags describe how to pass the operands to a rvv insn pattern.
> e.g.:
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 2067073185f..54c85ffb7d5 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -3556,7 +3556,7 @@ const pass_data pass_data_vsetvl = {
>RTL_PASS, /* type */
>"vsetvl", /* name */
>OPTGROUP_NONE, /* optinfo_flags */
> -  TV_NONE,  /* tv_id */
> +  TV_MACH_DEP,  /* tv_id */
>0,/* properties_required */
>0,/* properties_provided */
>0,/* properties_destroyed */
> --
> 2.36.3
>

Re: [PATCH] RISC-V: Add the Zihpm and Zicntr extensions

[Kito Cheng]

I realized we missed this on trunk, and I need this on adding -mcpu
for sfive cores, so I'm gonna push this to trunk.
Most concerns are around the assembler stuff, so I believe it's less
controversial on the toolchain driver side.

On Wed, Nov 23, 2022 at 6:01 AM Palmer Dabbelt  wrote:
>
> On Tue, 22 Nov 2022 13:50:28 PST (-0800), jeffreya...@gmail.com wrote:
> >
> > On 11/22/22 08:29, Palmer Dabbelt wrote:
> >> On Tue, 22 Nov 2022 07:20:15 PST (-0800), jeffreya...@gmail.com wrote:
> >>>
> >>> On 11/20/22 18:36, Kito Cheng wrote:
> >>>>> So the idea here is just to define the extension so that it gets
> >>>>> defined
> >>>>> in the ISA strings and passed through to the assembler, right?
> >>>> That will also define arch test marco:
> >>>>
> >>>> https://github.com/riscv-non-isa/riscv-c-api-doc/blob/master/riscv-c-api.md#architecture-extension-test-macro
> >>>>
> >>>
> >>> Sorry I should have been clearer and included the test macro(s) as well.
> >>>
> >>> So a better summary would be that while it doesn't change the codegen
> >>> behavior in the compiler, it does provide the mechanisms to pass along
> >>> isa strings to other tools such as the assembler and signal via the test
> >>> macros that this extension is available.
> >>
> >> IMO the important bit here is that we're not adding any compatibility
> >> flags, like we did when fence.i was removed from the ISA.  That's fine
> >> as long as we never remove these instructions from the base ISA in the
> >> software, but that's what's suggested by Andrew in the post.
> >
> > Right.  IIUC these instructions were never supposed to be in the base
> > ISA, but, in effect, snuck through.  We're retro-actively adding them as
> > an extension, at least in terms of ISA strings & test macros.  We're
> > currently (forever?) going to allow them in the assembler without
> > strictly requiring the extension be on.
>
> That'd the the idea.
>
> >> It's a super weird one, but there's a bunch of cases in RISC-V where
> >> we're told to just ignore words in the ISA manual.  Definitely a trap
> >> for users (and we already had some Linux folks get bit by the counter
> >> changes here), but that's just how RISC-V works.
> >
> > Mistakes happen.  The key is to adjust for them as best as we can.
> > I'd lean towards a stricter enforcement, bringing these
> > instructions/extension in line with how we handle the others. It'd
> > potentially mean source incompatibilities that would need to be fixed,
> > but they shouldn't be difficult and we're still early enough in the game
> > that we *could* take that route.  Andrew's position is more
> > accommodating of existing code and while I may not 100% agree with his
> > position, I understand it.
> >
> >
> > So while I'd lean towards a stricter checking, I can live with this
> > approach.  I wouldn't mind hearing from Kito, Philipp and others though.
>
> That's the sort of thing we've traditionally done: essentially just read
> the actual words in the PDF and produce implementations that match
> those, tagging versions when things change (the fence.i stuff is a good
> example).  After some amount of time we can then move the default spec
> version over to the new one.  That's a little bit of churn for users,
> but it shouldn't be all that bad.
>
> IMO that's the sane way to go, I'd certainly expect to be able to read
> the words in the PDFs and go implement things according to them.  It's
> pretty clearly not what the ISA folks want, though.
>
> There's also the secondary issue of getting ISA strings to match between
> the various bits of the software stack that uses them.  We're trying to
> move away from ISA strings as a stable uABI in Linux for exactly this
> reason, but ISA strings have already ended up all over the place so
> there's only so much we can do.

Re: [PATCH 0/5] RISC-V: Relax the -march string for accept any order

[Kito Cheng]

Pushed to trunk :)

On Tue, Jan 16, 2024 at 10:33 PM Jeff Law  wrote:
>
>
>
> On 1/9/24 17:58, Kito Cheng wrote:
> > Oops, I should leave more context here:
> >
> > Actually we discussed that years ago, and most people agree with that,
> > but I guess we are just missing that, and also the ISA string isn't so
> > terribly long yet at that moment, however...the number of extensions are
> > growth so fast in last year, so I think it's time to moving this forward.
> >
> > Also we (SiFive) will send patches for clang/LLVM to relax that as well :)
> >
> > https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14
> > <https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14>
> Then let's go forward.  It seems like as good a time as any with gcc-14
> and llvm-18 both right around the corner.
>
> jeff

Re: [PATCH] RISC-V: Add split pattern to generate SFB instructions. [PR113095]

[Kito Cheng]

Thanks! generally LGTM, but I would wait one more week to see any
other comments :)

On Fri, Jan 19, 2024 at 3:05 PM Monk Chiang  wrote:
>
> Since the match.pd transforms (zero_one == 0) ? y : z  y,
> into ((typeof(y))zero_one * z)  y. Add splitters to recongize
> this expression to generate SFB instructions.
>
> gcc/ChangeLog:
> PR target/113095
> * config/riscv/sfb.md: New splitters to rewrite single bit
> sign extension as the condition to SFB instructions.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/sfb.c: New test.
> ---
>  gcc/config/riscv/sfb.md  | 32 
>  gcc/testsuite/gcc.target/riscv/sfb.c | 24 +
>  2 files changed, 56 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sfb.c
>
> diff --git a/gcc/config/riscv/sfb.md b/gcc/config/riscv/sfb.md
> index 8ab747142c8..520b12c22f9 100644
> --- a/gcc/config/riscv/sfb.md
> +++ b/gcc/config/riscv/sfb.md
> @@ -35,3 +35,35 @@
>[(set_attr "length" "8")
> (set_attr "type" "sfb_alu")
> (set_attr "mode" "")])
> +
> +;; Combine creates this form ((typeof(y))zero_one * z)  y
> +;; for SiFive short forward branches.
> +
> +(define_split
> +  [(set (match_operand:X 0 "register_operand")
> +   (and:X (sign_extract:X (match_operand:X 1 "register_operand")
> +  (const_int 1)
> +  (match_operand 2 "immediate_operand"))
> +  (match_operand:X 3 "register_operand")))
> +   (clobber (match_operand:X 4 "register_operand"))]
> +  "TARGET_SFB_ALU"
> +  [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 
> 2)))
> +   (set (match_dup 0) (if_then_else:X (ne:X (match_dup 4) (const_int 0))
> + (match_dup 3)
> + (const_int 0)))])
> +
> +(define_split
> +  [(set (match_operand:X 0 "register_operand")
> +   (and:X (sign_extract:X (match_operand:X 1 "register_operand")
> +  (const_int 1)
> +  (match_operand 2 "immediate_operand"))
> +  (match_operand:X 3 "register_operand")))
> +   (clobber (match_operand:X 4 "register_operand"))]
> +  "TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)"
> +  [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
> +   (set (match_dup 0) (if_then_else:X (ne:X (match_dup 4) (const_int 0))
> + (match_dup 3)
> + (const_int 0)))]
> +{
> +  operands[2] = GEN_INT (1 << UINTVAL(operands[2]));
> +})
> diff --git a/gcc/testsuite/gcc.target/riscv/sfb.c 
> b/gcc/testsuite/gcc.target/riscv/sfb.c
> new file mode 100644
> index 000..22f164051f4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sfb.c
> @@ -0,0 +1,24 @@
> +//* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv32gc -mabi=ilp32d -mtune=sifive-7-series" } */
> +
> +int f1(unsigned int x, unsigned int y, unsigned int z)
> +{
> +  return ((x & 1) == 0) ? y : z ^ y;
> +}
> +
> +int f2(unsigned int x, unsigned int y, unsigned int z)
> +{
> +  return ((x & 1) != 0) ? z ^ y : y;
> +}
> +
> +int f3(unsigned int x, unsigned int y, unsigned int z)
> +{
> +  return ((x & 1) == 0) ? y : z | y;
> +}
> +
> +int f4(unsigned int x, unsigned int y, unsigned int z)
> +{
> +  return ((x & 1) != 0) ? z | y : y;
> +}
> +/* { dg-final { scan-assembler-times "bne" 4 } } */
> +/* { dg-final { scan-assembler-times "movcc" 4 } } */
> --
> 2.40.1
>

Re: [PATCH] RISC-V: Tweak the wording for the sorry message

[Kito Cheng]

Thanks, pushed to trunk :)

On Fri, Jan 19, 2024 at 10:36 AM juzhe.zh...@rivai.ai
 wrote:
>
> OK
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2024-01-19 10:34
> To: rep.dot.nop; jeffreyalaw; rdapp.gcc; juzhe.zhong; gcc-patches
> CC: Kito Cheng
> Subject: [PATCH] RISC-V: Tweak the wording for the sorry message
> Use "does not" rather than "cannot", because it's implementation issue.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
> sorry message.
> ---
> gcc/config/riscv/riscv.cc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index f1d5129397f..dd6e68a08c2 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -8798,13 +8798,13 @@ riscv_override_options_internal (struct gcc_options 
> *opts)
>   We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535.  */
>if (TARGET_MIN_VLEN_OPTS (opts) > 4096)
> -sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
> +sorry ("Current RISC-V GCC does not support VLEN greater than 4096bit 
> for "
>"'V' Extension");
>/* FIXME: We don't support RVV in big-endian for now, we may enable RVV 
> with
>   big-endian after finishing full coverage testing.  */
>if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
> -sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
> +sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
>/* Convert -march to a chunks count.  */
>riscv_vector_chunks = riscv_convert_vector_bits (opts);
> --
> 2.34.1
>
>

Re: [PATCH] RISC-V:Raname UNSPEC_CLMUL in vector-crypto.md

[Kito Cheng]

Thanks, pushed to trunk :)

On Fri, Jan 19, 2024 at 10:30 AM KuanLin Chen  wrote:
>
>  UNSPEC_CLMUL is defined to define_c_enum in riscv.md, so
>  it shouldn't be redefined to define_int_iterator again.
>
> gcc/ChangeLog:
>
> * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to UNSPEC_CLMUL_VC.
>

[PATCH] RISC-V: Tweak the wording for the sorry message

[Kito Cheng]

Use "does not" rather than "cannot", because it's implementation issue.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_override_options_internal): Tweak
sorry message.
---
 gcc/config/riscv/riscv.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f1d5129397f..dd6e68a08c2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8798,13 +8798,13 @@ riscv_override_options_internal (struct gcc_options 
*opts)
 
  We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535.  */
   if (TARGET_MIN_VLEN_OPTS (opts) > 4096)
-sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
+sorry ("Current RISC-V GCC does not support VLEN greater than 4096bit for "
   "'V' Extension");
 
   /* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
  big-endian after finishing full coverage testing.  */
   if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
-sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
+sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
 
   /* Convert -march to a chunks count.  */
   riscv_vector_chunks = riscv_convert_vector_bits (opts);
-- 
2.34.1

Re: [PATCH] RISC-V: Support vi variant for vec_cmp

[Kito Cheng]

LGTM, thanks :)

On Thu, Jan 18, 2024 at 5:59 PM Juzhe-Zhong  wrote:
>
> While running various benchmarks, I notice we miss vi variant support for 
> integer comparison.
> That is, we can vectorize code into vadd.vi but we can't vectorize into 
> vmseq.vi.
>
> Consider this following case:
>
> void
> foo (int n, int **__restrict a)
> {
>   int b;
>   int c;
>   int d;
>   for (b = 0; b < n; b++)
> for (long e = 8; e > 0; e--)
>   a[b][e] = a[b][e] == 15;
> }
>
> Before this patch:
>
> vsetivlizero,4,e32,m1,ta,ma
> vmv.v.i v4,15
> vmv.v.i v3,1
> vmv.v.i v2,0
> .L3:
> ld  a5,0(a1)
> addia4,a5,4
> addia5,a5,20
> vle32.v v1,0(a5)
> vle32.v v0,0(a4)
> vmseq.vvv0,v0,v4
>
> After this patch:
>
> ld  a5,0(a1)
> addia4,a5,4
> addia5,a5,20
> vle32.v v1,0(a5)
> vle32.v v0,0(a4)
> vmseq.viv0,v0,15
>
> It's the missing feature caused by our some mistakes, support vi variant for 
> vec_cmp like other patterns (add, sub, ..., etc).
>
> Tested with no regression, ok for trunk ?
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Support vi variant.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c: New test.
> * gcc.target/riscv/rvv/autovec/cmp/macro.h: New test.
>
> ---
>  gcc/config/riscv/autovec.md   |  4 +--
>  .../riscv/rvv/autovec/cmp/cmp_vi-1.c  | 16 +++
>  .../riscv/rvv/autovec/cmp/cmp_vi-2.c  | 16 +++
>  .../riscv/rvv/autovec/cmp/cmp_vi-3.c  | 28 +++
>  .../riscv/rvv/autovec/cmp/cmp_vi-4.c  | 28 +++
>  .../riscv/rvv/autovec/cmp/cmp_vi-5.c  | 16 +++
>  .../riscv/rvv/autovec/cmp/cmp_vi-6.c  | 16 +++
>  .../riscv/rvv/autovec/cmp/cmp_vi-7.c  | 28 +++
>  .../riscv/rvv/autovec/cmp/cmp_vi-8.c  | 28 +++
>  .../riscv/rvv/autovec/cmp/cmp_vi-9.c  | 18 
>  .../gcc.target/riscv/rvv/autovec/cmp/macro.h  | 11 
>  11 files changed, 207 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-7.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-8.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/macro.h
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 706cd9717cb..5ec1c59bdd4 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -664,7 +664,7 @@
>[(set (match_operand: 0 "register_operand")
> (match_operator: 1 "comparison_operator"
>   [(match_operand:V_VLSI 2 "register_operand")
> -  (match_operand:V_VLSI 3 "register_operand")]))]
> +  (match_operand:V_VLSI 3 "nonmemory_operand")]))]
>"TARGET_VECTOR"
>{
>  riscv_vector::expand_vec_cmp (operands[0], GET_CODE (operands[1]),
> @@ -677,7 +677,7 @@
>[(set (match_operand: 0 "register_operand")
> (match_operator: 1 "comparison_operator"
>   [(match_operand:V_VLSI 2 "register_operand")
> -  (match_operand:V_VLSI 3 "register_operand")]))]
> +  (match_operand:V_VLSI 3 "nonmemory_operand")]))]
>"TARGET_VECTOR"
>{
>  riscv_vector::expand_vec_cmp (operands[0], GET_CODE (operands[1]),
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c
> new file mode 100644
> index 000..10c232f77bd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "macro.h"
> +
> +CMP_VI (ne_char, char, n, !=, 15)
> +CMP_VI 

Re: [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0

[Kito Cheng]

LGTM

On Fri, Jan 12, 2024 at 3:32 PM juzhe.zh...@rivai.ai
 wrote:
>
> This patch needs kito review. I can't approve that.
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Jun Sha (Joshua)
> Date: 2024-01-12 11:20
> To: gcc-patches
> CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; 
> christoph.muellner; juzhe.zhong; kito.cheng; Jun Sha (Joshua); Jin Ma; 
> Xianmiao Qu
> Subject: [PATCH v4] RISC-V: Introduce XTheadVector as a subset of V1.0.0
> This patch is to introduce basic XTheadVector support
> (march string parsing and a test for __riscv_xtheadvector)
> according to https://github.com/T-head-Semi/thead-extension-spec/
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc
> (riscv_subset_list::parse): Add new vendor extension.
> * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
> Add test marco.
> * config/riscv/riscv.opt:  Add new mask.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test.
> * gcc.target/riscv/rvv/xtheadvector.c: New test.
>
> Co-authored-by: Jin Ma 
> Co-authored-by: Xianmiao Qu 
> Co-authored-by: Christoph Müllner 
> ---
> gcc/common/config/riscv/riscv-common.cc   | 23 +++
> gcc/config/riscv/riscv-c.cc   |  8 +--
> gcc/config/riscv/riscv.opt|  2 ++
> .../riscv/predef-__riscv_th_v_intrinsic.c | 11 +
> .../gcc.target/riscv/rvv/xtheadvector.c   | 13 +++
> 5 files changed, 55 insertions(+), 2 deletions(-)
> create mode 100644 
> gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 0301d170a41..449722070d4 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -368,6 +368,7 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>{"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
>{"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
>{"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0},
>{"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1251,6 +1252,15 @@ riscv_subset_list::check_conflict_ext ()
>if (lookup ("zcmp"))
> error_at (m_loc, "%<-march=%s%>: zcd conflicts with zcmp", m_arch);
>  }
> +
> +  if ((lookup ("v") || lookup ("zve32x")
> + || lookup ("zve64x") || lookup ("zve32f")
> + || lookup ("zve64f") || lookup ("zve64d")
> + || lookup ("zvl32b") || lookup ("zvl64b")
> + || lookup ("zvl128b") || lookup ("zvfh"))
> + && lookup ("xtheadvector"))
> +error_at (m_loc, "%<-march=%s%>: xtheadvector conflicts with vector "
> +"extension or its sub-extensions", m_arch);
> }
> /* Parsing function for multi-letter extensions.
> @@ -1743,6 +1753,19 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"xtheadmemidx",  _options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
>{"xtheadmempair", _options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
>{"xtheadsync",_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
> +  {"xtheadvector",  _options::x_riscv_xthead_subext, MASK_XTHEADVECTOR},
> +  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_32},
> +  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_64},
> +  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_32},
> +  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_64},
> +  {"xtheadvector",  _options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_16},
> +  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL32B},
> +  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL64B},
> +  {"xtheadvector",  _options::x_riscv_zvl_flags, MASK_ZVL128B},
> +  {"xtheadvector",  _options::x_riscv_zf_subext, MASK_ZVFHMIN},
> +  {"xtheadvector",  _options::x_riscv_zf_subext, MASK_ZVFH},
> +  {"xtheadvector",  _options::x_target_flags, MASK_FULL_V},
> +  {"xtheadvector",  _options::x_target_flags, MASK_VECTOR},
>{"xventanacondops", _options::x_riscv_xventana_subext, 
> MASK_XVENTANACONDOPS},
> diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
> index ba60cd8b555..422ddc2c308 100644
> --- a/gcc/config/riscv/riscv-c.cc
> +++ b/gcc/config/riscv/riscv-c.cc
> @@ -142,6 +142,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
>  riscv_ext_version_value (0, 11));
>  }
> +   if (TARGET_XTHEADVECTOR)
> + builtin_define_with_int_value ("__riscv_th_v_intrinsic",
> +  riscv_ext_version_value (0, 11));
> +
>/* Define architecture extension test macros.  */
>builtin_define_with_int_value ("__riscv_arch_test", 1);
> @@ -195,8 +199,8 @@ riscv_pragma_intrinsic (cpp_reader *)
>  {
>if (!TARGET_VECTOR)
> {
> -   error ("%<#pragma riscv intrinsic%> option %qs needs 'V' extension "
> - 

Re: [PATCH] riscv: Remove Bool keywords from riscv.opt

[Kito Cheng]

OK, thanks :)

On Thu, Jan 18, 2024 at 4:17 PM Jakub Jelinek  wrote:
>
> Hi!
>
> As I wrote recently, Bool is an undocumented unsupported keyword, as
> can be seen by
> grep Bool doc/options.texi *.awk
> The option parsing just parses and ignores all keywords it doesn't handle.
> But, because it isn't a supported keyword, I think we shouldn't have it in
> *.opt files, because that just means people copy it over to other places
> even when it doesn't have any effect.
>
> Tested with a cross to riscv64-linux, none of the generated
> options.{h,cc} options-{save,urls}.cc
> files change with the patch, only optionlist does (but that is just
> used as a source for those files).
>
> Ok for trunk?
>
> 2024-01-18  Jakub Jelinek  
>
> * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
> minline-strcmp, minline-strncmp, minline-strlen,
> -param=riscv-vector-abi): Remove Bool keywords.
>
> --- gcc/config/riscv/riscv.opt.jj   2024-01-18 08:44:33.441919890 +0100
> +++ gcc/config/riscv/riscv.opt  2024-01-18 08:58:22.788359898 +0100
> @@ -103,7 +103,7 @@ Target Mask(SAVE_RESTORE)
>  Use smaller but slower prologue and epilogue code.
>
>  mshorten-memrefs
> -Target Bool Var(riscv_mshorten_memrefs) Init(1)
> +Target Var(riscv_mshorten_memrefs) Init(1)
>  Convert BASE + LARGE_OFFSET addresses to NEW_BASE + SMALL_OFFSET to allow 
> more
>  memory accesses to be generated as compressed instructions.  Currently 
> targets
>  32-bit integer load/stores.
> @@ -134,12 +134,12 @@ Target Mask(EXPLICIT_RELOCS)
>  Use %reloc() operators, rather than assembly macros, to load addresses.
>
>  mrelax
> -Target Bool Var(riscv_mrelax) Init(1)
> +Target Var(riscv_mrelax) Init(1)
>  Take advantage of linker relaxations to reduce the number of instructions
>  required to materialize symbol addresses.
>
>  mcsr-check
> -Target Bool Var(riscv_mcsr_check) Init(0)
> +Target Var(riscv_mcsr_check) Init(0)
>  Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
>  The ISA-dependent CSR are only valid when the specific ISA is set.  The
>  read-only CSR can not be written by the CSR instructions.
> @@ -483,15 +483,15 @@ Target Var(TARGET_INLINE_SUBWORD_ATOMIC)
>  Always inline subword atomic operations.
>
>  minline-strcmp
> -Target Bool Var(riscv_inline_strcmp) Init(0)
> +Target Var(riscv_inline_strcmp) Init(0)
>  Inline strcmp calls if possible.
>
>  minline-strncmp
> -Target Bool Var(riscv_inline_strncmp) Init(0)
> +Target Var(riscv_inline_strncmp) Init(0)
>  Inline strncmp calls if possible.
>
>  minline-strlen
> -Target Bool Var(riscv_inline_strlen) Init(0)
> +Target Var(riscv_inline_strlen) Init(0)
>  Inline strlen calls if possible.
>
>  -param=riscv-strcmp-inline-limit=
> @@ -542,7 +542,7 @@ madjust-lmul-cost
>  Target Var(TARGET_ADJUST_LMUL_COST) Init(0)
>
>  -param=riscv-vector-abi
> -Target Undocumented Bool Var(riscv_vector_abi) Init(0)
> +Target Undocumented Var(riscv_vector_abi) Init(0)
>  Enable the use of vector registers for function arguments and return value.
>  This is an experimental switch and may be subject to change in the future.
>
>
> Jakub
>

Re: [PATCH] RISC-V: Report Sorry when users enable RVV in big-endian mode [PR113404]

[Kito Cheng]

LGTM, the big endian for RISC-V has been there for a while, but we
don't pay enough attention to that, so I think reporting sorry for now
is a very reasonable way :)

On Tue, Jan 16, 2024 at 11:05 AM Juzhe-Zhong  wrote:
>
> As PR113404 mentioned: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113404
>
> We have ICE when we enable RVV in big-endian mode:
>
> during RTL pass: expand
> a-float-point-dynamic-frm-66.i:2:14: internal compiler error: in to_constant, 
> at poly-int.h:588
> 0xab4c2c poly_int<2u, unsigned short>::to_constant() const
> /repo/gcc-trunk/gcc/poly-int.h:588
> 0xab4de1 poly_int<2u, unsigned short>::to_constant() const
> /repo/gcc-trunk/gcc/tree.h:4055
> 0xab4de1 default_function_arg_padding(machine_mode, tree_node const*)
> /repo/gcc-trunk/gcc/targhooks.cc:844
> 0x12e2327 locate_and_pad_parm(machine_mode, tree_node*, int, int, int, 
> tree_node*, args_size*, locate_and_pad_arg_data*)
> /repo/gcc-trunk/gcc/function.cc:4061
> 0x12e2aca assign_parm_find_entry_rtl
> /repo/gcc-trunk/gcc/function.cc:2614
> 0x12e2c89 assign_parms
> /repo/gcc-trunk/gcc/function.cc:3693
> 0x12e59df expand_function_start(tree_node*)
> /repo/gcc-trunk/gcc/function.cc:5152
> 0x112fafb execute
> /repo/gcc-trunk/gcc/cfgexpand.cc:6739
>
> Report users that we don't support RVV in big-endian mode for the following 
> reasons:
> 1. big-endian in RISC-V is pretty rare case.
> 2. We didn't test RVV in big-endian and we don't have enough time to test it 
> since it's stage 4 now.
>
> Naive disallow RVV in big-endian.
>
> Tested no regression, ok for trunk ?
>
> PR target/113404
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_override_options_internal): Report 
> sorry for RVV in big-endian mode.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/big_endian-1.c: New test.
> * gcc.target/riscv/rvv/base/big_endian-2.c: New test.
>
> ---
>  gcc/config/riscv/riscv.cc  | 5 +
>  gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-1.c | 5 +
>  gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c | 5 +
>  3 files changed, 15 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 89caf156f03..41626fa34e4 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -8787,6 +8787,11 @@ riscv_override_options_internal (struct gcc_options 
> *opts)
>  sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
>"'V' Extension");
>
> +  /* FIXME: We don't support RVV in big-endian for now, we may enable RVV 
> with
> + big-endian after finishing full coverage testing.  */
> +  if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
> +sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
> +
>/* Convert -march to a chunks count.  */
>riscv_vector_chunks = riscv_convert_vector_bits (opts);
>  }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-1.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-1.c
> new file mode 100644
> index 000..9eaf7ad33b2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-1.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -mbig-endian -O3" } */
> +
> +#pragma riscv intrinsic "vector"
> +vfloat32m1_t foo (vfloat32m1_t) {} // { dg-excess-errors "sorry, 
> unimplemented: Current RISC-V GCC cannot support RVV in big-endian mode" }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c
> new file mode 100644
> index 000..86cf58370bf
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/big_endian-2.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_zve32x -mabi=lp64d -mbig-endian -O3" } */
> +
> +#pragma riscv intrinsic "vector"
> +vint32m1_t foo (vint32m1_t) {} // { dg-excess-errors "sorry, unimplemented: 
> Current RISC-V GCC cannot support RVV in big-endian mode" }
> --
> 2.36.3
>

Re: [PATCH v4 0/3] RISC-V: Add intrinsics for Bitmanip and Scalar Crypto extensions

[Kito Cheng]

Ok :)


Christoph Müllner  於 2024年1月15日 週一 23:17 寫道：

> On Mon, Jan 15, 2024 at 9:35 AM Liao Shihua  wrote:
> >
> > Update v3 -> v4:
> >   1.Typo fix.
> >   2.Only test *intrinsic-32 on rv32 and *intrinsic-64 on rv64.
> >   3.Update Copyright year to 2024.
>
> Thanks, for fixing the rv32/rv64 issues!
> I've tested this series: no regressions and all new tests pass.
> I've also reviewed this series again, and I think it is ready.
> I can push once a maintainer approves (e.g. Kito or Jeff).
>
> Thanks for working on this!
>
> >
> > Update v2 -> v3:
> >   1. Change pattern mode form X to GPR in orcb, clmul, and brev8.
> >   2. Add emulated testsuite.
> >   3. Removed duplicate testsuite between built-in and intrinsic.
> >   4. Typo fix.
> >
> > Update v1 -> v2:
> >   1. Rename *_intrinsic-* to *_intrinsic-XLEN.
> >   2. Typo fix.
> >   3. Intrinsics with immediate arguments will use marcos at O0 .
> >
> > It's a little patch add just provides a mapping from the RV intrinsics
> to the builtin
> > names within GCC.
> >
> > Liao Shihua (3):
> >   RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function
> > testsuites
> >   RISC-V: Add C intrinsic for Scalar Crypto Extension
> >   RISC-V: Add C intrinsic for Scalar Bitmanip Extension
> >
> >  gcc/config.gcc|   2 +-
> >  gcc/config/riscv/bitmanip.md  |  10 +-
> >  gcc/config/riscv/crypto.md|   4 +-
> >  gcc/config/riscv/riscv-builtins.cc|  22 ++
> >  gcc/config/riscv/riscv-cmo.def|  12 +-
> >  gcc/config/riscv/riscv-ftypes.def |   2 +
> >  gcc/config/riscv/riscv-scalar-crypto.def  |  22 +-
> >  gcc/config/riscv/riscv_bitmanip.h | 297 +
> >  gcc/config/riscv/riscv_crypto.h   | 309 ++
> >  .../riscv/scalar_bitmanip_intrinsic-32.c  |  97 ++
> >  .../scalar_bitmanip_intrinsic-64-emulated.c   |  33 ++
> >  .../riscv/scalar_bitmanip_intrinsic-64.c  | 115 +++
> >  .../riscv/scalar_crypto_intrinsic-32.c| 115 +++
> >  .../riscv/scalar_crypto_intrinsic-64.c| 123 +++
> >  .../gcc.target/riscv/zbb_32_bswap-1.c |  11 -
> >  gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c  |  11 -
> >  gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c  |  12 -
> >  .../riscv/{zbb_32_bswap-2.c => zbb_bswap16.c} |   3 +-
> >  gcc/testsuite/gcc.target/riscv/zbbw.c |  26 --
> >  gcc/testsuite/gcc.target/riscv/zbc32.c|  23 --
> >  gcc/testsuite/gcc.target/riscv/zbc64.c|  23 --
> >  gcc/testsuite/gcc.target/riscv/zbkb32.c   |  18 -
> >  gcc/testsuite/gcc.target/riscv/zbkb64.c   |   5 -
> >  gcc/testsuite/gcc.target/riscv/zbkc32.c   |  17 -
> >  gcc/testsuite/gcc.target/riscv/zbkc64.c   |  17 -
> >  gcc/testsuite/gcc.target/riscv/zbkx32.c   |  18 -
> >  gcc/testsuite/gcc.target/riscv/zbkx64.c   |  18 -
> >  gcc/testsuite/gcc.target/riscv/zknd32-2.c |  28 --
> >  gcc/testsuite/gcc.target/riscv/zknd64-2.c |  42 ---
> >  gcc/testsuite/gcc.target/riscv/zkne32-2.c |  28 --
> >  gcc/testsuite/gcc.target/riscv/zkne64-2.c |  34 --
> >  .../gcc.target/riscv/zknh-sha256-32.c |  10 -
> >  .../gcc.target/riscv/zknh-sha256-64.c |  28 --
> >  .../gcc.target/riscv/zknh-sha512-32.c |  42 ---
> >  .../gcc.target/riscv/zknh-sha512-64.c |  31 --
> >  gcc/testsuite/gcc.target/riscv/zksed32-2.c|  29 --
> >  gcc/testsuite/gcc.target/riscv/zksed64-2.c|  29 --
> >  gcc/testsuite/gcc.target/riscv/zksh32.c   |  19 --
> >  gcc/testsuite/gcc.target/riscv/zksh64.c   |  19 --
> >  39 files changed, 1149 insertions(+), 555 deletions(-)
> >  create mode 100644 gcc/config/riscv/riscv_bitmanip.h
> >  create mode 100644 gcc/config/riscv/riscv_crypto.h
> >  create mode 100644
> gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-32.c
> >  create mode 100644
> gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64-emulated.c
> >  create mode 100644
> gcc/testsuite/gcc.target/riscv/scalar_bitmanip_intrinsic-64.c
> >  create mode 100644
> gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-32.c
> >  create mode 100644
> gcc/testsuite/gcc.target/riscv/scalar_crypto_intrinsic-64.c
> >  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbb_32_bswap-1.c
> >  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-1.c
> >  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbb_bswap-2.c
> >  rename gcc/testsuite/gcc.target/riscv/{zbb_32_bswap-2.c =>
> zbb_bswap16.c} (59%)
> >  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbbw.c
> >  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc32.c
> >  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbc64.c
> >  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
> >  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
> >  delete mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
> >  delete mode 100644