Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension

2024-01-25 Thread Kito Cheng 
pushed :)

On Thu, Jan 25, 2024 at 9:53 PM Kito Cheng  wrote:
>
> It's stage 4, so I think it would be great to not disturb code base
> too much, and adding intrinsic without adding VLS modes should be
> better way to go, and  here is not really something serious coding
> style issue, just few minor indentation issue, so I gonna run
> regression to make not break anything else and then commit to trunk :)

Re: [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension

2024-01-25 Thread Kito Cheng 
It's stage 4, so I think it would be great to not disturb code base
too much, and adding intrinsic without adding VLS modes should be
better way to go, and  here is not really something serious coding
style issue, just few minor indentation issue, so I gonna run
regression to make not break anything else and then commit to trunk :)

[PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension

2024-01-16 Thread Mary Bennett 
v2 -> v3:
 * Removed duplicate ftype.

This patch series presents the comprehensive implementation of the SIMD
extension for CORE-V.

Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to
ensure its correctness and compatibility with the existing codebase.
However, your input, reviews, and suggestions are invaluable in making this
extension even more robust.

The CORE-V builtins are described in the specification [1] and work can be
found in the OpenHW group's Github repository [2].

[1] 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

[2] github.com/openhwgroup/corev-gcc

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

RISC-V: Add support for XCVsimd extension in CV32E40P
RISC-V: Fix XCValu test

 gcc/common/config/riscv/riscv-common.cc   |2 +
 gcc/config/riscv/constraints.md   |   30 +
 gcc/config/riscv/corev.def|  156 ++
 gcc/config/riscv/corev.md | 1908 +
 gcc/config/riscv/predicates.md|   20 +
 gcc/config/riscv/riscv-builtins.cc|1 +
 gcc/config/riscv/riscv-ftypes.def |8 +
 gcc/config/riscv/riscv.cc |8 +
 gcc/config/riscv/riscv.opt|2 +
 gcc/doc/extend.texi   |  886 
 gcc/doc/sourcebuild.texi  |3 +
 .../gcc.target/riscv/cv-alu-fail-compile.c|   40 +-
 .../riscv/cv-simd-abs-b-compile-1.c   |   11 +
 .../riscv/cv-simd-abs-h-compile-1.c   |   11 +
 .../riscv/cv-simd-add-b-compile-1.c   |   11 +
 .../riscv/cv-simd-add-div2-compile-1.c|   11 +
 .../riscv/cv-simd-add-div4-compile-1.c|   11 +
 .../riscv/cv-simd-add-div8-compile-1.c|   11 +
 .../riscv/cv-simd-add-h-compile-1.c   |   11 +
 .../riscv/cv-simd-add-sc-b-compile-1.c|   30 +
 .../riscv/cv-simd-add-sc-h-compile-1.c|   30 +
 .../riscv/cv-simd-and-b-compile-1.c   |   11 +
 .../riscv/cv-simd-and-h-compile-1.c   |   11 +
 .../riscv/cv-simd-and-sc-b-compile-1.c|   30 +
 .../riscv/cv-simd-and-sc-h-compile-1.c|   30 +
 .../riscv/cv-simd-avg-b-compile-1.c   |   11 +
 .../riscv/cv-simd-avg-h-compile-1.c   |   11 +
 .../riscv/cv-simd-avg-sc-b-compile-1.c|   30 +
 .../riscv/cv-simd-avg-sc-h-compile-1.c|   30 +
 .../riscv/cv-simd-avgu-b-compile-1.c  |   11 +
 .../riscv/cv-simd-avgu-h-compile-1.c  |   11 +
 .../riscv/cv-simd-avgu-sc-b-compile-1.c   |   24 +
 .../riscv/cv-simd-avgu-sc-h-compile-1.c   |   24 +
 .../riscv/cv-simd-cmpeq-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpeq-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpeq-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpeq-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpge-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpge-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpge-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpge-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpgeu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgeu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgeu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpgeu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmpgt-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpgt-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpgt-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpgt-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpgtu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgtu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpgtu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpgtu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmple-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmple-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmple-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmple-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpleu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpleu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpleu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpleu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmplt-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmplt-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmplt-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmplt-sc-h-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpltu-b-compile-1.c|   11 +
 .../riscv/cv-simd-cmpltu-h-compile-1.c|   11 +
 .../riscv/cv-simd-cmpltu-sc-b-compile-1.c |   24 +
 .../riscv/cv-simd-cmpltu-sc-h-compile-1.c |   24 +
 .../riscv/cv-simd-cmpne-b-compile-1.c |   11 +
 .../riscv/cv-simd-cmpne-h-compile-1.c |   11 +
 .../riscv/cv-simd-cmpne-sc-b-compile-1.c  |   30 +
 .../riscv/cv-simd-cmpne-sc-h-compile-1.c  |   30 +