[gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick
scons: `build/ALPHA_SE/m5.debug' is up to date. scons: `build/ALPHA_SE_MOESI_hammer/m5.debug' is up to date. scons: `build/ALPHA_SE_MESI_CMP_directory/m5.debug' is up to date. scons: `build/ALPHA_SE_MOESI_CMP_directory/m5.debug' is up to date. scons: `build/ALPHA_SE_MOESI_CMP_token/m5.debug' is up to date. scons: `build/ALPHA_FS/m5.debug' is up to date. scons: `build/MIPS_SE/m5.debug' is up to date. scons: `build/POWER_SE/m5.debug' is up to date. scons: `build/SPARC_SE/m5.debug' is up to date. scons: `build/SPARC_FS/m5.debug' is up to date. scons: `build/X86_SE/m5.debug' is up to date. scons: `build/X86_FS/m5.debug' is up to date. scons: `build/ARM_SE/m5.debug' is up to date. scons: `build/ARM_FS/m5.debug' is up to date. scons: `build/ALPHA_SE/m5.fast' is up to date. scons: `build/ALPHA_SE_MOESI_hammer/m5.fast' is up to date. scons: `build/ALPHA_SE_MESI_CMP_directory/m5.fast' is up to date. scons: `build/ALPHA_SE_MOESI_CMP_directory/m5.fast' is up to date. scons: `build/ALPHA_SE_MOESI_CMP_token/m5.fast' is up to date. scons: `build/ALPHA_FS/m5.fast' is up to date. scons: `build/MIPS_SE/m5.fast' is up to date. scons: `build/POWER_SE/m5.fast' is up to date. scons: `build/SPARC_SE/m5.fast' is up to date. scons: `build/SPARC_FS/m5.fast' is up to date. scons: `build/X86_SE/m5.fast' is up to date. scons: `build/X86_FS/m5.fast' is up to date. scons: `build/ARM_SE/m5.fast' is up to date. scons: `build/ARM_FS/m5.fast' is up to date. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby passed. * build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp passed. * build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp passed. * build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest passed. * build/ALPHA_SE/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby passed. * build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby passed. * build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer passed. * build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token passed. * build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. *
[gem5-dev] changeset in gem5: Ruby: Remove some unused typedefs
changeset 02d7ac5fb855 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=02d7ac5fb855
description:
Ruby: Remove some unused typedefs
This patch removes some of the unused typedefs. It also moves
some of the typedefs from Global.hh to TypeDefines.hh. The patch
also eliminates the file NodeID.hh.
diffstat:
src/cpu/testers/rubytest/Check.hh| 1 -
src/mem/protocol/RubySlicc_Types.sm | 2 +-
src/mem/ruby/SConscript | 1 -
src/mem/ruby/common/Address.hh | 3 +-
src/mem/ruby/common/DataBlock.hh | 2 +-
src/mem/ruby/common/Driver.hh| 1 -
src/mem/ruby/common/Global.hh| 11 +--
src/mem/ruby/common/Histogram.hh | 2 +-
src/mem/ruby/common/NetDest.hh | 1 -
src/mem/ruby/common/Set.hh | 1 -
src/mem/ruby/common/TypeDefines.hh | 5 +
src/mem/ruby/eventqueue/RubyEventQueue.hh| 2 +-
src/mem/ruby/network/Network.hh | 1 -
src/mem/ruby/network/Topology.hh | 3 +-
src/mem/ruby/network/garnet/NetworkHeader.hh | 3 -
src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh | 1 +
src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh | 1 +
src/mem/ruby/network/simple/PerfectSwitch.cc | 3 +-
src/mem/ruby/network/simple/PerfectSwitch.hh | 1 -
src/mem/ruby/network/simple/SimpleNetwork.hh | 1 -
src/mem/ruby/network/simple/Throttle.cc | 4 +-
src/mem/ruby/network/simple/Throttle.hh | 1 -
src/mem/ruby/profiler/AccessTraceForAddress.hh | 1 -
src/mem/ruby/profiler/AddressProfiler.hh | 1 -
src/mem/ruby/profiler/CacheProfiler.hh | 1 -
src/mem/ruby/profiler/MemCntrlProfiler.hh| 2 +-
src/mem/ruby/profiler/Profiler.hh| 1 -
src/mem/ruby/recorder/CacheRecorder.hh | 1 -
src/mem/ruby/recorder/TraceRecord.hh | 1 -
src/mem/ruby/recorder/Tracer.hh | 1 -
src/mem/ruby/slicc_interface/Message.hh | 1 +
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | 1 -
src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh | 1 -
src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 1 -
src/mem/ruby/system/MachineID.hh | 1 -
src/mem/ruby/system/NodeID.hh| 45
src/mem/slicc/symbols/StateMachine.py| 2 +-
src/mem/slicc/symbols/Type.py| 2 -
38 files changed, 20 insertions(+), 94 deletions(-)
diffs (truncated from 493 to 300 lines):
diff -r 5fb918115c07 -r 02d7ac5fb855 src/cpu/testers/rubytest/Check.hh
--- a/src/cpu/testers/rubytest/Check.hh Mon Oct 31 01:09:44 2011 -0700
+++ b/src/cpu/testers/rubytest/Check.hh Thu Nov 03 22:46:45 2011 -0500
@@ -37,7 +37,6 @@
#include mem/protocol/TesterStatus.hh
#include mem/ruby/common/Address.hh
#include mem/ruby/common/Global.hh
-#include mem/ruby/system/NodeID.hh
class SubBlock;
diff -r 5fb918115c07 -r 02d7ac5fb855 src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm Mon Oct 31 01:09:44 2011 -0700
+++ b/src/mem/protocol/RubySlicc_Types.sm Thu Nov 03 22:46:45 2011 -0500
@@ -48,7 +48,7 @@
bool isEmpty();
}
-external_type(NodeID, default=0);
+external_type(NodeID, default=0, primitive=yes);
external_type(MachineID);
MessageBuffer getMandatoryQueue(int core_id);
diff -r 5fb918115c07 -r 02d7ac5fb855 src/mem/ruby/SConscript
--- a/src/mem/ruby/SConscript Mon Oct 31 01:09:44 2011 -0700
+++ b/src/mem/ruby/SConscript Thu Nov 03 22:46:45 2011 -0500
@@ -109,7 +109,6 @@
MakeInclude('system/MachineID.hh')
MakeInclude('system/MemoryControl.hh')
MakeInclude('system/WireBuffer.hh')
-MakeInclude('system/NodeID.hh')
MakeInclude('system/PerfectCacheMemory.hh')
MakeInclude('system/PersistentTable.hh')
MakeInclude('system/Sequencer.hh')
diff -r 5fb918115c07 -r 02d7ac5fb855 src/mem/ruby/common/Address.hh
--- a/src/mem/ruby/common/Address.hhMon Oct 31 01:09:44 2011 -0700
+++ b/src/mem/ruby/common/Address.hhThu Nov 03 22:46:45 2011 -0500
@@ -33,8 +33,7 @@
#include iomanip
#include base/hashmap.hh
-#include mem/ruby/common/Global.hh
-#include mem/ruby/system/NodeID.hh
+#include mem/ruby/common/TypeDefines.hh
const int ADDRESS_WIDTH = 64; // address width in bytes
diff -r 5fb918115c07 -r 02d7ac5fb855 src/mem/ruby/common/DataBlock.hh
---
[gem5-dev] changeset in gem5: x86: Add microop for fence
changeset 9bdd52a2214c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9bdd52a2214c
description:
x86: Add microop for fence
This patch adds a new microop for memory barrier. The microop itself
does
nothing, but since it is marked as a memory barrier, the O3 CPU should
flush
all the pending loads and stores before the fence to the memory system.
diffstat:
src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py|
36 ++
src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py |
8 +
src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py |
24
src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py |
12 ++
src/arch/x86/isa/insts/general_purpose/logical.py|
28 +
src/arch/x86/isa/insts/general_purpose/semaphores.py |
8 +
src/arch/x86/isa/microops/specop.isa |
53 ++
7 files changed, 169 insertions(+), 0 deletions(-)
diffs (truncated from 747 to 300 lines):
diff -r 78da831670e4 -r 9bdd52a2214c
src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
--- a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
Thu Nov 03 22:52:02 2011 -0500
+++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py
Thu Nov 03 22:52:21 2011 -0500
@@ -67,18 +67,22 @@
def macroop ADD_LOCKED_M_I
{
limm t2, imm
+mfence
ldstl t1, seg, sib, disp
add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
+mfence
};
def macroop ADD_LOCKED_P_I
{
rdip t7
limm t2, imm
+mfence
ldstl t1, seg, riprel, disp
add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
+mfence
};
def macroop ADD_M_R
@@ -98,17 +102,21 @@
def macroop ADD_LOCKED_M_R
{
+mfence
ldstl t1, seg, sib, disp
add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
+mfence
};
def macroop ADD_LOCKED_P_R
{
rdip t7
+mfence
ldstl t1, seg, riprel, disp
add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
+mfence
};
def macroop ADD_R_M
@@ -168,18 +176,22 @@
def macroop SUB_LOCKED_M_I
{
limm t2, imm
+mfence
ldstl t1, seg, sib, disp
sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
+mfence
};
def macroop SUB_LOCKED_P_I
{
rdip t7
limm t2, imm
+mfence
ldstl t1, seg, riprel, disp
sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
+mfence
};
def macroop SUB_M_R
@@ -199,17 +211,21 @@
def macroop SUB_LOCKED_M_R
{
+mfence
ldstl t1, seg, sib, disp
sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
+mfence
};
def macroop SUB_LOCKED_P_R
{
rdip t7
+mfence
ldstl t1, seg, riprel, disp
sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
+mfence
};
def macroop ADC_R_R
@@ -243,18 +259,22 @@
def macroop ADC_LOCKED_M_I
{
limm t2, imm
+mfence
ldstl t1, seg, sib, disp
adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
+mfence
};
def macroop ADC_LOCKED_P_I
{
rdip t7
limm t2, imm
+mfence
ldstl t1, seg, riprel, disp
adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
+mfence
};
def macroop ADC_M_R
@@ -274,17 +294,21 @@
def macroop ADC_LOCKED_M_R
{
+mfence
ldstl t1, seg, sib, disp
adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
+mfence
};
def macroop ADC_LOCKED_P_R
{
rdip t7
+mfence
ldstl t1, seg, riprel, disp
adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
+mfence
};
def macroop ADC_R_M
@@ -344,18 +368,22 @@
def macroop SBB_LOCKED_M_I
{
limm t2, imm
+mfence
ldstl t1, seg, sib, disp
sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
+mfence
};
def macroop SBB_LOCKED_P_I
{
rdip t7
limm t2, imm
+mfence
ldstl t1, seg, riprel, disp
sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
+mfence
};
def macroop SBB_M_R
@@ -375,17 +403,21 @@
def macroop SBB_LOCKED_M_R
{
+mfence
ldstl t1, seg, sib, disp
sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, sib, disp
+mfence
};
def macroop SBB_LOCKED_P_R
{
rdip t7
+mfence
ldstl t1, seg, riprel, disp
sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
stul t1, seg, riprel, disp
+mfence
};
def macroop NEG_R
@@ -410,16 +442,20 @@
def macroop NEG_LOCKED_M
{
+mfence
ldstl t1, seg, sib, disp
sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
stul t1, seg, sib, disp
+mfence
};
def macroop
[gem5-dev] changeset in gem5: MESI Protocol: Add functions for profiling mi...
changeset d9c61e6f1848 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d9c61e6f1848
description:
MESI Protocol: Add functions for profiling misses
diffstat:
src/mem/protocol/MESI_CMP_directory-L1cache.sm | 15 +++
src/mem/protocol/MESI_CMP_directory-L2cache.sm | 18 +-
2 files changed, 32 insertions(+), 1 deletions(-)
diffs (83 lines):
diff -r 9bdd52a2214c -r d9c61e6f1848
src/mem/protocol/MESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.smThu Nov 03 22:52:21
2011 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.smFri Nov 04 11:26:12
2011 -0500
@@ -679,6 +679,17 @@
mandatoryQueue_in.recycle();
}
+ action(uu_profileInstMiss, \ui, desc=Profile the demand miss) {
+peek(mandatoryQueue_in, RubyRequest) {
+L1IcacheMemory.profileMiss(in_msg);
+}
+ }
+
+ action(uu_profileDataMiss, \ud, desc=Profile the demand miss) {
+peek(mandatoryQueue_in, RubyRequest) {
+L1DcacheMemory.profileMiss(in_msg);
+}
+ }
//*
// TRANSITIONS
@@ -698,6 +709,7 @@
oo_allocateL1DCacheBlock;
i_allocateTBE;
a_issueGETS;
+uu_profileDataMiss;
k_popMandatoryQueue;
}
@@ -705,6 +717,7 @@
pp_allocateL1ICacheBlock;
i_allocateTBE;
ai_issueGETINSTR;
+uu_profileInstMiss;
k_popMandatoryQueue;
}
@@ -712,6 +725,7 @@
oo_allocateL1DCacheBlock;
i_allocateTBE;
b_issueGETX;
+uu_profileDataMiss;
k_popMandatoryQueue;
}
@@ -729,6 +743,7 @@
transition(S, Store, SM) {
i_allocateTBE;
c_issueUPGRADE;
+uu_profileDataMiss;
k_popMandatoryQueue;
}
diff -r 9bdd52a2214c -r d9c61e6f1848
src/mem/protocol/MESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.smThu Nov 03 22:52:21
2011 -0500
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.smFri Nov 04 11:26:12
2011 -0500
@@ -716,9 +716,25 @@
}
}
+ GenericRequestType convertToGenericType(CoherenceRequestType type) {
+if(type == CoherenceRequestType:GETS) {
+ return GenericRequestType:GETS;
+} else if(type == CoherenceRequestType:GETX) {
+ return GenericRequestType:GETX;
+} else if(type == CoherenceRequestType:GET_INSTR) {
+ return GenericRequestType:GET_INSTR;
+} else if(type == CoherenceRequestType:UPGRADE) {
+ return GenericRequestType:UPGRADE;
+} else {
+ DPRINTF(RubySlicc, %s\n, type);
+ error(Invalid CoherenceRequestType\n);
+}
+ }
+
action(uu_profileMiss, \u, desc=Profile the demand miss) {
peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- //profile_L2Cache_miss(convertToGenericType(in_msg.Type),
in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch,
L1CacheMachIDToProcessorNum(in_msg.Requestor));
+ L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type),
+ in_msg.AccessMode, in_msg.Prefetch);
}
}
___
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[gem5-dev] changeset in gem5: GARNET: adding a fault model for resilient on...
changeset df3b7a1e883f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=df3b7a1e883f description: GARNET: adding a fault model for resilient on-chip network research. This patch adds a fault model, which provides the probability of a number of architectural faults in the interconnection network (e.g., data corruption, misrouting). These probabilities can be used to realistically inject faults in GARNET and faithfully evaluate the effectiveness of novel resilient NoC architectures. diffstat: configs/ruby/Ruby.py | 10 +- src/mem/ruby/network/fault_model/FaultModel.cc| 278 + src/mem/ruby/network/fault_model/FaultModel.hh| 142 src/mem/ruby/network/fault_model/FaultModel.py| 302 ++ src/mem/ruby/network/fault_model/SConscript | 43 + src/mem/ruby/network/garnet/BaseGarnetNetwork.cc |3 + src/mem/ruby/network/garnet/BaseGarnetNetwork.hh |4 + src/mem/ruby/network/garnet/BaseGarnetNetwork.py |2 + src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc | 17 + src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh |1 + src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc| 29 + src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh| 12 + 12 files changed, 842 insertions(+), 1 deletions(-) diffs (truncated from 968 to 300 lines): diff -r d9c61e6f1848 -r df3b7a1e883f configs/ruby/Ruby.py --- a/configs/ruby/Ruby.py Fri Nov 04 11:26:12 2011 -0500 +++ b/configs/ruby/Ruby.py Fri Nov 04 18:40:22 2011 -0400 @@ -40,6 +40,8 @@ help=the number of rows in the mesh topology) parser.add_option(--garnet-network, type=string, default=None, help='fixed'|'flexible') +parser.add_option(--network-fault-model, action=store_true, default=False, + help=enable network fault model: see src/mem/ruby/network/fault_model/) # ruby mapping options parser.add_option(--numa-high-bit, type=int, default=0, @@ -109,7 +111,13 @@ print Error: could not create topology %s % options.topology raise -network = NetworkClass(ruby_system = ruby, topology = net_topology) +if options.network_fault_model: +assert(options.garnet_network == fixed) +fault_model = FaultModel() +network = NetworkClass(ruby_system = ruby, topology = net_topology,\ + enable_fault_model=True, fault_model = fault_model) +else: +network = NetworkClass(ruby_system = ruby, topology = net_topology) # # Loop through the directory controlers. diff -r d9c61e6f1848 -r df3b7a1e883f src/mem/ruby/network/fault_model/FaultModel.cc --- /dev/null Thu Jan 01 00:00:00 1970 + +++ b/src/mem/ruby/network/fault_model/FaultModel.ccFri Nov 04 18:40:22 2011 -0400 @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2011 Massachusetts Institute of Technology + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Konstantinos Aisopos + */ + +/* + * Official Tool Website: www.mit.edu/~kaisopos/FaultModel + * + * If you use our tool for academic research, we request that you cite: + * Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling + * System-Level Modeling of Variation-Induced Faults in Networks-on-Chip. + *
