Re: [gem5-dev] Review Request 3446: hsail, gpu-compute: fixes to appease clang++

2016-10-24 Thread Joe Gross 

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Ship it!


This fixed a bunch of ubsan warnings with gcc6.1.0 for me.

- Joe Gross


On April 13, 2016, 10:09 a.m., Tony Gutierrez wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3446/
> ---
> 
> (Updated April 13, 2016, 10:09 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11443:c90af82c70e4
> ---
> hsail,gpu-compute: fixes to appease clang++
> 
> fixes to appease clang++. tested on:
> 
> Ubuntu clang version 3.5.0-4ubuntu2~trusty2
> (tags/RELEASE_350/final) (based on LLVM 3.5.0)
> 
> Ubuntu clang version 3.6.0-2ubuntu1~trusty1
> (tags/RELEASE_360/final) (based on LLVM 3.6.0)
> 
> the fixes address the following five issues:
> 
> 1) the exec continuations in gpu_static_inst.hh were marked
>as protected when they should be public. here we mark
>them as public
> 
> 2) the Abs instruction uses std::abs() in its execute method.
>because Abs is templated, it can also operate on U32 and U64,
>types, which cause Abs::execute() to pass uint32_t and uint64_t
>types to std::abs() respectively. this triggers a warning
>because std::abs() has no effect in this case. to rememdy this
>we add template specialization for the execute() method of Abs
>when its template paramter is U32 or U64.
> 
> 3) Some potocols that utilize the code in cprintf.hh were missing
>includes to BoolVec.hh, which defines operator<< for the BoolVec
>type. This would cause issues when the generated code would try
>to pass a BoolVec type to a method in cprintf.hh that used
>operator<< on an instance of a BoolVec.
> 
> 4) Surprise, clang doesn't like it when you clobber all the bits
>in a newly allocated object. I.e., this code:
> 
>tlb = new GpuTlbEntry[size];
>std::memset(tlb, 0, sizeof(GpuTlbEntry) * size);
> 
>Let's use std::vector to track the TLB entries in the GpuTlb now...
> 
> 5) There were a few variables used only in DPRINTFs, so we mark them
>with M5_VAR_USED.
> 
> 
> Diffs
> -
> 
>   src/arch/hsail/gen.py b31738224fb0eb259efc25f6d6efab5a962f29d0 
>   src/arch/x86/process.cc b31738224fb0eb259efc25f6d6efab5a962f29d0 
>   src/gpu-compute/gpu_static_inst.hh b31738224fb0eb259efc25f6d6efab5a962f29d0 
>   src/gpu-compute/gpu_tlb.hh b31738224fb0eb259efc25f6d6efab5a962f29d0 
>   src/gpu-compute/gpu_tlb.cc b31738224fb0eb259efc25f6d6efab5a962f29d0 
>   src/gpu-compute/hsail_code.hh b31738224fb0eb259efc25f6d6efab5a962f29d0 
>   src/mem/slicc/symbols/StateMachine.py 
> b31738224fb0eb259efc25f6d6efab5a962f29d0 
> 
> Diff: http://reviews.gem5.org/r/3446/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Tony Gutierrez
> 
>

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Re: [gem5-dev] Review Request 3683: config: Break out base options for usage with NULL ISA

2016-10-24 Thread Jieming Yin 

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Ship it!


Ship It!

- Jieming Yin


On Oct. 24, 2016, 9:10 a.m., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3683/
> ---
> 
> (Updated Oct. 24, 2016, 9:10 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11688:3b7d93ec1cf1
> ---
> config: Break out base options for usage with NULL ISA
> 
> This patch breaks out the most basic configuration options into a set
> of base options, to allow them to be used also by scripts that do not
> involve any ISA, and thus no actual CPUs or devices.
> 
> The patch also fixes a few modules so that they can be imported in a
> NULL build, and avoid dragging in FSConfig every time Options is
> imported.
> 
> 
> Diffs
> -
> 
>   configs/common/CpuConfig.py b3d5f0e9e258 
>   configs/common/FSConfig.py b3d5f0e9e258 
>   configs/common/Options.py b3d5f0e9e258 
>   configs/common/PlatformConfig.py b3d5f0e9e258 
>   configs/common/Simulation.py b3d5f0e9e258 
>   configs/example/garnet_synth_traffic.py b3d5f0e9e258 
>   configs/example/ruby_direct_test.py b3d5f0e9e258 
>   configs/example/ruby_gpu_random_test.py b3d5f0e9e258 
>   configs/example/ruby_mem_test.py b3d5f0e9e258 
>   configs/example/ruby_random_test.py b3d5f0e9e258 
> 
> Diff: http://reviews.gem5.org/r/3683/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Andreas Hansson
> 
>

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Re: [gem5-dev] Review Request 3684: alpha: Remove ALPHA support and supplemental files

2016-10-24 Thread Andreas Hansson 

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src/cpu/o3/rename_map.cc (line 99)


It would be great if someone familiar with the o3 model could double check 
this modification.


- Andreas Hansson


On Oct. 24, 2016, 8:43 p.m., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3684/
> ---
> 
> (Updated Oct. 24, 2016, 8:43 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11689:e1835e5846b9
> ---
> alpha: Remove ALPHA support and supplemental files
> 
> This patch removes support for ALPHA, and correspondingly also removes
> any devices, tests, supporting functions, and configurations unique to
> ALPHA.
> 
> R.I.P.
> 
> A few things that are worth re-adding using something other than
> ALPHA:
> 
> 1) A two-system regresssion using Ethernet
> 
> 2) Ruby tester regressions using NULL for the variuos Ruby protocols
> 
> 
> Diffs
> -
> 
>   
> tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
>  b3d5f0e9e258 
>   
> tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini 
> b3d5f0e9e258 
>   tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr 
> b3d5f0e9e258 
>   tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout 
> b3d5f0e9e258 
>   
> tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt 
> b3d5f0e9e258 
>   
> tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
>  b3d5f0e9e258 
>   
> tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
>  b3d5f0e9e258 
>   
> tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
>  b3d5f0e9e258 
>   
> tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
>  b3d5f0e9e258 
>   
> tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
>  b3d5f0e9e258 
>   
> tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
>  b3d5f0e9e258 
>   
> tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini 
> b3d5f0e9e258 
>   tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr 
> b3d5f0e9e258 
>   tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout 
> b3d5f0e9e258 
>   
> tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt 
> b3d5f0e9e258 
>   
> tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
>  b3d5f0e9e258 
>   
> tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
>  b3d5f0e9e258 
>   
> tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
>  b3d5f0e9e258 
>   
> tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
>  b3d5f0e9e258 
>   
> tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
>  b3d5f0e9e258 
>   
> tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
>  b3d5f0e9e258 
>   
> tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
>  b3d5f0e9e258 
>   tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini 
> b3d5f0e9e258 
>   tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr b3d5f0e9e258 
>   tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout b3d5f0e9e258 
>   tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b3d5f0e9e258 
>   tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b3d5f0e9e258 
>   tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr b3d5f0e9e258 
>   tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b3d5f0e9e258 
>   tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b3d5f0e9e258 
>   tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini 
> b3d5f0e9e258 
>   tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr b3d5f0e9e258 
>   tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b3d5f0e9e258 
>   tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt 
> b3d5f0e9e258 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
>  b3d5f0e9e258 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
>  b3d5f0e9e258 
>   
> tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
>  b3d5f0e9e258 
>   
>

[gem5-dev] Removal of ALPHA from gem5

2016-10-24 Thread Andreas Hansson 
Hi all,

The day has come.

As previously discussed, http://reviews.gem5.org/r/3684/ removes support for 
ALPHA from gem5. Ultimately this has to be a community decision. Thus, if 
anyone is actually relying on ALPHA for their work please let us know within 
the next two weeks.

If there are any questions or concerns, please speak up. Depending on the 
feedback, I aim to push this patch on November 14th.

Kind regards,

Andreas

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[gem5-dev] Review Request 3684: alpha: Remove ALPHA support and supplemental files

2016-10-24 Thread Andreas Hansson 

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Review request for Default.


Repository: gem5


Description
---

Changeset 11689:e1835e5846b9
---
alpha: Remove ALPHA support and supplemental files

This patch removes support for ALPHA, and correspondingly also removes
any devices, tests, supporting functions, and configurations unique to
ALPHA.

R.I.P.

A few things that are worth re-adding using something other than
ALPHA:

1) A two-system regresssion using Ethernet

2) Ruby tester regressions using NULL for the variuos Ruby protocols


Diffs
-

  
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
 b3d5f0e9e258 
  tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini 
b3d5f0e9e258 
  tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr 
b3d5f0e9e258 
  tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout 
b3d5f0e9e258 
  tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt 
b3d5f0e9e258 
  
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
 b3d5f0e9e258 
  
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
 b3d5f0e9e258 
  
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr 
b3d5f0e9e258 
  
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout 
b3d5f0e9e258 
  
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
 b3d5f0e9e258 
  
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
 b3d5f0e9e258 
  tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini 
b3d5f0e9e258 
  tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr 
b3d5f0e9e258 
  tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout 
b3d5f0e9e258 
  tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt 
b3d5f0e9e258 
  
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
 b3d5f0e9e258 
  
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
 b3d5f0e9e258 
  
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
 b3d5f0e9e258 
  
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
 b3d5f0e9e258 
  
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
 b3d5f0e9e258 
  
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
 b3d5f0e9e258 
  
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
 b3d5f0e9e258 
  tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b3d5f0e9e258 
  tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr b3d5f0e9e258 
  tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout b3d5f0e9e258 
  tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b3d5f0e9e258 
  tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b3d5f0e9e258 
  tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr b3d5f0e9e258 
  tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b3d5f0e9e258 
  tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b3d5f0e9e258 
  tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b3d5f0e9e258 
  tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr b3d5f0e9e258 
  tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b3d5f0e9e258 
  tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b3d5f0e9e258 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
 b3d5f0e9e258 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
 b3d5f0e9e258 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
 b3d5f0e9e258 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
 b3d5f0e9e258 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
 b3d5f0e9e258 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
 b3d5f0e9e258 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
 b3d5f0e9e258 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
 b3d5f0e9e258 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
 b3d5f0e9e258 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
 b3d5f0e9e258 
  
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout

Re: [gem5-dev] Review Request 3502: mem: Split the hit_latency into tag_latency and data_latency

2016-10-24 Thread Andreas Hansson 


> On July 27, 2016, 4:52 p.m., Andreas Hansson wrote:
> > src/mem/cache/tags/base_set_assoc.hh, line 228
> > 
> >
> > Could you add a comment here?
> > 
> > It seems to me this code is not right, as it checks if the data is 
> > technically written now, but we only need the data at time T.
> > 
> > Should we not rather add the dataLatency to the blk->whenReady and then 
> > do the plus or max opteration?
> 
> Sophiane SENNI wrote:
> I actually don't really understand what this code represents, which was 
> already present before applying the patch. Because it seems to show a case 
> where the cache latency is greater than accessLatency, when the lat variable 
> is updated as follows:
> lat = cache->ticksToCycles(blk->whenReady - curTick())
> Can this situation actually occur ?
> 
> Andreas Hansson wrote:
> blk->whenReady represents the fact that the block is technically not 
> available yet. Due to how we do timing modelling we annotate the block when 
> it arrives, but have to remember when it is _actually_ availalbe. Thus, 
> anything we do here should add on top of the blk->whenReady. Same for fa_lru
> 
> Sophiane SENNI wrote:
> Ok. So if I understood, we actually need to apply the accessLatency on 
> top of the blk->whenReady. Hence, the good code would be as follows:
> 
> if (blk->whenReady > curTick()
> && cache->ticksToCycles(blk->whenReady - curTick())
> > accessLatency) {
> lat = cache->ticksToCycles(blk->whenReady - curTick()) + 
> accessLatency;
> }
> 
> Does this change make more sense ?

Yes. Also, could you add a comment to explain what is happening here.


> On July 27, 2016, 4:52 p.m., Andreas Hansson wrote:
> > src/mem/cache/tags/fa_lru.cc, line 188
> > 
> >
> > here we don't care about blk->whenReady?
> 
> Sophiane SENNI wrote:
> I we care about blk->whenReady in base_set_assoc.hh, I assume we have 
> also to care about it here.

Agreed.


- Andreas


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On Oct. 24, 2016, 2:56 p.m., Sophiane SENNI wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3502/
> ---
> 
> (Updated Oct. 24, 2016, 2:56 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11688:9dba209f1590
> ---
> mem: Split the hit_latency into tag_latency and data_latency
> 
> If the cache access mode is parallel, i.e. "sequential_access" parameter
> is set to "False", tags and data are accessed in parallel. Therefore,
> the hit_latency is the maximum latency between tag_latency and
> data_latency. On the other hand, if the cache access mode is
> sequential, i.e. "sequential_access" parameter is set to "True",
> tags and data are accessed sequentially. Therefore, the hit_latency
> is the sum of tag_latency plus data_latency.
> 
> 
> Diffs
> -
> 
>   src/mem/cache/tags/base.cc 4aac82f10951 
>   src/mem/cache/tags/base_set_assoc.hh 4aac82f10951 
>   src/mem/cache/tags/fa_lru.cc 4aac82f10951 
>   configs/common/Caches.py 4aac82f10951 
>   configs/common/O3_ARM_v7a.py 4aac82f10951 
>   configs/example/arm/devices.py 4aac82f10951 
>   configs/learning_gem5/part1/caches.py 4aac82f10951 
>   src/mem/cache/Cache.py 4aac82f10951 
>   src/mem/cache/base.hh 4aac82f10951 
>   src/mem/cache/base.cc 4aac82f10951 
>   src/mem/cache/tags/Tags.py 4aac82f10951 
>   src/mem/cache/tags/base.hh 4aac82f10951 
> 
> Diff: http://reviews.gem5.org/r/3502/diff/
> 
> 
> Testing
> ---
> 
> Tested using --Debug-flags=Cache
> 
> 
> Thanks,
> 
> Sophiane SENNI
> 
>

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Re: [gem5-dev] Review Request 3683: config: Break out base options for usage with NULL ISA

2016-10-24 Thread Andreas Hansson 


> On Oct. 20, 2016, 10:14 p.m., Jieming Yin wrote:
> > configs/common/FSConfig.py, line 45
> > 
> >
> > Should it be "from common import PlatformConfig" here as well, just 
> > like in Options.py? This script might cause a problem if 
> > /gem5/configs/common is not added to path.

Sorted. Any further comments? Note that I also changed the name of the function 
adding the non-ISA options, to avoid "base" and "common" saying roughly the 
same thing.


- Andreas


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On Oct. 24, 2016, 9:10 a.m., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3683/
> ---
> 
> (Updated Oct. 24, 2016, 9:10 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11688:3b7d93ec1cf1
> ---
> config: Break out base options for usage with NULL ISA
> 
> This patch breaks out the most basic configuration options into a set
> of base options, to allow them to be used also by scripts that do not
> involve any ISA, and thus no actual CPUs or devices.
> 
> The patch also fixes a few modules so that they can be imported in a
> NULL build, and avoid dragging in FSConfig every time Options is
> imported.
> 
> 
> Diffs
> -
> 
>   configs/common/CpuConfig.py b3d5f0e9e258 
>   configs/common/FSConfig.py b3d5f0e9e258 
>   configs/common/Options.py b3d5f0e9e258 
>   configs/common/PlatformConfig.py b3d5f0e9e258 
>   configs/common/Simulation.py b3d5f0e9e258 
>   configs/example/garnet_synth_traffic.py b3d5f0e9e258 
>   configs/example/ruby_direct_test.py b3d5f0e9e258 
>   configs/example/ruby_gpu_random_test.py b3d5f0e9e258 
>   configs/example/ruby_mem_test.py b3d5f0e9e258 
>   configs/example/ruby_random_test.py b3d5f0e9e258 
> 
> Diff: http://reviews.gem5.org/r/3683/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Andreas Hansson
> 
>

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Re: [gem5-dev] Review Request 3502: mem: Split the hit_latency into tag_latency and data_latency

2016-10-24 Thread Sophiane SENNI 


> On oct. 21, 2016, 1:29 après-midi, Pierre-Yves Péneau wrote:
> > Hi,
> > 
> > Someone can commit this patch ? I don't have right access on the 
> > repository, either Sophiane.
> > Thank you.
> 
> Jason Lowe-Power wrote:
> Sorry we've been so slow on this patch. A couple of questions before I 
> commit.
> 
> 1. Are all of Andreas H.'s comments resolved? I'd like to see a "Ship It" 
> from him.
> 2. You need to make sure the regressions are passing. I understand that 
> our regression testing is poor, but I know that the learning_gem5 regression 
> is failing because of this patch. The file 
> configs/learning_gem5/part1/caches.py needs to be updated. There are likely 
> other files that need to be updated as well (configs/examples/arm/devices.py 
> comes to mind, there may be others).
> 
> Pierre-Yves Péneau wrote:
> 1. Sophiane answered to Andreas H.' issues but I did not respond (quote: 
> "Please go ahead with the patch as is"). I assume it's ok even without a 
> "Ship It" from him.
> 2. Regression tests have been done. Failures are due to missing CPU2000 
> benchmarks. The review will be update soon.

The regression tests passed, except the ones that require proprietary binaries.


- Sophiane


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On oct. 24, 2016, 2:56 après-midi, Sophiane SENNI wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3502/
> ---
> 
> (Updated oct. 24, 2016, 2:56 après-midi)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11688:9dba209f1590
> ---
> mem: Split the hit_latency into tag_latency and data_latency
> 
> If the cache access mode is parallel, i.e. "sequential_access" parameter
> is set to "False", tags and data are accessed in parallel. Therefore,
> the hit_latency is the maximum latency between tag_latency and
> data_latency. On the other hand, if the cache access mode is
> sequential, i.e. "sequential_access" parameter is set to "True",
> tags and data are accessed sequentially. Therefore, the hit_latency
> is the sum of tag_latency plus data_latency.
> 
> 
> Diffs
> -
> 
>   src/mem/cache/tags/base.cc 4aac82f10951 
>   src/mem/cache/tags/base_set_assoc.hh 4aac82f10951 
>   src/mem/cache/tags/fa_lru.cc 4aac82f10951 
>   configs/common/Caches.py 4aac82f10951 
>   configs/common/O3_ARM_v7a.py 4aac82f10951 
>   configs/example/arm/devices.py 4aac82f10951 
>   configs/learning_gem5/part1/caches.py 4aac82f10951 
>   src/mem/cache/Cache.py 4aac82f10951 
>   src/mem/cache/base.hh 4aac82f10951 
>   src/mem/cache/base.cc 4aac82f10951 
>   src/mem/cache/tags/Tags.py 4aac82f10951 
>   src/mem/cache/tags/base.hh 4aac82f10951 
> 
> Diff: http://reviews.gem5.org/r/3502/diff/
> 
> 
> Testing
> ---
> 
> Tested using --Debug-flags=Cache
> 
> 
> Thanks,
> 
> Sophiane SENNI
> 
>

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Re: [gem5-dev] Review Request 3502: mem: Split the hit_latency into tag_latency and data_latency

2016-10-24 Thread Sophiane SENNI 

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---

(Updated Oct. 24, 2016, 2:56 p.m.)


Review request for Default.


Repository: gem5


Description (updated)
---

Changeset 11688:9dba209f1590
---
mem: Split the hit_latency into tag_latency and data_latency

If the cache access mode is parallel, i.e. "sequential_access" parameter
is set to "False", tags and data are accessed in parallel. Therefore,
the hit_latency is the maximum latency between tag_latency and
data_latency. On the other hand, if the cache access mode is
sequential, i.e. "sequential_access" parameter is set to "True",
tags and data are accessed sequentially. Therefore, the hit_latency
is the sum of tag_latency plus data_latency.


Diffs (updated)
-

  src/mem/cache/tags/base.cc 4aac82f10951 
  src/mem/cache/tags/base_set_assoc.hh 4aac82f10951 
  src/mem/cache/tags/fa_lru.cc 4aac82f10951 
  configs/common/Caches.py 4aac82f10951 
  configs/common/O3_ARM_v7a.py 4aac82f10951 
  configs/example/arm/devices.py 4aac82f10951 
  configs/learning_gem5/part1/caches.py 4aac82f10951 
  src/mem/cache/Cache.py 4aac82f10951 
  src/mem/cache/base.hh 4aac82f10951 
  src/mem/cache/base.cc 4aac82f10951 
  src/mem/cache/tags/Tags.py 4aac82f10951 
  src/mem/cache/tags/base.hh 4aac82f10951 

Diff: http://reviews.gem5.org/r/3502/diff/


Testing
---

Tested using --Debug-flags=Cache


Thanks,

Sophiane SENNI

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Re: [gem5-dev] Review Request 3502: mem: Split the hit_latency into tag_latency and data_latency

2016-10-24 Thread Pierre-Yves Péneau 


> On Oct. 21, 2016, 3:29 p.m., Pierre-Yves Péneau wrote:
> > Hi,
> > 
> > Someone can commit this patch ? I don't have right access on the 
> > repository, either Sophiane.
> > Thank you.
> 
> Jason Lowe-Power wrote:
> Sorry we've been so slow on this patch. A couple of questions before I 
> commit.
> 
> 1. Are all of Andreas H.'s comments resolved? I'd like to see a "Ship It" 
> from him.
> 2. You need to make sure the regressions are passing. I understand that 
> our regression testing is poor, but I know that the learning_gem5 regression 
> is failing because of this patch. The file 
> configs/learning_gem5/part1/caches.py needs to be updated. There are likely 
> other files that need to be updated as well (configs/examples/arm/devices.py 
> comes to mind, there may be others).

1. Sophiane answered to Andreas H.' issues but I did not respond (quote: 
"Please go ahead with the patch as is"). I assume it's ok even without a "Ship 
It" from him.
2. Regression tests have been done. Failures are due to missing CPU2000 
benchmarks. The review will be update soon.


- Pierre-Yves


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On July 28, 2016, 12:31 p.m., Sophiane SENNI wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3502/
> ---
> 
> (Updated July 28, 2016, 12:31 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11536:1a3a96d435ed
> ---
> mem: Split the hit_latency into tag_latency and data_latency
> 
> If the cache access mode is parallel, i.e. "sequential_access" parameter 
> is set to "False", tags and data are accessed in parallel. Therefore,
> the hit_latency is the maximum latency between tag_latency and
> data_latency. On the other hand, if the cache access mode is
> sequential, i.e. "sequential_access" parameter is set to "True", 
> tags and data are accessed sequentially. Therefore, the hit_latency
> is the sum of tag_latency plus data_latency.
> 
> 
> Diffs
> -
> 
>   configs/common/Caches.py 4aac82f109517217e6bfb3812689280e7a8fa842 
>   configs/common/O3_ARM_v7a.py 4aac82f109517217e6bfb3812689280e7a8fa842 
>   src/mem/cache/Cache.py 4aac82f109517217e6bfb3812689280e7a8fa842 
>   src/mem/cache/base.hh 4aac82f109517217e6bfb3812689280e7a8fa842 
>   src/mem/cache/base.cc 4aac82f109517217e6bfb3812689280e7a8fa842 
>   src/mem/cache/tags/Tags.py 4aac82f109517217e6bfb3812689280e7a8fa842 
>   src/mem/cache/tags/base.hh 4aac82f109517217e6bfb3812689280e7a8fa842 
>   src/mem/cache/tags/base.cc 4aac82f109517217e6bfb3812689280e7a8fa842 
>   src/mem/cache/tags/base_set_assoc.hh 
> 4aac82f109517217e6bfb3812689280e7a8fa842 
>   src/mem/cache/tags/fa_lru.cc 4aac82f109517217e6bfb3812689280e7a8fa842 
> 
> Diff: http://reviews.gem5.org/r/3502/diff/
> 
> 
> Testing
> ---
> 
> Tested using --Debug-flags=Cache
> 
> 
> Thanks,
> 
> Sophiane SENNI
> 
>

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Re: [gem5-dev] Review Request 3683: config: Break out base options for usage with NULL ISA

2016-10-24 Thread Andreas Hansson 

---
This is an automatically generated e-mail. To reply, visit:
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---

(Updated Oct. 24, 2016, 9:10 a.m.)


Review request for Default.


Repository: gem5


Description (updated)
---

Changeset 11688:3b7d93ec1cf1
---
config: Break out base options for usage with NULL ISA

This patch breaks out the most basic configuration options into a set
of base options, to allow them to be used also by scripts that do not
involve any ISA, and thus no actual CPUs or devices.

The patch also fixes a few modules so that they can be imported in a
NULL build, and avoid dragging in FSConfig every time Options is
imported.


Diffs (updated)
-

  configs/common/CpuConfig.py b3d5f0e9e258 
  configs/common/FSConfig.py b3d5f0e9e258 
  configs/common/Options.py b3d5f0e9e258 
  configs/common/PlatformConfig.py b3d5f0e9e258 
  configs/common/Simulation.py b3d5f0e9e258 
  configs/example/garnet_synth_traffic.py b3d5f0e9e258 
  configs/example/ruby_direct_test.py b3d5f0e9e258 
  configs/example/ruby_gpu_random_test.py b3d5f0e9e258 
  configs/example/ruby_mem_test.py b3d5f0e9e258 
  configs/example/ruby_random_test.py b3d5f0e9e258 

Diff: http://reviews.gem5.org/r/3683/diff/


Testing
---


Thanks,

Andreas Hansson

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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2016-10-24 Thread Cron Daemon 
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby: 
passed.
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby: 
passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing: passed.
* build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing: passed.
* build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby: 
passed.
* build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic: 
passed.
* build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
passed.* build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
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 * build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing: 
passed.
* 
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passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
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* 
build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic:
 passed.
* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer:
 passed.
 * 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer:
 passed.* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer:
 passed.* 
build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer:
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* 
build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level:
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* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
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* build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest: passed.
* build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter: passed.
* build/NULL/tests/opt/quick/se/51.memcheck/null/none/memcheck: passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: passed.
*