date:20170808

[gem5-dev] Change in public/gem5[master]: mem: Signal the local monitor when clearing the global monitor

2017-08-08 Thread Curtis Dunham (Gerrit)

Curtis Dunham has uploaded a new patch set (#2) to the change originally  
created by Nikos Nikoleris. ( https://gem5-review.googlesource.com/3760 )


Change subject: mem: Signal the local monitor when clearing the global  
monitor

..

mem: Signal the local monitor when clearing the global monitor

ARM systems require the coordination of the global and local
monitors. When the system is run without caches the global monitor is
implemented in the abstract memory object. This change adds a callback
from the abstract memory that notifies the local monitor when the
global monitor is cleared.

Additionally, for ARM systems the local monitor signals the event
register and wakes the thread context up. Subsequent wait-for-event
(WFE) instructions will be immediately signaled.

Change-Id: If6c038f3a6bea7239ba4258f07f39c7f9a30500b
Reviewed-by: Andreas Sandberg 
---
M src/arch/alpha/locked_mem.hh
M src/arch/arm/locked_mem.hh
A src/arch/generic/locked_mem.hh
M src/arch/mips/locked_mem.hh
A src/arch/null/locked_mem.hh
M src/arch/power/locked_mem.hh
M src/arch/riscv/locked_mem.hh
M src/arch/sparc/locked_mem.hh
M src/arch/x86/locked_mem.hh
M src/mem/abstract_mem.cc
10 files changed, 196 insertions(+), 104 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: If6c038f3a6bea7239ba4258f07f39c7f9a30500b
Gerrit-Change-Number: 3760
Gerrit-PatchSet: 2
Gerrit-Owner: Nikos Nikoleris 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Signal an event when executing store exclusives

2017-08-08 Thread Curtis Dunham (Gerrit)


Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/4480

to review the following change.


Change subject: arch-arm: Signal an event when executing store exclusives
..

arch-arm: Signal an event when executing store exclusives

When a store exclusive is executed, whether it is successful or not,
the exclusives monitor is cleared and therefore we need to signal an
event for the PE.

Change-Id: I383c88c769c0ac5f5d36c4b5d39c9681134d3a20
Reviewed-by: Andreas Sandberg 
---
M src/arch/arm/isa/insts/str.isa
M src/arch/arm/isa/insts/str64.isa
2 files changed, 10 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index 3f59569..a1b365c 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2010-2011 ARM Limited
+// Copyright (c) 2010-2011,2017 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -228,7 +228,8 @@

 def __init__(self, *args, **kargs):
 super(StoreImmEx, self).__init__(*args, **kargs)
-self.codeBlobs["postacc_code"] = "Result = !writeResult;"
+self.codeBlobs["postacc_code"] = \
+  "Result = !writeResult; SevMailbox = 1;"

 class StoreImm(StoreImmInst, StoreSingle):
 decConstBase = 'LoadStoreImm'
@@ -307,7 +308,8 @@

 def __init__(self, *args, **kargs):
 super(StoreDoubleImmEx, self).__init__(*args, **kargs)
-self.codeBlobs["postacc_code"] = "Result = !writeResult;"
+self.codeBlobs["postacc_code"] = \
+  "Result = !writeResult; SevMailbox = 1;"

 class StoreDoubleImm(StoreImmInst, StoreDouble):
 decConstBase = 'LoadStoreDImm'
diff --git a/src/arch/arm/isa/insts/str64.isa  
b/src/arch/arm/isa/insts/str64.isa

index c15dca1..f281c60 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-

-// Copyright (c) 2011-2013 ARM Limited
+// Copyright (c) 2011-2013,2017 ARM Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -277,7 +277,8 @@
 execBase = 'StoreEx64'
 def __init__(self, *args, **kargs):
 super(StoreEx64, self).__init__(*args, **kargs)
-self.codeBlobs["postacc_code"] = "XResult = !writeResult;"
+self.codeBlobs["postacc_code"] = \
+ "XResult = !writeResult; SevMailbox = 1;"

 def buildStores64(mnem, NameBase, size, flavor="normal"):
 StoreImm64(mnem, NameBase + "_IMM", size, flavor=flavor).emit()
@@ -343,7 +344,8 @@
 writeback = False
 def __init__(self, *args, **kargs):
 super(StoreImmDEx64, self).__init__(*args, **kargs)
-self.codeBlobs["postacc_code"] = "XResult = !writeResult;"
+self.codeBlobs["postacc_code"] = \
+ "XResult = !writeResult; SevMailbox = 1;"

 class StoreRegU64(StoreReg64):
 decConstBase = 'LoadStoreRegU64'

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I383c88c769c0ac5f5d36c4b5d39c9681134d3a20
Gerrit-Change-Number: 4480
Gerrit-PatchSet: 1
Gerrit-Owner: Curtis Dunham 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Nikos Nikoleris 
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Re: [gem5-dev] "RamBank" SimObject

2017-08-08 Thread Gabe Black

Yeah, working through all this config stuff I'm a bit frustrated by what it
is, but I'm also not sure what it should be instead.

Gabe

On Tue, Aug 8, 2017 at 12:05 AM, Andreas Hansson 
wrote:

> Hi Gabe,
>
> It is not that simple.
>
> The whole point is that the crossbar does any address interleaving, so
> that it can be used both for memories and caches (or really any slave
> downstream). Moreover, there is no need for a single level of crossbars to
> actually have all addresses represented. It can be used to build trees,
> diamonds, etc. See the HMC construction for example where we split
> addresses across links, then quadrants, and finally to the vaults/channels.
>
> We spent quite some time thinking about how to best represent this, and I
> think the best option would actually be to use some form of sub system and
> port-group type construct, perhaps combined with a more refined AddrRange.
> There are a lot of challenges that need to be addressed though, and
> previous whiteboard discussions have not yielded a design that actually
> encompasses all the important use-cases.
>
> It would be great to see a good design for this, but it¹s definitely not
> obvious what it would be.
>
> Andreas
>
> On 08/08/2017, 03:17, "gem5-dev on behalf of Gabe Black"
>  wrote:
>
> >Hi folks. I notice that there's a fair bit of code in MemConfig.py which
> >sets up a bank of memory objects to interleave memory accesses among
> >themselves and collectively act as a single memory. This seems like
> >something which should be bound up into a wrapping object, perhaps a
> >RamBank SimObject, which would abstract the complexity of setting up the
> >interleaving. There could be a specialized DramBank object which would
> >help
> >get rid of the ugly issubclass() in create_mem_ctrl function.
> >
> >Gabe
> >___
> >gem5-dev mailing list
> >gem5-dev@gem5.org
> >http://m5sim.org/mailman/listinfo/gem5-dev
>
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
> ___
> gem5-dev mailing list
> gem5-dev@gem5.org
> http://m5sim.org/mailman/listinfo/gem5-dev
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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2017-08-08 Thread Cron Daemon

* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing: FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/o3-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic: FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing: FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/o3-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing: FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby:
 FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* 
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual:
 CHANGED!
* 
build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing: 
CHANGED!
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
passed.
* build/NULL/tests/opt/quick/se/51.memcheck/null/none/memcheck: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: passed.
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 passed.
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 passed.
* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
 passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 passed.
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: passed.

Re: [gem5-dev] "RamBank" SimObject

2017-08-08 Thread Andreas Hansson

Hi Gabe,

It is not that simple.

The whole point is that the crossbar does any address interleaving, so
that it can be used both for memories and caches (or really any slave
downstream). Moreover, there is no need for a single level of crossbars to
actually have all addresses represented. It can be used to build trees,
diamonds, etc. See the HMC construction for example where we split
addresses across links, then quadrants, and finally to the vaults/channels.

We spent quite some time thinking about how to best represent this, and I
think the best option would actually be to use some form of sub system and
port-group type construct, perhaps combined with a more refined AddrRange.
There are a lot of challenges that need to be addressed though, and
previous whiteboard discussions have not yielded a design that actually
encompasses all the important use-cases.

It would be great to see a good design for this, but it¹s definitely not
obvious what it would be.

Andreas

On 08/08/2017, 03:17, "gem5-dev on behalf of Gabe Black"
 wrote:

>Hi folks. I notice that there's a fair bit of code in MemConfig.py which
>sets up a bank of memory objects to interleave memory accesses among
>themselves and collectively act as a single memory. This seems like
>something which should be bound up into a wrapping object, perhaps a
>RamBank SimObject, which would abstract the complexity of setting up the
>interleaving. There could be a specialized DramBank object which would
>help
>get rid of the ugly issubclass() in create_mem_ctrl function.
>
>Gabe
>___
>gem5-dev mailing list
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>http://m5sim.org/mailman/listinfo/gem5-dev

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[gem5-dev] Change in public/gem5[master]: mem-cache: Delete squashed HWPrefetches

2017-08-08 Thread Pau Cabre (Gerrit)

Pau Cabre has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/4340 )


Change subject: mem-cache: Delete squashed HWPrefetches
..

mem-cache: Delete squashed HWPrefetches

Request and Packet for squashed HWPrefetches were not deleted

Change-Id: I9b66bb01b8ed6a5ddfaaa8739a68165dc4a7006c
Signed-off-by: Pau Cabre 
Reviewed-on: https://gem5-review.googlesource.com/4340
Maintainer: Nikos Nikoleris 
Reviewed-by: Nikos Nikoleris 
---
M src/mem/cache/cache.cc
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved



diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index fdc14a7..169ef0d 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -2419,6 +2419,11 @@
 // mshr when all had previously been utilized
 clearBlocked(Blocked_NoMSHRs);
 }
+
+// given that no response is expected, delete Request and  
Packet

+delete tgt_pkt->req;
+delete tgt_pkt;
+
 return false;
 }
 }

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I9b66bb01b8ed6a5ddfaaa8739a68165dc4a7006c
Gerrit-Change-Number: 4340
Gerrit-PatchSet: 2
Gerrit-Owner: Pau Cabre 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Pau Cabre 
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[gem5-dev] Change in public/gem5[master]: mem: Signal the local monitor when clearing the global monitor

[gem5-dev] Change in public/gem5[master]: arch-arm: Signal an event when executing store exclusives

Re: [gem5-dev] "RamBank" SimObject

[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

Re: [gem5-dev] "RamBank" SimObject

[gem5-dev] Change in public/gem5[master]: mem-cache: Delete squashed HWPrefetches

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