[gem5-dev] Change in gem5/gem5[master]: we add PRFM PST instruction for arm

2018-10-19 Thread kodamayu (Gerrit) 
kodamayu has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13675



Change subject: we add PRFM PST instruction for arm
..

we add PRFM PST instruction for arm

Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13
---
M src/arch/arm/insts/mem64.cc
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa/insts/ldr64.isa
M src/mem/cache/base.cc
M src/mem/packet.cc
M src/mem/packet.hh
M src/mem/request.hh
7 files changed, 35 insertions(+), 8 deletions(-)



diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index fa8fdf0..660e56e 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -64,7 +64,11 @@
 Memory64::startDisassembly(std::ostream ) const
 {
 printMnemonic(os, "", false);
-printIntReg(os, dest);
+if (isDataPrefetch()||isInstPrefetch()){
+printPFflags(os, dest);
+}else{
+printIntReg(os, dest);
+}
 ccprintf(os, ", [");
 printIntReg(os, base);
 }
diff --git a/src/arch/arm/insts/static_inst.cc  
b/src/arch/arm/insts/static_inst.cc

index bd6f115..f245cd4 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -324,6 +324,16 @@
 }
 }

+void ArmStaticInst::printPFflags(std::ostream , int flag) const
+{
+const char *flagtoprfop[]= { "PLD", "PLI", "PST", "Reserved"};
+const char *flagtotarget[] = { "L1", "L2", "L3", "Reserved"};
+const char *flagtopolicy[] = { "KEEP", "STRM"};
+
+ccprintf(os, "%s%s%s", flagtoprfop[(flag>>3)&3],
+ flagtotarget[(flag>>1)&3], flagtopolicy[flag&1]);
+}
+
 void
 ArmStaticInst::printFloatReg(std::ostream , RegIndex reg_idx) const
 {
diff --git a/src/arch/arm/isa/insts/ldr64.isa  
b/src/arch/arm/isa/insts/ldr64.isa

index 7c17726..54e50d7 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -74,6 +74,10 @@
 elif self.flavor == "iprefetch":
 self.memFlags.append("Request::PREFETCH")
 self.instFlags = ['IsInstPrefetch']
+elif self.flavor == "mprefetch":
+self.memFlags.append("dest>>3)&3)==2)? \
+ (Request::PF_EXCLUSIVE):(Request::PREFETCH))")
+self.instFlags = ['IsDataPrefetch']
 if self.micro:
 self.instFlags.append("IsMicroop")

@@ -176,7 +180,7 @@
 self.buildEACode()

 # Code that actually handles the access
-if self.flavor in ("dprefetch", "iprefetch"):
+if self.flavor in ("dprefetch", "iprefetch", "mprefetch"):
 accCode = 'uint64_t temp M5_VAR_USED = Mem%s;'
 elif self.flavor == "fp":
 if self.size in (1, 2, 4):
@@ -365,10 +369,11 @@
 buildLoads64("ldr", "LDRSFP64", 4, False, flavor="fp")
 buildLoads64("ldr", "LDRDFP64", 8, False, flavor="fp")

-LoadImm64("prfm", "PRFM64_IMM", 8, flavor="dprefetch").emit()
-LoadReg64("prfm", "PRFM64_REG", 8, flavor="dprefetch").emit()
-LoadLit64("prfm", "PRFM64_LIT", 8, literal=True,  
flavor="dprefetch").emit()

-LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="dprefetch").emit()
+LoadImm64("prfm", "PRFM64_IMM", 8, flavor="mprefetch").emit()
+LoadReg64("prfm", "PRFM64_REG", 8, flavor="mprefetch").emit()
+LoadLit64("prfm", "PRFM64_LIT", 8, literal=True,
+  flavor="mprefetch").emit()
+LoadImm64("prfum", "PRFUM64_IMM", 8, flavor="mprefetch").emit()

 LoadImm64("ldurb", "LDURB64_IMM", 1, False).emit()
 LoadImm64("ldursb", "LDURSBW64_IMM", 1, True).emit()
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 183d93f..b9641d9 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1654,7 +1654,7 @@

 // should writebacks be included here?  prior code was inconsistent...
 #define SUM_NON_DEMAND(s) \
-(s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
+(s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq] + s[MemCmd::SoftPFExReq])

 demandHits
 .name(name() + ".demand_hits")
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 866bc90..4369e16 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -105,6 +105,9 @@
 /* SoftPFReq */
 { SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse),
 SoftPFResp, "SoftPFReq" },
+/* SoftPFExReq */
+{ SET6(IsRead, NeedsWritable, IsInvalidate, IsRequest,
+   IsSWPrefetch, NeedsResponse), SoftPFResp, "SoftPFExReq" },
 /* HardPFReq */
 { SET5(IsRead, IsRequest, IsHWPrefetch, NeedsResponse, FromCache),
 HardPFResp, "HardPFReq" },
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index f0b7c2f..c59db36 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -94,6 +94,7 @@
 WriteClean,// writes dirty data below without evicting
 CleanEvict,
 SoftPFReq,
+SoftPFExReq,
 HardPFReq,
 SoftPFResp,

[gem5-dev] Change in gem5/gem5[master]: python: Add utility function to override config parameters

2018-10-19 Thread Ciro Santilli (Gerrit) 
Ciro Santilli has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/12984 )


Change subject: python: Add utility function to override config parameters
..

python: Add utility function to override config parameters

Add a utility method, SimObject.apply_config that can be used to
implement SimObject param overrides from the command line. This
function provides safe and convenient semantics for CLI assignment:

* The override expression is evaluated in a restricted environment. The
  only global variables are the child objects and params from the root
  object.

* Only params can be overridden. For example, calling methods or setting
  attributes on SimObjects isn't possible.

* Vectors use non-standard list semantics which enable something similar
  to glob expansion on the shell. For example, setting:

  root.system.cpu[0:2].numThreads = 2

  will override numThreads for cpu 0 and 1 and:

  root.system.cpus[0,2].numThreads = 2

  sets it for cpus 0 and 2.

The intention is that the helper method is called to override default
values before calling m5.instantiate.

Change-Id: I73f99da21d6d8ce1ff2ec8db2bb34338456f6799
Reviewed-on: https://gem5-review.googlesource.com/c/12984
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
---
M src/python/m5/SimObject.py
1 file changed, 82 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 0a5436f..44f26ea 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017 ARM Limited
+# Copyright (c) 2017-2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -934,6 +934,63 @@
 if not "created" in self.__dict__:
   self.__dict__[name] = value

+class SimObjectCliWrapperException(Exception):
+def __init__(self, message):
+super(Exception, self).__init__(message)
+
+class SimObjectCliWrapper(object):
+"""
+Wrapper class to restrict operations that may be done
+from the command line on SimObjects.
+
+Only parameters may be set, and only children may be accessed.
+
+Slicing allows for multiple simultaneous assignment of items in
+one statement.
+"""
+
+def __init__(self, sim_objects):
+self.__dict__['_sim_objects'] = list(sim_objects)
+
+def __getattr__(self, key):
+return SimObjectCliWrapper(sim_object._children[key]
+for sim_object in self._sim_objects)
+
+def __setattr__(self, key, val):
+for sim_object in self._sim_objects:
+if key in sim_object._params:
+if sim_object._params[key].isCmdLineSettable():
+setattr(sim_object, key, val)
+else:
+raise SimObjectCliWrapperException(
+'tried to set or unsettable' \
+'object parameter: ' + key)
+else:
+raise SimObjectCliWrapperException(
+'tried to set or access non-existent' \
+'object parameter: ' + key)
+
+def __getitem__(self, idx):
+"""
+Extends the list() semantics to also allow tuples,
+for example object[1, 3] selects items 1 and 3.
+"""
+out = []
+if isinstance(idx, tuple):
+for t in idx:
+out.extend(self[t]._sim_objects)
+else:
+if isinstance(idx, int):
+_range = range(idx, idx + 1)
+elif not isinstance(idx, slice):
+raise SimObjectCliWrapperException( \
+'invalid index type: ' + repr(idx))
+for sim_object in self._sim_objects:
+if isinstance(idx, slice):
+_range = range(*idx.indices(len(sim_object)))
+out.extend(sim_object[i] for i in _range)
+return SimObjectCliWrapper(out)
+
 # The SimObject class is the root of the special hierarchy.  Most of
 # the code in this class deals with the configuration hierarchy itself
 # (parent/child node relationships).
@@ -1525,6 +1582,30 @@
 for dt in item.generateDeviceTree(state):
 yield dt

+# On a separate method otherwise certain buggy Python versions
+# would fail with: SyntaxError: unqualified exec is not allowed
+# in function 'apply_config'
+def _apply_config_get_dict(self):
+return {
+child_name: SimObjectCliWrapper(
+iter(self._children[child_name]))
+for child_name in self._children
+}
+
+def apply_config(self, params):
+"""
+exec a list

[gem5-dev] Change in gem5/gem5[master]: config: add --param to fs.py, se.py and fs_bigLITTLE.py

2018-10-19 Thread Ciro Santilli (Gerrit) 
Ciro Santilli has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/12985 )


Change subject: config: add --param to fs.py, se.py and fs_bigLITTLE.py
..

config: add --param to fs.py, se.py and fs_bigLITTLE.py

The option allows to set SimObject params from the CLI.

The existing config scripts have a large number of options that simply set
a single SimObject parameter, and many still are not exposed.

This commit allows users to pass arbitrary parameters from the command
line to prevent the need for this kind of trivial option.

Change-Id: Ic4bd36948aca4998d2eaf6369c85d3668efa3944
Reviewed-on: https://gem5-review.googlesource.com/c/12985
Reviewed-by: Andreas Sandberg 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M configs/common/Options.py
M configs/common/Simulation.py
M configs/example/arm/fs_bigLITTLE.py
3 files changed, 18 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/configs/common/Options.py b/configs/common/Options.py
index aed8881..c36dc38 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -125,6 +125,14 @@
 parser.add_option("--maxtime", type="float", default=None,
   help="Run to the specified absolute simulated time  
in "

   "seconds")
+parser.add_option("-P", "--param", action="append", default=[],
+help="Set a SimObject parameter relative to the root node. "
+ "An extended Python multi range slicing syntax can be used "
+ "for arrays. For example: "
+ "'system.cpu[0,1,3:8:2].max_insts_all_threads = 42' "
+ "sets max_insts_all_threads for cpus 0, 1, 3, 5 and 7 "
+ "Direct parameters of the root object are not accessible, "
+ "only parameters of its children.")

 # Add common options that assume a non-NULL ISA.
 def addCommonOptions(parser):
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index f306a03..23a7783 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -597,6 +597,7 @@
 checkpoint_dir = None
 if options.checkpoint_restore:
 cpt_starttick, checkpoint_dir = findCptDir(options, cptdir,  
testsys)

+root.apply_config(options.param)
 m5.instantiate(checkpoint_dir)

 # Initialization is complete.  If we're not in control of simulation
diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 7d66c03..8cf89e3 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -182,6 +182,14 @@
 parser.add_argument("--sim-quantum", type=str, default="1ms",
 help="Simulation quantum for parallel  
simulation. " \

 "Default: %(default)s")
+parser.add_argument("-P", "--param", action="append", default=[],
+help="Set a SimObject parameter relative to the root node. "
+ "An extended Python multi range slicing syntax can be used "
+ "for arrays. For example: "
+ "'system.cpu[0,1,3:8:2].max_insts_all_threads = 42' "
+ "sets max_insts_all_threads for cpus 0, 1, 3, 5 and 7 "
+ "Direct parameters of the root object are not accessible, "
+ "only parameters of its children.")
 return parser

 def build(options):
@@ -330,6 +338,7 @@
 addOptions(parser)
 options = parser.parse_args()
 root = build(options)
+root.apply_config(options.param)
 instantiate(options)
 run()


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ic4bd36948aca4998d2eaf6369c85d3668efa3944
Gerrit-Change-Number: 12985
Gerrit-PatchSet: 8
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-CC: Daniel Carvalho 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Move evictBlock(CacheBlk*, PacketList&) to base

2018-10-19 Thread Daniel Carvalho (Gerrit) 
Daniel Carvalho has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13656



Change subject: mem-cache: Move evictBlock(CacheBlk*, PacketList&) to base
..

mem-cache: Move evictBlock(CacheBlk*, PacketList&) to base

Move evictBlock(CacheBlk*, PacketList&) to base cache,
as it is both sub-classes implementations are equal.

Change-Id: I80fbd16813bfcc4938fb01ed76abe29b3f8b3018
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
M src/mem/cache/noncoherent_cache.cc
M src/mem/cache/noncoherent_cache.hh
6 files changed, 11 insertions(+), 24 deletions(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 0eeb192..e730b3e 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1298,6 +1298,15 @@
 blk->invalidate();
 }

+void
+BaseCache::evictBlock(CacheBlk *blk, PacketList )
+{
+PacketPtr pkt = evictBlock(blk);
+if (pkt) {
+writebacks.push_back(pkt);
+}
+}
+
 PacketPtr
 BaseCache::writebackBlk(CacheBlk *blk)
 {
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 92748a3..47352c6 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -685,7 +685,7 @@
  * @param blk Block to invalidate
  * @param writebacks Return a list of packets with writebacks
  */
-virtual void evictBlock(CacheBlk *blk, PacketList ) = 0;
+void evictBlock(CacheBlk *blk, PacketList );

 /**
  * Invalidate a cache block.
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 116b543..cb8bb0a 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -177,7 +177,7 @@
 // flush and invalidate any existing block
 CacheBlk *old_blk(tags->findBlock(pkt->getAddr(),  
pkt->isSecure()));

 if (old_blk && old_blk->isValid()) {
-evictBlock(old_blk, writebacks);
+BaseCache::evictBlock(old_blk, writebacks);
 }

 blk = nullptr;
@@ -851,15 +851,6 @@
 return pkt;
 }

-void
-Cache::evictBlock(CacheBlk *blk, PacketList )
-{
-PacketPtr pkt = evictBlock(blk);
-if (pkt) {
-writebacks.push_back(pkt);
-}
-}
-
 PacketPtr
 Cache::cleanEvictBlk(CacheBlk *blk)
 {
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index f8eccfe..9d5b907 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -141,8 +141,6 @@

 M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;

-void evictBlock(CacheBlk *blk, PacketList ) override;
-
 /**
  * Create a CleanEvict request for the given block.
  *
diff --git a/src/mem/cache/noncoherent_cache.cc  
b/src/mem/cache/noncoherent_cache.cc

index b4ffed7..ae53bb3 100644
--- a/src/mem/cache/noncoherent_cache.cc
+++ b/src/mem/cache/noncoherent_cache.cc
@@ -355,15 +355,6 @@
 return pkt;
 }

-void
-NoncoherentCache::evictBlock(CacheBlk *blk, PacketList )
-{
-PacketPtr pkt = evictBlock(blk);
-if (pkt) {
-writebacks.push_back(pkt);
-}
-}
-
 NoncoherentCache*
 NoncoherentCacheParams::create()
 {
diff --git a/src/mem/cache/noncoherent_cache.hh  
b/src/mem/cache/noncoherent_cache.hh

index 2a60f4c..0c28255 100644
--- a/src/mem/cache/noncoherent_cache.hh
+++ b/src/mem/cache/noncoherent_cache.hh
@@ -124,8 +124,6 @@

 M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;

-void evictBlock(CacheBlk *blk, PacketList ) override;
-
   public:
 NoncoherentCache(const NoncoherentCacheParams *p);
 };

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add support for first-/non-faulting loads

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13523 )


Change subject: arch-arm: Add support for first-/non-faulting loads
..

arch-arm: Add support for first-/non-faulting loads

In addition to the ISA-level changes, this changeset includes all the
necessary modifications to the various CPU models to properly handle
the new faulting behaviours.

Change-Id: I3c9e66bfee6a642570cf46980ba7e3a96a17b599
Signed-off-by: Gabor Dozsa 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
M src/arch/arm/insts/sve_macromem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/registers.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/dyn_inst.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
M src/cpu/utils.hh
M src/mem/abstract_mem.cc
M src/mem/packet.hh
M src/mem/request.hh
M src/sim/faults.cc
M src/sim/faults.hh
33 files changed, 1,115 insertions(+), 507 deletions(-)


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[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Increase LSQ buffer sizes to match max vector length

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13525 )


Change subject: cpu-o3: Increase LSQ buffer sizes to match max vector length
..

cpu-o3: Increase LSQ buffer sizes to match max vector length

Change-Id: I5890c7cfa147125ce3389001f85d56d4b5a9911d
Signed-off-by: Gabor Dozsa 
---
M src/cpu/o3/lsq_unit.hh
1 file changed, 8 insertions(+), 5 deletions(-)


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Gerrit-Change-Number: 13525
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Gabrielli 
Gerrit-Reviewer: Gabor Dozsa 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add support for SVE load/store structures

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13524 )


Change subject: arch-arm: Add support for SVE load/store structures
..

arch-arm: Add support for SVE load/store structures

Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff
Signed-off-by: Giacomo Gabrielli 
---
M src/arch/arm/insts/sve_macromem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/registers.hh
6 files changed, 1,304 insertions(+), 1 deletion(-)


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Gerrit-Branch: master
Gerrit-Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff
Gerrit-Change-Number: 13524
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Gabrielli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Javier 
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[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Add cache read ports limit to LSQ

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13517 )


Change subject: cpu-o3: Add cache read ports limit to LSQ
..

cpu-o3: Add cache read ports limit to LSQ

This change introduces cache read ports to limit the number of
per-cycle loads. Previously only the number of per-cycle stores
could be limited.

Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4
Signed-off-by: Gabor Dozsa 
Reviewed-by: Giacomo Gabrielli 
---
M src/cpu/o3/O3CPU.py
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit_impl.hh
4 files changed, 50 insertions(+), 19 deletions(-)


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Gerrit-Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4
Gerrit-Change-Number: 13517
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Gabrielli 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE contiguous loads/stores

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13519 )


Change subject: arch-arm: Add initial support for SVE contiguous  
loads/stores

..

arch-arm: Add initial support for SVE contiguous loads/stores

Thanks to Pau Cabre and Adria Armejach Sanosa for their contribution
of bugfixes.

Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46
Signed-off-by: Giacomo Gabrielli 
---
M src/arch/arm/SConscript
A src/arch/arm/insts/sve_mem.cc
A src/arch/arm/insts/sve_mem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/insts.isa
A src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/templates/sve.isa
A src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/isa/templates/templates.isa
10 files changed, 1,429 insertions(+), 1 deletion(-)


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Gerrit-Change-Id: If8983cf85d95cddb187c90967a94ddfe2414bc46
Gerrit-Change-Number: 13519
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Gerrit-Owner: Giacomo Gabrielli 
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[gem5-dev] Change in gem5/gem5[master]: cpu-o3: O3 LSQ Generalisation

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13516 )


Change subject: cpu-o3: O3 LSQ Generalisation
..

cpu-o3: O3 LSQ Generalisation

This patch does a large modification of the LSQ in the O3 model. The
main goal of the patch is to remove the 'an operation can be served with
one or two memory requests' assumption that is present in the LSQ
and the instruction with the req, reqLow, reqHigh triplet, and
generalising it to operations that can be addressed with one request,
and operations that require many requests, embodied in the
SingleDataRequest and the SplitDataRequest.

This modification has been done mimicking the minor model to an extent,
shifting the responsibilities of dealing with VtoP translation and
tracking the status and resources from the DynInst to the LSQ via the
LSQRequest. The LSQRequest models the information concerning the
operation, handles the creation of fragments for translation and request
as well as assembling/splitting the data accordingly.

With this modifications, the implementation of vector ISAs, particularly
on the memory side, become more rich, as the new model permits a
dissociation of the ISA characteristics as vector length, from the
microarchitectural characteristics that govern how contiguous loads are
executing, allowing exploration of different LSQ to DL1 bus widths to
understand the tradeoffs in complexity and performance.

Part of the complexities introduced stem from the fact that gem5 keeps a
large amount of metadata regarding, in particular, memory operations,
thus, when an instruction is squashed while some operation as TLB lookup
or cache access is ongoing, when the relevant structure communicates to
the LSQ that the operation is over, it tries to access some pieces of
data that should have died when the instruction is squashed, leading to
asserts, panics, or memory corruption. To ensure the correct behaviour,
the LSQRequest rely on assesing who is their owner, and self-destroying
if they detect their owner is done with the request, and there will be
no subsequent action. For example, in the case of an instruction
squashed whal the TLB is doing a walk to serve the translation, when the
translation is served by the TLB, the LSQRequest detects that the
instruction was squashed, and as the translation is done, no one else
expect to access its information, and therefore, it self-destructs.
Having destroyed the LSQRequest earlier, would lead to wrong behaviour
as the TLB walk may access some fields of it.

Additional authors:
- Gabor Dozsa 

Change-Id: I9578a1a3f6b899c390cdd886856a24db68ff7d0c
Signed-off-by: Giacomo Gabrielli 
---
M src/base/refcnt.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/o3/probe/elastic_trace.cc
11 files changed, 1,887 insertions(+), 1,273 deletions(-)


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Gerrit-Change-Id: I9578a1a3f6b899c390cdd886856a24db68ff7d0c
Gerrit-Change-Number: 13516
Gerrit-PatchSet: 4
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[gem5-dev] Change in gem5/gem5[master]: base: Iterable CircularQueue implementation

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#10) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13127 )


Change subject: base: Iterable CircularQueue implementation
..

base: Iterable CircularQueue implementation

The former implementation of CircleBuf is functional but a bit too
tailored to match a use-case. This patches introduces a new iterable
circular queue, which adds some more functionality so it can also be
used for the newer LSQ implementation, where iteration and iterators
are a very desirable feature.

Additional contributors: Gabor Dozsa.

Change-Id: I5cfb95c8abc1f5e566a114acdbf23fc52a38ce5e
Signed-off-by: Giacomo Gabrielli 
---
A src/base/circular_queue.hh
1 file changed, 629 insertions(+), 0 deletions(-)


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Gerrit-Branch: master
Gerrit-Change-Id: I5cfb95c8abc1f5e566a114acdbf23fc52a38ce5e
Gerrit-Change-Number: 13127
Gerrit-PatchSet: 10
Gerrit-Owner: Giacomo Gabrielli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE gather/scatter loads/stores

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13521 )


Change subject: arch-arm: Add initial support for SVE gather/scatter  
loads/stores

..

arch-arm: Add initial support for SVE gather/scatter loads/stores

In addition to the code for implementing decoding and execution of
these instructions, a couple of additional features have been
implemented:

1. a mechanism to skip the memory access part of a load/store
operation - used by gather loads for implementing zeroing
predication;

2. the Arm decoder was augmented in a previous changeset to keep track
of the active SVE vector length - this feature is now used by
gather/scatter operations to determine the right number of microops to
be generated.

Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2
Signed-off-by: Giacomo Gabrielli 
---
M src/arch/arm/decoder.hh
A src/arch/arm/insts/sve_macromem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/registers.hh
M src/arch/isa_parser.py
M src/cpu/base_dyn_inst.hh
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
18 files changed, 1,491 insertions(+), 107 deletions(-)


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Gerrit-Branch: master
Gerrit-Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2
Gerrit-Change-Number: 13521
Gerrit-PatchSet: 4
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for the Scalable Vector Extension

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13515 )


Change subject: arch-arm: Add initial support for the Scalable Vector  
Extension

..

arch-arm: Add initial support for the Scalable Vector Extension

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- an additional predicate register file;
- basic system-level support.

Additional authors:
- Javier Setoain 
- Gabor Dozsa 
- Giacomo Travaglini 

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli 
---
M configs/common/FSConfig.py
M configs/common/Options.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/fs.py
M configs/example/se.py
M src/arch/SConscript
M src/arch/alpha/isa.hh
M src/arch/alpha/registers.hh
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
A src/arch/arm/insts/sve.cc
A src/arch/arm/insts/sve.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/formats.isa
A src/arch/arm/isa/formats/sve_2nd_level.isa
A src/arch/arm/isa/formats/sve_top_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/mem.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
A src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/operands.isa
A src/arch/arm/isa/templates/sve.isa
M src/arch/arm/isa/templates/templates.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/process.cc
M src/arch/arm/registers.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
A src/arch/generic/pred_reg.hh
M src/arch/generic/vec_reg.hh
M src/arch/isa_parser.py
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/null/registers.hh
M src/arch/power/isa.hh
M src/arch/power/registers.hh
M src/arch/riscv/isa.hh
M src/arch/riscv/registers.hh
M src/arch/sparc/isa.hh
M src/arch/sparc/registers.hh
M src/arch/x86/isa.hh
M src/arch/x86/registers.hh
M src/cpu/FuncUnit.py
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/exec_context.hh
M src/cpu/exetrace.cc
M src/cpu/inst_res.hh
M src/cpu/minor/MinorCPU.py
M src/cpu/minor/exec_context.hh
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/FUPool.py
M src/cpu/o3/FuncUnitConfig.py
M src/cpu/o3/O3CPU.py
M src/cpu/o3/comm.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/op_class.hh
M src/cpu/reg_class.cc
M src/cpu/reg_class.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/static_inst.hh
M src/cpu/thread_context.cc
M src/cpu/thread_context.hh
M src/sim/insttracer.hh
M src/sim/serialize.cc
98 files changed, 12,528 insertions(+), 129 deletions(-)


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Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Gerrit-Change-Number: 13515
Gerrit-PatchSet: 4
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Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[master]: mem: Add support for partial stores and wide memory accesses

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13518 )


Change subject: mem: Add support for partial stores and wide memory accesses
..

mem: Add support for partial stores and wide memory accesses

This changeset adds support for partial (or masked) stores, i.e.
stores that can disable writes to individual bytes within the target
address range.  In addition, this changeset extends the code to crack
memory accesses across most CPU models (TimingSimpleCPU still TBD), so
that arbitrarily wide memory accesses are supported.  These changes
are required for supporting ISAs with wide vectors.

Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92
Signed-off-by: Giacomo Gabrielli 
---
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/lsq.cc
M src/cpu/minor/lsq.hh
M src/cpu/o3/cpu.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/simple/atomic.cc
M src/cpu/simple/atomic.hh
M src/cpu/simple/base.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/simple/timing.hh
A src/cpu/utils.hh
M src/mem/abstract_mem.cc
M src/mem/cache/cache.cc
M src/mem/packet.hh
M src/mem/request.hh
21 files changed, 409 insertions(+), 170 deletions(-)


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Gerrit-Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92
Gerrit-Change-Number: 13518
Gerrit-PatchSet: 4
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Treat SVE prefetch instructions as no-ops

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13522 )


Change subject: arch-arm: Treat SVE prefetch instructions as no-ops
..

arch-arm: Treat SVE prefetch instructions as no-ops

Change-Id: Ife0424e274dd65d6dc4f6e5cc5e37d17b03be0d8
Signed-off-by: Giacomo Gabrielli 
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
1 file changed, 10 insertions(+), 6 deletions(-)


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Gerrit-Change-Id: Ife0424e274dd65d6dc4f6e5cc5e37d17b03be0d8
Gerrit-Change-Number: 13522
Gerrit-PatchSet: 4
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[gem5-dev] Change in gem5/gem5[master]: cpu-o3: Add support for pinned writes

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded a new patch set (#4) to the change  
originally created by Giacomo Gabrielli. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13520 )


Change subject: cpu-o3: Add support for pinned writes
..

cpu-o3: Add support for pinned writes

This patch adds support for pinning registers for a certain number of
consecutive writes.  This is only relevant for timing CPU models
(functional-only models are unaffected), and it is primarily needed to
provide a realistic execution model for micro-coded operations whose
microops can write to non-overlapping portions of a destination
register, e.g.  vector gather loads.  In those cases, this mechanism
can disable renaming for a sequence of consecutive writes, thus making
the resulting execution more efficient: allocating a new physical
register for each microop would introduce a read-modify-write chain of
dependencies, while with these modifications the microops can write
back in parallel.

Please note that this new feature is only leveraged by O3CPU for the
time being.

Change-Id: I07eb5fdbd1fa0b748c9bdc1174d9f330fda34f81
Signed-off-by: Giacomo Gabrielli 
---
M src/cpu/o3/comm.hh
M src/cpu/o3/free_list.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/reg_class.hh
9 files changed, 92 insertions(+), 41 deletions(-)


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Gerrit-Change-Id: I07eb5fdbd1fa0b748c9bdc1174d9f330fda34f81
Gerrit-Change-Number: 13520
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Gabrielli 
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[gem5-dev] Change in gem5/gem5[master]: Remove circular

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13655



Change subject: Remove circular
..

Remove circular

Change-Id: I4c2b0cd1c994bb2e57adbe8678d01e00aaa9662e
---
M src/base/circular_queue.hh
1 file changed, 1 insertion(+), 21 deletions(-)



diff --git a/src/base/circular_queue.hh b/src/base/circular_queue.hh
index f745fe4..9c9d224 100644
--- a/src/base/circular_queue.hh
+++ b/src/base/circular_queue.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -624,26 +624,6 @@
 }
 return iterator(this, idx, round);
 }
-
-/** Return an iterator to an index in the vector.
- * Same as the previous except that in the case in which the queue is  
full
- * and idx == head, in which case the past-the-end iterator is  
returned.

- */
-iterator getBoundaryIterator(size_t idx) {
-assert(isValidIdx(idx) || add(_tail, 1) == idx);
-if (_head == idx && (_empty || (add(_tail, 1) == _head)))
-return end();
-
-uint32_t round = _round;
-if (idx > _tail) {
-if (idx >= _head && _head > _tail && !_empty) {
-round -= 1;
-}
-} else if (idx < _head && _tail + 1 == _size) {
-round += 1;
-}
-return iterator(this, idx, round);
-}
 };

 #endif /* __BASE_CIRCULARQUEUE_HH__ */

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I4c2b0cd1c994bb2e57adbe8678d01e00aaa9662e
Gerrit-Change-Number: 13655
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: arm: treat aarch64 hints as NOPs instead of panic

2018-10-19 Thread Ciro Santilli (Gerrit) 
Ciro Santilli has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13476 )


Change subject: arm: treat aarch64 hints as NOPs instead of panic
..

arm: treat aarch64 hints as NOPs instead of panic

Change-Id: Ida2a746e6188171bd2e4da92a4efb33fcbaa2b69
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/13476
Maintainer: Andreas Sandberg 
---
M src/arch/arm/isa/formats/aarch64.isa
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index cd106ab..26c65ec 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -369,7 +369,8 @@
 }
 break;
 }
-return new Unknown64(machInst);
+return new WarnUnimplemented(
+"unallocated_hint", machInst);
 } else if (crn == 0x3 && op1 == 0x3) {
 switch (op2) {
   case 0x2:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ida2a746e6188171bd2e4da92a4efb33fcbaa2b69
Gerrit-Change-Number: 13476
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arm: update hint instruction decoding to match ARMv8.5

2018-10-19 Thread Ciro Santilli (Gerrit) 
Ciro Santilli has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13475 )


Change subject: arm: update hint instruction decoding to match ARMv8.5
..

arm: update hint instruction decoding to match ARMv8.5

This fixes:

- unallocated hints that have since been allocated
- unallocated and unimplemented hint instructions being treated as
  Unknown instead of the correct NOP
- missing encoding for DBG on A32

Unallocated and unimplemented hints give a warning if executed.

The most important fix was for the CSDB Spectre mitigation
instruction, which was added recently and previously unallocated and
treated as Unknown.

The Linux kernel v4.18 ARMv7 uses CSDB it and boot would
fail with "undefined instruction" since Linux commit
1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613

Change-Id: I283da3f08a9af4148edc6fb3ca2930cbb97126b8
Reviewed-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/13475
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/branch.isa
M src/arch/arm/isa/formats/data.isa
3 files changed, 136 insertions(+), 37 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved



diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index aa38fd4..cd106ab 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -292,22 +292,84 @@
 if (rt != 0x1f || l)
 return new Unknown64(machInst);
 if (crn == 0x2 && op1 == 0x3) {
-switch (op2) {
+switch (crm) {
   case 0x0:
-return new NopInst(machInst);
+switch (op2) {
+  case 0x0:
+return new NopInst(machInst);
+  case 0x1:
+return new YieldInst(machInst);
+  case 0x2:
+return new WfeInst(machInst);
+  case 0x3:
+return new WfiInst(machInst);
+  case 0x4:
+return new SevInst(machInst);
+  case 0x5:
+return new SevlInst(machInst);
+}
+break;
   case 0x1:
-return new YieldInst(machInst);
+switch (op2) {
+  case 0x0:
+return new WarnUnimplemented(
+"pacia", machInst);
+  case 0x2:
+return new WarnUnimplemented(
+"pacib", machInst);
+  case 0x4:
+return new WarnUnimplemented(
+"autia", machInst);
+  case 0x6:
+return new WarnUnimplemented(
+"autib", machInst);
+}
+break;
   case 0x2:
-return new WfeInst(machInst);
+switch (op2) {
+  case 0x0:
+return new WarnUnimplemented(
+"esb", machInst);
+  case 0x1:
+return new WarnUnimplemented(
+"psb csync", machInst);
+  case 0x2:
+return new WarnUnimplemented(
+"tsb csync", machInst);
+  case 0x4:
+return new WarnUnimplemented(
+"csdb", machInst);
+}
+break;
   case 0x3:
-return new WfiInst(machInst);
+switch (op2) {
+  case 0x0:
+  case 0x1:
+return new WarnUnimplemented(
+"pacia", machInst);
+  case 0x2:
+  case 0x3:
+return new WarnUnimplemented(
+"pacib", machInst);
+

[gem5-dev] Change in gem5/gem5[master]: sim: Move BitUnion overloading to show/parseParams

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13636



Change subject: sim: Move BitUnion overloading to show/parseParams
..

sim: Move BitUnion overloading to show/parseParams

This patch is moving template overloading for BitUnions into the
showParam, parseParams functions. Henceforth BitUnion types will use the
common param wrapper.
This patch implicitly implements (UN)SERIALIZE_CONTAINER for BitUnions.

Change-Id: I0e1faadb4afd4dc9de5dc5fca40041e349c9ba73
Signed-off-by: Giacomo Travaglini 
---
M src/sim/serialize.hh
1 file changed, 23 insertions(+), 55 deletions(-)



diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh
index adaefdd..5434777 100644
--- a/src/sim/serialize.hh
+++ b/src/sim/serialize.hh
@@ -285,6 +285,29 @@
 os << value;
 }

+template 
+bool
+parseParam(const std::string , BitUnionType )
+{
+auto storage = static_cast>(value);
+auto res = to_number(s, storage);
+value = storage;
+return res;
+}
+
+template 
+void
+showParam(CheckpointOut , const BitUnionType )
+{
+auto storage = static_cast>(value);
+
+// For a BitUnion8, the storage type is an unsigned char.
+// Since we want to serialize a number we need to cast to
+// unsigned int
+os << ((sizeof(storage) == 1) ?
+static_cast(storage) : storage);
+}
+
 // Treat 8-bit ints (chars) as ints on output, not as chars
 template <>
 inline void
@@ -354,13 +377,6 @@
 os << "\n";
 }

-template 
-void
-paramOut(CheckpointOut , const std::string , const BitUnionType  
)

-{
-paramOut(cp, name, static_cast >(p));
-}
-
 template 
 void
 paramIn(CheckpointIn , const std::string , T )
@@ -372,15 +388,6 @@
 }
 }

-template 
-void
-paramIn(CheckpointIn , const std::string , BitUnionType )
-{
-BitUnionBaseType b;
-paramIn(cp, name, b);
-p = b;
-}
-
 template 
 bool
 optParamIn(CheckpointIn , const std::string ,
@@ -397,20 +404,6 @@
 }
 }

-template 
-bool
-optParamIn(CheckpointIn , const std::string ,
-   BitUnionType , bool warn = true)
-{
-BitUnionBaseType b;
-if (optParamIn(cp, name, b, warn)) {
-p = b;
-return true;
-} else {
-return false;
-}
-}
-
 template 
 void
 arrayParamOut(CheckpointOut , const std::string ,
@@ -628,31 +621,6 @@
 }
 }

-template 
-static void
-arrayParamOut(CheckpointOut , const std::string ,
-  const BitUnionType *param, unsigned size)
-{
-// We copy the array into a vector. This is needed since we cannot
-// directly typecast a pointer to BitUnionType into a pointer
-// of BitUnionBaseType but we can typecast BitUnionType
-// to BitUnionBaseType since we overloaded the typecast operator
-std::vector> bitunion_vec(param, param + size);
-
-arrayParamOut(cp, name, bitunion_vec);
-}
-
-template 
-static void
-arrayParamIn(CheckpointIn , const std::string ,
- BitUnionType *param, unsigned size)
-{
-std::vector> bitunion_vec(size);
-
-arrayParamIn(cp, name, bitunion_vec);
-std::copy(bitunion_vec.begin(), bitunion_vec.end(), param);
-}
-
 void
 debug_serialize(const std::string _dir);


--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I0e1faadb4afd4dc9de5dc5fca40041e349c9ba73
Gerrit-Change-Number: 13636
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: sim: Move paramIn/Out definition to header file

2018-10-19 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/13635



Change subject: sim: Move paramIn/Out definition to header file
..

sim: Move paramIn/Out definition to header file

This patch is moving the definitions of paramIn/Out templates to
the header file. In this way we gain:

1) We don't have to do explicit instantiation anymore for user defined
types. This spares us from including data type header files into
serialize.cc

2) We can overload show/parseParam for BitUnions or any other type
that requires special handling when serializing. Just by overloading
the two templates we get all the containers' (list, vector, array..)
serialization for free

2) gtest: With the idea of adding unit tests for Serializable objects,
we can avoid importing serialize.cc and just redefine Serializable
methods in the test source, implementing a Serializable stub

Change-Id: I45a9bb87d5ef886a3668fd477005cd105f612e36
Signed-off-by: Giacomo Travaglini 
---
M src/sim/serialize.cc
M src/sim/serialize.hh
2 files changed, 481 insertions(+), 592 deletions(-)



diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc
index a03a396..095a44c 100644
--- a/src/sim/serialize.cc
+++ b/src/sim/serialize.cc
@@ -57,12 +57,8 @@
 #include 
 #include 

-#include "arch/generic/vec_reg.hh"
-#include "base/framebuffer.hh"
 #include "base/inifile.hh"
-#include "base/logging.hh"
 #include "base/output.hh"
-#include "base/str.hh"
 #include "base/trace.hh"
 #include "debug/Checkpoint.hh"
 #include "sim/eventq.hh"
@@ -75,412 +71,11 @@

 using namespace std;

-//
-// The base implementations use to_number for parsing and '<<' for
-// displaying, suitable for integer types.
-//
-template 
-bool
-parseParam(const string , T )
-{
-return to_number(s, value);
-}
-
-template 
-void
-showParam(CheckpointOut , const T )
-{
-os << value;
-}
-
-//
-// Template specializations:
-// - char (8-bit integer)
-// - floating-point types
-// - bool
-// - string
-//
-
-// Treat 8-bit ints (chars) as ints on output, not as chars
-template <>
-void
-showParam(CheckpointOut , const char )
-{
-os << (int)value;
-}
-
-
-template <>
-void
-showParam(CheckpointOut , const signed char )
-{
-os << (int)value;
-}
-
-
-template <>
-void
-showParam(CheckpointOut , const unsigned char )
-{
-os << (unsigned int)value;
-}
-
-
-template <>
-bool
-parseParam(const string , float )
-{
-return to_number(s, value);
-}
-
-template <>
-bool
-parseParam(const string , double )
-{
-return to_number(s, value);
-}
-
-template <>
-bool
-parseParam(const string , bool )
-{
-return to_bool(s, value);
-}
-
-// Display bools as strings
-template <>
-void
-showParam(CheckpointOut , const bool )
-{
-os << (value ? "true" : "false");
-}
-
-
-// String requires no processing to speak of
-template <>
-bool
-parseParam(const string , string )
-{
-value = s;
-return true;
-}
-
 int Serializable::ckptMaxCount = 0;
 int Serializable::ckptCount = 0;
 int Serializable::ckptPrevCount = -1;
 std::stack Serializable::path;

-template 
-void
-paramOut(CheckpointOut , const string , const T )
-{
-os << name << "=";
-showParam(os, param);
-os << "\n";
-}
-
-template 
-void
-arrayParamOut(CheckpointOut , const string , const vector  
)

-{
-typename vector::size_type size = param.size();
-os << name << "=";
-if (size > 0)
-showParam(os, param[0]);
-for (typename vector::size_type i = 1; i < size; ++i) {
-os << " ";
-showParam(os, param[i]);
-}
-os << "\n";
-}
-
-template 
-void
-arrayParamOut(CheckpointOut , const string , const list )
-{
-typename list::const_iterator it = param.begin();
-
-os << name << "=";
-if (param.size() > 0)
-showParam(os, *it);
-it++;
-while (it != param.end()) {
-os << " ";
-showParam(os, *it);
-it++;
-}
-os << "\n";
-}
-
-template 
-void
-arrayParamOut(CheckpointOut , const string , const set )
-{
-typename set::const_iterator it = param.begin();
-
-os << name << "=";
-if (param.size() > 0)
-showParam(os, *it);
-it++;
-while (it != param.end()) {
-os << " ";
-showParam(os, *it);
-it++;
-}
-os << "\n";
-}
-
-template 
-void
-paramIn(CheckpointIn , const string , T )
-{
-const string (Serializable::currentSection());
-string str;
-if (!cp.find(section, name, str) || !parseParam(str, param)) {
-fatal("Can't unserialize '%s:%s'\n", section, name);
-}
-}
-
-template 
-bool
-optParamIn(CheckpointIn , const string , T , bool warn)
-{
-const string (Serializable::currentSection());
-string str;
-if (!cp.find(section, name, str) || !parseParam(str, param)) {
-if (warn)
-warn("optional parameter %s:%s not present\n", section, name);
-return false;
-} else {
-return true;
-

[gem5-dev] Cron /z/m5/regression/do-regression quick

2018-10-19 Thread Cron Daemon 
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
 FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
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* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED!
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
CHANGED!
* build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: 
CHANGED!
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: 
CHANGED!
* build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: 
CHANGED!
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED!
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED!
* 
build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic:
 CHANGED!
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
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* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
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* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
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* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
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* build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: 
CHANGED!
* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: 
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* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp:
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* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
 CHANGED!
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: 
CHANGED!
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp:
 CHANGED!
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
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* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp:
 CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: 
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* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: 
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* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: 
CHANGED!
* build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED!
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: 
CHANGED!
* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: 
CHANGED!
* 
build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple:
 CHANGED!* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: 
CHANGED!
* build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: