Re: [gem5-dev] Port configuration overhaul
My doc is updated with what my patches turned into, so PTAL if you have a chance. I think it turned out to be pretty straightforward which should make it an easier read. I took a look at Andrea's patch, and it has some pretty interesting ideas in there. One prominent difference I see is that I made the Port class my primitive, and he made MasterPort and SlavePort (or similar parent classes) his primitives. My version makes symmetrical port connections more natural which is important for Ethernet ports, something he may not have considered since I don't see mention of it in his description. One thing he does which I thought was particularly interesting is to make it so that a module can implement the Port interface itself. I do notice that there are a lot of classes (and I've implemented at least a few) where the Port class is basically just a thin wrapper which delegates calls from the peer to its parent SimObject/MemObject. It's appealing to remove a lot of that boilerplate when possible. Perhaps we can have a template DelegatingPort class which takes its parent's class as a parameter and then does all the delegating? That would avoid having that same pattern manually reimplemented over and over, like I think some of the templated versions of the Event class have done. One thing that it's a little concerning about his approach is that it inherits some of the fanciness and complexity of the TLM approach, and has a built in and likely unavoidable layer of indirection in a high traffic interface. One thing I've noticed in my pretty extensive expeditions diving into the guts of systemc is that there are some fundamental design decisions and implementation choices that seem fairly innocuous, but put a limit on how good performance can be. For instance they use std::vector a lot, and have to do weird tricks like swapping a middle element with the final element in the vector and then shortening it by one to avoid really bad performance when deleting an interior vector element. That works, but it basically stirs your vectors and can make behavior erratic (and can be very annoying to replicated to pass regression tests, *sigh*). Also they don't do as much as they could to avoid context switches by keeping all the "method" "processes" (systemc's version of those terms) bunched together. The point being that while system is prominent and doing things in a systemc-ish way can make it easier to learn and less confusing, blindly imitating it can be a recipe for trouble. Another difference I see (neither good nor bad) is that this seems to have a slightly different objective than what I'm going for. It looks like Andrea was trying to make gem5's protocol and port mechanism extensible to the point where it would include the TLM mechanisms as a subset, and then could either use them natively or connect gem5 and TLM models together under the same roof so to speak. What I'm trying to do is to leave gem5's protocol and ports mostly alone, and to make TLM's sockets, Ethernet interfaces, etc., all separate lobes of the Port mechanism which can be managed with common mechanisms but which are still all their own things with their own rules, etc. For instance, I don't really see any config related code in Andrea's patch. Note that these are not mutually exclusive either. We could, for instance, use my approach to rationalize how ports are configured and connected, and then also use Andrea's approach to modify gem5's protocol within the MasterPort/SlavePort lobe, and/or use it to bridge the MasterPort/SlavePort and TLM lobes. I would still worry a bit about the complexity, but if you're willing to live with that in the first place I don't think there would be any additional issues. From a practical perspective, moving Andrea's change forward 6-7 years would probably be a non-trivial porting effort, so my (somewhat biased, somewhat selfish) suggestion would be to go ahead with my approach and then look to porting his in whole or in part after that. Gabe On Thu, Mar 7, 2019 at 11:42 AM Steve Reinhardt wrote: > Thanks for digging this up, Jason. I knew this issue had been addressed > multiple times before (I think I even had a patch at one point that was a > smaller change, but held it off in favor of Andreas's version). I don't > know why Andreas's change was never committed either. > > Anyway, it will be good to see this cleaned up, regardless of whether we go > with Andreas's code or Gabe's proposal or some hybrid. I've been out of > the loop long enough that I don't have a specific preference. > > Steve > > > On Thu, Mar 7, 2019 at 10:19 AM Jason Lowe-Power > wrote: > > > Hey Gabe, > > > > I was digging through the old reviewboard and found this patch that also > > re-did this interface: http://reviews.gem5.org/r/1301 > > > > I'm not sure why this was never committed. > > > > I believe Andreas H's goal was to enable TLM-2 interfaces with the gem5, > > IIRC. > > > > Just something to consider. > > > > Cheers, > >
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Removed default arg from get() in prefetch/base.hh
Ryan Gambord has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17070 )
Change subject: mem-cache: Removed default arg from get() in
prefetch/base.hh
..
mem-cache: Removed default arg from get() in prefetch/base.hh
commit b0d1643 caused building against NULL to break due to
NULLIsa::GuestByteOrder not being defined.
Removal of default argument in src/mem/cache/prefetch/base.hh fixes
this.
Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0
Signed-off-by: Ryan Gambord
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17070
Reviewed-by: Daniel Carvalho
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
---
M src/mem/cache/prefetch/base.hh
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 05895f2..3ef607f 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -201,7 +201,7 @@
*/
template
inline T
-get(ByteOrder endian = TheISA::GuestByteOrder) const
+get(ByteOrder endian) const
{
if (data == nullptr) {
panic("PrefetchInfo::get called with a request with no
data.");
--
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Gerrit-Change-Number: 17070
Gerrit-PatchSet: 5
Gerrit-Owner: Ryan Gambord
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Javier Bueno Hedo
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Ryan Gambord
Gerrit-CC: Gabe Black
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-hsail: changed gen.py shebang from python(3) to python2.7
Ryan Gambord has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/17008 ) Change subject: arch-hsail: changed gen.py shebang from python(3) to python2.7 .. arch-hsail: changed gen.py shebang from python(3) to python2.7 gen.py includes code_formatter from m5.util. code_formatter uses the python2 __metaclass__ attribute, which is ignored by python3, causing the code_formatter.pattern attribute to be unset. This prevented scons from building against HSAIL_X86 Signed-off-by: Ryan Gambord Change-Id: I5a8bf9e730fd629eb7f9a7ac2dce928235a0dae4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17008 Reviewed-by: Andrea Mondelli Reviewed-by: Anthony Gutierrez Maintainer: Anthony Gutierrez --- M src/arch/hsail/gen.py 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved Andrea Mondelli: Looks good to me, but someone else must approve diff --git a/src/arch/hsail/gen.py b/src/arch/hsail/gen.py index 23ce02e..8dcc92c 100755 --- a/src/arch/hsail/gen.py +++ b/src/arch/hsail/gen.py @@ -1,6 +1,4 @@ -#! /usr/bin/python - -# +#!/usr/bin/env python2.7 # Copyright (c) 2015 Advanced Micro Devices, Inc. # All rights reserved. # -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17008 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5a8bf9e730fd629eb7f9a7ac2dce928235a0dae4 Gerrit-Change-Number: 17008 Gerrit-PatchSet: 3 Gerrit-Owner: Ryan Gambord Gerrit-Reviewer: Andrea Mondelli Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Ryan Gambord Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Syscall_Emulation for Shared Memory
Hi Maryam, The code that you are looking at is going to change soon. There is a changeset on the google reviewboard which will add some fidelity to the tracing of mmap/munmaps from the perspective of SE mode (https://gem5-review.googlesource.com/c/public/gem5/+/12307). Feel free to review it if it's interesting to you. 1) I don't understand what you are asking. 2) The new patch has an implementation. 3) We could probably add an implementation that flushes file-backed mmaps to the host file. I have never run into a situation where this was needed in an application that was being simulated (so it doesn't have an implementation). 4) It turns out that fork is not used in Linux to create a new process. It uses the clone system call instead. (You can verify this by using the Linux strace command with your application. You should only see a clone call.) You should take a look at the clone implementation. Regards, Brandon -Original Message- From: gem5-dev On Behalf Of Maryam Babaie Sent: Friday, March 8, 2019 4:06 PM To: m5-...@m5sim.org Subject: [gem5-dev] Syscall_Emulation for Shared Memory Hi all, I have some questions regarding the system calls available in SE mode on gem5 for X86. I appreciate if any one shares their insight about them: 1. For the mmap syscall, the function "mmapImpl" has been implemented. Up-to which extend this function will work properly for mmap syscall? 2. For munmap syscall, they have put the munmapFunc, but the body of the corresponding function is actually empty. So, does this mean it is actually not supported on gem5? 3. msync syscall is flagged as unimplementedFunc. So, does this mean that mmap will still work but the writes will not be reflected persistently in the region? 4. Since the fork syscall is also flagged as unimplementedFunc , how is the concept of Copy on Write (generally shared pages) able to be simulated and handled in gem5? Regards ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: add new option to getrlimit syscall
Brandon Potter has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17109
Change subject: sim-se: add new option to getrlimit syscall
..
sim-se: add new option to getrlimit syscall
The NPROC option was not serviced by the getrlimit syscall.
This changeset adds in the necessary code to service the option.
Change-Id: I679d3949c3bbb0628188f4e33034028d7726fdcb
---
M src/sim/syscall_emul.hh
1 file changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index d59fa72..1d4f399 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1959,6 +1959,12 @@
rlp->rlim_max = TheISA::htog(rlp->rlim_max);
break;
+ case OS::TGT_RLIMIT_NPROC:
+rlp->rlim_cur = rlp->rlim_max = tc->getSystemPtr()->numContexts();
+rlp->rlim_cur = TheISA::htog(rlp->rlim_cur);
+rlp->rlim_max = TheISA::htog(rlp->rlim_max);
+break;
+
default:
warn("getrlimit: unimplemented resource %d", resource);
return -EINVAL;
--
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[gem5-dev] Change in gem5/gem5[master]: sim-se: remove mem proxy in ThreadContext
Brandon Potter has uploaded a new patch set (#11). ( https://gem5-review.googlesource.com/c/public/gem5/+/12305 ) Change subject: sim-se: remove mem proxy in ThreadContext .. sim-se: remove mem proxy in ThreadContext Many parts of the source code use a memory proxy reference to access the simulated memory space in Syscall Emulation Mode. However, it would be nice if all memory responsibilities were delegated to a single object rather than spread across many objects. This patch helps to consolidate the memory responsibilities inside the MemState class by removing the ThreadContext's memory proxy. Change-Id: Ic1a6c3017c412a24db91770396d0a9bde790421d --- M src/arch/alpha/faults.cc M src/arch/alpha/linux/process.cc M src/arch/alpha/process.cc M src/arch/alpha/process.hh M src/arch/arm/freebsd/process.cc M src/arch/arm/linux/process.cc M src/arch/arm/process.cc M src/arch/arm/remote_gdb.cc M src/arch/arm/tlb.cc M src/arch/generic/tlb.cc M src/arch/mips/linux/process.cc M src/arch/mips/process.cc M src/arch/mips/remote_gdb.cc M src/arch/mips/tlb.cc M src/arch/power/linux/process.cc M src/arch/power/process.cc M src/arch/power/remote_gdb.cc M src/arch/power/tlb.cc M src/arch/riscv/linux/process.cc M src/arch/riscv/process.cc M src/arch/riscv/process.hh M src/arch/riscv/remote_gdb.cc M src/arch/riscv/tlb.cc M src/arch/sparc/faults.cc M src/arch/sparc/linux/syscalls.cc M src/arch/sparc/process.cc M src/arch/sparc/process.hh M src/arch/sparc/remote_gdb.cc M src/arch/sparc/solaris/process.cc M src/arch/x86/linux/process.cc M src/arch/x86/process.cc M src/arch/x86/process.hh M src/arch/x86/pseudo_inst.cc M src/arch/x86/remote_gdb.cc M src/arch/x86/tlb.cc M src/base/remote_gdb.cc M src/cpu/checker/thread_context.hh M src/cpu/o3/thread_context.hh M src/cpu/thread_context.hh M src/cpu/thread_state.cc M src/cpu/thread_state.hh M src/gpu-compute/cl_driver.cc M src/gpu-compute/compute_unit.cc M src/gpu-compute/gpu_tlb.cc M src/gpu-compute/shader.cc M src/mem/se_translating_port_proxy.cc M src/mem/se_translating_port_proxy.hh M src/sim/SConscript M src/sim/faults.cc A src/sim/mem_state.cc M src/sim/mem_state.hh R src/sim/mem_state_impl.hh M src/sim/process.cc M src/sim/process.hh M src/sim/syscall_emul.cc M src/sim/syscall_emul.hh 56 files changed, 1,292 insertions(+), 644 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12305 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic1a6c3017c412a24db91770396d0a9bde790421d Gerrit-Change-Number: 12305 Gerrit-PatchSet: 11 Gerrit-Owner: Brandon Potter Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: add a faux-filesystem
Brandon Potter has uploaded a new patch set (#12). ( https://gem5-review.googlesource.com/c/public/gem5/+/12119 ) Change subject: sim-se: add a faux-filesystem .. sim-se: add a faux-filesystem This change introduces the concept of a faux-filesystem. The faux-filesystem creates a directory structure in m5out (or whatever output dir the user specifies) where system calls may be redirected. This is useful to avoid non-determinism when reading files with varying path names (e.g., variations from run-to-run if the simulation is scheduled on a cluster where paths may change). Also, this changeset allows circumventing host pseudofiles which have information specific to the host processor (such as cache hierarchy or processor information). Bypassing host pseudofiles can be useful when executing runtimes in the absence of an operating system kernel since runtimes may try to query standard files (i.e. /proc or /sys) which are not relevant to an application executing in syscall emulation mode. Change-Id: I90821b3b403168b904a662fa98b85def1628621c --- A configs/common/FileSystemConfig.py M configs/common/Options.py M configs/example/se.py M src/kern/linux/linux.cc M src/sim/Process.py A src/sim/RedirectPath.py M src/sim/SConscript M src/sim/System.py M src/sim/process.cc M src/sim/process.hh A src/sim/redirect_path.cc A src/sim/redirect_path.hh M src/sim/syscall_emul.cc M src/sim/syscall_emul.hh M src/sim/system.cc M src/sim/system.hh 16 files changed, 619 insertions(+), 99 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12119 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I90821b3b403168b904a662fa98b85def1628621c Gerrit-Change-Number: 12119 Gerrit-PatchSet: 12 Gerrit-Owner: Brandon Potter Gerrit-Reviewer: Brandon Potter Gerrit-CC: Andreas Sandberg Gerrit-CC: Giacomo Travaglini Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: sim-se: add new getpgrp system call
Brandon Potter has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17111
Change subject: sim-se: add new getpgrp system call
..
sim-se: add new getpgrp system call
This changeset adds new (relatively simple) system call
support. The getpgrp call returns a thread context's
pgid.
Change-Id: I361bdbfb9c01b761ddd5a4923d23f86971f8d614
---
M src/arch/x86/linux/process.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc
index f92575f..ab57b78 100644
--- a/src/arch/x86/linux/process.cc
+++ b/src/arch/x86/linux/process.cc
@@ -344,7 +344,7 @@
/* 108 */ SyscallDesc("getegid", getegidFunc),
/* 109 */ SyscallDesc("setpgid", setpgidFunc),
/* 110 */ SyscallDesc("getppid", getppidFunc),
-/* 111 */ SyscallDesc("getpgrp", unimplementedFunc),
+/* 111 */ SyscallDesc("getpgrp", getpgrpFunc),
/* 112 */ SyscallDesc("setsid", unimplementedFunc),
/* 113 */ SyscallDesc("setreuid", unimplementedFunc),
/* 114 */ SyscallDesc("setregid", unimplementedFunc),
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index 17ce9b7..b3f675c 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -971,6 +971,13 @@
}
SyscallReturn
+getpgrpFunc(SyscallDesc *desc, int callnum, ThreadContext *tc)
+{
+auto process = tc->getProcessPtr();
+return process->pgid();
+}
+
+SyscallReturn
setpgidFunc(SyscallDesc *desc, int callnum, ThreadContext *tc)
{
int index = 0;
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 0abd814..8dd049d 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -245,6 +245,9 @@
/// Target chown() handler.
SyscallReturn chownFunc(SyscallDesc *desc, int num, ThreadContext *tc);
+/// Target getpgrpFunc() handler.
+SyscallReturn getpgrpFunc(SyscallDesc *desc, int num, ThreadContext *tc);
+
/// Target setpgid() handler.
SyscallReturn setpgidFunc(SyscallDesc *desc, int num, ThreadContext *tc);
--
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[gem5-dev] Change in gem5/gem5[master]: sim-se: small performance optimization
Brandon Potter has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17108
Change subject: sim-se: small performance optimization
..
sim-se: small performance optimization
A local variable was being set inside a loop when it should
have been set outside the loop. This changeset moves the
variable to the appropriate place.
Change-Id: If7655b501bd819c39d35dea4c316b4b9ed3173a2
---
M src/sim/process.cc
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 7d1a78d..961913d 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -202,8 +202,8 @@
* host file descriptors are also dup'd so that the flags for the
* host file descriptor is independent of the other process.
*/
+std::shared_ptr nfds = np->fds;
for (int tgt_fd = 0; tgt_fd < fds->getSize(); tgt_fd++) {
-std::shared_ptr nfds = np->fds;
std::shared_ptr this_fde = (*fds)[tgt_fd];
if (!this_fde) {
nfds->setFDEntry(tgt_fd, nullptr);
--
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[gem5-dev] Change in gem5/gem5[master]: sim-se, tests: add a new sim-se test
Brandon Potter has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17112
Change subject: sim-se, tests: add a new sim-se test
..
sim-se, tests: add a new sim-se test
This changeset adds a test to check the redirection features
added in faux-filesystem changeset. The test contains a
"chdir" system call to "/proc" which should be redirected to
"$(gem5-dir)/m5out/fs/proc" (as specified by the config files).
After "chdir", the test subsequently outputs the "/proc/cpuinfo"
file which should output a configuration of a fake cpu with
values set by a Python configuration file.
Note, the test will call "clone" once. To avoid a runtime error,
make sure that you run this test with "-n2" supplied to the
"config/example/se.py" script.
Change-Id: I505b046b7a4feddfa93a6ef0f0773ac43078cc94
---
A tests/test-progs/chdir-print/Makefile
A tests/test-progs/chdir-print/chdir-print.c
2 files changed, 50 insertions(+), 0 deletions(-)
diff --git a/tests/test-progs/chdir-print/Makefile
b/tests/test-progs/chdir-print/Makefile
new file mode 100644
index 000..6a357d5
--- /dev/null
+++ b/tests/test-progs/chdir-print/Makefile
@@ -0,0 +1,20 @@
+
+CPP := g++
+
+TEST_OBJS := chdir-print.o
+TEST_PROGS := $(TEST_OBJS:.o=)
+
+# Rules
==
+
+.PHONY: default clean
+
+default: $(TEST_PROGS)
+
+clean:
+ $(RM) $(TEST_OBJS) $(TEST_PROGS)
+
+$(TEST_PROGS): $(TEST_OBJS)
+ $(CPP) -static -o $@ $@.o
+
+%.o: %.c Makefile
+ $(CPP) -c -o $@ $*.c -msse3
diff --git a/tests/test-progs/chdir-print/chdir-print.c
b/tests/test-progs/chdir-print/chdir-print.c
new file mode 100644
index 000..0cf56f9
--- /dev/null
+++ b/tests/test-progs/chdir-print/chdir-print.c
@@ -0,0 +1,30 @@
+#include
+#include
+#include
+#include
+
+const int BUFFER_SIZE = 64;
+
+int main(void)
+{
+char *cwd = getcwd(NULL, PATH_MAX);
+printf("cwd: %s\n", cwd);
+free(cwd);
+
+chdir("/proc");
+
+cwd = getcwd(NULL, PATH_MAX);
+printf("cwd: %s\n", cwd);
+free(cwd);
+
+FILE *fp;
+char buffer[BUFFER_SIZE];
+fp = popen("cat cpuinfo", "r");
+if (fp != NULL) {
+while (fgets(buffer, BUFFER_SIZE, fp) != NULL)
+printf("%s", buffer);
+pclose(fp);
+}
+
+return 0;
+}
--
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[gem5-dev] Change in gem5/gem5[master]: sim-se: fstat64 bugfix
Brandon Potter has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/17110 Change subject: sim-se: fstat64 bugfix .. sim-se: fstat64 bugfix The fstat64 system call does an upcast on entries in the file descriptor array to check if the file descriptor has a backing host-filesystem file opened. It does so because it needs to pass the host fd into the fstat call (since we rely on the host filesystem to service filesystem system calls). The upcast was overly specific. This changeset alters the system call to use the most general base class of the file descriptor entries that can satisfy the code. Change-Id: I10daf820257cea4d678ee6917e01e9cc9cd1cf5e --- M src/sim/syscall_emul.hh 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh index 1d4f399..0abd814 100644 --- a/src/sim/syscall_emul.hh +++ b/src/sim/syscall_emul.hh @@ -1367,7 +1367,7 @@ int tgt_fd = p->getSyscallArg(tc, index); Addr bufPtr = p->getSyscallArg(tc, index); -auto ffdp = std::dynamic_pointer_cast((*p->fds)[tgt_fd]); +auto ffdp = std::dynamic_pointer_cast((*p->fds)[tgt_fd]); if (!ffdp) return -EBADF; int sim_fd = ffdp->getSimFD(); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17110 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I10daf820257cea4d678ee6917e01e9cc9cd1cf5e Gerrit-Change-Number: 17110 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Potter Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: configs: faux-filesystem fix w/ classic se mode
Brandon Potter has uploaded a new patch set (#12). ( https://gem5-review.googlesource.com/c/public/gem5/+/12120 ) Change subject: configs: faux-filesystem fix w/ classic se mode .. configs: faux-filesystem fix w/ classic se mode These changes are needed so that the config scripts can report cache hierarchy information to the faux filesystem. This is useful for the ROCm runtime when it reads psuedofiles from the host filesystem from "/proc". Change-Id: I51af4d41c49dcf719a4a540346fe3e17b2eb95f7 --- M configs/common/CacheConfig.py M configs/example/se.py 2 files changed, 37 insertions(+), 3 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12120 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I51af4d41c49dcf719a4a540346fe3e17b2eb95f7 Gerrit-Change-Number: 12120 Gerrit-PatchSet: 12 Gerrit-Owner: Brandon Potter Gerrit-CC: Giacomo Travaglini Gerrit-CC: Jason Lowe-Power Gerrit-CC: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fixing implicit fallthrough build errors
Ryan Gambord has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17071 )
Change subject: arch-arm: Fixing implicit fallthrough build errors
..
arch-arm: Fixing implicit fallthrough build errors
2c242d6 introduced implicit-fallthrough errors when building against
ARM.
Added "default: return new Unknown(machInst);" to offending switch
statements; please verify this is the corret behavior
Signed-off-by: Ryan Gambord
Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17071
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
---
M src/arch/arm/isa/formats/fp.isa
1 file changed, 5 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/isa/formats/fp.isa
b/src/arch/arm/isa/formats/fp.isa
index c159dc6..cb806f6 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -2101,6 +2101,7 @@
} else {
return new VcvtaFpUIntD(machInst, vdInt,
vm);
}
+ default: return new Unknown(machInst);
}
case 0x1:
switch(size) {
@@ -2121,6 +2122,7 @@
} else {
return new VcvtnFpUIntD(machInst, vdInt,
vm);
}
+ default: return new Unknown(machInst);
}
case 0x2:
switch(size) {
@@ -2141,6 +2143,7 @@
} else {
return new VcvtpFpUIntD(machInst, vdInt,
vm);
}
+ default: return new Unknown(machInst);
}
case 0x3:
switch(size) {
@@ -2161,7 +2164,9 @@
} else {
return new VcvtmFpUIntD(machInst, vdInt,
vm);
}
+ default: return new Unknown(machInst);
}
+ default: return new Unknown(machInst);
}
}
} else if (b31_b24 && !b23 && b11_b9 && !op3 && b4){
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959
Gerrit-Change-Number: 17071
Gerrit-PatchSet: 6
Gerrit-Owner: Ryan Gambord
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Ryan Gambord
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-hsail: changed gen.py shebang from python(3) to python2.7
Hello Anthony Gutierrez, Andrea Mondelli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17008 to look at the new patch set (#2). Change subject: arch-hsail: changed gen.py shebang from python(3) to python2.7 .. arch-hsail: changed gen.py shebang from python(3) to python2.7 gen.py includes code_formatter from m5.util. code_formatter uses the python2 __metaclass__ attribute, which is ignored by python3, causing the code_formatter.pattern attribute to be unset. This prevented scons from building against HSAIL_X86 Signed-off-by: Ryan Gambord Change-Id: I5a8bf9e730fd629eb7f9a7ac2dce928235a0dae4 --- M src/arch/hsail/gen.py 1 file changed, 1 insertion(+), 3 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17008 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5a8bf9e730fd629eb7f9a7ac2dce928235a0dae4 Gerrit-Change-Number: 17008 Gerrit-PatchSet: 2 Gerrit-Owner: Ryan Gambord Gerrit-Reviewer: Andrea Mondelli Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Ryan Gambord Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Removed default arg from get() in prefetch/base.hh
Hello Nikos Nikoleris, Javier Bueno Hedo, Daniel Carvalho, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17070 to look at the new patch set (#4). Change subject: mem-cache: Removed default arg from get() in prefetch/base.hh .. mem-cache: Removed default arg from get() in prefetch/base.hh commit b0d1643 caused building against NULL to break due to NULLIsa::GuestByteOrder not being defined. Removal of default argument in src/mem/cache/prefetch/base.hh fixes this. Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0 Signed-off-by: Ryan Gambord --- M src/mem/cache/prefetch/base.hh 1 file changed, 1 insertion(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17070 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0 Gerrit-Change-Number: 17070 Gerrit-PatchSet: 4 Gerrit-Owner: Ryan Gambord Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Ryan Gambord Gerrit-CC: Gabe Black Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fixing implicit fallthrough build errors
Hello Giacomo Travaglini, Andreas Sandberg, Ciro Santilli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17071 to look at the new patch set (#5). Change subject: arch-arm: Fixing implicit fallthrough build errors .. arch-arm: Fixing implicit fallthrough build errors 2c242d6 introduced implicit-fallthrough errors when building against ARM. Added "default: return new Unknown(machInst);" to offending switch statements; please verify this is the corret behavior Signed-off-by: Ryan Gambord Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959 --- M src/arch/arm/isa/formats/fp.isa 1 file changed, 5 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17071 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959 Gerrit-Change-Number: 17071 Gerrit-PatchSet: 5 Gerrit-Owner: Ryan Gambord Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Ryan Gambord Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fixing implicit fallthrough build errors
Hello Giacomo Travaglini, Andreas Sandberg, Ciro Santilli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17071 to look at the new patch set (#4). Change subject: arch-arm: Fixing implicit fallthrough build errors .. arch-arm: Fixing implicit fallthrough build errors 2c242d6 introduced implicit-fallthrough errors when building against ARM. Added "default: return new Unknown(machInst);" to offending switch statements; please verify this is the corret behavior Signed-off-by: Ryan Gambord Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959 --- M src/arch/arm/isa/formats/fp.isa 1 file changed, 5 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17071 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959 Gerrit-Change-Number: 17071 Gerrit-PatchSet: 4 Gerrit-Owner: Ryan Gambord Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Ryan Gambord Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fixed initialization array size
Giacomo Travaglini has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/17088 ) Change subject: arch-arm: Fixed initialization array size .. arch-arm: Fixed initialization array size Doubled the size of the zeroed auxiliary vector since 2 * intSize on aarch64 > sizeof(uint64). Change-Id: I5196b000a696e9ea3f2b5daa5d5bb071794369aa --- M src/arch/arm/process.cc 1 file changed, 3 insertions(+), 3 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17088 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5196b000a696e9ea3f2b5daa5d5bb071794369aa Gerrit-Change-Number: 17088 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fixed initialization array size
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17088
Change subject: arch-arm: Fixed initialization array size
..
arch-arm: Fixed initialization array size
Doubled the size of the zeroed auxiliary vector since 2 * intSize on
aarch64 > sizeof(uint64).
Change-Id: I5196b000a696e9ea3f2b5daa5d5bb071794369aa
---
M src/arch/arm/process.cc
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 553bac5..0ddb5ff 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2012, 2018 ARM Limited
+ * Copyright (c) 2010, 2012, 2018, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -440,10 +440,10 @@
(uint8_t*)&(auxv[x].getAuxVal()),
intSize);
}
-//Write out the terminating zeroed auxilliary vector
-const uint64_t zero = 0;
+//Write out the terminating zeroed auxillary vector
+const IntType zero[2] = {0, 0};
initVirtMem.writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
-(uint8_t*), 2 * intSize);
+(uint8_t*)zero, 2 * intSize);
copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5196b000a696e9ea3f2b5daa5d5bb071794369aa
Gerrit-Change-Number: 17088
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Removed default argument from get() in
Hello Nikos Nikoleris, Javier Bueno Hedo, Daniel Carvalho, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17070 to look at the new patch set (#3). Change subject: mem-cache: Removed default argument from get() in .. mem-cache: Removed default argument from get() in commit b0d1643 caused building against NULL to break due to NULLIsa::GuestByteOrder not being defined. Removal of default argument in src/mem/cache/prefetch/base.hh fixes this. Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0 Signed-off-by: Ryan Gambord --- M src/mem/cache/prefetch/base.hh 1 file changed, 1 insertion(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17070 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0 Gerrit-Change-Number: 17070 Gerrit-PatchSet: 3 Gerrit-Owner: Ryan Gambord Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Ryan Gambord Gerrit-CC: Gabe Black Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fixing implicit fallthrough build errors
Hello Giacomo Travaglini, Andreas Sandberg, Ciro Santilli, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17071 to look at the new patch set (#3). Change subject: arch-arm: Fixing implicit fallthrough build errors .. arch-arm: Fixing implicit fallthrough build errors 2c242d6 introduced implicit-fallthrough errors when building against ARM. Added "default: return new Unknown(machInst);" to offending switch statements; please verify this is the corret behavior Signed-off-by: Ryan Gambord Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959 --- M src/arch/arm/isa/formats/fp.isa 1 file changed, 5 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17071 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959 Gerrit-Change-Number: 17071 Gerrit-PatchSet: 3 Gerrit-Owner: Ryan Gambord Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Ryan Gambord Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Revert "mem-cache: Remove Packet dependency in Tags"
Daniel Carvalho has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17049 )
Change subject: mem-cache: Revert "mem-cache: Remove Packet dependency in
Tags"
..
mem-cache: Revert "mem-cache: Remove Packet dependency in Tags"
Reverting patch due to polymorphism limitations.
This reverts commit 86a54d91936b524c0ef0f282959f0fc29bafe7eb.
Change-Id: Ie032dcc5176448c62118c89732b3cc6b8efd5a13
Signed-off-by: Daniel R. Carvalho
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17049
Reviewed-by: Giacomo Travaglini
Reviewed-by: Jason Lowe-Power
Reviewed-by: Nikos Nikoleris
Maintainer: Nikos Nikoleris
---
M src/mem/cache/base.cc
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/tags/sector_tags.cc
M src/mem/cache/tags/sector_tags.hh
8 files changed, 25 insertions(+), 46 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Giacomo Travaglini: Looks good to me, but someone else must approve
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index a42f2eb..9f708b3 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1359,8 +1359,7 @@
}
// Insert new block at victimized entry
-tags->insertBlock(addr, is_secure, pkt->req->masterId(),
- pkt->req->taskId(), victim);
+tags->insertBlock(pkt, victim);
return victim;
}
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index 7237f18..4855ebd 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -98,20 +98,21 @@
}
void
-BaseTags::insertBlock(const Addr addr, const bool is_secure,
- const int src_master_ID, const uint32_t task_ID,
- CacheBlk *blk)
+BaseTags::insertBlock(const PacketPtr pkt, CacheBlk *blk)
{
assert(!blk->isValid());
// Previous block, if existed, has been removed, and now we have
// to insert the new one
+
// Deal with what we are bringing in
-assert(src_master_ID < system->maxMasters());
-occupancies[src_master_ID]++;
+MasterID master_id = pkt->req->masterId();
+assert(master_id < system->maxMasters());
+occupancies[master_id]++;
// Insert block with tag, src master id and task id
-blk->insert(extractTag(addr), is_secure, src_master_ID, task_ID);
+blk->insert(extractTag(pkt->getAddr()), pkt->isSecure(), master_id,
+pkt->req->taskId());
// Check if cache warm up is done
if (!warmedUp && tagsInUse.value() >= warmupBound) {
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 840193b..296837e 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -58,6 +58,7 @@
#include "base/statistics.hh"
#include "base/types.hh"
#include "mem/cache/cache_blk.hh"
+#include "mem/packet.hh"
#include "params/BaseTags.hh"
#include "sim/clocked_object.hh"
@@ -305,15 +306,10 @@
/**
* Insert the new block into the cache and update stats.
*
- * @param addr Address of the block.
- * @param is_secure Whether the block is in secure space or not.
- * @param src_master_ID The source requestor ID.
- * @param task_ID The new task ID.
+ * @param pkt Packet holding the address to update
* @param blk The block to update.
*/
-virtual void insertBlock(const Addr addr, const bool is_secure,
- const int src_master_ID, const uint32_t
task_ID,
- CacheBlk *blk);
+virtual void insertBlock(const PacketPtr pkt, CacheBlk *blk);
/**
* Regenerate the block address.
diff --git a/src/mem/cache/tags/base_set_assoc.hh
b/src/mem/cache/tags/base_set_assoc.hh
index b1fa884..c39a813 100644
--- a/src/mem/cache/tags/base_set_assoc.hh
+++ b/src/mem/cache/tags/base_set_assoc.hh
@@ -60,6 +60,7 @@
#include "mem/cache/replacement_policies/replaceable_entry.hh"
#include "mem/cache/tags/base.hh"
#include "mem/cache/tags/indexing_policies/base.hh"
+#include "mem/packet.hh"
#include "params/BaseSetAssoc.hh"
/**
@@ -182,18 +183,13 @@
/**
* Insert the new block into the cache and update replacement data.
*
- * @param addr Address of the block.
- * @param is_secure Whether the block is in secure space or not.
- * @param src_master_ID The source requestor ID.
- * @param task_ID The new task ID.
+ * @param pkt Packet holding the address to update
* @param blk The block to update.
*/
-void insertBlock(const Addr addr, const bool is_secure,
- const int src_master_ID, const uint32_t task_ID,
- CacheBlk *blk) override
+void insertBlock(const PacketPtr pkt, CacheBlk
[gem5-dev] Change in gem5/gem5[master]: arch, base: Added NullByteOrder to enum ByteOrder
Hello Nikos Nikoleris, Javier Bueno Hedo, Daniel Carvalho, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/17070 to look at the new patch set (#2). Change subject: arch, base: Added NullByteOrder to enum ByteOrder .. arch, base: Added NullByteOrder to enum ByteOrder commit b0d1643 caused building against NULL to break due to NULLIsa::GuestByteOrder not being defined. Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0 Signed-off-by: Ryan Gambord --- M src/arch/null/isa_traits.hh M src/base/types.hh M src/mem/cache/prefetch/base.hh M src/sim/byteswap.hh 4 files changed, 23 insertions(+), 11 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17070 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I99a4abb4be1418fadec145481164f7caa3334ca0 Gerrit-Change-Number: 17070 Gerrit-PatchSet: 2 Gerrit-Owner: Ryan Gambord Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Javier Bueno Hedo Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Ryan Gambord Gerrit-CC: Gabe Black Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
