Re: [gem5-dev] Alpha regression tests failing

2019-04-30 Thread Gabe Black 
This looks very suspicious, just looking at CL subject lines:

149c1fc2d configs: Remove default kernel value from system creation



On Tue, Apr 30, 2019 at 3:50 PM Gabe Black  wrote:

> To bound finding the point things broke, it looks like this change
> works/doesn't crash:
>
> 2a28a4f8d2ac1471ef3ba943fa5f52a2331759bf
>
> and this one doesn't work/does crash:
>
> b2efb725921c9387852f439ad20964c428072dd7
>
> which leaves about 45 CLs to look through.
>
> On Tue, Apr 30, 2019 at 3:39 PM Gabe Black  wrote:
>
>> Oh, also, the reason the kernel symbol table is empty is because the
>> "kernel" parameter is showing up as "" in the create() function (at least,
>> maybe earlier) for LinuxAlphaSystemParams, even though it's clearly not ""
>> in the m5out/config.ini file. I don't know why there's that mismatch.
>>
>> Gabe
>>
>> On Tue, Apr 30, 2019 at 3:37 PM Gabe Black  wrote:
>>
>>> Hey folks, I just noticed that the Alpha regression tests are failing,
>>> and it seems to be because the kernel symbol table is empty for some
>>> reason. I don't have a lot of time today, but I'll try to find where they
>>> stopped working. If you're bored, please feel free to dive in and help
>>> figure out what's going on. This may affect more than just Alpha.
>>>
>>> Gabe
>>>
>>
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Re: [gem5-dev] Alpha regression tests failing

2019-04-30 Thread Gabe Black 
Oh, also, the reason the kernel symbol table is empty is because the
"kernel" parameter is showing up as "" in the create() function (at least,
maybe earlier) for LinuxAlphaSystemParams, even though it's clearly not ""
in the m5out/config.ini file. I don't know why there's that mismatch.

Gabe

On Tue, Apr 30, 2019 at 3:37 PM Gabe Black  wrote:

> Hey folks, I just noticed that the Alpha regression tests are failing, and
> it seems to be because the kernel symbol table is empty for some reason. I
> don't have a lot of time today, but I'll try to find where they stopped
> working. If you're bored, please feel free to dive in and help figure out
> what's going on. This may affect more than just Alpha.
>
> Gabe
>
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[gem5-dev] Alpha regression tests failing

2019-04-30 Thread Gabe Black 
Hey folks, I just noticed that the Alpha regression tests are failing, and
it seems to be because the kernel symbol table is empty for some reason. I
don't have a lot of time today, but I'll try to find where they stopped
working. If you're bored, please feel free to dive in and help figure out
what's going on. This may affect more than just Alpha.

Gabe
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Re: [gem5-dev] gerrit pickiness interacting with kokoro

2019-04-30 Thread Gabe Black 
Ok, I'll consider that a +2. If someone decides to have an opinion later on
we can change it back :-).

Gabe

On Tue, Apr 30, 2019 at 11:50 AM Gutierrez, Anthony <
anthony.gutier...@amd.com> wrote:

> I am fine with this.
>
> Tony
>
> -Original Message-
> From: gem5-dev  On Behalf Of Gabe Black
> Sent: Monday, April 29, 2019 7:39 PM
> To: gem5 Developer List 
> Cc: Rahul Thakur 
> Subject: Re: [gem5-dev] gerrit pickiness interacting with kokoro
>
> [CAUTION: External Email]
>
> Hello again. I asked the gurus, and they say we probably want to set
> content merging to true. Any objections? I'd like to flip that switch
> before I go on my trip, so by the end of the week.
>
> Gabe
>
> On Sat, Apr 27, 2019 at 5:09 PM Gabe Black  wrote:
>
> > Hi folks. It's historically been an issue with gerrit as we have it
> > set up for use in gem5 that it seems to be pretty picky about when a
> > change can be submitted, and I've had to fairly often (but not always)
> > perform a trivial rebase through the gerrit UI so that it's happy and
> > will let me submit a CL. In the past this has been annoying, but not a
> > big deal since it just takes a few clicks to placate gerrit.
> >
> > Now that we have kokoro running and verifying CLs (which is a very
> > good thing), rebases have the unfortunate side effect of clearing the
> > verified bit which necessitates running the CI again on essentially
> > the same CL, including a several hour wait. So far this has been a
> > bigger annoyance than before with the added latency getting a CL
> > submitted, but since there haven't (yet) been any series with a lot of
> > those delays stack on top of each other it hasn't been a huge problem.
> >
> > What I'd like to know is what people think about making gerrit less
> > picky (not sure how that translates to settings TBH) so that these
> > trivial rebases aren't as necessary. Looking at the settings, I see
> > that the "Submit type" is "Rebase Always" and the "Allow content
> > merges" setting is false. There are other settings, but these seem like
> the most relevant ones.
> >
> > This page takes a bit about the philosophy behind the submit type
> setting:
> >
> >
> > https://gerrit-review.googlesource.com/Documentation/intro-project-own
> > er.html
> >
> > With a more complete description of all the submit types over here:
> >
> >
> > https://gerrit-review.googlesource.com/Documentation/config-project-co
> > nfig.html#submit-type
> >
> > If people agree that this is something we should try to change, we can
> > probably ask the gerrit gurus here at Google what settings we can
> > adjust to get the desired effect.
> >
> > Gabe
> >
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[gem5-dev] Change in gem5/gem5[master]: sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.

2019-04-30 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18469 )


Change subject: sparc: Move the interrupt types out of isa_traits.hh into  
interrupts.hh.

..

sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.

Those types aren't generic or used outside of SPARC.

Change-Id: I9bb154920a9625f12388c3d295dc933ab51fadde
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18469
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/tlb.cc
M src/arch/sparc/ua2005.cc
M src/dev/sparc/iob.cc
5 files changed, 15 insertions(+), 12 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
index e6c9266..abc899e 100644
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/sparc/interrupts.hh
@@ -43,6 +43,18 @@
 namespace SparcISA
 {

+enum InterruptTypes
+{
+IT_TRAP_LEVEL_ZERO,
+IT_HINTP,
+IT_INT_VEC,
+IT_CPU_MONDO,
+IT_DEV_MONDO,
+IT_RES_ERROR,
+IT_SOFT_INT,
+NumInterruptTypes
+};
+
 class Interrupts : public SimObject
 {
   private:
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 58d8437..5bcfc04 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -61,18 +61,6 @@
 const Addr PAddrImplMask = ULL(0x00FF);
 const Addr BytesInPageMask = ULL(0x1FFF);

-enum InterruptTypes
-{
-IT_TRAP_LEVEL_ZERO,
-IT_HINTP,
-IT_INT_VEC,
-IT_CPU_MONDO,
-IT_DEV_MONDO,
-IT_RES_ERROR,
-IT_SOFT_INT,
-NumInterruptTypes
-};
-
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index b2078dd..8564c43 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -34,6 +34,7 @@

 #include "arch/sparc/asi.hh"
 #include "arch/sparc/faults.hh"
+#include "arch/sparc/interrupts.hh"
 #include "arch/sparc/registers.hh"
 #include "base/bitfield.hh"
 #include "base/compiler.hh"
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 4cafff4..389549b 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

+#include "arch/sparc/interrupts.hh"
 #include "arch/sparc/isa.hh"
 #include "arch/sparc/kernel_stats.hh"
 #include "arch/sparc/registers.hh"
diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc
index f146536..1df6dec 100644
--- a/src/dev/sparc/iob.cc
+++ b/src/dev/sparc/iob.cc
@@ -40,6 +40,7 @@
 #include 

 #include "arch/sparc/faults.hh"
+#include "arch/sparc/interrupts.hh"
 #include "arch/sparc/isa_traits.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9bb154920a9625f12388c3d295dc933ab51fadde
Gerrit-Change-Number: 18469
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: sparc: Move translation constants from isa_traits.hh into tlb.hh.

2019-04-30 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18470 )


Change subject: sparc: Move translation constants from isa_traits.hh into  
tlb.hh.

..

sparc: Move translation constants from isa_traits.hh into tlb.hh.

These aren't used outside of SPARC. Also get rid of some unused
constants.

Change-Id: Icfe119f88189348245a6f225a61e62dfa93ea951
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18470
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/tlb.hh
2 files changed, 5 insertions(+), 12 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 5bcfc04..f42cdb9 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -44,23 +44,11 @@
 // This makes sure the big endian versions of certain functions are used.
 using namespace BigEndianGuest;

-// real address virtual mapping
-// sort of like alpha super page, but less frequently used
-const Addr SegKPMEnd  = ULL(0xfffc);
-const Addr SegKPMBase = ULL(0xfac0);
-
 const Addr PageShift = 13;
 const Addr PageBytes = ULL(1) << PageShift;

 StaticInstPtr decodeInst(ExtMachInst);

-/// TLB Stuff 
-const Addr StartVAddrHole = ULL(0x8000);
-const Addr EndVAddrHole = ULL(0x7FFF);
-const Addr VAddrAMask = ULL(0x);
-const Addr PAddrImplMask = ULL(0x00FF);
-const Addr BytesInPageMask = ULL(0x1FFF);
-
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index e5e6753..0d173da 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -44,6 +44,11 @@
 namespace SparcISA
 {

+const Addr StartVAddrHole = ULL(0x8000);
+const Addr EndVAddrHole = ULL(0x7FFF);
+const Addr VAddrAMask = ULL(0x);
+const Addr PAddrImplMask = ULL(0x00FF);
+
 class TLB : public BaseTLB
 {
 // These faults need to be able to populate the tlb in SE mode.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Icfe119f88189348245a6f225a61e62dfa93ea951
Gerrit-Change-Number: 18470
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch: Stop using TheISA within the ISAs.

2019-04-30 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18488 )


Change subject: arch: Stop using TheISA within the ISAs.
..

arch: Stop using TheISA within the ISAs.

We know for sure what the ISA is, so there's no need for the
indirection.

Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488
Reviewed-by: Brandon Potter 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/alpha/utility.cc
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
M src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/tracers/tarmac_base.cc
M src/arch/arm/tracers/tarmac_base.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_parser.hh
M src/arch/arm/tracers/tarmac_record.hh
M src/arch/arm/tracers/tarmac_record_v8.cc
M src/arch/arm/tracers/tarmac_record_v8.hh
M src/arch/arm/tracers/tarmac_tracer.cc
M src/arch/arm/tracers/tarmac_tracer.hh
M src/arch/mips/utility.cc
M src/arch/power/stacktrace.hh
M src/arch/riscv/stacktrace.hh
M src/arch/sparc/utility.cc
M src/arch/x86/process.cc
20 files changed, 58 insertions(+), 62 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Brandon Potter: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index c03e7b0..c644911 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -100,7 +100,7 @@
 void
 skipFunction(ThreadContext *tc)
 {
-TheISA::PCState newPC = tc->pcState();
+PCState newPC = tc->pcState();
 newPC.set(tc->readIntReg(ReturnAddressReg));
 tc->pcState(newPC);
 }
diff --git a/src/arch/arm/isa/insts/fp64.isa  
b/src/arch/arm/isa/insts/fp64.isa

index 26803e7..7decbac 100644
--- a/src/arch/arm/isa/insts/fp64.isa
+++ b/src/arch/arm/isa/insts/fp64.isa
@@ -45,7 +45,7 @@
 exec_output = ""

 zeroSveVecRegUpperPartCode = '''
-TheISA::ISA::zeroSveVecRegUpperPart(%s,
+ArmISA::ISA::zeroSveVecRegUpperPart(%s,
 ArmStaticInst::getCurSveVecLen(xc->tcBase()));
 '''

diff --git a/src/arch/arm/isa/insts/ldr64.isa  
b/src/arch/arm/isa/insts/ldr64.isa

index fe7eaf0..56112a7 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -185,7 +185,7 @@
 accCode = 'uint64_t temp M5_VAR_USED = Mem%s;'
 elif self.flavor == "fp":
 accEpilogCode = '''
-TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
+ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
 ArmStaticInst::getCurSveVecLen(
 xc->tcBase()));
 '''
@@ -239,10 +239,10 @@
 # Code that actually handles the access
 if self.flavor == "fp":
 accEpilogCode = '''
-TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
+ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
 ArmStaticInst::getCurSveVecLen(
 xc->tcBase()));
-TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
+ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
 ArmStaticInst::getCurSveVecLen(
 xc->tcBase()));
 '''
diff --git a/src/arch/arm/isa/insts/neon64_mem.isa  
b/src/arch/arm/isa/insts/neon64_mem.isa

index 8f53369..03ad294 100644
--- a/src/arch/arm/isa/insts/neon64_mem.isa
+++ b/src/arch/arm/isa/insts/neon64_mem.isa
@@ -45,7 +45,7 @@
 exec_output = ''

 zeroSveVecRegUpperPartCode = '''
-TheISA::ISA::zeroSveVecRegUpperPart(%s,
+ArmISA::ISA::zeroSveVecRegUpperPart(%s,
 ArmStaticInst::getCurSveVecLen(xc->tcBase()));
 '''

diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index e5e9e24..c46a34d 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1555,7 +1555,7 @@
 code = sveEnabledCheckCode + '''
 unsigned eCount = ArmStaticInst::getCurSveVecLen(
 xc->tcBase());
-TheISA::VecRegContainer tmpVecC;
+ArmISA::VecRegContainer tmpVecC;
 auto auxOp1 = tmpVecC.as();
 for (unsigned i = 0; i < eCount; ++i) {
 auxOp1[i] = AA64FpOp1_x[i];
@@ -1616,7 +1616,7 @@
 code = sveEnabledCheckCode + '''
 unsigned eCount = ArmStaticInst::getCurSveVecLen(
 xc->tcBase());
-TheISA::VecRegContainer tmpVecC;
+ArmISA::VecRegContainer tmpVecC;
 auto tmpVec = tmpVecC.as();
 int ePow2Count = 1;
 while (ePow2Count < eCount) {
@@ -1761,7 +1761,7 @@
 code =

[gem5-dev] Change in gem5/gem5[master]: x86: Get rid of some unnecessary TheISA-es in x86.

2019-04-30 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18471 )


Change subject: x86: Get rid of some unnecessary TheISA-es in x86.
..

x86: Get rid of some unnecessary TheISA-es in x86.

The X86ISA namespace is already available.

Change-Id: I5774968fdfb30b01eba52cdec5e6ef2c75cb66e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18471
Reviewed-by: Brandon Potter 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/x86/memhelpers.hh
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Brandon Potter: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/memhelpers.hh b/src/arch/x86/memhelpers.hh
index 416439b..59db401 100644
--- a/src/arch/x86/memhelpers.hh
+++ b/src/arch/x86/memhelpers.hh
@@ -179,7 +179,7 @@
 {
 if (traceData)
 traceData->setData(mem);
-mem = TheISA::htog(mem);
+mem = htog(mem);
 return xc->writeMem((uint8_t *), dataSize, addr, flags, res);
 }

@@ -209,7 +209,7 @@
 {
 if (traceData)
 traceData->setData(mem);
-uint64_t host_mem = TheISA::htog(mem);
+uint64_t host_mem = htog(mem);
 Fault fault =
   xc->writeMem((uint8_t *)_mem, dataSize, addr, flags, res);
 if (fault == NoFault && res)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5774968fdfb30b01eba52cdec5e6ef2c75cb66e4
Gerrit-Change-Number: 18471
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Brandon Potter 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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Re: [gem5-dev] gerrit pickiness interacting with kokoro

2019-04-30 Thread Gutierrez, Anthony 
I am fine with this.

Tony

-Original Message-
From: gem5-dev  On Behalf Of Gabe Black
Sent: Monday, April 29, 2019 7:39 PM
To: gem5 Developer List 
Cc: Rahul Thakur 
Subject: Re: [gem5-dev] gerrit pickiness interacting with kokoro

[CAUTION: External Email]

Hello again. I asked the gurus, and they say we probably want to set content 
merging to true. Any objections? I'd like to flip that switch before I go on my 
trip, so by the end of the week.

Gabe

On Sat, Apr 27, 2019 at 5:09 PM Gabe Black  wrote:

> Hi folks. It's historically been an issue with gerrit as we have it 
> set up for use in gem5 that it seems to be pretty picky about when a 
> change can be submitted, and I've had to fairly often (but not always) 
> perform a trivial rebase through the gerrit UI so that it's happy and 
> will let me submit a CL. In the past this has been annoying, but not a 
> big deal since it just takes a few clicks to placate gerrit.
>
> Now that we have kokoro running and verifying CLs (which is a very 
> good thing), rebases have the unfortunate side effect of clearing the 
> verified bit which necessitates running the CI again on essentially 
> the same CL, including a several hour wait. So far this has been a 
> bigger annoyance than before with the added latency getting a CL 
> submitted, but since there haven't (yet) been any series with a lot of 
> those delays stack on top of each other it hasn't been a huge problem.
>
> What I'd like to know is what people think about making gerrit less 
> picky (not sure how that translates to settings TBH) so that these 
> trivial rebases aren't as necessary. Looking at the settings, I see 
> that the "Submit type" is "Rebase Always" and the "Allow content 
> merges" setting is false. There are other settings, but these seem like the 
> most relevant ones.
>
> This page takes a bit about the philosophy behind the submit type setting:
>
>
> https://gerrit-review.googlesource.com/Documentation/intro-project-own
> er.html
>
> With a more complete description of all the submit types over here:
>
>
> https://gerrit-review.googlesource.com/Documentation/config-project-co
> nfig.html#submit-type
>
> If people agree that this is something we should try to change, we can 
> probably ask the gerrit gurus here at Google what settings we can 
> adjust to get the desired effect.
>
> Gabe
>
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Re: [gem5-dev] RFC: Remove Cached Params in Objects

2019-04-30 Thread Gabe Black 
Hi Brandon. I think the idea of dynamic SimObjects is a bit broken, at
least with how things are designed now. There's the issue you mentioned,
but then also the various phases of SimObject setup (init, regStats,
loadState, etc.) aren't going to happen like they're supposed to, or at
least when they're supposed to. Also objects that count on the python
config to set up various properties like finding a parent system object
(for instance) can't work when the python hierarchy is gone or at least
inaccessible.

I think the "correct" way to do what you're trying to do would be to make
the Process object not a SimObject at all, and to have a new SimObject
which reflects the executable/binary you're loading to create a Process.
That object would be known and fixed at config time, and it could result in
0-n Processes during simulation. That would also be a decent collecting
point for serialization during checkpoint creation/loading (which dynamic
SimObjects would likely also break).

Gabe

On Tue, Apr 30, 2019 at 9:00 AM Potter, Brandon 
wrote:

> Hi all,
>
> I merged changeset 2367198921 which added support for dynamically creating
> Process objects during simulation. This feature is needed to allow
> applications to call the clone system call (which serves to fork a process)
> in the middle of simulation.
>
> Inadvertently, this creates a problem with dynamically creating SimObjects
> which might be new to the simulator.
>
> The Process class uses a SimObject class as a base class. Both Process and
> SimObject use Params (normally set by Python) to initialize themselves.
> During clone, I duplicate the ProcessParams and pass them into the Process
> constructor while dynamically allocating an instance of a Process object.
> After I initialized ProcessParams and use them to create the new Process
> object, I deleted them (not wanting to leak memory). However, the SimObject
> class caches a const pointer to Params which can cause memory corruption
> after the free if the pointer is accessed. (Jason points this out with
> https://gem5-review.googlesource.com/c/public/gem5/+/18068.)
>
> The issue can be avoided by removing the cached Params pointer and instead
> only storing the relevant fields which are accessed by the class. However,
> SimObject establishes an accessor API for Params which other classes have
> also implemented. The derived classes essentially implement the same method
> with a cast to convert the Params to the derived class type.
>
> This leaves me in a bit of a bind since I am not sure what the established
> design principle is regarding Params. Conceptually, there is no reason why
> we could not store the relevant fields which each of the Params types
> provide in the respective classes. However, it is a fairly extensive change
> which could be contentious.
>
> Does anyone have a suggestion on how to go about resolving the issue?
>
> Regards,
> Brandon
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[gem5-dev] Cron /z/m5/regression/do-regression quick

2019-04-30 Thread Cron Daemon 
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
FAILED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 FAILED!
* 
build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic:
 FAILED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
FAILED!
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 FAILED!
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED!
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
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* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
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* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
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* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
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* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby:
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* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: 
FAILED!
* 
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: 
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: 
FAILED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: 
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* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
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* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: 
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* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
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* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED!
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
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* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED!
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* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED!
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
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* build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: 
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* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: 
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* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: 
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* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED!
* 
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* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp:
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* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: 
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* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: 
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* 
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* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: 
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* 
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* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: 
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* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: 
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* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: 
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* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: CHANGED!
* 
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* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHANGED!

[gem5-dev] RFC: Remove Cached Params in Objects

2019-04-30 Thread Potter, Brandon 
Hi all,

I merged changeset 2367198921 which added support for dynamically creating 
Process objects during simulation. This feature is needed to allow applications 
to call the clone system call (which serves to fork a process) in the middle of 
simulation.

Inadvertently, this creates a problem with dynamically creating SimObjects 
which might be new to the simulator.

The Process class uses a SimObject class as a base class. Both Process and 
SimObject use Params (normally set by Python) to initialize themselves. During 
clone, I duplicate the ProcessParams and pass them into the Process constructor 
while dynamically allocating an instance of a Process object. After I 
initialized ProcessParams and use them to create the new Process object, I 
deleted them (not wanting to leak memory). However, the SimObject class caches 
a const pointer to Params which can cause memory corruption after the free if 
the pointer is accessed. (Jason points this out with 
https://gem5-review.googlesource.com/c/public/gem5/+/18068.)

The issue can be avoided by removing the cached Params pointer and instead only 
storing the relevant fields which are accessed by the class. However, SimObject 
establishes an accessor API for Params which other classes have also 
implemented. The derived classes essentially implement the same method with a 
cast to convert the Params to the derived class type.

This leaves me in a bit of a bind since I am not sure what the established 
design principle is regarding Params. Conceptually, there is no reason why we 
could not store the relevant fields which each of the Params types provide in 
the respective classes. However, it is a fairly extensive change which could be 
contentious.

Does anyone have a suggestion on how to go about resolving the issue?

Regards,
Brandon
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[gem5-dev] Change in gem5/gem5[master]: sim-se: add eventfd system call

2019-04-30 Thread Brandon Potter (Gerrit) 

Hello Alexandru Duțu, John Alsop, Andrea Mondelli,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/12125

to look at the new patch set (#22).

Change subject: sim-se: add eventfd system call
..

sim-se: add eventfd system call

Change-Id: I7aeb4fe808d0c8f2fb8041e3662d330d8458f09c
---
M src/arch/x86/linux/process.cc
M src/sim/fd_entry.hh
M src/sim/syscall_emul.hh
3 files changed, 53 insertions(+), 3 deletions(-)


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Gerrit-Change-Id: I7aeb4fe808d0c8f2fb8041e3662d330d8458f09c
Gerrit-Change-Number: 12125
Gerrit-PatchSet: 22
Gerrit-Owner: Brandon Potter 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Andrea Mondelli 
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Remove writebacks packet list

2019-04-30 Thread Daniel Carvalho (Gerrit) 

Hello kokoro, Jason Lowe-Power, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/18209

to look at the new patch set (#3).

Change subject: mem-cache: Remove writebacks packet list
..

mem-cache: Remove writebacks packet list

Previously all atomic writebacks concerned a single block,
therefore, when a block was evicted, no other block would be
pending eviction. With sector tags (and compression),
however, a single replacement can generate many evictions.

This can cause problems, since a writeback that evicts a block
may evict blocks in the lower cache. If one of these conflict
with one of the blocks pending eviction in the higher level, the
snoop must inform it to the lower level. Since atomic mode does
not have a writebuffer, this kind of conflict wouldn't be noticed.

Therefore, instead of evicting multiple blocks at once, we
do it one by one.

Change-Id: I2fc2f9eb0f26248ddf91adbe987d158f5a2e592b
Signed-off-by: Daniel R. Carvalho 
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
M src/mem/cache/noncoherent_cache.cc
M src/mem/cache/noncoherent_cache.hh
6 files changed, 157 insertions(+), 190 deletions(-)


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Gerrit-PatchSet: 3
Gerrit-Owner: Daniel Carvalho 
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[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add compression and decompression calls

2019-04-30 Thread Daniel Carvalho (Gerrit) 

Hello kokoro, Jason Lowe-Power, Daniel Carvalho, Nikos Nikoleris,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/11410

to look at the new patch set (#16).

Change subject: mem-cache: Add compression and decompression calls
..

mem-cache: Add compression and decompression calls

Add a compressor to the base cache class and compress within
block allocation and decompress on writebacks.

This change does not implement data expansion (fat writes) yet,
nor it adds the compression latency to the block write time.

Change-Id: Ie36db65f7487c9b05ec4aedebc2c7651b4cb4821
---
M src/mem/cache/Cache.py
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.cc
M src/mem/cache/compressors/base.cc
M src/mem/cache/compressors/base.hh
M src/mem/cache/tags/compressed_tags.cc
M src/mem/cache/tags/compressed_tags.hh
8 files changed, 103 insertions(+), 5 deletions(-)


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Gerrit-PatchSet: 16
Gerrit-Owner: Daniel Carvalho 
Gerrit-Reviewer: Daniel Carvalho 
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Re: [gem5-dev] Gem5 Full System Crashes

2019-04-30 Thread Gabor Dozsa 
Hi Stefan,

This seems to be a bug. There is a fix on the reviewbord:  
https://gem5-review.googlesource.com/c/public/gem5/+/18508. Please give it a 
try!

Cheers,
- Gabor

On 25/04/2019, 16:54, "gem5-dev on behalf of Stefan Waczynski" 
 wrote:

I will place them into the body of the email:

Script:
m5 checkpoint
ls
ls
ls
ls

LibC Backtrace:
gem5 compiled Apr 10 2019 12:23:15
gem5 started Apr 11 2019 16:30:49
gem5 executing on brahms, pid 6734
command line: ./build/X86/gem5.opt configs/example/fs.py
--kernel=/homes/swaczyns/fs_img/binaries/x86_64-vmlinux-2.6.22.9
--disk-image=/homes/swaczyns/fs_img/disks/linux-x86.img
--checkpoint-restor=1 --cpu-type=DerivO3CPU -n 2 --caches --l2cache

Global frequency set at 1 ticks per second
warn: failed to generate dot output from m5out/config.dot
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (512 Mbytes)
info: kernel located at:
/homes/swaczyns/fs_img/binaries/x86_64-vmlinux-2.6.22.9
system.pc.com_1.device: Listening for connections on port 3456
  0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
0: system.remote_gdb: listening for remote gdb on port 7000
0: system.remote_gdb: listening for remote gdb on port 7001
warn: Reading current count from inactive timer.
Switch at curTick count:1
info: Entering event queue @ 5123792249500.  Starting simulation...
Switched CPUS @ tick 5123792259500
switching cpus
info: Entering event queue @ 5123792259500.  Starting simulation...
warn: ClockedObject: Already in the requested power state, request ignored
 REAL SIMULATION 
info: Entering event queue @ 5123792260500.  Starting simulation...
warn: Tried to clear PCI interrupt 14
warn: Don't know what interrupt to clear for console.
gem5.opt: build/X86/cpu/o3/lsq_impl.hh:810: void
LSQ::SplitDataRequest::finish(const Fault&, const RequestPtr&,
ThreadContext*, BaseTLB::Mode) [with Impl = O3CPUImpl; Fault =
std::shared_ptr; RequestPtr = std::shared_ptr]:
Assertion `req == _requests[numTranslatedFragments] || this->isDelayed()'
failed.
Program aborted at tick 513357950
--- BEGIN LIBC BACKTRACE ---
./build/X86/gem5.opt(_Z15print_backtracev+0x15)[0x1320c15]
./build/X86/gem5.opt(_Z12abortHandleri+0x39)[0x132bbb9]
/lib/x86_64-linux-gnu/libpthread.so.0(+0xfcb0)[0x7fdd423e0cb0]
/lib/x86_64-linux-gnu/libc.so.6(gsignal+0x35)[0x7fdd40a74035]

/lib/x86_64-linux-gnu/libc.so.6(abort+0x17b)[0x7fdd40a7779b]
/lib/x86_64-linux-gnu/libc.so.6(+0x2ee1e)[0x7fdd40a6ce1e]
/lib/x86_64-linux-gnu/libc.so.6(+0x2eec2)[0x7fdd40a6cec2]

./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE16SplitDataRequest6finishERKSt10shared_ptrI9FaultBaseERKS3_I7RequestEP13ThreadContextN7BaseTLB4ModeE+0x32c)[0x1461bdc]

./build/X86/gem5.opt(_ZN6X86ISA3TLB15translateTimingERKSt10shared_ptrI7RequestEP13ThreadContextPN7BaseTLB11TranslationENS8_4ModeE+0x87)[0x812b07]

./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE10LSQRequest25sendFragmentToTranslationEi+0x87)[0x1460c27]

./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE16SplitDataRequest19initiateTranslationEv+0x502)[0x1462932]

./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE11pushRequestERK14RefCountingPtrI13BaseO3DynInstIS0_EEbPhjm5FlagsImEPmP15AtomicOpFunctor+0x208)[0x1464488]

./build/X86/gem5.opt(_ZN11BaseDynInstI9O3CPUImplE15initiateMemReadEmj5FlagsImE+0x77)[0x140f687]

./build/X86/gem5.opt(_ZNK10X86ISAInst5LdBig11initiateAccEP11ExecContextPN5Trace10InstRecordE+0x118)[0xc32958]

./build/X86/gem5.opt(_ZN13BaseO3DynInstI9O3CPUImplE11initiateAccEv+0x35)[0x1437645]

./build/X86/gem5.opt(_ZN7LSQUnitI9O3CPUImplE11executeLoadERK14RefCountingPtrI13BaseO3DynInstIS0_EE+0x42)[0x146cb32]

./build/X86/gem5.opt(_ZN3LSQI9O3CPUImplE11executeLoadERK14RefCountingPtrI13BaseO3DynInstIS0_EE+0x27)[0x145ea77]

./build/X86/gem5.opt(_ZN10DefaultIEWI9O3CPUImplE12executeInstsEv+0xf2d)[0x145028d]
./build/X86/gem5.opt(_ZN10DefaultIEWI9O3CPUImplE4tickEv+0x132)[0x1452d52]
./build/X86/gem5.opt(_ZN9FullO3CPUI9O3CPUImplE4tickEv+0x83)[0x1429c43]
./build/X86/gem5.opt(_ZN10EventQueue10serviceOneEv+0xc5)[0x1327275]
./build/X86/gem5.opt(_Z9doSimLoopP10EventQueue+0x38)[0x1335f68]
./build/X86/gem5.opt(_Z8simulatem+0xd3a)[0x133703a]
./build/X86/gem5.opt[0xd6489c]
./build/X86/gem5.opt[0xd47fd0]
/usr/lib/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x4f18)[0x7fdd41f70188]
/usr/lib/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x855)[0x7fdd41f306b5]
/usr/lib/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x5420)[0x7fdd41f70690]
/usr/lib/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x855)[0x7fdd41f306b5]
/usr/lib/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x5420)[0x7fdd41f70690]
/usr/lib/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x855)[0x7fdd41f306b5]

[gem5-dev] Change in gem5/gem5[master]: x86: Mark translation as delayed in case of a hw page table walk

2019-04-30 Thread Gabor Dozsa (Gerrit) 
Gabor Dozsa has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18508



Change subject: x86: Mark translation as delayed in case of a hw page table  
walk

..

x86: Mark translation as delayed in case of a hw page table walk

This information is used by the LSQ in the O3 cpu (since commit
"51becd2... cpu-o3: O3 LSQ Generalisation")

Change-Id: I35fe7e2f8428641d863af0e79e28b0b259fb0b00
Signed-off-by: Gabor Dozsa 
---
M src/arch/x86/tlb.cc
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 33de058..84965b8 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -443,6 +443,8 @@
 TLB::translate(req, tc, translation, mode, delayedResponse, true);
 if (!delayedResponse)
 translation->finish(fault, req, tc, mode);
+else
+translation->markDelayed();
 }

 Walker *

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[gem5-dev] Change in gem5/gem5[master]: cpu: Remove hwrei from the generic interfaces.

2019-04-30 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18432 )


Change subject: cpu: Remove hwrei from the generic interfaces.
..

cpu: Remove hwrei from the generic interfaces.

This mechanism is specific to Alpha and doesn't belong sprinkled around
the CPU's generic mechanisms.

Change-Id: I87904d1a08df2b03eb770205e2c4b94db25201a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18432
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/alpha/ev5.cc
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/dyn_inst_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
11 files changed, 0 insertions(+), 103 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index e3e025e..e64523d 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -485,28 +485,6 @@

 using namespace AlphaISA;

-Fault
-SimpleThread::hwrei()
-{
-auto *stats = dynamic_cast*>(kernelStats);

-assert(stats || !kernelStats);
-
-PCState pc = pcState();
-if (!(pc.pc() & 0x3))
-return std::make_shared();
-
-pc.npc(readMiscRegNoEffect(IPR_EXC_ADDR));
-pcState(pc);
-
-CPA::cpa()->swAutoBegin(this, pc.npc());
-
-if (stats)
-stats->hwrei();
-
-// FIXME: XXX check for interrupts? XXX
-return NoFault;
-}
-
 /**
  * Check for special simulator handling of specific PAL calls.
  * If return value is false, actual PAL call will be suppressed.
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 96f6cc7..acbe94f 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -539,7 +539,6 @@
 void setStCondFailures(unsigned int sc_failures) override {}
 /

-Fault hwrei() override { return thread->hwrei(); }
 bool simPalCheck(int palFunc) override
 { return thread->simPalCheck(palFunc); }
 void wakeup(ThreadID tid) override { }
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 58d756c..0477f3f 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -315,12 +315,6 @@
  */

 /**
- * Somewhat Alpha-specific function that handles returning from an
- * error or interrupt.
- */
-virtual Fault hwrei() = 0;
-
-/**
  * Check for special simulator handling of specific PAL calls.  If
  * return value is false, actual PAL call will be suppressed.
  */
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 4ac621a..03f8e09 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -365,16 +365,6 @@
 return thread.setMiscReg(reg.index(), val);
 }

-Fault
-hwrei() override
-{
-#if THE_ISA == ALPHA_ISA
-return thread.hwrei();
-#else
-return NoFault;
-#endif
-}
-
 bool
 simPalCheck(int palFunc) override
 {
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 70417d5..ba6e80f 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -918,24 +918,6 @@
 }

 template 
-Fault
-FullO3CPU::hwrei(ThreadID tid)
-{
-#if THE_ISA == ALPHA_ISA
-// Need to clear the lock flag upon returning from an interrupt.
-this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid);
-
-auto *stats = dynamic_cast(
-this->thread[tid]->kernelStats);
-assert(stats);
-stats->hwrei();
-
-// FIXME: XXX check for interrupts? XXX
-#endif
-return NoFault;
-}
-
-template 
 bool
 FullO3CPU::simPalCheck(int palFunc, ThreadID tid)
 {
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index c2c4853..bd1479a 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -385,9 +385,6 @@
 /** Traps to handle given fault. */
 void trap(const Fault , ThreadID tid, const StaticInstPtr );

-/** HW return from error interrupt. */
-Fault hwrei(ThreadID tid);
-
 bool simPalCheck(int palFunc, ThreadID tid);

 /** Check if a change in renaming is needed for vector registers.
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 0188660..9b6c1fb 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -248,8 +248,6 @@
 }
 }
 }
-/** Calls hardware return from error interrupt. */
-Fault hwrei() override;
 /** Traps to handle specified fault. */
 void trap(const Fault );
 bool simPalCheck(int palFunc) override;
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 03437a5..5fb5973 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -185,34 +185,6 @@
 }

 template 
-Fault

[gem5-dev] Change in gem5/gem5[master]: alpha: Implement simPalCheck within the ISA description.

2019-04-30 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18433 )


Change subject: alpha: Implement simPalCheck within the ISA description.
..

alpha: Implement simPalCheck within the ISA description.

This doesn't need to be plumbed through generic interfaces. If the
function/instruction got more complex in the future (unlikely since
Alpha doesn't really see development these days), it could be moved to
a helper function defined within Alpha files.

Change-Id: Ib746fad7bb13c5cc9c6ee555c3a46ce686771c12
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18433
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
---
M src/arch/alpha/isa/decoder.isa
M src/arch/alpha/isa/main.isa
2 files changed, 25 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 5635d38..8732d70 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -858,7 +858,30 @@
 } else {
 // check to see if simulator wants to do something special
 // on this PAL call (including maybe suppress it)
-bool dopal = xc->simPalCheck(palFunc);
+bool dopal = true;
+ThreadContext *tc = xc->tcBase();
+auto *base_stats = tc->getKernelStats();
+auto *stats = dynamic_cast(
+base_stats);
+assert(stats || !base_stats);
+if (stats)
+stats->callpal(palFunc, tc);
+
+System *sys = tc->getSystemPtr();
+
+switch (palFunc) {
+  case PAL::halt:
+xc->tcBase()->halt();
+if (--System::numSystemsRunning == 0)
+exitSimLoop("all cpus halted");
+break;
+
+  case PAL::bpt:
+  case PAL::bugchk:
+if (sys->breakpoint())
+dopal = false;
+break;
+}

 if (dopal) {
 xc->setMiscReg(IPR_EXC_ADDR, NPC);
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index f77b1f9..3f7e1a3 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -77,6 +77,7 @@

 #include "arch/alpha/decoder.hh"
 #include "arch/alpha/kernel_stats.hh"
+#include "arch/alpha/osfpal.hh"
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/regredir.hh"
 #include "arch/generic/memhelpers.hh"

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib746fad7bb13c5cc9c6ee555c3a46ce686771c12
Gerrit-Change-Number: 18433
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: cpu: alpha: Delete all occurrances of the simPalCheck function.

2019-04-30 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18434 )


Change subject: cpu: alpha: Delete all occurrances of the simPalCheck  
function.

..

cpu: alpha: Delete all occurrances of the simPalCheck function.

This is now handled within the ISA description.

Change-Id: Ie409bb46d102e59d4eb41408d9196fe235626d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18434
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/alpha/ev5.cc
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/dyn_inst_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
11 files changed, 0 insertions(+), 120 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index e64523d..676d7a7 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -482,35 +482,3 @@
 }

 } // namespace AlphaISA
-
-using namespace AlphaISA;
-
-/**
- * Check for special simulator handling of specific PAL calls.
- * If return value is false, actual PAL call will be suppressed.
- */
-bool
-SimpleThread::simPalCheck(int palFunc)
-{
-auto *stats = dynamic_cast*>(kernelStats);

-assert(stats || !kernelStats);
-
-if (stats)
-stats->callpal(palFunc, this);
-
-switch (palFunc) {
-  case PAL::halt:
-halt();
-if (--System::numSystemsRunning == 0)
-exitSimLoop("all cpus halted");
-break;
-
-  case PAL::bpt:
-  case PAL::bugchk:
-if (system->breakpoint())
-return false;
-break;
-}
-
-return true;
-}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index acbe94f..7582e5e 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -539,8 +539,6 @@
 void setStCondFailures(unsigned int sc_failures) override {}
 /

-bool simPalCheck(int palFunc) override
-{ return thread->simPalCheck(palFunc); }
 void wakeup(ThreadID tid) override { }
 // Assume that the normal CPU's call to syscall was successful.
 // The checker's state would have already been updated by the syscall.
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 0477f3f..5909af6 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -311,19 +311,6 @@

 /**
  * @{
- * @name Alpha-Specific Interfaces
- */
-
-/**
- * Check for special simulator handling of specific PAL calls.  If
- * return value is false, actual PAL call will be suppressed.
- */
-virtual bool simPalCheck(int palFunc) = 0;
-
-/** @} */
-
-/**
- * @{
  * @name ARM-Specific Interfaces
  */

diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 03f8e09..55391c3 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -365,16 +365,6 @@
 return thread.setMiscReg(reg.index(), val);
 }

-bool
-simPalCheck(int palFunc) override
-{
-#if THE_ISA == ALPHA_ISA
-return thread.simPalCheck(palFunc);
-#else
-return false;
-#endif
-}
-
 void
 syscall(int64_t callnum, Fault *fault) override
 {
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index ba6e80f..50de81b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -918,33 +918,6 @@
 }

 template 
-bool
-FullO3CPU::simPalCheck(int palFunc, ThreadID tid)
-{
-#if THE_ISA == ALPHA_ISA
-auto *stats = dynamic_cast(
-this->thread[tid]->kernelStats);
-if (stats)
-stats->callpal(palFunc, this->threadContexts[tid]);
-
-switch (palFunc) {
-  case PAL::halt:
-halt();
-if (--System::numSystemsRunning == 0)
-exitSimLoop("all cpus halted");
-break;
-
-  case PAL::bpt:
-  case PAL::bugchk:
-if (this->system->breakpoint())
-return false;
-break;
-}
-#endif
-return true;
-}
-
-template 
 void
 FullO3CPU::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist)
 {
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index bd1479a..c754fe8 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -385,8 +385,6 @@
 /** Traps to handle given fault. */
 void trap(const Fault , ThreadID tid, const StaticInstPtr );

-bool simPalCheck(int palFunc, ThreadID tid);
-
 /** Check if a change in renaming is needed for vector registers.
  * The vecMode variable is updated and propagated to rename maps.
  *
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 9b6c1fb..131ffd2 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@